From ed226a5d4ee8fb93f9e2a054e6905e99c70bf50c Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Wed, 27 Sep 2017 18:24:04 +0200 Subject: Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux set_uhs_signaling routine in the Xenon driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Platform/Marvell/Drivers/SdMmc') diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194da7..4d4833fb58 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( if (IsDdr) { HostCtrl2 = BIT2; } else if (ClockFreq == 52) { + HostCtrl2 = BIT1; + } else if (ClockFreq == 26) { HostCtrl2 = BIT0; } else { HostCtrl2 = 0; -- cgit v1.2.3