From 8a6202d658436df7cbd6821bee5ffe0a70e72638 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Fri, 1 Sep 2017 13:17:53 +0200 Subject: Drivers/Net/Pp2Dxe: Move registers' description to macros Registers' offset are constant for each PP2 controller instance, so use macros with relative addresses for their description. This allowed to remove 5 PCD's and will ease enabling second controller on Armada8k. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 10 ++++++++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 12 ++++++------ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 6 ------ 3 files changed, 16 insertions(+), 12 deletions(-) (limited to 'Platform/Marvell/Drivers') diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index f283db2d49..868be53031 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define BIT(nr) (1 << (nr)) #endif +/* PP2v2 registers offsets */ +#define MVPP22_SMI_OFFSET 0x12a200 +#define MVPP22_MPCS_OFFSET 0x130000 +#define MVPP22_XPCS_OFFSET 0x130400 +#define MVPP22_GMAC_OFFSET 0x130e00 +#define MVPP22_GMAC_REG_SIZE 0x1000 +#define MVPP22_XLG_OFFSET 0x130f00 +#define MVPP22_XLG_REG_SIZE 0x1000 +#define MVPP22_RFU1_OFFSET 0x441000 + /* RX Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 1e2ccd0dbe..d53f3b7398 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd ( Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance]; Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance]; Pp2Context->Port.Speed = Speed[Pp2Context->Instance]; - Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) + - PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex; - Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) + - PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex; } EFI_STATUS @@ -1174,8 +1170,8 @@ Pp2DxeInitialise ( } Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress); - Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress); - Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress); + Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; + Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET; Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency); /* Prepare buffers */ @@ -1259,6 +1255,10 @@ Pp2DxeInitialise ( Pp2Context->Port.TxpNum = 1; Pp2Context->Port.Priv = Mvpp2Shared; Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance; + Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET + + MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex; + Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET + + MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopIndex; /* Gather accumulated configuration data of all ports' MAC's */ NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 9052fe27b7..ecd82b618d 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -74,18 +74,12 @@ gMarvellTokenSpaceGuid.PcdPhyConnectionTypes gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPp2ClockFrequency - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed gMarvellTokenSpaceGuid.PcdPp2NumPorts gMarvellTokenSpaceGuid.PcdPp2PortIds - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress gMarvellTokenSpaceGuid.PcdPp2SharedAddress - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize [Depex] TRUE -- cgit v1.2.3