From 4e78eed491f9b923e38a8c1da7f0644cb10d8615 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Fri, 23 Dec 2016 10:50:17 +0800 Subject: BroxtonSiPkg: Add ResetVector Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 0 -> 1556 bytes .../Cpu/ResetVector/Vtf0/Bin/ResetVector.inf | 30 + .../BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/vtf0.bsf | 57 ++ .../Cpu/ResetVector/Vtf0/CommonMacros.inc | 31 + .../Cpu/ResetVector/Vtf0/DebugDisabled.asm | 26 + .../Cpu/ResetVector/Vtf0/Ia16/Init16.asm | 50 ++ .../Cpu/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 133 ++++ .../Cpu/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 59 ++ .../Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm | 801 +++++++++++++++++++++ .../BroxtonSiPkg/Cpu/ResetVector/Vtf0/Main.asm | 40 + .../Cpu/ResetVector/Vtf0/Port80Debug.asm | 28 + .../Cpu/ResetVector/Vtf0/PostCodes.inc | 25 + .../BroxtonSiPkg/Cpu/ResetVector/Vtf0/ReadMe.txt | 41 ++ .../Cpu/ResetVector/Vtf0/ResetVectorCode.asm | 45 ++ .../Cpu/ResetVector/Vtf0/SerialDebug.asm | 132 ++++ .../Vtf1/Bin/ResetVector.ia32.port80.raw | Bin 0 -> 244 bytes .../Cpu/ResetVector/Vtf1/Bin/ResetVector.inf | 30 + .../Cpu/ResetVector/Vtf1/CommonMacros.inc | 31 + .../Cpu/ResetVector/Vtf1/DebugDisabled.asm | 26 + .../ResetVector/Vtf1/Ia32/SearchForSecEntry.asm | 211 ++++++ .../BroxtonSiPkg/Cpu/ResetVector/Vtf1/Main.asm | 43 ++ .../Cpu/ResetVector/Vtf1/Port80Debug.asm | 28 + .../Cpu/ResetVector/Vtf1/PostCodes.inc | 25 + .../BroxtonSiPkg/Cpu/ResetVector/Vtf1/ReadMe.txt | 41 ++ .../Cpu/ResetVector/Vtf1/ResetVectorCode.asm | 44 ++ .../Cpu/ResetVector/Vtf1/SerialDebug.asm | 106 +++ 26 files changed, 2083 insertions(+) create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/vtf0.bsf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/CommonMacros.inc create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/DebugDisabled.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Init16.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Main.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Port80Debug.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/PostCodes.inc create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ReadMe.txt create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ResetVectorCode.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/SerialDebug.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.ia32.port80.raw create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/CommonMacros.inc create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/DebugDisabled.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Ia32/SearchForSecEntry.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Main.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Port80Debug.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/PostCodes.inc create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ReadMe.txt create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ResetVectorCode.asm create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/SerialDebug.asm (limited to 'Silicon/BroxtonSoC') diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw new file mode 100644 index 0000000000..f1fc0417a9 Binary files /dev/null and b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw differ diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.inf new file mode 100644 index 0000000000..e0615cba18 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.inf @@ -0,0 +1,30 @@ +## @file +# Reset Vector binary. +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ResetVector + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.1 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Binaries.Ia32] + RAW|ResetVector.ia32.port80.raw|* diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/vtf0.bsf b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/vtf0.bsf new file mode 100644 index 0000000000..ba64145d1e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/vtf0.bsf @@ -0,0 +1,57 @@ +StructDef +Find "$SIG" +$CarBase 4 bytes +$CarSize 4 bytes +$IBBSource 4 bytes +$IBBBase 4 bytes +$IBBSize 4 bytes +$IBBLSource 4 bytes +$IBBLBase 4 bytes +$IBBLSize 4 bytes +EndStruct + +;============================================================================== +; BMP Info Block Definitions +;------------------------------------------------------------------------------ + +BeginInfoBlock + PPVer "0.2" + Image EOF Thru EOF At EOF +EndInfoBlock + + +;============================================================================== +; Page Definitions +;------------------------------------------------------------------------------ + +Page "Revision History" + TitleB "Broxton IBBL BMP Script File" +EndPage + +Page "IBBL binary configuration" + +EditNum $CarBase, " Cache As Ram Base Address:", HEX, +Help "This is the Cache As Ram Base Address." + +EditNum $CarSize, " Cache As Ram Size:", HEX, +Help "This is the Cache As Ram Size." + +EditNum $IBBSource, " IBB Base Address in SRAM/SPI:", HEX, +Help "This is the IBB Base Address in SRAM/SPI." + +EditNum $IBBBase, " IBB Base Address in CAR:", HEX, +Help "This is the IBB Base Address in CAR." + +EditNum $IBBSize, " IBB Size:", HEX, +Help "This is the IBB Size." + +EditNum $IBBLSource, " IBBL Base Address in SRAM/SPI:", HEX, +Help "This is the IBBL Base Address in SRAM/SPI." + +EditNum $IBBLBase, " IBBL Base Address in CAR:", HEX, +Help "This is the IBBL Base Address in CAR." + +EditNum $IBBLSize, " IBBL Size:", HEX, +Help "This is the IBBL Size." + +EndPage diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/CommonMacros.inc b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/CommonMacros.inc new file mode 100644 index 0000000000..98b234c3e7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/CommonMacros.inc @@ -0,0 +1,31 @@ +;; @file +; Common macros used in the ResetVector VTF module. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define ADDR16_OF(x) (0x10000 - fourGigabytes + x) +%define ADDR_OF(x) (0x100000000 - fourGigabytes + x) + +%macro OneTimeCall 1 + jmp %1 +%1 %+ OneTimerCallReturn: +%endmacro + +%macro OneTimeCallRet 1 + jmp %1 %+ OneTimerCallReturn +%endmacro + +StartOfResetVectorCode: + +%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode) + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/DebugDisabled.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/DebugDisabled.asm new file mode 100644 index 0000000000..d8dd7c41fc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/DebugDisabled.asm @@ -0,0 +1,26 @@ +;; @file +; Debug disabled. +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 +%endmacro + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Init16.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Init16.asm new file mode 100644 index 0000000000..a92961c257 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Init16.asm @@ -0,0 +1,50 @@ +;; @file +; 16-bit initialization code. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +; +; @param[out] DI 'BP' to indicate boot-strap processor +; +EarlyBspInitReal16: + mov di, 'BP' + jmp short Main16 + +; +; @param[out] DI 'AP' to indicate application processor +; +EarlyApInitReal16: + mov di, 'AP' + jmp short Main16 + +; +; Modified: EAX +; +; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test) +; @param[out] ESP Initial value of the EAX register (BIST: Built-in Self Test) +; +EarlyInit16: + ; + ; ESP - Initial value of the EAX register (BIST: Built-in Self Test) + ; + movd mm0, eax + rdtsc + movd mm2, eax + movd mm3, edx + + debugInitialize + + OneTimeCallRet EarlyInit16 + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm new file mode 100644 index 0000000000..1a126f963a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -0,0 +1,133 @@ +;; @file +; Transition from 16 bit real mode into 32 bit flat protected mode. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define SEC_DEFAULT_CR0 0x40000023 +%define SEC_DEFAULT_CR4 0x640 + +BITS 16 + +ALIGN 2 + +gdtr: + dw GDT_END - GDT_BASE - 1 ; GDT limit + dd ADDR_OF(GDT_BASE) + +ALIGN 16 + +; +; Macros for GDT entries +; + +%define PRESENT_FLAG(p) (p << 7) +%define DPL(dpl) (dpl << 5) +%define SYSTEM_FLAG(s) (s << 4) +%define DESC_TYPE(t) (t) + +; Type: data, expand-up, writable, accessed +%define DATA32_TYPE 3 + +; Type: execute, readable, expand-up, accessed +%define CODE32_TYPE 0xb + +; Type: execute, readable, expand-up, accessed +%define CODE64_TYPE 0xb + +%define GRANULARITY_FLAG(g) (g << 7) +%define DEFAULT_SIZE32(d) (d << 6) +%define CODE64_FLAG(l) (l << 5) +%define UPPER_LIMIT(l) (l) + +; +; The Global Descriptor Table (GDT) +; +CarMap: + dd ADDR_OF (HOBStructure) +GDT_BASE: +; null descriptor +NULL_SEL equ $-GDT_BASE + DW 0 ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB 0 ; sys flag, dpl, type + DB 0 ; limit 19:16, flags + DB 0 ; base 31:24 + +; linear data segment descriptor +LINEAR_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +; linear code segment descriptor +LINEAR_CODE_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +%ifdef ARCH_X64 +; linear code (64-bit) segment descriptor +LINEAR_CODE64_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 +%endif +GDT_END: + +; +; Modified: EAX, EBX +; +TransitionFromReal16To32BitFlat: + + debugShowPostCode POSTCODE_16BIT_MODE + + cli + + mov bx, 0xf000 + mov ds, bx + + mov bx, ADDR16_OF(gdtr) + +o32 lgdt [cs:bx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere) +BITS 32 +jumpTo32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + OneTimeCallRet TransitionFromReal16To32BitFlat + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm new file mode 100644 index 0000000000..24255662b4 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,59 @@ +;; @file +; First code exectuted by processor after resetting. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +ALIGN 16 +FITHeader: + DQ 0,0,0,0 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp short EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 ; 0fffffff0 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + nop + nop + jmp short EarlyBspInitReal16 +ALIGN 16 + +fourGigabytes: + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm new file mode 100644 index 0000000000..9fa43fcc3e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm @@ -0,0 +1,801 @@ +;; @file +; Search for the Boot Firmware Volume (BFV) base address. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define IA32_MTRR_CAP 0x0FE +%define MTRR_PHYS_BASE_0 0x0200 +%define MTRR_PHYS_MASK_0 0x0201 +%define MTRR_PHYS_BASE_1 0x0202 +%define MTRR_PHYS_MASK_1 0x0203 +%define MTRR_PHYS_BASE_2 0x0204 +%define MTRR_PHYS_MASK_2 0x0205 +%define MTRR_PHYS_BASE_3 0x0206 +%define MTRR_PHYS_MASK_3 0x0207 +%define MTRR_PHYS_BASE_4 0x0208 +%define MTRR_PHYS_MASK_4 0x0209 +%define MTRR_PHYS_BASE_5 0x020A +%define MTRR_PHYS_MASK_5 0x020B +%define MTRR_PHYS_BASE_6 0x020C +%define MTRR_PHYS_MASK_6 0x020D +%define MTRR_PHYS_BASE_7 0x020E +%define MTRR_PHYS_MASK_7 0x020F +%define MTRR_PHYS_BASE_8 0x0210 +%define MTRR_PHYS_MASK_8 0x0211 +%define MTRR_PHYS_BASE_9 0x0212 +%define MTRR_PHYS_MASK_9 0x0213 +%define MTRR_FIX_64K_00000 0x0250 +%define MTRR_FIX_16K_80000 0x0258 +%define MTRR_FIX_16K_A0000 0x0259 +%define MTRR_FIX_4K_C0000 0x0268 +%define MTRR_FIX_4K_C8000 0x0269 +%define MTRR_FIX_4K_D0000 0x026A +%define MTRR_FIX_4K_D8000 0x026B +%define MTRR_FIX_4K_E0000 0x026C +%define MTRR_FIX_4K_E8000 0x026D +%define MTRR_FIX_4K_F0000 0x026E +%define MTRR_FIX_4K_F8000 0x026F +%define MTRR_DEF_TYPE 0x02FF + +%define MTRR_MEMORY_TYPE_UC 0x00 +%define MTRR_MEMORY_TYPE_WC 0x01 +%define MTRR_MEMORY_TYPE_WT 0x04 +%define MTRR_MEMORY_TYPE_WP 0x05 +%define MTRR_MEMORY_TYPE_WB 0x06 + +%define MTRR_DEF_TYPE_E 0x0800 +%define MTRR_DEF_TYPE_FE 0x0400 +%define MTRR_PHYSMASK_VALID 0x0800 +%define SRAMBase 0xFFFE0000 +%define SRAMSize 0x20000 + +%define HOST2CSE 0x70 +%define CSE2HOST 0x60 + +; +; Define the high 32 bits of MTRR masking +; This should be read from CPUID EAX = 080000008h, EAX bits [7:0] +; But for most platforms this will be a fixed supported size so it is +; fixed to save space. +; +%define MTRR_PHYS_MASK_VALID 0x0800 +%define MTRR_PHYS_MASK_HIGH 0x00000000F ; For 36 bit addressing +%define IA32_MISC_ENABLE 0x1A0 +%define FAST_STRING_ENABLE_BIT 0x01 +%define CR0_CACHE_DISABLE 0x040000000 +%define CR0_NO_WRITE 0x020000000 +%define IA32_PLATFORM_ID 0x017 +%define IA32_BIOS_UPDT_TRIG 0x079 +%define IA32_BIOS_SIGN_ID 0x08B +%define PLATFORM_INFO 0x0CE +%define NO_EVICT_MODE 0x2E0 +%define NO_EVICTION_ENABLE_BIT 0x01 + +; +; Cache init and test values +; These are inverted to flip each bit at least once +; +%define CACHE_INIT_VALUE 0xA5A5A5A5 + +;ECP porting + +%define CACHE_TEST_VALUE 0x5aa55aa5 + +; +; Processor MSR definitions +; +%define MSR_BBL_CR_CTL3 0x11E ; L2 cache configuration MSR +%define B_MSR_BBL_CR_CTL3_L2_NOT_PRESENT 23 ; L2 not present +%define B_MSR_BBL_CR_CTL3_L2_ENABLED 8 ; L2 enabled +%define B_MSR_BBL_CR_CTL3_L2_HARDWARE_ENABLED 0 ; L2 hardware enabled + +; +; Fv Header +; +%define FVH_SIGINATURE_OFFSET 0x28 +%define FVH_SIGINATURE_VALID_VALUE 0x4856465F ; valid signature:_FVH +%define FVH_HEADER_LENGTH_OFFSET 0x30 +%define FVH_EXTHEADER_OFFSET_OFFSET 0x34 +%define FVH_EXTHEADER_SIZE_OFFSET 0x10 + +; +; Ffs Header +; +%define FSP_HEADER_GUID_DWORD1 0x912740BE +%define FSP_HEADER_GUID_DWORD2 0x47342284 +%define FSP_HEADER_GUID_DWORD3 0xB08471B9 +%define FSP_HEADER_GUID_DWORD4 0x0C3F3527 +%define FFS_HEADER_SIZE_VALUE 0x18 + +; +; Section Header +; +%define SECTION_HEADER_TYPE_OFFSET 0x03 +%define RAW_SECTION_HEADER_SIZE_VALUE 0x04 + +; +; Fsp Header +; +%define FSP_HEADER_IMAGEBASE_OFFSET 0x1C +%define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 +%define FspReservedSizeOnStackTop 0x40 +struc UpdateHeaderStruc + .dHeaderVersion RESD 1 ; Header version# + .dUpdateRevision RESD 1 ; Update revision# + .dDate RESD 1 ; Date in binary (08/13/07 as 0x08132007) + .dProcessorSignature RESD 1 ; CPU type, family, model, stepping + .dChecksum RESD 1 ; Checksum + .dLoaderRevision RESD 1 ; Update loader version# + .dProcessorFlags RESD 1 ; Processor Flags + .dDataSize RESD 1 ; Size of encrypted data + .dTotalSize RESD 1 ; Total size of update in bytes + .bReserved RESD 12 ; 12 bytes reserved +endstruc + +struc HobStruc + .Sign RESD 1 ; Signiture# + .CarBase RESD 1 ; Cache As Ram Base Address + .CarSize RESD 1 ; Cache As Ram Size + .IBBSource RESD 1 ; IBBM Address in SRAM + .IBBBase RESD 1 ; IBBM Base in CAR. + .IBBSize RESD 1 ; IBBM Size + .IBBLSource RESD 1 ; IBBL Address in SRAM + .IBBLBase RESD 1 ; IBBL Base in CAR. + .IBBLSize RESD 1 ; IBBL Size + .FITBase RESD 1 ; FIT Base Address + .StackHeapBase RESD 1 ; STACK&HEAP Base . + .StackHeapSize RESD 1 ; STACK&HEAP Size + .HostToCse RESD 1 + .CseToHost RESD 1 + .ChunkIndex RESD 1 + .NumberOfChunks RESD 1 + .IbbSizeLeft RESD 1 + .Chunksize RESD 1 + .IbblPerfRecord0 RESQ 1 ; The QWROD Performance record0 of IBBL + .IbblPerfRecord1 RESQ 1 ; The QWROD Performance record1 of IBBL + .IbblPerfRecord2 RESQ 1 ; The QWROD Performance record2 of IBBL + .IbblPerfRecord3 RESQ 1 ; The QWROD Performance record3 of IBBL + .IbblPerfRecord4 RESQ 1 ; The QWROD Performance record4 of IBBL + .IbblPerfRecord5 RESQ 1 ; The QWROD Performance record5 of IBBL +endstruc + +%macro ADDR_OF_CAR 2 +mov %1, [ADDR_OF(HOBStructure) + HobStruc.IBBLBase] +add %1, [ADDR_OF(HOBStructure) + HobStruc.IBBLSize] +sub %1, fourGigabytes - %2 +%endmacro + +ALIGN 16 +HOBStructure: +istruc HobStruc + dd "$SIG" ; .Sign + dd 0xFEF00000 ; .CarBase + dd 0x00100000 ; .CarSize + dd 0xFFF00000 ; .IBBSource = Not used + dd 0xFEF45000 ; .IBBBase = .CarBase + dd 0x00078000 ; .IBBSize = PcdFlashFvIBBMSize = FLASH_REGION_FV_IBBM_SIZE in .fdf + dd 0xFFFFF000 ; .IBBLSource = 0x100000000 - .IBBLSize = PcdFlashFvIBBLBase + dd 0xFEF40000 ; .IBBLBase = .IBBBase + .IBBSize + dd 0x00001000 ; .IBBLSize = PcdFlashFvIBBLSize = FLASH_REGION_FV_IBBL_SIZE in .fdf + dd 0xFEF41000 ; .FITBase + dd 0xFEF00000 ; .Stack&Heap Base + dd 0x16000 ; .Stack&Heap Size + dd 0 ; .HostToCse + dd 0 ; .CseToHost + dd 0 ; .ChunkIndex + dd 0 ; .NumberOfChunks + dd 0 ; .IbbSizeLeft + dd 0 ; .Chunksize + dq 0 ; .IbblPerfRecord0 + dq 0 ; .IbblPerfRecord1 + dq 0 ; .IbblPerfRecord2 + dq 0 ; .IbblPerfRecord3 + dq 0 ; .IbblPerfRecord4 + dq 0 ; .IbblPerfRecord5 +iend +;%macro ShowPostCode 1 +; out 0x80, ax +; mov ecx, %1 / 400 +; loop $ +;%endmacro + +BITS 32 + + +RuninCAR: + rdtsc + movd mm6, eax + movd mm7, edx + + ; + ; Optionally Test the Region... + ; + + ; + ; Test area by writing and reading + ; + cld + mov edi, [ADDR_OF(HOBStructure) + HobStruc.StackHeapBase] + mov ecx, [ADDR_OF(HOBStructure) + HobStruc.StackHeapSize] + shr ecx, 2 + mov eax, CACHE_TEST_VALUE + TestDataStackArea: + stosd + cmp eax, DWORD [edi-4] + jnz DataStackTestFail + loop TestDataStackArea + jmp DataStackTestPass + + ; + ; Cache test failed + ; + DataStackTestFail: + debugShowPostCode 0xD0 + jmp $ + + ; + ; Configuration test failed + ; + ConfigurationTestFailed: + debugShowPostCode 0xD1 + jmp $ + + DataStackTestPass: + + ; + ; relocate GDT to CAR to let CSE use SRAM for IBBM + ; + ADDR_OF_CAR ebx, gdtr + ADDR_OF_CAR esi, GDT_BASE + mov dword [ebx+2],esi + lgdt [ebx] + ADDR_OF_CAR ebp, HOBStructure + mov dword[esi-4], ebp ; save HobStructure pointer near Gdt base for easy locating later. + + mov eax, 0x80007800; + mov dx, 0CF8h + out dx, eax + add dx, 4 + in eax, dx + cmp eax, 0xFFFFFFFF + jz SKIPCSE ; if HECI PCI device does not exist, which mean we are not run on PSS2.0 + ; jmp SKIPCSE +; mov ax, 1234h +; ShowPostCode 0x1000000 + xor ebx, ebx + mov ecx, 0x8b ; Microcode Info MSR + rdmsr + cmp edx, 0 + je uCodeNotLoad + mov ebx, 0x40000000 +uCodeNotLoad: + or ebx, 0x80000000 + + mov eax, dword [ebp + HobStruc.IBBSize] + shl eax, 4 + and eax, 0x3FFFFFFF + add eax, ebx + mov dword [ebp + HobStruc.HostToCse], eax ; value of HOST_TO_SEC + mov dword [ebp + HobStruc.ChunkIndex], 0 ; current chunk index for copying + + mov eax, 0x80007800 + HOST2CSE ; PCI HECI HOST_TO_CSE register + mov dx, 0CF8h + out dx, eax + mov eax, [ebp + HobStruc.HostToCse] + add dx, 4 + out dx, eax +; out 80h, eax + +polling: + mov eax, 0x80007800 + CSE2HOST ; + mov dx, 0CF8h + out dx, eax + add dx, 4 + in eax, dx + mov [ebp + HobStruc.CseToHost], eax ; value of CSE_TO_HOST + ; eax: 29:28, number of chunks; 27:14, sizes in 1Ks. +; out 80h, eax + + mov ebx, eax + bswap ebx + shr ebx, 4 + and ebx, 3 + + cmp ebx, 0 + jnz success + mov ax, 2300h + mov al, bl +; ShowPostCode 0x4000000 + jmp polling +success: + cmp ebx, 3 + jnz next + inc ebx +next: + mov [ebp + HobStruc.NumberOfChunks],ebx ; [ebp+12] number of chunks + mov ebx, eax; + and ebx, 0fffc000h + shr ebx, 4 ; bit 27:14, sizes in 1Ks. + mov [ebp + HobStruc.IbbSizeLeft], ebx ; size of IBB + + ; calculate Chunk Size + mov eax, SRAMSize + xor edx, edx + div dword [ebp + HobStruc.NumberOfChunks] + mov [ebp + HobStruc.Chunksize], eax + +; mov ax, 123Ah +; ShowPostCode 0x4000000 + +RecheckCSEReady: + mov al, byte [ebp + HobStruc.CseToHost] + mov ah, byte [ebp + HobStruc.HostToCse] ; check whether there is ring buffer ready to copy + and ax, 0x0F0F + xor al, ah +; out 80h, al +; mov ecx, 0x4000000 +; loop $ +; ShowPostCode 0x4000000 + cmp al, 0 + jnz startcopy + +; mov ax, 2345h +; ShowPostCode 0x4000000 + + mov eax, 0x80007800 + CSE2HOST + mov dx, 0CF8h + out dx, eax + add dx, 4 + in eax, dx + mov [ebp + HobStruc.CseToHost], eax ; value of SEC_TO_HOST + + out 80h, eax + jmp RecheckCSEReady + +startcopy: + mov bl, al; + mov eax, [ebp + HobStruc.ChunkIndex] +; ShowPostCode 0x4000000 + xor edx, edx + div dword [ebp + HobStruc.NumberOfChunks]; edx: ring buffer index + + ; ecx is the index of ring buffer executing + mov ecx,edx; + + ; calculated the source address in ring buffer + mov esi, SRAMBase + mov eax, [ebp + HobStruc.Chunksize] + mul edx + add esi, eax + + ; calculate the destination address in Cache + mov edi, [ebp + HobStruc.IBBBase] + mov eax, [ebp + HobStruc.Chunksize] + mul dword [ebp + HobStruc.ChunkIndex] + add edi, eax + + mov dl, 01h; + shl dl, cl ; edx, the value of current ring buffer + + and bl, dl ; ebx will be used to flip HOST_TO_CSE chunk values. + xchg bl, dl + cmp dl, 0 + jz RecheckCSEReady + + ; calculate the size + mov ecx, [ebp + HobStruc.Chunksize] ; [ebp + 20], chunk size, [ebp + 16], size not copied. + cmp [ebp + HobStruc.IbbSizeLeft], ecx + ja bigger + mov ecx, [ebp + HobStruc.IbbSizeLeft] +bigger: + sub [ebp + HobStruc.IbbSizeLeft], ecx + mov eax, esi + out 80h, eax + mov eax, edi + out 80h, eax + mov eax, ecx + out 80h, eax + + shr ecx, 6 +copy2: + MOVNTDQA xmm0, [esi] + MOVNTDQA xmm1, [esi+16] + MOVNTDQA xmm2, [esi+32] + MOVNTDQA xmm3, [esi+48] + MOVDQA [edi], xmm0 + MOVDQA [edi+16], xmm1 + MOVDQA [edi+32], xmm2 + MOVDQA [edi+48], xmm3 + add esi,64 + add edi, 64 + loop copy2 + + mov al, byte [ebp + HobStruc.CseToHost] + and al, bl + + mov cl, byte [ebp + HobStruc.HostToCse] + not bl + and cl,bl + or al, cl + mov byte [ebp + HobStruc.HostToCse],al + + mov eax, 0x80007800 + HOST2CSE + mov dx, 0CF8h + out dx, eax + + mov eax, [ebp + HobStruc.HostToCse] + add dx, 4 + out dx, eax + out 80h, eax + +; ShowPostCode 0x4000000 + + inc dword [ebp + HobStruc.ChunkIndex] + cmp dword [ebp + HobStruc.IbbSizeLeft], 0 + + jnz RecheckCSEReady + +; mov ax, 3456h +; ShowPostCode 0x4000000 + jmp noskipcse +; +SKIPCSE: + mov esi, [ebp + HobStruc.IBBSource] + mov edi, [ebp + HobStruc.IBBBase] + mov ecx, [ebp + HobStruc.IBBSize] + shr ecx, 2 + rep movsd + +noskipcse: + mov ecx, 4800h + xchg esi, edi + rep lodsd + + ; + ; For every copy of code from SRAM to NEM this has to be set to avoid dirty iL1 + ; if (for some reason)Code-B is cached in iL1, and then Code-A modifes data next to Code-B, + ; the Core will eject both the data and code-B from iL1. So wrmsr 120 before jmping to Code-A. + ; GLM HSD ES 4942265 + ; + mov ecx, 0120h ;Power_misc + rdmsr + or eax, 0100h ;BIT 8 + wrmsr + + mov esi, [ebp + HobStruc.IBBBase] + mov eax, [esi+020h] ; get FvLength +; mov eax, [ebp + HobStruc.IBBSize] + add esi, eax + sub esi, 0x10 + mov eax, esi + out 80h, eax + mov eax, [esi] + out 80h, eax + + ; + ; Save the Start Time of Reset Vector to IbblPerfRecord0 + ; + movd eax, mm2 + movd edx, mm3 + mov [ebp + HobStruc.IbblPerfRecord0], eax + mov [ebp + HobStruc.IbblPerfRecord0 + 4], edx + ; + ; Save the End Time of InitNEM to IbblPerfRecord1 + ; + movd eax, mm4 + movd edx, mm5 + mov [ebp + HobStruc.IbblPerfRecord1], eax + mov [ebp + HobStruc.IbblPerfRecord1 + 4], edx + ; + ; Save the End Time of IBBLSdw to IbblPerfRecord2 + ; + movd eax, mm6 + movd edx, mm7 + mov [ebp + HobStruc.IbblPerfRecord2], eax + mov [ebp + HobStruc.IbblPerfRecord2 + 4], edx + ; + ; Save the End Time of IBBM Load to IbblPerfRecord3 + ; + rdtsc + mov [ebp + HobStruc.IbblPerfRecord3], eax + mov [ebp + HobStruc.IbblPerfRecord3 + 4], edx + + ; + ; Jump to Virtual Reset Vector in IBBM + ; + + WaitVerify: + mov eax, 0x80007800 + CSE2HOST ; + mov dx, 0CF8h + out dx, eax + add dx, 4 + in eax, dx + and eax, 0600h + cmp eax, 0600h + jne WaitVerify + + ; + ; Save the End Time of IBBM Verify to IbblPerfRecord4 + ; + rdtsc + mov [ebp + HobStruc.IbblPerfRecord4], eax + mov [ebp + HobStruc.IbblPerfRecord4 + 4], edx + + ; + ; Restore initial EAX value into the EAX register + ; + mov eax, esp + + jmp esi ;jump to \Vtf1\Main.asm #40 + +InitNEM: + ; Enable cache for use as stack and for caching code + ; The algorithm is specified in the processor BIOS writer's guide + + ; Ensure that the system is in flat 32 bit protected mode. + ; + ; Platform Specific - configured earlier + ; + ; Ensure that only one logical processor in the system is the BSP. + ; (Required step for clustered systems). + ; + ; Platform Specific - configured earlier + + ; Ensure all APs are in the Wait for SIPI state. + ; This includes all other logical processors in the same physical processor + ; as the BSP and all logical processors in other physical processors. + ; If any APs are awake, the BIOS must put them back into the Wait for + ; SIPI state by issuing a broadcast INIT IPI to all excluding self. + ; + mov edi, 0xFEE00300 ; 0FEE00300h - Send INIT IPI to all excluding self + mov eax, 0x000C4500; ORAllButSelf + ORSelfINIT ; 0000C4500h + mov [edi], eax + + loop1: + mov eax, [edi] + bt eax, 12 ; Check if send is in progress + jc loop1 ; Loop until idle + + ; + ; Load microcode update into BSP. + ; + ; Ensure that all variable-range MTRR valid flags are clear and + ; IA32_MTRR_DEF_TYPE MSR E flag is clear. Note: This is the default state + ; after hardware reset. + ; + ; Platform Specific - MTRR are usually in default state. + ; + + ; + ; Initialize all fixed-range and variable-range MTRR register fields to 0. + ; + mov ecx, IA32_MTRR_CAP ; get variable MTRR support + rdmsr + movzx ebx, al ; EBX = number of variable MTRR pairs + shl ebx, 2 ; *4 for Base/Mask pair and WORD size + add ebx, 24 ; EBX = size of Fixed and Variable MTRRs + + xor eax, eax ; Clear the low dword to write + xor edx, edx ; Clear the high dword to write + + InitMtrrLoop: + add ebx, -2 + mov esi, ADDR_OF(MtrrInitTable) + movzx ecx, word [cs:esi+ebx] + ; ecx <- address of mtrr to zero + wrmsr + jnz InitMtrrLoop ; loop through the whole table + + ; + ; Configure the default memory type to un-cacheable (UC) in the + ; IA32_MTRR_DEF_TYPE MSR. + ; + mov ecx, MTRR_DEF_TYPE ; Load the MTRR default type index + rdmsr + and eax, 0xFFFFF300; NOT (0x0000CFF) ; Clear the enable bits and def type UC. + wrmsr + + ; + ; Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + ; based on the physical address size supported for this processor + ; This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + ; + ; Examples: + ; MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + ; MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + ; + mov eax, 0x80000008 ; Address sizes leaf + cpuid + sub al, 32 + movzx eax, al + xor esi, esi + bts esi, eax + dec esi ; esi <- MTRR_PHYS_MASK_HIGH + + ; + ; Configure the DataStack region as write-back (WB) cacheable memory type + ; using the variable range MTRRs. + ; + + ; + ; Set the base address of the DataStack cache range + ; + mov eax, [ADDR_OF(HOBStructure) + HobStruc.CarBase] + or eax, MTRR_MEMORY_TYPE_WB + ; Load the write-back cache value + xor edx, edx ; clear upper dword + mov ecx, MTRR_PHYS_BASE_0 ; Load the MTRR index + wrmsr ; the value in MTRR_PHYS_BASE_0 + + ; + ; Set the mask for the DataStack cache range + ; Compute MTRR mask value: Mask = NOT (Size - 1) + ; + + mov eax, [ADDR_OF(HOBStructure) + HobStruc.CarSize] + bsr ecx, eax ; Get the least significant set bit of 1 for length + bsf edx, eax ; Get the reversed most significant set bit of 1 for length + cmp ecx, edx + jz noadjust + mov eax, 2 + shl eax, cl +noadjust: + dec eax + not eax + or eax, MTRR_PHYS_MASK_VALID + ; turn on the Valid flag + mov edx, esi ; edx <- MTRR_PHYS_MASK_HIGH + mov ecx, MTRR_PHYS_MASK_0 ; For proper addressing above 4GB + wrmsr ; the value in MTRR_PHYS_BASE_0 + + mov ecx, MTRR_DEF_TYPE ; Load the MTRR default type index + rdmsr + or eax, MTRR_DEF_TYPE_E ; Enable variable range MTRRs + wrmsr + + ; + ; Enable the logical processor's (BSP) cache: execute INVD and set + ; CR0.CD = 0, CR0.NW = 0. + ; + mov eax, cr0 + and eax, 0x9FFFFFFF; NOT (CR0_CACHE_DISABLE + CR0_NO_WRITE) + invd + mov cr0, eax + ; + ; Enable No-Eviction Mode Setup State by setting + ; NO_EVICT_MODE MSR 2E0h bit [0] = '1'. + ; + mov ecx, NO_EVICT_MODE + rdmsr + or eax, 1 + wrmsr + + ; + ; One location in each 64-byte cache line of the DataStack region + ; must be written to set all cache values to the modified state. + ; + mov edi, [ADDR_OF(HOBStructure) + HobStruc.CarBase] + mov ecx, [ADDR_OF(HOBStructure) + HobStruc.CarSize] + shr ecx, 6 + mov eax, CACHE_INIT_VALUE +write: + mov [edi], eax + sfence + add edi, 64 + loop write + + ; + ; Enable No-Eviction Mode Run State by setting + ; NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + ; + mov ecx, NO_EVICT_MODE + rdmsr + or eax, 2 + wrmsr + + ; + ; Finished with cache configuration + ; +OneTimeCallRet InitNEM + + +SwtichToCAR: + rdtsc + movd mm4, eax + movd mm5, edx + mov esi, [ADDR_OF(HOBStructure) + HobStruc.IBBLSource] + mov ecx, [ADDR_OF(HOBStructure) + HobStruc.IBBLSize] + mov edi, [ADDR_OF(HOBStructure) + HobStruc.IBBLBase] + shr ecx, 2 + rep movsd + + mov ecx, 4800h + mov esi, [ADDR_OF(HOBStructure) + HobStruc.CarBase] + rep lodsd + + ; Copy FIT structure to CAR for use in PEI + mov edi, 0xffffffc0 ; load the FIT pointer + mov esi, [edi] ; load location of FIT + + add esi, 0x8 ; get the address of the FIT table size + mov eax, [esi] ; get the value that contians the FIT table size + and eax, 0x00ffffff ; mask off the FIT table Size which is only 24bit + shl eax, 2 ; since size is in 16 bytes chunks, multiply by 4 to get #of Dword to copy + mov ecx, eax ; move the size value to ecx to prepare for the move + sub esi, 0x8 ; restore the esi by the FIT table entry address + + ; calculate the destination address in CAR for FIT copy - just after IBBL + mov edi, [ADDR_OF(HOBStructure) + HobStruc.FITBase] + rep movsd ; copy the FIT structure into CAR. + + ; + ; For every copy of code from SRAM to NEM this has to be set to avoid dirty iL1 + ; GLM HSD ES 4942265 + ; + mov ecx, 0120h ;Power_misc + rdmsr + or eax, 0100h ;BIT 8 + wrmsr + + ; + ; calculate the address in CAR for IBBL and jmp to, and so CSE can put IBBM into SRAM. + ; + ADDR_OF_CAR esi, RuninCAR + jmp esi + nop + HLT + + ; Add enough nop's to ensure that Size(InitNem) + Size(SwitchToCar) > 12*64 (768 bytes) + ; to ensure that end code in "RuninCAR" is far enough from .data of IBBL.fv + ALIGN 64 + HLT + ALIGN 64 ;1 cache line (64bytes) + HLT + ALIGN 64 + HLT + + +MtrrInitTable: + DW MTRR_DEF_TYPE + DW MTRR_FIX_64K_00000 + DW MTRR_FIX_16K_80000 + DW MTRR_FIX_16K_A0000 + DW MTRR_FIX_4K_C0000 + DW MTRR_FIX_4K_C8000 + DW MTRR_FIX_4K_D0000 + DW MTRR_FIX_4K_D8000 + DW MTRR_FIX_4K_E0000 + DW MTRR_FIX_4K_E8000 + DW MTRR_FIX_4K_F0000 + DW MTRR_FIX_4K_F8000 + DW MTRR_PHYS_BASE_0 + DW MTRR_PHYS_MASK_0 + DW MTRR_PHYS_BASE_1 + DW MTRR_PHYS_MASK_1 + DW MTRR_PHYS_BASE_2 + DW MTRR_PHYS_MASK_2 + DW MTRR_PHYS_BASE_3 + DW MTRR_PHYS_MASK_3 + DW MTRR_PHYS_BASE_4 + DW MTRR_PHYS_MASK_4 + DW MTRR_PHYS_BASE_5 + DW MTRR_PHYS_MASK_5 + DW MTRR_PHYS_BASE_6 + DW MTRR_PHYS_MASK_6 + DW MTRR_PHYS_BASE_7 + DW MTRR_PHYS_MASK_7 + DW MTRR_PHYS_BASE_8 + DW MTRR_PHYS_MASK_8 + DW MTRR_PHYS_BASE_9 + DW MTRR_PHYS_MASK_9 + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Main.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Main.asm new file mode 100644 index 0000000000..8576a6d5f2 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Main.asm @@ -0,0 +1,40 @@ +;; @file +; Main routine of the pre-SEC code up through the jump into SEC. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +; +; Modified: EBX, ECX, EDX, EBP +; +; @param[in,out] RAX/EAX Initial value of the EAX register +; (BIST: Built-in Self Test) +; @param[in,out] DI 'BP': boot-strap processor, or +; 'AP': application processor +; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV) +; +; @return None This routine jumps to SEC and does not return +; +Main16: + OneTimeCall EarlyInit16 + + ; + ; Transition the processor from 16-bit real mode to 32-bit flat mode + ; + OneTimeCall TransitionFromReal16To32BitFlat + +BITS 32 + OneTimeCall InitNEM + jmp SwtichToCAR + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Port80Debug.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Port80Debug.asm new file mode 100644 index 0000000000..e5d28e1629 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Port80Debug.asm @@ -0,0 +1,28 @@ +;; @file +; Port 0x80 debug support macros. +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 + mov al, %1 + out 0x80, al +%endmacro + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/PostCodes.inc b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/PostCodes.inc new file mode 100644 index 0000000000..3fe94e6ed3 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/PostCodes.inc @@ -0,0 +1,25 @@ +;; @file +; Definitions of POST CODES for the reset vector module +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define POSTCODE_16BIT_MODE 0x16 +%define POSTCODE_32BIT_MODE 0x32 +%define POSTCODE_64BIT_MODE 0x64 + +%define POSTCODE_BFV_NOT_FOUND 0xb0 +%define POSTCODE_BFV_FOUND 0xb1 + +%define POSTCODE_SEC_NOT_FOUND 0xf0 +%define POSTCODE_SEC_FOUND 0xf1 + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ReadMe.txt b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ReadMe.txt new file mode 100644 index 0000000000..e6e5b54243 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ReadMe.txt @@ -0,0 +1,41 @@ + +=== HOW TO USE VTF0 === + +Add this line to your FDF FV section: +INF RuleOverride=RESET_VECTOR USE = IA32 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf +(For X64 SEC/PEI change IA32 to X64 => 'USE = X64') + +In your FDF FFS file rules sections add: +[Rule.Common.SEC.RESET_VECTOR] + FILE RAW = $(NAMED_GUID) { + RAW RAW |.raw + } + +=== VTF0 Boot Flow === + +1. Transition to IA32 flat mode +2. Locate BFV (Boot Firmware Volume) by checking every 4kb boundary +3. Locate SEC image +4. X64 VTF0 transitions to X64 mode +5. Call SEC image entry point + +== VTF0 SEC input parameters == + +All inputs to SEC image are register based: +EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test) +DI - 'BP': boot-strap processor, or 'AP': application processor +EBP/RBP - Pointer to the start of the Boot Firmware Volume + +=== HOW TO BUILD VTF0 === + +Dependencies: +* Python 2.5~2.7 +* Nasm 2.03 or newer + +To rebuild the VTF0 binaries: +1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0 +2. nasm and python should be in executable path +3. Run this command: + python Build.py +4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ResetVectorCode.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ResetVectorCode.asm new file mode 100644 index 0000000000..5b5719c062 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/ResetVectorCode.asm @@ -0,0 +1,45 @@ +;; @file +; This file includes all other code files to assemble the reset vector code. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%ifdef ARCH_IA32 + %ifdef ARCH_X64 + %error "Only one of ARCH_IA32 or ARCH_X64 can be defined." + %endif +%elifdef ARCH_X64 +%else + %error "Either ARCH_IA32 or ARCH_X64 must be defined." +%endif + +%include "CommonMacros.inc" + +%include "PostCodes.inc" + +%ifdef DEBUG_NONE + %include "DebugDisabled.asm" +%elifdef DEBUG_PORT80 + %include "Port80Debug.asm" +%elifdef DEBUG_SERIAL + %include "SerialDebug.asm" +%else + %error "No debug type was specified." +%endif + +%include "Ia32/InitNEM.asm" + +%include "Ia16/Real16ToFlat32.asm" +%include "Main.asm" +%include "Ia16/Init16.asm" +%include "Ia16/ResetVectorVtf0.asm" + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/SerialDebug.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/SerialDebug.asm new file mode 100644 index 0000000000..65aea33d50 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/SerialDebug.asm @@ -0,0 +1,132 @@ +;; @file +; Serial port debug support macros. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +;//--------------------------------------------- +;// UART Register Offsets +;//--------------------------------------------- +%define BAUD_LOW_OFFSET 0x00 +%define BAUD_HIGH_OFFSET 0x01 +%define IER_OFFSET 0x01 +%define LCR_SHADOW_OFFSET 0x01 +%define FCR_SHADOW_OFFSET 0x02 +%define IR_CONTROL_OFFSET 0x02 +%define FCR_OFFSET 0x02 +%define EIR_OFFSET 0x02 +%define BSR_OFFSET 0x03 +%define LCR_OFFSET 0x03 +%define MCR_OFFSET 0x04 +%define LSR_OFFSET 0x05 +%define MSR_OFFSET 0x06 + +;//--------------------------------------------- +;// UART Register Bit Defines +;//--------------------------------------------- +%define LSR_TXRDY 0x20 +%define LSR_RXDA 0x01 +%define DLAB 0x01 + +; UINT16 gComBase = 0x3f8; +; UINTN gBps = 115200; +; UINT8 gData = 8; +; UINT8 gStop = 1; +; UINT8 gParity = 0; +; UINT8 gBreakSet = 0; + +%define DEFAULT_COM_BASE 0x3f8 +%define DEFAULT_BPS 115200 +%define DEFAULT_DATA 8 +%define DEFAULT_STOP 1 +%define DEFAULT_PARITY 0 +%define DEFAULT_BREAK_SET 0 + +%define SERIAL_DEFAULT_LCR ( \ + (DEFAULT_BREAK_SET << 6) | \ + (DEFAULT_PARITY << 3) | \ + (DEFAULT_STOP << 2) | \ + (DEFAULT_DATA - 5) \ + ) + +%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE + +%macro inFromSerialPort 1 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + in al, dx +%endmacro + +%macro waitForSerialTxReady 0 + +%%waitingForTx: + inFromSerialPort LSR_OFFSET + test al, LSR_TXRDY + jz %%waitingForTx + +%endmacro + +%macro outToSerialPort 2 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + mov al, %2 + out dx, al +%endmacro + +%macro debugShowCharacter 1 + waitForSerialTxReady + outToSerialPort 0, %1 +%endmacro + +%macro debugShowHexDigit 1 + %if (%1 < 0xa) + debugShowCharacter BYTE ('0' + (%1)) + %else + debugShowCharacter BYTE ('a' + ((%1) - 0xa)) + %endif +%endmacro + +%macro debugNewline 0 + debugShowCharacter `\r` + debugShowCharacter `\n` +%endmacro + +%macro debugShowPostCode 1 + debugShowHexDigit (((%1) >> 4) & 0xf) + debugShowHexDigit ((%1) & 0xf) + debugNewline +%endmacro + +BITS 16 + +%macro debugInitialize 0 + jmp real16InitDebug +real16InitDebugReturn: +%endmacro + +real16InitDebug: + ; + ; Set communications format + ; + outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR) + + ; + ; Configure baud rate + ; + outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8) + outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff) + + ; + ; Switch back to bank 0 + ; + outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR + + jmp real16InitDebugReturn + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.ia32.port80.raw b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.ia32.port80.raw new file mode 100644 index 0000000000..a7dff844a6 Binary files /dev/null and b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.ia32.port80.raw differ diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.inf new file mode 100644 index 0000000000..e0615cba18 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Bin/ResetVector.inf @@ -0,0 +1,30 @@ +## @file +# Reset Vector binary. +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ResetVector + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.1 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +[Binaries.Ia32] + RAW|ResetVector.ia32.port80.raw|* diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/CommonMacros.inc b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/CommonMacros.inc new file mode 100644 index 0000000000..98b234c3e7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/CommonMacros.inc @@ -0,0 +1,31 @@ +;; @file +; Common macros used in the ResetVector VTF module. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define ADDR16_OF(x) (0x10000 - fourGigabytes + x) +%define ADDR_OF(x) (0x100000000 - fourGigabytes + x) + +%macro OneTimeCall 1 + jmp %1 +%1 %+ OneTimerCallReturn: +%endmacro + +%macro OneTimeCallRet 1 + jmp %1 %+ OneTimerCallReturn +%endmacro + +StartOfResetVectorCode: + +%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode) + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/DebugDisabled.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/DebugDisabled.asm new file mode 100644 index 0000000000..d8dd7c41fc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/DebugDisabled.asm @@ -0,0 +1,26 @@ +;; @file +; Debug disabled. +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 +%endmacro + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Ia32/SearchForSecEntry.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Ia32/SearchForSecEntry.asm new file mode 100644 index 0000000000..e2cb78c404 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Ia32/SearchForSecEntry.asm @@ -0,0 +1,211 @@ +;; @file +; Search for the SEC Core entry point. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 32 +struc HobStruc + .Sign RESD 1 ; Signiture# + .CarBase RESD 1 ; Cache As Ram Base Address + .CarSize RESD 1 ; Cache As Ram Size + .IBBSource RESD 1 ; IBB Address in SRAM + .IBBBase RESD 1 ; IBB Base in CAR. + .IBBSize RESD 1 ; IBB Size + .IBBLSource RESD 1 ; IBBL Address in SRAM + .IBBLBase RESD 1 ; IBBL Base in CAR. + .IBBLSize RESD 1 ; IBBL Size +endstruc + +%define EFI_FV_FILETYPE_SECURITY_CORE 0x03 + +; +; Modified: EAX, EBX, ECX, EDX +; Preserved: EDI, EBP, ESP +; +; @param[in] EBP Address of Boot Firmware Volume (BFV) +; @param[out] ESI SEC Core Entry Point Address +; +Flat32SearchForSecEntryPoint: + + ; + ; Initialize EBP and ESI to 0 + ; + xor ebx, ebx + mov esi, ebx + + ; + ; Pass over the BFV header + ; + mov eax, [ebp + HobStruc.IBBBase] + mov bx, [eax + 0x30] + add eax, ebx + jc secEntryPointWasNotFound + + jmp searchingForFfsFileHeaderLoop + +moveForwardWhileSearchingForFfsFileHeaderLoop: + ; + ; Make forward progress in the search + ; + inc eax + jc secEntryPointWasNotFound + +searchingForFfsFileHeaderLoop: + test eax, eax + jz secEntryPointWasNotFound + + ; + ; Ensure 8 byte alignment + ; + add eax, 7 + jc secEntryPointWasNotFound + and al, 0xf8 + + ; + ; Look to see if there is an FFS file at eax + ; + mov bl, [eax + 0x17] + test bl, 0x20 + jz moveForwardWhileSearchingForFfsFileHeaderLoop + mov ecx, [eax + 0x14] + and ecx, 0x00ffffff + or ecx, ecx + jz moveForwardWhileSearchingForFfsFileHeaderLoop + add ecx, eax + jz jumpSinceWeFoundTheLastFfsFile + jc moveForwardWhileSearchingForFfsFileHeaderLoop +jumpSinceWeFoundTheLastFfsFile: + + ; + ; There seems to be a valid file at eax + ; + cmp byte [eax + 0x12], EFI_FV_FILETYPE_SECURITY_CORE ; Check File Type + jne readyToTryFfsFileAtEcx + +fileTypeIsSecCore: + OneTimeCall GetEntryPointOfFfsFile + test eax, eax + jnz doneSeachingForSecEntryPoint + +readyToTryFfsFileAtEcx: + ; + ; Try the next FFS file at ECX + ; + mov eax, ecx + jmp searchingForFfsFileHeaderLoop + +secEntryPointWasNotFound: + xor eax, eax + +doneSeachingForSecEntryPoint: + mov esi, eax + + test esi, esi + jnz secCoreEntryPointWasFound + +secCoreEntryPointWasNotFound: + ; + ; Hang if the SEC entry point was not found + ; + debugShowPostCode POSTCODE_SEC_NOT_FOUND + jz $ + +secCoreEntryPointWasFound: + debugShowPostCode POSTCODE_SEC_FOUND + + OneTimeCallRet Flat32SearchForSecEntryPoint + +%define EFI_SECTION_PE32 0x10 +%define EFI_SECTION_TE 0x12 + +; +; Input: +; EAX - Start of FFS file +; ECX - End of FFS file +; +; Output: +; EAX - Entry point of PE32 (or 0 if not found) +; +; Modified: +; EBX +; +GetEntryPointOfFfsFile: + test eax, eax + jz getEntryPointOfFfsFileErrorReturn + add eax, 0x18 ; EAX = Start of section + +getEntryPointOfFfsFileLoopForSections: + cmp eax, ecx + jae getEntryPointOfFfsFileErrorReturn + + cmp byte [eax + 3], EFI_SECTION_PE32 + je getEntryPointOfFfsFileFoundPe32Section + + cmp byte [eax + 3], EFI_SECTION_TE + je getEntryPointOfFfsFileFoundTeSection + + ; + ; The section type was not PE32 or TE, so move to next section + ; + mov ebx, dword [eax] + and ebx, 0x00ffffff + add eax, ebx + jc getEntryPointOfFfsFileErrorReturn + + ; + ; Ensure that FFS section is 32-bit aligned + ; + add eax, 3 + jc getEntryPointOfFfsFileErrorReturn + and al, 0xfc + jmp getEntryPointOfFfsFileLoopForSections + +getEntryPointOfFfsFileFoundPe32Section: + add eax, 4 ; EAX = Start of PE32 image + + cmp word [eax], 'MZ' + jne getEntryPointOfFfsFileErrorReturn + movzx ebx, word [eax + 0x3c] + add ebx, eax + + ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) + cmp dword [ebx], `PE\x00\x00` + jne getEntryPointOfFfsFileErrorReturn + + ; *EntryPoint = (VOID *)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff)); + add eax, [ebx + 0x4 + 0x14 + 0x10] + jmp getEntryPointOfFfsFileReturn + +getEntryPointOfFfsFileFoundTeSection: + add eax, 4 ; EAX = Start of TE image + mov ebx, eax + + ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) + cmp word [ebx], 'VZ' + jne getEntryPointOfFfsFileErrorReturn + ; *EntryPoint = (VOID *)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + + ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize); + add eax, [ebx + 0x8] + add eax, 0x28 + movzx ebx, word [ebx + 0x6] + sub eax, ebx + jmp getEntryPointOfFfsFileReturn + +getEntryPointOfFfsFileErrorReturn: + mov eax, 0 + +getEntryPointOfFfsFileReturn: + OneTimeCallRet GetEntryPointOfFfsFile + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Main.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Main.asm new file mode 100644 index 0000000000..1dc85e9c93 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Main.asm @@ -0,0 +1,43 @@ +;; @file +; Main routine of the pre-SEC code up through the jump into SEC. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 32 +Main32: + ; + ; Search for the SEC entry point + ; + OneTimeCall Flat32SearchForSecEntryPoint + + ; + ; ESI - SEC Core entry point + ; EBP - Start of BFV + ; + + ; + ; Restore initial EAX value into the EAX register + ; + mov eax, esp + + ; + ; Jump to the 32-bit SEC entry point + ; + jmp esi + +ALIGN 16 + out 0x80, ax + jmp short Main32 +ALIGN 16 + Gigabytes: + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Port80Debug.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Port80Debug.asm new file mode 100644 index 0000000000..e5d28e1629 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/Port80Debug.asm @@ -0,0 +1,28 @@ +;; @file +; Port 0x80 debug support macros. +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 + mov al, %1 + out 0x80, al +%endmacro + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/PostCodes.inc b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/PostCodes.inc new file mode 100644 index 0000000000..e952f05f9e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/PostCodes.inc @@ -0,0 +1,25 @@ +;; @file +; Definitions of POST CODES for the reset vector module. +; +; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%define POSTCODE_16BIT_MODE 0x16 +%define POSTCODE_32BIT_MODE 0x32 +%define POSTCODE_64BIT_MODE 0x64 + +%define POSTCODE_BFV_NOT_FOUND 0xb0 +%define POSTCODE_BFV_FOUND 0xb1 + +%define POSTCODE_SEC_NOT_FOUND 0xf0 +%define POSTCODE_SEC_FOUND 0xf1 + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ReadMe.txt b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ReadMe.txt new file mode 100644 index 0000000000..e6e5b54243 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ReadMe.txt @@ -0,0 +1,41 @@ + +=== HOW TO USE VTF0 === + +Add this line to your FDF FV section: +INF RuleOverride=RESET_VECTOR USE = IA32 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf +(For X64 SEC/PEI change IA32 to X64 => 'USE = X64') + +In your FDF FFS file rules sections add: +[Rule.Common.SEC.RESET_VECTOR] + FILE RAW = $(NAMED_GUID) { + RAW RAW |.raw + } + +=== VTF0 Boot Flow === + +1. Transition to IA32 flat mode +2. Locate BFV (Boot Firmware Volume) by checking every 4kb boundary +3. Locate SEC image +4. X64 VTF0 transitions to X64 mode +5. Call SEC image entry point + +== VTF0 SEC input parameters == + +All inputs to SEC image are register based: +EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test) +DI - 'BP': boot-strap processor, or 'AP': application processor +EBP/RBP - Pointer to the start of the Boot Firmware Volume + +=== HOW TO BUILD VTF0 === + +Dependencies: +* Python 2.5~2.7 +* Nasm 2.03 or newer + +To rebuild the VTF0 binaries: +1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0 +2. nasm and python should be in executable path +3. Run this command: + python Build.py +4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ResetVectorCode.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ResetVectorCode.asm new file mode 100644 index 0000000000..05e4a38d1f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/ResetVectorCode.asm @@ -0,0 +1,44 @@ +;; @file +; This file includes all other code files to assemble the reset vector code. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +%ifdef ARCH_IA32 + %ifdef ARCH_X64 + %error "Only one of ARCH_IA32 or ARCH_X64 can be defined." + %endif +%elifdef ARCH_X64 +%else + %error "Either ARCH_IA32 or ARCH_X64 must be defined." +%endif + +%include "CommonMacros.inc" + +%include "PostCodes.inc" + +%ifdef DEBUG_NONE + %include "DebugDisabled.asm" +%elifdef DEBUG_PORT80 + %include "Port80Debug.asm" +%elifdef DEBUG_SERIAL + %include "SerialDebug.asm" +%else + %error "No debug type was specified." +%endif + +%include "Ia32/SearchForSecEntry.asm" + +%include "Main.asm" + + + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/SerialDebug.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/SerialDebug.asm new file mode 100644 index 0000000000..4df4cb90ae --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf1/SerialDebug.asm @@ -0,0 +1,106 @@ +;; @file +; Serial port debug support macros. +; +; Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED +; +;; + +;//--------------------------------------------- +;// UART Register Offsets +;//--------------------------------------------- +%define BAUD_LOW_OFFSET 0x00 +%define BAUD_HIGH_OFFSET 0x01 +%define IER_OFFSET 0x01 +%define LCR_SHADOW_OFFSET 0x01 +%define FCR_SHADOW_OFFSET 0x02 +%define IR_CONTROL_OFFSET 0x02 +%define FCR_OFFSET 0x02 +%define EIR_OFFSET 0x02 +%define BSR_OFFSET 0x03 +%define LCR_OFFSET 0x03 +%define MCR_OFFSET 0x04 +%define LSR_OFFSET 0x05 +%define MSR_OFFSET 0x06 + +;//--------------------------------------------- +;// UART Register Bit Defines +;//--------------------------------------------- +%define LSR_TXRDY 0x20 +%define LSR_RXDA 0x01 +%define DLAB 0x01 + +; UINT16 gComBase = 0x3f8; +; UINTN gBps = 115200; +; UINT8 gData = 8; +; UINT8 gStop = 1; +; UINT8 gParity = 0; +; UINT8 gBreakSet = 0; + +%define DEFAULT_COM_BASE 0x3f8 +%define DEFAULT_BPS 115200 +%define DEFAULT_DATA 8 +%define DEFAULT_STOP 1 +%define DEFAULT_PARITY 0 +%define DEFAULT_BREAK_SET 0 + +%define SERIAL_DEFAULT_LCR ( \ + (DEFAULT_BREAK_SET << 6) | \ + (DEFAULT_PARITY << 3) | \ + (DEFAULT_STOP << 2) | \ + (DEFAULT_DATA - 5) \ + ) + +%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE + +%macro inFromSerialPort 1 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + in al, dx +%endmacro + +%macro waitForSerialTxReady 0 + +%%waitingForTx: + inFromSerialPort LSR_OFFSET + test al, LSR_TXRDY + jz %%waitingForTx + +%endmacro + +%macro outToSerialPort 2 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + mov al, %2 + out dx, al +%endmacro + +%macro debugShowCharacter 1 + waitForSerialTxReady + outToSerialPort 0, %1 +%endmacro + +%macro debugShowHexDigit 1 + %if (%1 < 0xa) + debugShowCharacter BYTE ('0' + (%1)) + %else + debugShowCharacter BYTE ('a' + ((%1) - 0xa)) + %endif +%endmacro + +%macro debugNewline 0 + debugShowCharacter `\r` + debugShowCharacter `\n` +%endmacro + +%macro debugShowPostCode 1 + debugShowHexDigit (((%1) >> 4) & 0xf) + debugShowHexDigit ((%1) & 0xf) + debugNewline +%endmacro + -- cgit v1.2.3