From 90bcd27ee4f7596ad0d2c02e343e4aaa7ad89456 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Tue, 17 Jan 2017 16:07:34 +0800 Subject: Add USB peripheral mode Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang Reviewed-by: David Wei --- .../BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Silicon/BroxtonSoC') diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h index eeb03e2ba2..bc55746bf9 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h @@ -17,7 +17,7 @@ - Registers / bits of new devices introduced in a SC generation will be just named as "_SC_" without inserted. - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -563,6 +563,14 @@ #define B_XDCI_POW_PG_CONF_D3HEN BIT18 ///< D3-Hot Enable #define B_XDCI_POW_PG_CONF_DEVIDLEN BIT17 ///< DEVIDLE Enable + +#define R_OTG_BAR0 0x10 ///< BAR 0 +#define B_OTG_BAR0_BA 0xFFE00000 ///< Base Address +#define V_OTG_BAR0_SIZE 0x200000 +#define N_OTG_BAR0_ALIGNMENT 21 +#define B_OTG_BAR0_PREF BIT3 ///< Prefetchable +#define B_OTG_BAR0_ADDRNG (BIT2 | BIT1) ///< Address Range +#define B_OTG_BAR0_SPTYP BIT0 ///< Space Type (Memory) #define R_OTG_GEN_INPUT_REGRW 0xC0 #define B_OTG_GEN_INPUT_REGRW_CPSU3 (BIT11 | BIT10) ///< Current Power State u3pmu #define B_OTG_GEN_INPUT_REGRW_CPSU2 (BIT9 | BIT8) ///< Current Power State u2pmu -- cgit v1.2.3