From 8322634459ac602d9fbcca30e96b24ff098acb3c Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Wed, 3 May 2017 14:48:15 +0100 Subject: Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey Imported from commit efd798c1eb of https://git.linaro.org/uefi/OpenPlatformPkg.git Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- .../Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf | 60 ++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 94 ++ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl | 88 ++ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 38 + .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl | 38 + .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 29 + .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 956 +++++++++++++++++++++ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl | 86 ++ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl | 181 ++++ .../Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl | 136 +++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 67 ++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 93 ++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 96 +++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 274 ++++++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 130 +++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 80 ++ .../Pv660/Pv660AcpiTables/Pv660Platform.h | 48 ++ .../Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 169 ++++ .../Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 51 ++ Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 64 ++ 20 files changed, 2778 insertions(+) create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL create mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc (limited to 'Silicon/Hisilicon/Pv660/Pv660AcpiTables') diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..3c50ddadb6 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf @@ -0,0 +1,60 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Pv660AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt/Dsdt.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + Iort.asl + Spcr.aslc + Dbg2.aslc + SASSSDT.ASL + SATASSDT.ASL + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + Silicon/Hisilicon/HisiPkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc new file mode 100644 index 0000000000..3a8313adfd --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc @@ -0,0 +1,94 @@ +/** @file +* Debug Port Table 2 (DBG2) +* +* Copyright (c) 2012 - 2014, Linaro Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Pv660Platform.h" + +#include +#include +#include +#include + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof(EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, //OemDataLength + 0, //OemDataOffset + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_BYTE, + FixedPcdGet64(PcdSerialRegisterBase) + } + }, + { + 0x1000 + }, + "COM0" + } + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000000..e995295747 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + // + // A57x16 Processor declaration + // + Device(CPU0) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CPU1) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CPU2) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CPU3) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + Device(CPU4) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CPU5) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CPU6) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CPU7) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + Device(CPU8) { + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CPU9) { + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + Device(CP10) { + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP11) { + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + Device(CP12) { + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP13) { + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + Device(CP14) { + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP15) { + Name(_HID, "ACPI0007") + Name(_UID, 15) + } +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000000..e3fc0d3565 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl @@ -0,0 +1,38 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + Device(COM0) { + Name(_HID, "HISI0031") //it is not 16550 compatible + Name(_CID, "8250dw") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x80300000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-frequency", 200000000}, + Package () {"reg-io-width", 4}, + Package () {"reg-shift", 2}, + } + }) + } +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl new file mode 100644 index 0000000000..5188060732 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl @@ -0,0 +1,38 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + // sysctl dsa + Device(CTL0) { + Name(_HID, "HISI0061") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC0000000, 0x10000) + }) + } + // sysctl pcie + Device(CTL1) { + Name(_HID, "HISI0061") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xB0000000, 0x10000) + }) + } + // sysctl peri_c + Device(CTL2) { + Name(_HID, "HISI0061") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x80000000, 0x10000) + }) + } +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 0000000000..c0cc6d2e93 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,29 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include "Pv660Platform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP05 ", EFI_ACPI_ARM_OEM_REVISION) { + include ("Mbig.asl") + include ("CPU.asl") + include ("Com.asl") + include ("Usb.asl") + include ("Ctl.asl") + include ("Hns.asl") + include ("Pci.asl") +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl new file mode 100644 index 0000000000..881aa1477e --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -0,0 +1,956 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device (MDIO) + { + OperationRegion(CLKR, SystemMemory, 0x80000338, 8) + Field(CLKR, DWordAcc, NoLock, Preserve) { + CLKE, 1, // clock enable + , 31, + CLKD, 1, // clode disable + , 31, + } + OperationRegion(RSTR, SystemMemory, 0x80000A38, 8) + Field(RSTR, DWordAcc, NoLock, Preserve) { + RSTE, 1, // reset + , 31, + RSTD, 1, // de-reset + , 31, + } + + Name(_HID, "HISI0141") + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0x803c0000 , 0x10000) + }) + + Method(_RST, 0, Serialized) { + Store (0x1, RSTE) + Sleep (10) + Store (0x1, CLKD) + Sleep (10) + Store (0x1, RSTD) + Sleep (10) + Store (0x1, CLKE) + Sleep (10) + } + } + + Device (DSF0) + { + OperationRegion(H3SR, SystemMemory, 0xC0000180, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + OperationRegion(H4SR, SystemMemory, 0xC0000190, 4) + Field(H4SR, DWordAcc, NoLock, Preserve) { + H4ST, 1, + , 31, //RESERVED + } + // DSAF RESET + OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) + Field(DRER, DWordAcc, NoLock, Preserve) { + DRTE, 1, + , 31, //RESERVED + DRTD, 1, + , 31, //RESERVED + } + // NT RESET + OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) + Field(NRER, DWordAcc, NoLock, Preserve) { + NRTE, 1, + , 31, //RESERVED + NRTD, 1, + , 31, //RESERVED + } + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // RCB PPE COM RESET + OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) + Field(RRTR, DWordAcc, NoLock, Preserve) { + RRTE, 1, + , 31, //RESERVED + RRTD, 1, + , 31, //RESERVED + } + + // ROCE + + // CPLD LED + + // Serdes + OperationRegion(H4LR, SystemMemory, 0xC2288100, 0x1000) + Field(H4LR, DWordAcc, NoLock, Preserve) { + H4L0, 16, // port0 + H4R0, 16, //RESERVED + Offset (0x400), + H4L1, 16, // port1 + H4R1, 16, //RESERVED + Offset (0x800), + H4L2, 16, // port2 + H4R2, 16, //RESERVED + Offset (0xc00), + H4L3, 16, // port3 + H4R3, 16, //RESERVED + } + OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L2, 16, // port4 + , 16, //RESERVED + Offset (0x400), + H3L3, 16, // port5 + , 16, //RESERVED + } + Name (_HID, "HISI00B1") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) + Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) + { + 149,150,151,152,153,154,26,27,155,156,157,158,159,160, //[14] ge fifo err 8 / xge 6 + 6,7,8,9,16,17,18,19,22,23,24,25, //[12] rcb com 4*3 + 0,1,2,3,4,5,12,13, //[8] ppe tnl 0-7 + 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, //[21] dsaf event int 3+18 + 161,162,163,164, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, //[256] sevice rcb 2*128 + 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, + 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, + 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, + 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, + 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, + 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, + 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511, + 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527, + 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, + 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, + 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "6port-16rss"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {\_SB.MBI1}}, + } + }) + + //reset XGE port + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XRST, 2, Serialized) { + ShiftLeft (0x2082082, Arg0, Local0) + Or (Local0, 0x1, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset XGE core + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XCRT, 2, Serialized) { + ShiftLeft (0x2080, Arg0, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset GE port + //Arg0 : GE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(GRST, 2, Serialized) { + If (LLessEqual (Arg0, 5)) { + //Service port + ShiftLeft (0x1041041, Arg0, Local0) + ShiftLeft (0x1, Arg0, Local1) + + If (LEqual (Arg1, 0)) { + Store(Local1, GR1E) + Store(Local0, GR0E) + } Else { + Store(Local0, GR0D) + Store(Local1, GR1D) + } + } + } + + //reset PPE port + //Arg0 : PPE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(PRST, 2, Serialized) { + ShiftLeft (0x1, Arg0, Local0) + If (LEqual (Arg1, 0)) { + Store(Local0, PRTE) + } Else { + Store(Local0, PRTD) + } + } + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 2, Serialized) { + ShiftLeft (Arg1, 10, Local0) + Switch (ToInteger(Arg0)) + { + case (0x0){ + Store (H4L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L0) + } + case (0x1){ + Store (H4L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L1) + } + case (0x2){ + Store (H4L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L2) + } + case (0x3){ + Store (H4L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L3) + } + case (0x4){ + Store (H3L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L2) + } + case (0x5){ + Store (H3L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L3) + } + } + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg1 : port + //Arg2 : 0 disable, 1 enable + Method(DRST, 3, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + Store (Arg2, Local0) + If (LEqual (Local0, 0)) + { + Store (0x1, DRTE) + Store (0x1, NRTE) + Sleep (10) + Store (0x1, RRTE) + } + Else + { + Store (0x1, DRTD) + Store (0x1, NRTD) + Sleep (10) + Store (0x1, RRTD) + } + } + //Reset PPE port + case (0x2) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + PRST (Local0, Local1) + } + + //Reset XGE core + case (0x3) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XCRT (Local0, Local1) + } + //Reset XGE port + case (0x4) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XRST (Local0, Local1) + } + + //Reset GE port + case (0x5) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + GRST (Local0, Local1) + } + } + } + + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[1] : port index in dsaf + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : port + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : port + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : port index in dsaf + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : port index in dsaf + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local1, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + SRLP (Local0, Local1) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (0, Local1) + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LLessEqual (Local0, 3)) + { + Store (H4ST, Local1) + } + ElseIf (LLessEqual (Local0, 5)) + { + Store (H3ST, Local1) + } + + Return (Local1) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT1) + { + Name (_ADR, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 1}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT4) + { + Name (_ADR, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 4}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 0}, + Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + Device (PRT5) + { + Name (_ADR, 0x5) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 5}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 1}, + Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + } +/* + Device (DSF1) + { + OperationRegion(H3SR, SystemMemory, 0xC0000180, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // ROCE + + // CPLD LED + + // Serdes + OperationRegion(H3LR, SystemMemory, 0xC2208100, 0x4) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L0, 16, // debug port0 + , 16, //RESERVED + } + Name(_HID, "HISI00B1") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc2000000 , 0x890000) + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 14, 15, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "single-port"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {\_SB.MBI1}}, + } + }) + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 1, Serialized) { + ShiftLeft (Arg0, 10, Local0) + Store (H3L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local1, H3L0) + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3) + //Arg1 : 0 disable, 1 enable + Method(DRST, 2, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + If (LEqual (Arg1, 0)) { + Store (0x100, PRTE) + } Else { + Store (0x100, PRTD) + } + } + //Reset PPE port + case (0x2) + { + If (LEqual (Arg1, 0)) { + Store(0x40, PRTE) + } Else { + Store(0x40, PRTD) + } + } + + //Reset GE port + case (0x5) + { + If (LEqual (Arg1, 0)) { + Store(0x15540, GR1E) + Store(0x100, PRTE) + } Else { + Store(0x15540, GR1D) + Store(0x100, PRTD) + } + } + } + } + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge) + // Arg3[1] : reserved + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : reserved + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : reserved + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : reserved + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : reserved + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 2)), Local0) + SRLP (Local0) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (H3ST, Local0) + Return (Local0) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 0}, + Package () {"mdio-node", Package (){\_SB.MDIO}}, + } + }) + } + } + Device (DSF2) + { + OperationRegion(H3SR, SystemMemory, 0xC0000180, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // ROCE + + // CPLD LED + + // Serdes + OperationRegion(H3LR, SystemMemory, 0xC2208500, 0x4) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L1, 16, // debug port1 + , 16, //RESERVED + } + Name(_HID, "HISI00B1") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc2100000 , 0x890000) + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 20, 21, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "single-port"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {\_SB.MBI1}}, + } + }) + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 1, Serialized) { + ShiftLeft (Arg0, 10, Local0) + Store (H3L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local1, H3L1) + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3) + //Arg1 : 0 disable, 1 enable + Method(DRST, 2, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + If (LEqual (Arg1, 0)) { + Store (0x200, PRTE) + } Else { + Store (0x2200, PRTD) + } + } + + //Reset PPE port + case (0x2) + { + If (LEqual (Arg1, 0)) { + Store(0x80, PRTE) + } Else { + Store(0x80, PRTD) + } + } + + //Reset GE port + case (0x5) + { + If (LEqual (Arg1, 0)) { + Store(0x2aa80, GR1E) + Store(0x200, PRTE) + } Else { + Store(0x2aa80, GR1D) + Store(0x200, PRTD) + } + } + } + } + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge) + // Arg3[1] : reserved + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : reserved + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : reserved + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : reserved + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : reserved + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 2)), Local0) + SRLP (Local0) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (H3ST, Local0) + Return (Local0) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 1}, + Package () {"mdio-node", Package (){\_SB.MDIO}}, + } + }) + } + } +*/ + Device (ETH5) { + Name(_HID, "HISI00C1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){\_SB.DSF0}}, + Package () {"port-idx-in-ae", 5}, + } + }) + } + Device (ETH4) { + Name(_HID, "HISI00C1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){\_SB.DSF0}}, + Package () {"port-idx-in-ae", 4}, + } + }) + } + Device (ETH0) { + Name(_HID, "HISI00C1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){\_SB.DSF0}}, + Package () {"port-idx-in-ae", 0}, + } + }) + } + Device (ETH1) { + Name(_HID, "HISI00C1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){\_SB.DSF0}}, + Package () {"port-idx-in-ae", 1}, + } + }) + } + +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl new file mode 100644 index 0000000000..e7d3f72510 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl @@ -0,0 +1,86 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + // Mbi-gen totem + Device(MBI0) { + Name(_HID, "HISI0151") + Name(_CID, "MBIGen") + Name(_UID, 0) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x8c030000, 0x10000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 256} + } + }) + } + + // mbi-gen dsa + Device(MBI1) { + Name(_HID, "HISI0151") + Name(_CID, "MBIGen") + Name(_UID, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc6030000, 0x10000) + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 640} + } + }) + } + + // mbi-gen m3 + Device(MBI2) { + Name(_HID, "HISI0151") + Name(_CID, "MBIGen") + Name(_UID, 2) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa3030000, 0x10000) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 256} + } + }) + } + + // mbi-gen pcie + Device(MBI3) { + Name(_HID, "HISI0151") + Name(_CID, "MBIGen") + Name(_UID, 3) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xb7030000, 0x10000) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 640} + } + }) + } +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl new file mode 100644 index 0000000000..244ff9375d --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl @@ -0,0 +1,181 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +Scope(_SB) +{ + // PCIe Root bus + Device (PCI1) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 1) // Segment of this Root complex + Name(_BBN, 64) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 64, // AddressMinimum - Minimum Bus Number + 127, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 64 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000b0000000, // Min Base Address pci address + 0x00000000b7feffff, // Max Base Address + 0x0000021f58000000, // Translate + 0x0000000007ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Min Base Address + 0x000000000000ffff, // Max Base Address + 0x000002200fff0000, // Translate + 0x0000000000010000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES1) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xb0080000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xb0006918, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { + + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI1) + + // PCIe Root bus + Device (PCI2) + { + Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 2) // Segment of this Root complex + Name(_BBN, 128) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 128, // AddressMinimum - Minimum Bus Number + 191, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 64 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0000000000000000, // Granularity + 0x00000000c0000000, // Min Base Address + 0x00000000c3feffff, // Max Base Address + 0x0000023f4c000000, // Translate + 0x0000000003ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Min Base Address + 0x000000000000ffff, // Max Base Address + 0x000002400fff0000, // Translate + 0x0000000000010000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xb0090000 , 0x10000) + }) + } + + OperationRegion(SCTR, SystemMemory, 0xb0006a18, 4) + Field(SCTR, AnyAcc, NoLock, Preserve) { + LSTA, 32, + } + Method(_DSM, 0x4, Serialized) { + If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) + { + switch(ToInteger(Arg2)) + { + // Function 0: Return LinkStatus + case(0) { + Store (0, Local0) + Store (LSTA, Local0) + Return (Local0) + } + default { + } + } + } + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return(Buffer(){0}) + } + } // Device(PCI2) +} + diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl new file mode 100644 index 0000000000..a0082af096 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl @@ -0,0 +1,136 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + Device (USB0) + { + Name (_HID, "PNP0D20") // _HID: Hardware ID + Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xA1000000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000014, + } + }) + Return (RBUF) /* \_SB_.USB0._CRS.RBUF */ + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"interrupt-parent",Package() {\_SB.MBI2}} + } + }) + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + Device (PRT1) + { + Name (_ADR, One) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + Zero, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + + }) + } + + Device (PRT2) + { + Name (_ADR, 0x02) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT3) + { + Name (_ADR, 0x03) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT4) + { + Name (_ADR, 0x04) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + } + } +} + diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc new file mode 100644 index 0000000000..d5bc299cea --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include + +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; + diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc new file mode 100644 index 0000000000..76b281f237 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc @@ -0,0 +1,93 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +//#include "ArmPlatform.h" +#include "Pv660Platform.h" + +#include +#include + +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0, // UINT64 Hypervisor Vendor Identify +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc new file mode 100644 index 0000000000..054eb2cb9c --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc @@ -0,0 +1,96 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Pv660Platform.h" + +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress +#ifdef notyet + PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + 0, 0, 0, 0), + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + 0, 0, 0, 0) + } +#else /* !notyet */ + 0, 0 + } +#endif + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; + diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl new file mode 100644 index 0000000000..8f38359580 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -0,0 +1,274 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 0000010C +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP05 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 0000000A +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for totem */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 + +/* ITS 1, for dsa */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 + +/* ITS 2, m3 */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 + +/* ITS 3, pcie */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 + +/* mbi-gen pc, named component */ +[0001] Type : 01 +[0002] Length : 003B +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000027 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0012] Device Name : "\_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 0000FFCC +[0004] Output Reference : 00000034 // point to its totem +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen dsa, named component */ +[0001] Type : 01 +[0002] Length : 003B +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000027 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0011] Device Name : "\_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 0000FFCC +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen m3, named component */ +[0001] Type : 01 +[0002] Length : 003B +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000027 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0011] Device Name : "\_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 0000FFCC +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + +/* mbi-gen pcie, named component */ +[0001] Type : 01 +[0002] Length : 003B +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000027 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0011] Device Name : "\_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 0000FFCC +[0004] Output Reference : 0000007C +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + + /* RC 0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000001 + +[0004] Input base : 00004000 +[0004] ID Count : 00004000 +[0004] Output Base : 00004000 +[0004] Output Reference : 0000007C +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 00008000 +[0004] ID Count : 00004000 +[0004] Output Base : 00008000 +[0004] Output Reference : 0000007C +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* +[0001] Type : 03 +[0002] Length : 005C +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 0000005C + +[0008] Base Address : 0000000000000000 +[0008] Span : 0000000000000000 +[0004] Model : 00000000 +[0004] Flags (decoded below) : 00000000 + DVM Supported : 0 + Coherent Walk : 0 +[0004] Global Interrupt Offset : 0000003C +[0004] Context Interrupt Count : 00000001 +[0004] Context Interrupt Offset : 0000004C +[0004] PMU Interrupt Count : 00000001 +[0004] PMU Interrupt Offset : 00000054 + +[0008] SMMU_NSgIrpt Interrupt : 0000000000000000 +[0008] SMMU_NSgCfgIrpt Interrupt : 0000000000000000 +[0008] Context Interrupt : 0000000000000000 +[0008] PMU Interrupt : 0000000000000000 +*/ diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc new file mode 100644 index 0000000000..d83584aa99 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc @@ -0,0 +1,130 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Pv660Platform.h" + +#include +#include +#include +#include +#include + +// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x20000 | ((ClusterId) << 8) | (CoreId)) + + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[4]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // GsivId, GicRBase, Mpidr) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v5.1). + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), + }, + + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), + { + EFI_ACPI_6_1_GIC_ITS_INIT(0,0x8C000000), // pc + EFI_ACPI_6_1_GIC_ITS_INIT(1,0xC6000000), // dsa + EFI_ACPI_6_1_GIC_ITS_INIT(2,0xA3000000), // m3 + EFI_ACPI_6_1_GIC_ITS_INIT(3,0xB7000000) // pcie + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc new file mode 100644 index 0000000000..69b7b38ede --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ + +#include +#include "Pv660Platform.h" + +#define ACPI_6_1_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 ullBaseAddress; + UINT16 usSegGroupNum; + UINT8 ucStartBusNum; + UINT8 ucEndBusNum; + UINT32 Reserved2; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[2]; +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + + { + 0x0000022000000000, //Base Address + 0x0001, //Segment Group Number + 0x40, //Start Bus Number + 0x7f, //End Bus Number + 0x00000000, //Reserved + }, + { + 0x0000024000000000, //Base Address + 0x0002, //Segment Group Number + 0x80, //Start Bus Number + 0xbf, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h new file mode 100644 index 0000000000..5c5b0f12e8 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + + +#ifndef _PV660_PLATFORM_H_ +#define _PV660_PLATFORM_H_ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','5',' ',' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define PV660_WATCHDOG_COUNT 2 + +#endif diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL new file mode 100644 index 0000000000..fa2c2d82da --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL @@ -0,0 +1,169 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ +#include "Pv660Platform.h" +DefinitionBlock ( + "SASSSDT.aml", // Output Filename + "SSDT", // Signature + 0x01, // SSDT Compliance Revision + "HISI ", // OEM ID + "SAS0", // Table ID + EFI_ACPI_ARM_OEM_REVISION // OEM Revision + ) +{ + External(\_SB.MBI1) + External(\_SB.MBI3) + Scope(_SB) { + Device(SAS0) { + Name(_HID, "HISI0161") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc1000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + //phy irq(0~79) + 259,263,264, + 269,273,274, + 279,283,284, + 289,293,294, + 299,303,304, + 309,313,314, + 319,323,324, + 329,333,334, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + //cq irq (80~111) + 336,337,338,339,340,341,342,343, + 344,345,346,347,348,349,350,351, + 352,353,354,355,356,357,358,359, + 360,361,362,363,364,365,366,367, + } + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 376, //chip fatal error irq(120) + 381, //chip fatal error irq(125) + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {\_SB.MBI1}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}}, + Package () {"queue-count", 32}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x338), + CLK, 32, + CLKD, 32, + Offset (0xa60), + RST, 32, + DRST, 32, + Offset (0x5a30), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS1) { + Name(_HID, "HISI0161") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xb1000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + //phy irq(0~79) + 259,263,264, + 269,273,274, + 279,283,284, + 289,293,294, + 299,303,304, + 309,313,314, + 319,323,324, + 329,333,334, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + //cq irq (80~111) + 336,337,338,339,340,341,342,343, + 344,345,346,347,348,349,350,351, + 352,353,354,355,356,357,358,359, + 360,361,362,363,364,365,366,367, + } + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 376, //chip fatal error irq(120) + 381, //chip fatal error irq(125) + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {\_SB.MBI3}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 32}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x318), + CLK, 32, + CLKD, 32, + Offset (0xa18), + RST, 32, + DRST, 32, + Offset (0x5a0c), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + } + +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL new file mode 100644 index 0000000000..f00664ce93 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL @@ -0,0 +1,51 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ +#include "Pv660Platform.h" + +DefinitionBlock ( + "SATASSDT.aml", // Output Filename + "SSDT", // Signature + 0x01, // DSDT Compliance Revision + "HISI ", // OEM ID + "SATA", // Table ID + EFI_ACPI_ARM_OEM_REVISION // OEM Revision + ) +{ +External(\_SB.MBI3) +Scope(_SB) { + Device (AHCI) + { + Name(_HID, "HISI0001") // HiSi AHCI + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00) + Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {\_SB.MBI3}} + } + }) + } + +} + +} diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc new file mode 100644 index 0000000000..5a9ce4a44f --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc @@ -0,0 +1,64 @@ +/** @file +* Serial Port Console Redirection Table (SPCR) +* +* Copyright (c) 2012 - 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include +#include +#include +#include +#include "Pv660Platform.h" + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + //Header; + ARM_ACPI_HEADER( + EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //InterfaceType; + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3]; + //BaseAddress; + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_BYTE, + FixedPcdGet64(PcdSerialRegisterBase) + }, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType; + 0, //Irq; + 349, //GlobalSystemInterrupt; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, //BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //StopBits; + 0, //FlowControl; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //TerminalType; + EFI_ACPI_RESERVED_BYTE, //Language; + 0xFFFF, //PciDeviceId; + 0xFFFF, //PciVendorId; + 0, //PciBusNumber; + 0, //PciDeviceNumber; + 0, //PciFunctionNumber; + 0, //PciFlags; + 0, //PciSegment; + EFI_ACPI_RESERVED_DWORD //Reserved2; +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; -- cgit v1.2.3