From 646b243c0e3ef49b98071ca2c3fec15299b4d72f Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Mon, 19 Jun 2017 10:55:06 +0800 Subject: Add KabylakeSiliconPkg reviewed-by: Jiewen Yao reviewed-by: Michael A Kubacki reviewed-by: Amy Chan reviewed-by: Rangasai V Chaganty reviewed-by: Chasel Chiu Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Signed-off-by: Chasel Chiu --- .../Pch/Include/ConfigBlock/Cio2Config.h | 72 +++ .../Pch/Include/ConfigBlock/DciConfig.h | 53 ++ .../Pch/Include/ConfigBlock/DmiConfig.h | 53 ++ .../Pch/Include/ConfigBlock/EspiConfig.h | 41 ++ .../Include/ConfigBlock/FlashProtectionConfig.h | 54 ++ .../Pch/Include/ConfigBlock/HdAudioConfig.h | 180 ++++++ .../Pch/Include/ConfigBlock/HpetConfig.h | 47 ++ .../Pch/Include/ConfigBlock/HsioConfig.h | 45 ++ .../Pch/Include/ConfigBlock/HsioPcieConfig.h | 76 +++ .../Pch/Include/ConfigBlock/HsioSataConfig.h | 71 ++ .../Pch/Include/ConfigBlock/InterruptConfig.h | 63 ++ .../Pch/Include/ConfigBlock/IoApicConfig.h | 61 ++ .../Pch/Include/ConfigBlock/IshConfig.h | 48 ++ .../Pch/Include/ConfigBlock/LanConfig.h | 44 ++ .../Pch/Include/ConfigBlock/LockDownConfig.h | 67 ++ .../Pch/Include/ConfigBlock/LpcConfig.h | 39 ++ .../Pch/Include/ConfigBlock/P2sbConfig.h | 50 ++ .../Pch/Include/ConfigBlock/PchGeneralConfig.h | 60 ++ .../Pch/Include/ConfigBlock/PcieRpConfig.h | 435 +++++++++++++ .../Pch/Include/ConfigBlock/PmConfig.h | 215 ++++++ .../Pch/Include/ConfigBlock/Port61Config.h | 34 + .../Pch/Include/ConfigBlock/SataConfig.h | 193 ++++++ .../Pch/Include/ConfigBlock/ScsConfig.h | 61 ++ .../Pch/Include/ConfigBlock/SerialIoConfig.h | 56 ++ .../Pch/Include/ConfigBlock/SerialIrqConfig.h | 48 ++ .../Pch/Include/ConfigBlock/SmbusConfig.h | 56 ++ .../Pch/Include/ConfigBlock/SpiConfig.h | 38 ++ .../Pch/Include/ConfigBlock/ThermalConfig.h | 176 +++++ .../Pch/Include/ConfigBlock/TraceHubConfig.h | 35 + .../Pch/Include/ConfigBlock/UsbConfig.h | 233 +++++++ .../Pch/Include/ConfigBlock/WatchDogConfig.h | 38 ++ .../KabylakeSiliconPkg/Pch/Include/GpioConfig.h | 338 ++++++++++ .../KabylakeSiliconPkg/Pch/Include/GpioPinsSklH.h | 248 +++++++ .../KabylakeSiliconPkg/Pch/Include/GpioPinsSklLp.h | 207 ++++++ .../Pch/Include/Library/GpioLib.h | 707 ++++++++++++++++++++ .../Pch/Include/Library/GpioNativeLib.h | 225 +++++++ .../Pch/Include/Library/OcWdtLib.h | 37 ++ .../Pch/Include/Library/PchCycleDecodingLib.h | 345 ++++++++++ .../Pch/Include/Library/PchEspiLib.h | 102 +++ .../Pch/Include/Library/PchGbeLib.h | 64 ++ .../Pch/Include/Library/PchHsioLib.h | 114 ++++ .../Pch/Include/Library/PchInfoLib.h | 260 ++++++++ .../Pch/Include/Library/PchP2sbLib.h | 160 +++++ .../Pch/Include/Library/PchPcieRpLib.h | 110 ++++ .../Pch/Include/Library/PchPcrLib.h | 196 ++++++ .../Pch/Include/Library/PchPmcLib.h | 50 ++ .../Pch/Include/Library/PchPolicyLib.h | 113 ++++ .../Pch/Include/Library/PchPsfLib.h | 170 +++++ .../Pch/Include/Library/PchResetLib.h | 30 + .../Pch/Include/Library/PchSbiAccessLib.h | 162 +++++ .../Pch/Include/Library/PchSerialIoLib.h | 219 +++++++ .../Pch/Include/Library/PchSerialIoUartLib.h | 98 +++ .../Pch/Include/Library/PchSmmControlLib.h | 28 + .../Pch/Include/Library/PchWdtCommonLib.h | 113 ++++ .../Pch/Include/Library/SecPchLib.h | 27 + .../Pch/Include/Library/SpiFlashCommonLib.h | 104 +++ .../Pch/Include/Library/TraceHubInitLib.h | 49 ++ .../KabylakeSiliconPkg/Pch/Include/PchAccess.h | 71 ++ .../KabylakeSiliconPkg/Pch/Include/PchLimits.h | 101 +++ .../Pch/Include/PchPcieStorageDetectHob.h | 54 ++ .../Pch/Include/PchPolicyCommon.h | 54 ++ .../Pch/Include/PchPreMemPolicyCommon.h | 65 ++ .../Pch/Include/PchReservedResources.h | 62 ++ .../Pch/Include/PchResetPlatformSpecific.h | 28 + .../KabylakeSiliconPkg/Pch/Include/Ppi/PchReset.h | 98 +++ .../Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h | 32 + .../Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Wdt.h | 33 + .../Pch/Include/Protocol/PchAcpiSmiDispatch.h | 141 ++++ .../Pch/Include/Protocol/PchEmmcTuning.h | 74 +++ .../Pch/Include/Protocol/PchEspiSmiDispatch.h | 151 +++++ .../Include/Protocol/PchGpioUnlockSmiDispatch.h | 115 ++++ .../Pch/Include/Protocol/PchInfo.h | 57 ++ .../Pch/Include/Protocol/PchPcieSmiDispatch.h | 137 ++++ .../Pch/Include/Protocol/PchReset.h | 121 ++++ .../Pch/Include/Protocol/PchSmiDispatch.h | 139 ++++ .../Pch/Include/Protocol/PchSmmIoTrapControl.h | 72 +++ .../Include/Protocol/PchSmmPeriodicTimerControl.h | 72 +++ .../Pch/Include/Protocol/PchTcoSmiDispatch.h | 157 +++++ .../Pch/Include/Protocol/SerialGpio.h | 126 ++++ .../KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h | 299 +++++++++ .../KabylakeSiliconPkg/Pch/Include/Protocol/Wdt.h | 118 ++++ .../Pch/Include/Register/PchRegsCam.h | 151 +++++ .../Pch/Include/Register/PchRegsDci.h | 50 ++ .../Pch/Include/Register/PchRegsDmi.h | 214 ++++++ .../Pch/Include/Register/PchRegsFia.h | 123 ++++ .../Pch/Include/Register/PchRegsGpio.h | 529 +++++++++++++++ .../Pch/Include/Register/PchRegsHda.h | 201 ++++++ .../Pch/Include/Register/PchRegsHsio.h | 185 ++++++ .../Pch/Include/Register/PchRegsIsh.h | 74 +++ .../Pch/Include/Register/PchRegsItss.h | 94 +++ .../Pch/Include/Register/PchRegsLan.h | 148 +++++ .../Pch/Include/Register/PchRegsLpc.h | 610 +++++++++++++++++ .../Pch/Include/Register/PchRegsP2sb.h | 138 ++++ .../Pch/Include/Register/PchRegsPcie.h | 524 +++++++++++++++ .../Pch/Include/Register/PchRegsPcr.h | 111 ++++ .../Pch/Include/Register/PchRegsPmc.h | 652 +++++++++++++++++++ .../Pch/Include/Register/PchRegsPsf.h | 364 +++++++++++ .../Pch/Include/Register/PchRegsPsth.h | 72 +++ .../Pch/Include/Register/PchRegsSata.h | 720 +++++++++++++++++++++ .../Pch/Include/Register/PchRegsScs.h | 202 ++++++ .../Pch/Include/Register/PchRegsSerialIo.h | 325 ++++++++++ .../Pch/Include/Register/PchRegsSmbus.h | 149 +++++ .../Pch/Include/Register/PchRegsSpi.h | 309 +++++++++ .../Pch/Include/Register/PchRegsThermal.h | 107 +++ .../Pch/Include/Register/PchRegsTraceHub.h | 140 ++++ .../Pch/Include/Register/PchRegsUsb.h | 490 ++++++++++++++ 106 files changed, 16077 insertions(+) create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioConfig.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklH.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklLp.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchAccess.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchLimits.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPolicyCommon.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchReservedResources.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/PchReset.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Wdt.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchGpioUnlockSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchInfo.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchReset.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/SerialGpio.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Wdt.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsCam.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDci.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsFia.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHda.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsItss.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLan.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSata.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsScs.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsThermal.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsUsb.h (limited to 'Silicon/Intel/KabylakeSiliconPkg/Pch/Include') diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h new file mode 100644 index 0000000000..187d4cd506 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h @@ -0,0 +1,72 @@ +/** @file + CIO2 policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _CIO2_CONFIG_H_ +#define _CIO2_CONFIG_H_ + +#define CIO2_CONFIG_REVISION 1 +extern EFI_GUID gCio2ConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_SKYCAM_CIO2_CONFIG block describes SkyCam CIO2 device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + NOTE: For SKL PCH, while CIO2 is enabled, + RC will configure CIO2 controller as ACPI mode when PCH stepping < C0, and configure to PCI mode for C0 onwards. + **/ + UINT32 DeviceEnable : 2; ///< 0: Disabled, 1: Enabled + + UINT32 SkyCamPortATermOvrEnable : 1; ///< 0: Disable, 1: Enable - Termination override on port A + UINT32 SkyCamPortBTermOvrEnable : 1; ///< 0: Disable, 1: Enable - Termination override on port B + UINT32 SkyCamPortCTermOvrEnable : 1; ///< 0: Disable, 1: Enable - Termination override on port C + UINT32 SkyCamPortDTermOvrEnable : 1; ///< 0: Disable, 1: Enable - Termination override on port D + UINT32 RsvdBits : 26; + + // + // CIO2 FLS registers configuration. + // + + UINT32 PortATrimEnable : 1; ///< 0: Disable, 1: Enable - Port A Clk Trim + UINT32 PortBTrimEnable : 1; ///< 0: Disable, 1: Enable - Port B Clk Trim + UINT32 PortCTrimEnable : 1; ///< 0: Disable, 1: Enable - Port C Clk Trim + UINT32 PortDTrimEnable : 1; ///< 0: Disable, 1: Enable - Port D Clk Trim + UINT32 PortACtleEnable : 1; ///< 0: Disable, 1: Enable - Port A Ctle + UINT32 PortBCtleEnable : 1; ///< 0: Disable, 1: Enable - Port B Ctle + UINT32 PortCDCtleEnable : 1; ///< 0: Disable, 1: Enable - Port C/D Ctle + UINT32 RsvdBits0 : 25; + + UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value. Default is 0xE + UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value. Default is 0xE + UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value. Default is 0xE + UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value. Default is 0xD + UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value. Default is 0xD + UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value. Default is 0xD + UINT32 RsvdBits1 : 5; + + UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value. Default is 0xA + UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value. Default is 0xA + UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value. Default is 0x9 + UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value. Default is 0xA + UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value. Default is 0xBBBB + UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value. Default is 0xBBBB + UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value. Default is 0xCCCC + +} PCH_CIO2_CONFIG; + +#pragma pack (pop) + +#endif // _CIO2_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h new file mode 100644 index 0000000000..aba0677abc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h @@ -0,0 +1,53 @@ +/** @file + Dci policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _DCI_CONFIG_H_ +#define _DCI_CONFIG_H_ + +#define DCI_PREMEM_CONFIG_REVISION 2 +extern EFI_GUID gDciPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to Direct Connection Interface (DCI). + + Revision 1: + - Inital version. + Revision 2: + - Deprecate DciAutoDetect +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the host control is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature. + 0:Disabled; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + @deprecated from revision 2. + (Test) When set to Auto detect mode, it detects CCA being connected during BIOS post time. + This policy only applies when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, 1: Enable AUTO mode + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_DCI_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _DCI_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h new file mode 100644 index 0000000000..2fd5d1b171 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h @@ -0,0 +1,53 @@ +/** @file + DMI policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _DMI_CONFIG_H_ +#define _DMI_CONFIG_H_ + +#define DMI_CONFIG_REVISION 2 +extern EFI_GUID gDmiConfigGuid; + + +#pragma pack (push,1) + + +/** + The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. + + Revision 1: + - Initial version. + Revision 2: + - Add LegacyIoLowLatency support. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + 0: Disable; 1: Enable ASPM on PCH side of the DMI Link. + While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value. + **/ + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable DMI Power Optimizer on PCH side. + /** + Set to enable low latenc of legacy IO. + Some systems require lower IO latency irrespective of power. + This is a tradeoff between power and IO latency. + @note: Once this is enabled, DmiAspm is forced to disabled and so do Pcie DmiAspm in SystemAgent. + 0:Disable, 1:Enable + **/ + UINT32 LegacyIoLowLatency : 1; + UINT32 Rsvdbits : 29; ///< Reserved bits +} PCH_DMI_CONFIG; + +#pragma pack (pop) + +#endif // _DMI_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h new file mode 100644 index 0000000000..c952bf9f31 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h @@ -0,0 +1,41 @@ +/** @file + Espi policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _ESPI_CONFIG_H_ +#define _ESPI_CONFIG_H_ + +#define ESPI_CONFIG_REVISION 1 +extern EFI_GUID gEspiConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to ESPI. + + Revision 1: + - Initial version. Add BmeMasterSlaveEnabled support. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + eSPI Master and Slave BME settings. + When TRUE, then the BME bit enabled in eSPI Master and Slave. + 0: FALSE, 1: TRUE + **/ + UINT32 BmeMasterSlaveEnabled : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_ESPI_CONFIG; + +#pragma pack (pop) + +#endif // _ESPI_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h new file mode 100644 index 0000000000..b55aaa705a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h @@ -0,0 +1,54 @@ +/** @file + FlashProtection policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _FLASH_PROTECTION_CONFIG_H_ +#define _FLASH_PROTECTION_CONFIG_H_ + +#define FLASH_PROTECTION_CONFIG_REVISION 1 +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) + +/** + The PCH provides a method for blocking writes and reads to specific ranges + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +#pragma pack (pop) + +#endif // _FLASH_PROTECTION_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h new file mode 100644 index 0000000000..a0ebbbd84d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h @@ -0,0 +1,180 @@ +/** @file + HDAUDIO policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _HDAUDIO_CONFIG_H_ +#define _HDAUDIO_CONFIG_H_ + +#define HDAUDIO_CONFIG_REVISION 2 +extern EFI_GUID gHdAudioConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature. +/// +#define PCH_HDAUDIO_AUTO 2 + +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16)) +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16)) +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (PCH_HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32))) + +/// +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically +/// +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \ +{ \ + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \ + { __VA_ARGS__ } \ +} + +/** + Azalia verb table header + Every verb table should contain this defined header and followed by azalia verb commands. +**/ +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs following the header. +} PCH_HDA_VERB_TABLE_HEADER; + +#ifdef _MSC_VER +// +// Disable "zero-sized array in struct/union" extension warning. +// Used for neater verb table definitions. +// +#pragma warning (push) +#pragma warning (disable: 4200) +#endif +typedef struct { + PCH_HDA_VERB_TABLE_HEADER Header; + UINT32 Data[]; +} HDAUDIO_VERB_TABLE; +#ifdef _MSC_VER +#pragma warning (pop) +#endif + +enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP { + PchHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers. + PchHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers. + PchHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers. +}; + +enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE { + PchHdaIoBuf33V = 0, + PchHdaIoBuf18V = 1 +}; + +enum PCH_HDAUDIO_VC_TYPE { + PchHdaVc0 = 0, + PchHdaVc1 = 1 +}; + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled = 0, + PchHdaDmic2chArray = 1, + PchHdaDmic4chArray = 2, + PchHdaDmic1chArray = 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz = 0, + PchHdaLinkFreq12MHz = 1, + PchHdaLinkFreq24MHz = 2, + PchHdaLinkFreq48MHz = 3, + PchHdaLinkFreq96MHz = 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T = 0, + PchHdaIDispMode1T = 1 +} PCH_HDAUDIO_IDISP_TMODE; + +/** + This structure contains the policies which are related to HD Audio device (cAVS). + + Revision 1: + - Inital version. + Revision 2: + - Deprecate DspPpModuleMask: Pre/Post-processing modules (3rd Party IP) support moved to Platform Package. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not Intel HD Audio (Azalia) should be enabled. + If enabled (in Auto mode) and no codec exists the reference code will automatically disable + the HD Audio device. + 0: Disable, 1: Enable, 2: Auto (enabled if codec detected and initialized, disabled otherwise) + **/ + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; 1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Disable; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: 0: HD-A Link; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: 0: 3.3V; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enumerable + UINT32 RsvdBits0 : 13; ///< Reserved bits 1 + /** + Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: Disable; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: 0: Disable; 1: Enable + UINT32 RsvdBits1 : 28; ///< Reserved bits 2 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; + /** + @deprecated from revision 2. + Bitmask of supported DSP Pre/Post-Processing Modules. + Specific pre/post-processing module bit position must be coherent with the ACPI implementation: + \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support. + DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable + Default is zero. + **/ + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< (Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600. + UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4 + /** + Number of the verb table entry defined in VerbTablePtr. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks. + **/ + UINT8 VerbTableEntryNum; + /** + Pointer to a verb table array. + This pointer points to 32bits address, and is only eligible and consumed in post mem phase. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks. + The prototype of this is: + HDAUDIO_VERB_TABLE **VerbTablePtr; + **/ + UINT32 VerbTablePtr; +} PCH_HDAUDIO_CONFIG; + +#pragma pack (pop) + +#endif // _HDAUDIO_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h new file mode 100644 index 0000000000..30928e5d08 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h @@ -0,0 +1,47 @@ +/** @file + HPET policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _HPET_CONFIG_H_ +#define _HPET_CONFIG_H_ + +#define HPET_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHpetPreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determines if enable HPET timer. 0: Disable; 1: Enable. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halted. + **/ + UINT32 Enable : 1; + UINT32 BdfValid : 1; ///< Whether the BDF value is valid. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is 0x00. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Default is 0xFED00000. +} PCH_HPET_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HPET_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h new file mode 100644 index 0000000000..e4973fc25e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h @@ -0,0 +1,45 @@ +/** @file + HSIO policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _HSIO_CONFIG_H_ +#define _HSIO_CONFIG_H_ + +#define HSIO_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHsioPreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + /** + (Test) + 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent + 1- Enable ChipsetInit HECI message + **/ + UINT32 ChipsetInitMessage : 1; + /** + (Test) + 0- Disable + 1- Enable When eanbled, this is used to bypass the reset after ChipsetInit HECI message. + **/ + UINT32 BypassPhySyncReset : 1; + UINT32 RsvdBits : 30; +} PCH_HSIO_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h new file mode 100644 index 0000000000..cf7bd6251a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h @@ -0,0 +1,76 @@ +/** @file + HSIO pcie policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _HSIO_PCIE_CONFIG_H_ +#define _HSIO_PCIE_CONFIG_H_ + +#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHsioPciePreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits +} PCH_HSIO_PCIE_LANE_CONFIG; + +/** + The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes + Revision 1: + - Initial version. + Revision 2: + - Add PciePllSsc support. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Reserved[3]; +} PCH_HSIO_PCIE_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_PCIE_LANE_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h new file mode 100644 index 0000000000..53c1a01a17 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h @@ -0,0 +1,71 @@ +/** @file + Hsio Sata policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _HSIO_SATA_CONFIG_H_ +#define _HSIO_SATA_CONFIG_H_ + +#define HSIO_SATA_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHsioSataPreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits +} PCH_HSIO_SATA_PORT_LANE; + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; +} PCH_HSIO_SATA_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_SATA_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h new file mode 100644 index 0000000000..3b8e247a31 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h @@ -0,0 +1,63 @@ +/** @file + Interrupt policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _INTERRUPT_CONFIG_H_ +#define _INTERRUPT_CONFIG_H_ + +#define INTERRUPT_CONFIG_REVISION 1 +extern EFI_GUID gInterruptConfigGuid; + +#pragma pack (push,1) + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. +} PCH_INTERRUPT_CONFIG; + +#pragma pack (pop) + +#endif // _INTERRUPT_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h new file mode 100644 index 0000000000..c96e3a3a04 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h @@ -0,0 +1,61 @@ +/** @file + IoApic policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _IOAPIC_CONFIG_H_ +#define _IOAPIC_CONFIG_H_ + +#define IOAPIC_CONFIG_REVISION 1 +extern EFI_GUID gIoApicConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + /** + Revision 1: Init version + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, PCH code will not program these fields if this bit is not TRUE. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable IOAPIC Entry 24-119 + /** + Enable 8254 Static Clock Gating during early POST time. 0: Disable, 1: Enable + Set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. + Make sure it won't break legacy OS boot before enabling this. + **/ + UINT32 Early8254ClockGatingEnable : 1; + UINT32 RsvdBits1 : 6; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is 0x02. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is 0 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +#pragma pack (pop) + +#endif // _IOAPIC_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h new file mode 100644 index 0000000000..6a4f6c9ee0 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h @@ -0,0 +1,48 @@ +/** @file + ISH policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _ISH_CONFIG_H_ +#define _ISH_CONFIG_H_ + +#define ISH_CONFIG_REVISION 1 +extern EFI_GUID gIshConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_ISH_CONFIG block describes Integrated Sensor Hub device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< ISH Controler 0: Disable; 1: Enable. + UINT32 SpiGpioAssign : 1; ///< ISH SPI GPIO pins assigned: 0: False 1: True + UINT32 Uart0GpioAssign : 1; ///< ISH UART0 GPIO pins assigned: 0: False 1: True + UINT32 Uart1GpioAssign : 1; ///< ISH UART1 GPIO pins assigned: 0: False 1: True + UINT32 I2c0GpioAssign : 1; ///< ISH I2C0 GPIO pins assigned: 0: False 1: True + UINT32 I2c1GpioAssign : 1; ///< ISH I2C1 GPIO pins assigned: 0: False 1: True + UINT32 I2c2GpioAssign : 1; ///< ISH I2C2 GPIO pins assigned: 0: False 1: True + UINT32 Gp0GpioAssign : 1; ///< ISH GP_0 GPIO pin assigned: 0: False 1: True + UINT32 Gp1GpioAssign : 1; ///< ISH GP_1 GPIO pin assigned: 0: False 1: True + UINT32 Gp2GpioAssign : 1; ///< ISH GP_2 GPIO pin assigned: 0: False 1: True + UINT32 Gp3GpioAssign : 1; ///< ISH GP_3 GPIO pin assigned: 0: False 1: True + UINT32 Gp4GpioAssign : 1; ///< ISH GP_4 GPIO pin assigned: 0: False 1: True + UINT32 Gp5GpioAssign : 1; ///< ISH GP_5 GPIO pin assigned: 0: False 1: True + UINT32 Gp6GpioAssign : 1; ///< ISH GP_6 GPIO pin assigned: 0: False 1: True + UINT32 Gp7GpioAssign : 1; ///< ISH GP_7 GPIO pin assigned: 0: False 1: True + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: 0: False 1: True + UINT32 RsvdBits0 : 16; ///< Reserved Bits +} PCH_ISH_CONFIG; + +#pragma pack (pop) + +#endif // _ISH_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h new file mode 100644 index 0000000000..980f3ac709 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h @@ -0,0 +1,44 @@ +/** @file + Lan policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _LAN_CONFIG_H_ +#define _LAN_CONFIG_H_ + +#define LAN_CONFIG_REVISION 1 +extern EFI_GUID gLanConfigGuid; + +#pragma pack (push,1) + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determines if enable PCH internal LAN, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to disabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL register. + So it's recommendated to issue a global reset when changing the status for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 LtrEnable : 1; ///< 0: Disable; 1: Enable LTR capabilty of PCH internal LAN. + UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management; 1: Enabled, 0: Disabled; + UINT32 RsvdBits0 : 4; ///< Reserved bits + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported; 1: Enabled, 0: Disabled; + UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReqSupported is TRUE. + UINT32 RsvdBits1 : 20; ///< Reserved bits +} PCH_LAN_CONFIG; + +#pragma pack (pop) + +#endif // _LAN_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h new file mode 100644 index 0000000000..f083b3b50c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h @@ -0,0 +1,67 @@ +/** @file + Lock down policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _LOCK_DOWN_CONFIG_H_ +#define _LOCK_DOWN_CONFIG_H_ + +#define LOCK_DOWN_CONFIG_REVISION 1 +extern EFI_GUID gLockDownConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH + for security requirement. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; 1: Enable. + **/ + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + (Test) Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region can only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to take care + of BIOS modification (including SetVariable) in DXE or runtime phase after + EndOfDxe protocol is installed. 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + Enable InSMM.STS (EISS) in SPI + If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also + in order to write to BIOS regions of SPI Flash. If this bit is clear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programming in + PEI phase or early DXE phase. + 0: Clear EISS bit; 1: Set EISS bit. + **/ + UINT32 SpiEiss : 1; + UINT32 RsvdBits0 : 27; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +#pragma pack (pop) + +#endif // _LOCK_DOWN_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h new file mode 100644 index 0000000000..be1613a5c2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,39 @@ +/** @file + Lpc policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _LPC_CONFIG_H_ +#define _LPC_CONFIG_H_ + +#define LPC_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gLpcPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_LPC_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _LPC_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h new file mode 100644 index 0000000000..60b9828ebf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h @@ -0,0 +1,50 @@ +/** @file + P2sb policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _P2SB_CONFIG_H_ +#define _P2SB_CONFIG_H_ + +#define P2SB_CONFIG_REVISION 2 +extern EFI_GUID gP2sbConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to P2SB device. + Revision 1: + - Init version + Revision 2: + - Deprecate PsfUnlock and Add SbAccessUnlock to not lock SideBand register access. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) + This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. + NOTE: Do not set this policy "SbiUnlock" unless necessary. + **/ + UINT32 SbiUnlock : 1; + UINT32 PsfUnlock : 1; //@deprecated + /** + (Test) + The SideBand registers will be locked before 3rd party code execution. + This policy unlock the SideBand space. 0: Disable; 1: Enable. + NOTE: Do not set this policy "SbAccessUnlock" unless necessary. + **/ + UINT32 SbAccessUnlock : 1; + UINT32 RsvdBits : 29; +} PCH_P2SB_CONFIG; + +#pragma pack (pop) + +#endif // _P2SB_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h new file mode 100644 index 0000000000..c946e9a116 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h @@ -0,0 +1,60 @@ +/** @file + PCH General policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_GENERAL_CONFIG_H_ +#define _PCH_GENERAL_CONFIG_H_ + +#define PCH_GENERAL_CONFIG_REVISION 1 +#define PCH_GENERAL_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPchGeneralConfigGuid; +extern EFI_GUID gPchGeneralPreMemConfigGuid; + +#pragma pack (push,1) + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Subsystem Vendor ID and Subsystem ID of the PCH devices. + This fields will be ignored if the value of SubSystemVendorId and SubSystemId + are both 0. + **/ + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is 0x8086 + UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is 0x7270 + /** + This member describes whether or not the Compatibility Revision ID (CRID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_GENERAL_CONFIG; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT16 AcpiBase; ///< Power management I/O base address. Default is 0x1800. + UINT8 RsvdBytes[2]; + /** + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + **/ + UINT32 Port80Route : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_GENERAL_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_GENERAL_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h new file mode 100644 index 0000000000..873386afe7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h @@ -0,0 +1,435 @@ +/** @file + Pcie root port policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PCIE_CONFIG_H_ +#define _PCH_PCIE_CONFIG_H_ + +#define PCIE_RP_CONFIG_REVISION 4 +#define PCIE_RP_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPcieRpConfigGuid; +extern EFI_GUID gPcieRpPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +typedef enum { + PchPcieOverrideDisabled = 0, + PchPcieL1L2Override = 0x01, + PchPcieL1SubstatesOverride = 0x02, + PchPcieL1L2AndL1SubstatesOverride = 0x03, + PchPcieLtrOverride = 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM settings. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideConfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be override. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled, then: + rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored + **/ + UINT8 ForceLtrOverride; + UINT8 Reserved[3]; +} PCH_PCIE_DEVICE_OVERRIDE; + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 = 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +typedef enum { + PchPcieEqDefault = 0, ///< Use reference code default (software margining) + PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer + PchPcieEqSoftware = 2, ///< Use software margining flow + PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. +**/ +typedef struct { + UINT32 Enable : 1; ///< @deprecated. + UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals for LP and H. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts + to verify CLKREQ# signal is connected by testing pad state before enabling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable. + /** + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the root port. + **/ + UINT32 MaxPayload : 2; + UINT32 EnableHotplugSmi : 1; ///< Indicate whether the Hotplug Smi for Rootport is enabled, for TBT rootport we need to disable hotplug smi. 0: Disable; 1: Enable . + UINT32 RsvdBits1 : 3; ///< Reserved fields for future expansion w/o protocol change + + UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + 0: Default; 2: Software Search; 4: Fixed Coefficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. + /** + The PCH pin assigned to device PERST# signal if available, zero otherwise. + This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices + (mainly some graphic adapters) to successfully complete the software equalization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 DeviceResetPad; + UINT32 Rsvd1; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. + UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable. + UINT8 LtrConfigLock; ///< 0: Disable; 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is zero. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is zero. + // + // Gen3 Equalization settings + // + UINT32 Uptp : 4; ///< (Test) Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 5. + UINT32 Dptp : 4; ///< (Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7. + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled, then: + rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored + **/ + UINT32 ForceLtrOverride : 1; + UINT32 EnableCpm : 1; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism + UINT32 RsvdBits3 : 8; ///< Reserved Bits + /** + The number of milliseconds reference code will wait for link to exit Detect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port initialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful + if device power-up seqence is controlled by BIOS or a specific device requires more time to detect. + In case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + UINT16 Rsvd2; ///< Reserved bytes + UINT32 Rsvd3; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/** + The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers + Revision 1: Init version + Revision 2: Deprecate the PCIE RP enable in post mem. + Revision 3: Added DetectTimeoutMs parameter per port. The common DetectTimeoutMs is obsolete. + Revision 4: Added EnableHotplugSmi parameter per port. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc. + /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// List of coefficients used during equalization (applicable to both software and hardware EQ) + /// + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; + PCH_PCIE_EQ_PARAM Rsvd0[3]; + /// + /// (Test) This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable + or leaving untouched. + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility. + - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage + NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal, or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 21; + /** + @deprecated since revision 3, substituted by per-port timeout parameter + The number of milliseconds reference code will wait for link to exit Detect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port initialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful + if device power-up sequence is controlled by BIOS or a specific device requires more time to detect. + I case of non-common clock enabled the default timeout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + UINT16 Rsvd1; ///< Reserved bytes + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM settings. + This is a pointer points to a 32bit address. And it's only used in PostMem phase. + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + The prototype of this policy is: + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; + **/ + UINT32 PcieDeviceOverrideTablePtr; + +} PCH_PCIE_CONFIG; + +/** + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers + Revision 1: Init version + Add RpEnable in premem phase. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; +} PCH_PCIE_RP_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_PCIE_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h new file mode 100644 index 0000000000..f483987c97 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h @@ -0,0 +1,215 @@ +/** @file + Power Management policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PM_CONFIG_H_ +#define _PM_CONFIG_H_ + +#define PM_CONFIG_REVISION 4 +extern EFI_GUID gPmConfigGuid; + +#pragma pack (push,1) + +/** + This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; 1: Enable. + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 26; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power management settings. + The PowerResetStatusClear field would clear the Power/Reset status bits, please + set the bits if you want PCH Init driver to clear it, if you want to check the + status later then clear the bits. + + Revision 1: + - Initial version. + Revision 2: + - Deprecate CapsuleResetType and the capsule update always uses warmreset cycle. + Revision 3: + - Added SlpS0VmEnable. + Revision 4 + - Deprecate PciePllSsc and moved to PCH_HSIO_PCIE_PREMEM_CONFIG +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy + UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable. + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is PchSlpS350ms. + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is PchSlpS44s. + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is PchSlpSus4s. + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is PchSlpA2s. + UINT32 RsvdBits0 : 12; + /** + This member describes whether or not the LPC ClockRun feature of PCH should + be enabled. 0: Disable; 1: Enable + **/ + UINT32 LpcClockRun : 1; + UINT32 SlpStrchSusUp : 1; ///< 0: Disable; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: Enable. + Enery Report is must have feature. Wihtout Energy Report, the performance report + by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to try to reduce + its power by throttling, then it could try to disable Energy Report to do first debug. + This might be due to energy scaling factors are not correct or the LPM settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + (Test) + When set to true, this bit disallows host reads to PMC XRAM. + BIOS must set this bit (to disable and lock the feature) prior to passing control to OS + 0:Disable, 1:Enable + **/ + UINT32 PmcReadDisable : 1; + /** + @deprecated This determines the type of reset issued during the capsule update process by UpdateCapsule(). + Always Warm reset. + **/ + UINT32 CapsuleResetType : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, 1:Enable + + @warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted. + If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled. + **/ + UINT32 SlpS0Enable : 1; + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable. + /** + Set true to enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. + @note: This will have significant power impact when it's enabled. + If TCO timer is disabled, uCode ACPI timer emulation must be enabled, + and WDAT table must not be exposed to the OS. + 0: Disable, 1: Enable + **/ + UINT32 EnableTcoTimer : 1; + /** + Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. + 0: Disable, 1: Enable + **/ + UINT32 SlpS0VmEnable : 1; + UINT32 RsvdBits1 : 16; + /** + Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + @deprecated since revision 4 + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reserved bytes + +} PCH_PM_CONFIG; + +#pragma pack (pop) + +#endif // _PM_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h new file mode 100644 index 0000000000..d8b9cf6145 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h @@ -0,0 +1,34 @@ +/** @file + Port 61h policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PORT_61_CONFIG_H_ +#define _PORT_61_CONFIG_H_ + +#define PORT_61_CONFIG_REVISION 1 +extern EFI_GUID gPort61ConfigGuid; + +#pragma pack (push,1) + +/** + This structure is used for the emulation feature for Port61h read. The port is trapped + and the SMI handler will toggle bit4 according to the handler's internal state. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< 0: Disable; 1: Enable the emulation + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_PORT61H_SMM_CONFIG; + +#pragma pack (pop) + +#endif // _PORT_61_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h new file mode 100644 index 0000000000..0dc76e0c23 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h @@ -0,0 +1,193 @@ +/** @file + Sata policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SATA_CONFIG_H_ +#define _SATA_CONFIG_H_ + +#define SATA_CONFIG_REVISION 4 +extern EFI_GUID gSataConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +/** + This structure configures the features, property, and capability for each SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: Enable + UINT32 HotPlug : 1; ///< 0: Disable; 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; 1: Enable + UINT32 External : 1; ///< 0: Disable; 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: SSD + UINT32 DevSlp : 1; ///< 0: Disable; 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. Default is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 RaidAlternateId : 1; ///< @deprecated + UINT32 Raid0 : 1; ///< 0: Disable; 1: Enable RAID0 + UINT32 Raid1 : 1; ///< 0: Disable; 1: Enable RAID1 + UINT32 Raid10 : 1; ///< 0: Disable; 1: Enable RAID10 + UINT32 Raid5 : 1; ///< 0: Disable; 1: Enable RAID5 + UINT32 Irrt : 1; ///< 0: Disable; 1: Enable Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0: Disable; 1: Enable OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0: Disable; 1: Enable. Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0: Disable; 1: Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0: Disable; 1: Enable. Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0: Disable; 1: Enable RST Smart Storage caching Bit + UINT32 LegacyOrom : 1; ///< 0: Disable; 1: Enable RST Legacy OROM + /** + This option allows to configure SATA controller device ID while in RAID mode + Choosing Client will allow RST driver loading, RSTe driver will not be able to load + Choosing Alternate will not allow RST inbox driver loading in Windows + Choosing Server will allow RSTe driver loading, RST driver will not load + 0: Client; 1: Alternate; 2: Server + **/ + UINT32 RaidDeviceId : 2; + UINT32 OptaneMemory : 1; ///< 0: Disable; 1: Enable RST Optane(TM) Memory + UINT32 RsvdBits0 : 15; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure describes the details of Intel RST for PCIe Storage remapping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) + The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below: + SKL PCH-LP RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + SKL PCH-H RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/** + The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers. + + Revision 1: + - Initial version. + Revision 2: + - Added LegacyOrom in RST_SATA_RST_CONFIG to force RST Legacy Orom useage + Revision 3 + - Added RaidDeviceId in PCH_SATA_RST_CONFIG to allow choice of RAID device id + Revision 4 + - Added OptaneMemory in PCH_SATA_RST_CONFIG to enable RST optane memory +**/ +typedef struct { + /** + This member specifies the revision of the SATA Configuration structure. + Any backwards compatible changes to this structure will result in an update in the revision number. + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disable; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable SATA Power Optimizer on PCH side. + /** + EsataSpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + Please be noted, this setting could be cleared by HBA reset, which might be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should preserve the + setting before and after initialization. For support it after POST, it's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT32 EsataSpeedLimit : 1; + UINT32 RsvdBits0 : 27; ///< Reserved bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is PchSataModeAhci. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + 0h: PchSataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; +} PCH_SATA_CONFIG; + +#pragma pack (pop) + +#endif // _SATA_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h new file mode 100644 index 0000000000..05a2f5dbfa --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h @@ -0,0 +1,61 @@ +/** @file + Scs policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SCS_CONFIG_H_ +#define _SCS_CONFIG_H_ + +#define SCS_CONFIG_REVISION 1 +extern EFI_GUID gScsConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchScsSdDisabled = 0, + PchScsSdcardMode = 2 +} PCH_SCS_DEV_SD_MODE; + +typedef enum { + DriverStrength33Ohm = 0, + DriverStrength40Ohm, + DriverStrength50Ohm +} PCH_SCS_EMMC_DRIVER_STRENGTH; + +/// +/// The PCH_SCS_CONFIG block describes Storage and Communication Subsystem (SCS) settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC is enabled - 0: Disabled, 1: Enabled. + UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC HS400 Mode if ScsEmmcEnabled - 0: Disabled, 1: Enabled + /** + Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. 0: Disabled, 1: Enabled. + First Boot or CMOS clear, system boot with Default settings, set tuning required. + Subsequent Boots, Get Variable 'Hs400TuningData' + - if failed to get variable, set tuning required + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required. + - if driver strength value changes (ScsEmmcHs400DriverStrength) re-tuning is required. + **/ + UINT32 ScsEmmcHs400TuningRequired : 1; + UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning Data Valid + UINT32 ScsEmmcHs400RxStrobeDll1 : 7; ///< Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode) + UINT32 ScsEmmcHs400TxDataDll : 7; ///< Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode) + UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm + UINT32 ScsSdSwitch : 3; ///< Determine the operating mode of SDHC. Refer to PCH_SCS_DEV_SD_MODE for each value - 0: Disabled, 2: SDCard. + UINT32 RsvdBits : 7; + UINT32 Rsvd0; ///< Reserved bytes +} PCH_SCS_CONFIG; + +#pragma pack (pop) + +#endif // _SCS_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h new file mode 100644 index 0000000000..5caa24310a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h @@ -0,0 +1,56 @@ +/** @file + Serial IO policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SERIAL_IO_CONFIG_H_ +#define _SERIAL_IO_CONFIG_H_ + +#define SERIAL_IO_CONFIG_REVISION 1 +extern EFI_GUID gSerialIoConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers + to Acpi devices or Pci controllers, and also set the interrupt type to Acpi or Pci + through Policy. It also provides to configure the I2c0 and I2c1 voltage + to 1.8v or 3.3v by platform setting. + Please refer to PeiDxeSmmPchSerialIoLib.h for definition of device numbers and enum values for the below fields +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + 0: Disabled; 1: ACPI Mode; 2: PCI Mode; 3: Hidden mode, 4: Legacy UART mode, 5: Skip Init + @note: Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx, + the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0, + the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated + to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options + available for this UART controller on this board, and also override the policy default accordingly. + While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy. + @note: While DevMode is set to 5 (Skip Init), BIOS will not initialize this controller. GPIO and PSF configuration is skipped. + Platform is resonsible for configuring this controller. If platform initializes the Serial IO controller in + Hidden Mode, it MUST follow the predefined BAR address for the controller. + **/ + UINT8 DevMode[PCH_SERIALIO_MAX_CONTROLLERS]; + UINT8 Gpio; ///< 0: Disabled; 1: Enabled. + UINT8 I2cVoltage[PCH_SERIALIO_MAX_I2C_CONTROLLERS]; ///< Selects the IO voltage for I2C controllers. It can be 1.8v or 3.3v. 0: PchSerialIoIs33V; 1: PchSerialIoIs18V. + UINT8 SpiCsPolarity[PCH_SERIALIO_MAX_SPI_CONTROLLERS]; ///< Selects SPI ChipSelect signal polarity, 0=active low. + UINT8 UartHwFlowCtrl[PCH_SERIALIO_MAX_UART_CONTROLLERS]; ///< Enables UART hardware flow control, CTS and RTS lines, 0:disabled, 1:enabled + UINT8 Rsvd0[1]; ///< Bytes reserved for reuse when new fields are added to struct + UINT32 DebugUartNumber : 2; ///< UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2 + UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: diabled, 1: enabled + UINT32 RsvdBits0 : 29; +} PCH_SERIAL_IO_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IO_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h new file mode 100644 index 0000000000..b64579cd92 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h @@ -0,0 +1,48 @@ +/** @file + Serial IRQ policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SERIAL_IRQ_CONFIG_H_ +#define _SERIAL_IRQ_CONFIG_H_ + +#define SERIAL_IRQ_CONFIG_REVISION 1 +extern EFI_GUID gSerialIrqConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; 1: Enable. + UINT32 SirqMode : 2; ///< Serial IRQ Mode Select. Refer to PCH_SIRQ_MODE for each value. 0: quiet mode 1: continuous mode. + UINT32 StartFramePulse : 3; ///< Start Frame Pulse Width. Refer to PCH_START_FRAME_PULSE for each value. Default is PchSfpw4Clk. + UINT32 RsvdBits0 : 26; ///< Reserved bits +} PCH_LPC_SIRQ_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IRQ_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h new file mode 100644 index 0000000000..78ac72aa87 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h @@ -0,0 +1,56 @@ +/** @file + Smbus policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SMBUS_CONFIG_H_ +#define _SMBUS_CONFIG_H_ + +#define SMBUS_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gSmbusPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. +/// +typedef struct { + /** + Revision 1: Init version + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the SMBus controller of PCH should be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable or Enable Smbus dynamic power gating. + /// + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. + /// For security recommendations, SPD write disable bit must be set. + /// + UINT32 SpdWriteDisable : 1; + UINT32 RsvdBits0 : 28; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _SMBUS_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h new file mode 100644 index 0000000000..688fa314cb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h @@ -0,0 +1,38 @@ +/** @file + Spi policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SPI_CONFIG_H_ +#define _SPI_CONFIG_H_ + +#define SPI_CONFIG_REVISION 1 +extern EFI_GUID gSpiConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to SPI. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Force to show SPI controller. + 0: FALSE, 1: TRUE + NOTE: For Windows OS, it MUST BE false. It's optional for other OSs. + **/ + UINT32 ShowSpiController : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_SPI_CONFIG; + +#pragma pack (pop) + +#endif // _SPI_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h new file mode 100644 index 0000000000..8963da6ee7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h @@ -0,0 +1,176 @@ +/** @file + Thermal policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _THERMAL_CONFIG_H_ +#define _THERMAL_CONFIG_H_ + +#define THERMAL_CONFIG_REVISION 1 +extern EFI_GUID gThermalConfigGuid; + +#pragma pack (push,1) + +/** + This structure lists PCH supported throttling register setting for custimization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH + thermal status to the processor which is factored into the processor throttling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width + UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width + UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width + UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width + UINT32 RsvdBits1 : 16; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure lists PCH supported SATA thermal throttling register setting for custimization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLE; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This field reports the status of Thermal Device. When it reports ThermalDevice + is disabled, the PCI configuration space of thermal device will be hidden by + setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST. + **/ + UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, 1: Enabled in PCI mode, 2: Enabled in ACPI mode + UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 29; + /** + This field decides the settings of Thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + THERMAL_THROTTLE_LEVELS TTLevels; + /** + This field decides the settings of DMI throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + DMI_HW_WIDTH_CONTROL DmiHaAWC; + /** + This field decides the settings of Sata thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + SATA_THERMAL_THROTTLE SataTT; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is zero. + - 0x00 is the hottest + - 0x1FF is the lowest temperature + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +#pragma pack (pop) + +#endif // _THERMAL_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h new file mode 100644 index 0000000000..5455c40514 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h @@ -0,0 +1,35 @@ +/** @file + Trace Hub policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _TRACEHUB_CONFIG_H_ +#define _TRACEHUB_CONFIG_H_ + +#define TRACEHUB_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gTraceHubPreMemConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 EnableMode : 2; ///< 0 = Disable 2 = Host Debugger enabled + UINT32 RsvdBits0 : 30; ///< Reserved bits + UINT32 MemReg0Size; ///< Default is 0 (none). + UINT32 MemReg1Size; ///< Default is 0 (none). +} PCH_TRACE_HUB_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _TRACEHUB_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..c2cef0aa43 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,233 @@ +/** @file + USB policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _USB_CONFIG_H_ +#define _USB_CONFIG_H_ + +#define USB_CONFIG_REVISION 2 +extern EFI_GUID gUsbConfigGuid; + +#pragma pack (push,1) + +/// +/// Overcurrent pins, the values match the setting of PCH EDS, please refer to PCH EDS for more details +/// +typedef enum { + PchUsbOverCurrentPin0 = 0, + PchUsbOverCurrentPin1, + PchUsbOverCurrentPin2, + PchUsbOverCurrentPin3, + PchUsbOverCurrentPin4, + PchUsbOverCurrentPin5, + PchUsbOverCurrentPin6, + PchUsbOverCurrentPin7, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinMax +} PCH_USB_OVERCURRENT_PIN; + +/// +/// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace. +/// +enum PCH_USB_PORT_LOCATION{ + PchUsbPortLocationBackPanel = 0, + PchUsbPortLocationFrontPanel, + PchUsbPortLocationDock, + PchUsbPortLocationMiniPciE, + PchUsbPortLocationFlex, + PchUsbPortLocationInternalTopology, + PchUsbPortLocationSkip, + PchUsbPortLocationMax +}; + + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} PCH_USB20_AFE; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the port strength accordingly. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 2.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + PCH_USB20_AFE Afe; ///< USB2 AFE settings + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N of PCH is enabled by platform modules. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 3.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4 + + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) + HSIO_TX_DWORD5[21:16] + Default = 29h (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 6; + + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default = 00h + **/ + UINT32 HsioTxDownscaleAmp : 6; + + UINT32 RsvdBits1 : 18; ///< Reserved bits + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB30_PORT_CONFIG; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 + +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + /** + 0: Disable; 1: Enable SSIC support. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits1 : 31; +} PCH_XHCI_SSIC_PORT; +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT]; +} PCH_SSIC_CONFIG; + +/** + The PCH_XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_XDCI_CONFIG; + + +/** + This member describes the expected configuration of the PCH USB controllers, + Platform modules may need to refer Setup options, schematic, BIOS specification + to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring + the schematic. + + Revision 1: + - Initial version. + Revision 2: + - Added DelayPdoProgramming policy option. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled. + For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing. + 0:Disable , 1: Enable + **/ + UINT32 DisableComplianceMode : 1; + /** + This policy option if set will move Port Disable Override register programming to ReadyToBoot event during DXE phase. + If not enabled it will program Port Disable Override register in PEI phase during PCH initialization + 0: Program in PEI phase , 1: Program in DXE phase + **/ + UINT32 DelayPdoProgramming : 1; + UINT32 RsvdBits0 : 30; ///< Reserved bits + /** + These members describe whether the USB2 Port N of PCH is enabled by platform modules. + Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH. + Dock is only available for Mobile LPT. + **/ + PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by platform modules. + **/ + PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be enabled. + **/ + PCH_XDCI_CONFIG XdciConfig; + /** + These members describe some settings which are related to the SSIC ports. + **/ + PCH_SSIC_CONFIG SsicConfig; +} PCH_USB_CONFIG; + +#pragma pack (pop) + +#endif // _USB_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h new file mode 100644 index 0000000000..610c1092fb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h @@ -0,0 +1,38 @@ +/** @file + WatchDog policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _WATCH_DOG_CONFIG_H_ +#define _WATCH_DOG_CONFIG_H_ + +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gWatchDogPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable. + UINT32 RsvdBits : 31; +} PCH_WDT_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _WATCH_DOG_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioConfig.h new file mode 100644 index 0000000000..8b26020da2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioConfig.h @@ -0,0 +1,338 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enabled. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 17; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault = 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pad. + If GPIO is set to one of NativeX modes then following settings are not applicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chosen ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi = 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver. + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors) + **/ + GpioHostOwnGpio = 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input enabled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). + This type of GPIO Driver interrupt doesn't have any additional routing setting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + + + GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified + /// + /// @{ + /// @deprecated settings. Maintained only for compatibility. + /// + GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood") + GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset") + GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" ) + GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" ) + /// + /// @} + /// + /// + /// New GPIO reset configuration options + /// + /** + Resume Reset (RSMRST) + GPP: PadRstCfg = 00b = "Powergood" + GPD: PadRstCfg = 11b = "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset = 0x01, + /** + Host Deep Reset + PadRstCfg = 01b = "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset = 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg = 10b = "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset = 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg = 00b = "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset = 0x07 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Set GPIO termination and Pad Tolerance (applicable only for some pads) + Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. +**/ +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative = 0x1F, + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value +#define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioLockPadConfig and GpioLockOutputState can be OR'ed. + Lock settings reset is in Powergood domain. Care must be taken when using this setting + as fields it locks may be reset by a different signal and can be controllable + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides + functions which allow to unlock a GPIO pad. +**/ +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensions + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and native usage). + The override takes place at the internal pad state directly from buffer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklH.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..5230656791 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklH.h @@ -0,0 +1,248 @@ +/** @file + GPIO pins for SKL-PCH-H, + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// SKL H GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPD 0x0109 + +/// +/// SKL H GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPD0 0x01090000 +#define GPIO_SKL_H_GPD1 0x01090001 +#define GPIO_SKL_H_GPD2 0x01090002 +#define GPIO_SKL_H_GPD3 0x01090003 +#define GPIO_SKL_H_GPD4 0x01090004 +#define GPIO_SKL_H_GPD5 0x01090005 +#define GPIO_SKL_H_GPD6 0x01090006 +#define GPIO_SKL_H_GPD7 0x01090007 +#define GPIO_SKL_H_GPD8 0x01090008 +#define GPIO_SKL_H_GPD9 0x01090009 +#define GPIO_SKL_H_GPD10 0x0109000A +#define GPIO_SKL_H_GPD11 0x0109000B + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklLp.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklLp.h new file mode 100644 index 0000000000..999b417011 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/GpioPinsSklLp.h @@ -0,0 +1,207 @@ +/** @file + GPIO pins for SKL-PCH-LP, + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GPIO_PINS_SKL_LP_H_ +#define _GPIO_PINS_SKL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// SKL LP GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_LP_GROUP_GPP_A 0x0200 +#define GPIO_SKL_LP_GROUP_GPP_B 0x0201 +#define GPIO_SKL_LP_GROUP_GPP_C 0x0202 +#define GPIO_SKL_LP_GROUP_GPP_D 0x0203 +#define GPIO_SKL_LP_GROUP_GPP_E 0x0204 +#define GPIO_SKL_LP_GROUP_GPP_F 0x0205 +#define GPIO_SKL_LP_GROUP_GPP_G 0x0206 +#define GPIO_SKL_LP_GROUP_GPD 0x0207 + +/// +/// SKL LP GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h new file mode 100644 index 0000000000..5362beeea3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h @@ -0,0 +1,707 @@ +/** @file + Header file for GpioLib. + All function in this library is available for PEI, DXE, and SMM + + @note: When GPIO pads are owned by ME Firmware, BIOS/host should not + attempt to access these GPIO Pads registers, registers value + returned in this case will be 0xFF. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. + Separate fields could be set to hardware default if it does not matter, except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those include: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group + For group which has less then 32 pads per group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +/// +/// Possible values of Pad Ownership +/// If Pad is not under Host ownership then GPIO registers +/// are not accessible by host (e.g. BIOS) and reading them +/// will return 0xFFs. +/// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one group. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + Refer to BWG and EDS for GPIO GPE information. + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + Refer to BWG and EDS for GPIO GPE information. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Purpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ); + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h new file mode 100644 index 0000000000..5f2c57fd34 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h @@ -0,0 +1,225 @@ +/** @file + Header file for GpioLib for native and Si specific usage. + All function in this library is available for PEI, DXE, and SMM, + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GPIO_NATIVE_LIB_H_ +#define _GPIO_NATIVE_LIB_H_ + +#include + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ); + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT8 +GpioGetNumberOfGroups ( + VOID + ); +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ); + +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ); + +/** + This procedure will get group + + @param[in] GpioPad Gpio Pad + + @retval Value Group +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from GpioPad + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ); + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ); + +/** + This procedure will return GpioPad from GroupIndex and PadNumber + + @param[in] GroupIndex GPIO GroupIndex + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupIndexAndPadNumber ( + IN UINT32 GroupIndex, + IN UINT32 PadNumber + ); + +/** + This function sets SerialIo I2C controller pins into native mode + + @param[in] SerialIoI2cControllerNumber I2C controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2cPinsIntoNativeMode ( + IN UINT32 SerialIoI2cControllerNumber + ); + +/** + This function sets SerialIo I2C controller pins tolerance + + @param[in] SerialIoI2CControllerNumber I2C controller + @param[in] Pad1v8Tolerance TRUE: Enable 1v8 Pad tolerance + FALSE: Disable 1v8 Pad tolerance + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2CPinsTolerance ( + IN UINT32 SerialIoI2CControllerNumber, + IN BOOLEAN Pad1v8Tolerance + ); + +/** + This function sets SerialIo UART controller pins into native mode + + @param[in] SerialIoI2CControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoUartPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl + ); + +/** + This function sets SerialIo SPI controller pins into native mode + + @param[in] SerialIoI2CControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoSpiPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber + ); + +/** + This function checks if GPIO pin for SATA reset port is in GPIO MODE + + @param[in] SataPort SATA port number + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsSataResetPortInGpioMode ( + IN UINTN SataPort + ); + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad + ); + +#endif // _GPIO_NATIVE_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h new file mode 100644 index 0000000000..9f5da64dff --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h @@ -0,0 +1,37 @@ +/** @file + Header file for OC WDT Library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _OC_WDT_LIB_H_ +#define _OC_WDT_LIB_H_ + +/** + Check for unexpected reset. + If there was an unexpected reset, enforces WDT expiration. +**/ +VOID +OcWdtResetCheck ( + VOID + ); + +/** + This function install WDT PPI + + @retval EFI_STATUS Results of the installation of the WDT PPI +**/ +EFI_STATUS +EFIAPI +OcWdtInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h new file mode 100644 index 0000000000..30ad2713b5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h @@ -0,0 +1,345 @@ +/** @file + Header file for PchCycleDecodingLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_CYCLE_DECODING_LIB_H_ +#define _PCH_CYCLE_DECODING_LIB_H_ + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is IO space, so must not exceed 0xFFFF. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before changing base address. + 2. program PMC PCI offset 40h [15:2] to ACPI base address. + 3. set PMC PCI offset 44h [7] to enable ACPI base address. + 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F, PMC PCI Offset 40h bit[15:2], 1]. + 5. Program "ACPI Base Destination ID" PCR[DMI] + 27B8h[31:0] to [0x23A0]. + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH ACPI base address. + + @param[out] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + OUT UINT16 *Address + ); + +/** + Set PCH PWRM base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before changing PWRM base address. + 2. program PMC PCI offset 48h [31:16] to PM base address. + 3. set PMC PCI offset 44h [8] to enable PWRM base address. + 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the PWRMBASE to be 64KB aligned. + program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the memory allocated to PWRMBASE to be 64KB in size. + 5. program "PM Base Control" PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0]. + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ); + +/** + Get PCH PWRM base address. + + @param[out] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + OUT UINT32 *Address + ); + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseGet ( + OUT UINT16 *Address + ); + +/// +/// structure of LPC general IO range register +/// It contains base address, address mask, and enable status. +/// +typedef struct { + UINT32 BaseAddr :16; + UINT32 Length :15; + UINT32 Enable : 1; +} PCH_LPC_GEN_IO_RANGE; + +#define PCH_LPC_GEN_IO_RANGE_MAX 4 +/// +/// structure of LPC general IO range register list +/// It lists all LPC general IO ran registers supported by PCH. +/// +typedef struct { + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX]; +} PCH_LPC_GEN_IO_RANGE_LIST; + +/** + Set PCH LPC generic IO range. + For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length aligned. + This function basically checks the address and length, which should not overlap with all other generic ranges. + If no more generic range register available, it returns out of resource error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + The IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be skipped except 0x80-0x8F. + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ); + +/** + Get PCH LPC generic IO range list. + This function returns a list of base address, length, and enable for all LPC generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC generic IO range register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + ); + +/** + Set PCH LPC memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first before changing base address. + 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + ); + +/** + Get PCH LPC memory range decoding address. + + @param[out] Address Address of LPC memory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + OUT UINT32 *Address + ); + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable. + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC IO enable decoding. + Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ); + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that + the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12]) + before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default + IO range values. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO. + 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ); + +/** + Get IO APIC regsiters base address. + It returns IO APIC INDEX, DATA, and EOI regsiter address once the parameter is not NULL. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter address + @param[out] IoApicData Buffer of IO APIC DATA regsiter address + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OPTIONAL OUT UINT32 *IoApicIndex, + OPTIONAL OUT UINT32 *IoApicData + ); + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ); + +#endif // _PCH_CYCLE_DECODING_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h new file mode 100644 index 0000000000..2096645375 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h @@ -0,0 +1,102 @@ +/** @file + Header file for PchEspiLib. + All function in this library is available for PEI, DXE, and SMM, + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_ESPI_LIB_H_ +#define _PCH_ESPI_LIB_H_ + +/** + Is eSPI enabled in strap. + + @retval TRUE Espi is enabled in strap + @retval FALSE Espi is disabled in strap +**/ +BOOLEAN +IsEspiEnabled ( + VOID + ); + +/** + Get configuration from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp + @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation +**/ +EFI_STATUS +PchEspiSlaveGetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + OUT UINT32 *OutData + ); + +/** + Set eSPI slave configuration + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[in] InData Configuration data to write + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp + @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7FF has been locked + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation +**/ +EFI_STATUS +PchEspiSlaveSetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + IN UINT32 InData + ); + +/** + Get status from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation +**/ +EFI_STATUS +PchEspiSlaveGetStatus ( + IN UINT32 SlaveId, + OUT UINT16 *OutData + ); + +/** + eSPI slave in-band reset + + @param[in] SlaveId eSPI slave ID + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation +**/ +EFI_STATUS +PchEspiSlaveInBandReset ( + IN UINT32 SlaveId + ); + +#endif // _PEI_DXE_SMM_PCH_ESPI_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h new file mode 100644 index 0000000000..5461286634 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h @@ -0,0 +1,64 @@ +/** @file + Header file for PchGbeLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_GBE_LIB_H_ +#define _PCH_GBE_LIB_H_ + +/** + Check whether GbE region is valid + Check SPI region directly since GBE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ); + +/** + Returns GbE over PCIe port number based on a soft strap. + + @return Root port number (1-based) + @retval 0 GbE over PCIe disabled +**/ +UINT32 +PchGetGbePortNumber ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @deprecated Use PchIsGbePresent instead. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbeAvailable ( + VOID + ); + +#endif // _PCH_GBE_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h new file mode 100644 index 0000000000..65076800a9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h @@ -0,0 +1,114 @@ +/** @file + Header file for PchHsioLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_HSIO_LIB_H_ +#define _PCH_HSIO_LIB_H_ + +/** + Represents HSIO lane +**/ +typedef struct { + UINT8 Index; ///< Lane index + UINT8 Pid; ///< Sideband ID + UINT16 Base; ///< Sideband base address +} HSIO_LANE; + +/** + The function returns the Port Id and lane owner for the specified lane + + @param[in] PhyMode Phymode that needs to be checked + @param[out] Pid Common Lane End Point ID + @param[out] LaneOwner Lane Owner + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid lane number +**/ +EFI_STATUS +EFIAPI +PchGetLaneInfo ( + IN UINT32 LaneNum, + OUT UINT8 *PortId, + OUT UINT8 *LaneOwner + ); + +/** + Get HSIO lane representation needed to perform any operation on the lane. + + @param[in] LaneIndex Number of the HSIO lane + @param[out] HsioLane HSIO lane representation +**/ +VOID +HsioGetLane ( + IN UINT8 LaneIndex, + OUT HSIO_LANE *HsioLane + ); + +/** + Determine the lane number of a specified port + + @param[in] PcieLaneIndex PCIE Root Port Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetPcieLaneNum ( + UINT32 PcieLaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[in] SataLaneIndex Sata Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetSataLaneNum ( + UINT32 SataLaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[in] Usb3LaneIndex USB3 Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetUsb3LaneNum ( + UINT32 Usb3LaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[out] LaneNum GBE Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetGbeLaneNum ( + UINT8 *LaneNum + ); + +#endif // _PCH_HSIO_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..5902b92f18 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,260 @@ +/** @file + Header file for PchInfoLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include + +typedef enum { + PchH = 1, + PchLp, + PchUnknownSeries +} PCH_SERIES; + +typedef enum { + SklPch = 1, + KblPch, + PchUnknownGeneration +} PCH_GENERATION; + +typedef enum { + RstUnsupported = 0, + RstPremium, + RstOptane, + RstMaxMode +} RST_MODE; + +typedef enum { + PchMobileSku = 0, + PchDesktopSku, + PchServerSku, + PchUnknownSku, + PchMaxSku +} PCH_SKU_TYPE; + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +EFIAPI +PchStepping ( + VOID + ); + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ); + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ); + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +EFIAPI +GetPchGeneration ( + VOID + ); + +/** + Get PCH SKU type + + @retval PCH_SKU_TYPE Type of PCH SKU +**/ +PCH_SKU_TYPE +GetPchSkuType ( + VOID + ); + +/** + Get Lpc Did + + @retval UINT16 Lpc Did +**/ +UINT16 +EFIAPI +GetLpcDid ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ); + +/** + Get Pch Maximum Sata Port Number + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID + ); + +/** + Get Pch Usb Maximum Physical Port Number + + @retval Pch Usb Maximum Physical Port Number +**/ +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID + ); + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb2PortNum ( + VOID + ); + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID + ); + +/** + Get PCH stepping ASCII string + The return string is zero terminated. + + @param [in] PchStep Pch stepping + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + IN PCH_STEPPING PchStep, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH series ASCII string + The return string is zero terminated. + + @param [in] PchSeries Pch series + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSeriesStr ( + IN PCH_SERIES PchSeries, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @param [in] LpcDid LPC device id + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSkuStr ( + IN UINT16 LpcDid, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get RST mode supported by the silicon + + @retval RST_MODE RST mode supported by silicon +**/ +RST_MODE +EFIAPI +GetSupportedRstMode ( + VOID + ); + +/** + Check if current SKU supports Optane mode + + @retval TRUE This SKU supports Optane mode + @retval FALSE This SKU doesn't support Optane mode +**/ +BOOLEAN +EFIAPI +IsOptaneModeSupported ( + VOID + ); + +/** + Check if current SKU supports RAID feature + + @retval TRUE This SKU supports RAID + @retval FALSE This SKU doesn't support RAID +**/ +BOOLEAN +EFIAPI +IsPchRaidSupported ( + VOID + ); +#endif // _PCH_INFO_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h new file mode 100644 index 0000000000..8083ac4efd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h @@ -0,0 +1,160 @@ +/** @file + Header file for PchP2sbLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_P2SB_LIB_H_ +#define _PCH_P2SB_LIB_H_ + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet32 ( + IN UINTN Offset, + OUT UINT32 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet16 ( + IN UINTN Offset, + OUT UINT16 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 1byte. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet8 ( + IN UINTN Offset, + OUT UINT8 *OutData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet32 ( + IN UINTN Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet16 ( + IN UINTN Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 1bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet8 ( + IN UINTN Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controller. + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ); + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not after. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controller. + @param[out] OrgStatus Original P2SB hidding/unhidden status + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ); + +#endif // _PCH_P2SB_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..d5084772dd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h @@ -0,0 +1,110 @@ +/** @file + Header file for PchPcieRpLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PCIERP_LIB_H_ +#define _PCH_PCIERP_LIB_H_ + +#define RST_PCIE_STORAGE_CR_1 0 +#define RST_PCIE_STORAGE_CR_2 1 +#define RST_PCIE_STORAGE_CR_3 2 +#define RST_PCIE_STORAGE_CR_INVALID 99 + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCH_PCIE_CONTROLLER_INFO; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Root Port physical Number by Pch Pcie Root Port Device and Function Number + + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding physical Root Port index (0-based) + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpNumber ( + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ); + +/** + Gets base address of PCIe root port. + + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINTN +PchPcieBase ( + IN UINT32 RpIndex + ); + +/** + Determines whether L0s is supported on current stepping. + + @return TRUE if L0s is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieL0sSupported ( + VOID + ); + +/** + Some early SKL PCH steppings require Native ASPM to be disabled due to hardware issues: + - RxL0s exit causes recovery + - Disabling PCIe L0s capability disables L1 + Use this function to determine affected steppings. + + @return TRUE if Native ASPM is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieNativeAspmSupported ( + VOID + ); + +/** + Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type + + @param[in] RootPortNum Root Port Number + + @retval UINT32 The RST PCIe Storage Cycle Router Number +**/ +UINT32 +RstGetCycleRouterNumber ( + IN UINT32 RootPortNum + ); + +#endif // _PCH_PCIERP_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..149168993f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h @@ -0,0 +1,196 @@ +/** @file + Header file for PchPcrLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +#endif // _PCH_PCR_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h new file mode 100644 index 0000000000..61a955802a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h @@ -0,0 +1,50 @@ +/** @file + Header file for PchPmcLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PMC_LIB_H_ +#define _PCH_PMC_LIB_H_ + +typedef enum { + WarmBoot = 1, + ColdBoot, + PwrFlr, + PwrFlrSys, + PwrFlrPch, + PchPmStatusMax +} PCH_PM_STATUS; + +/** + Query PCH to determine the Pm Status + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Status TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ); + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ); + +#endif // _PCH_PMC_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h new file mode 100644 index 0000000000..f4e3659960 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h @@ -0,0 +1,113 @@ +/** @file + Prototype of the PeiPchPolicy library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PEI_PCH_POLICY_LIB_H_ +#define _PEI_PCH_POLICY_LIB_H_ + +#include + +/** + Print whole PCH_PREMEM_POLICY_PPI and serial out. + + @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance +**/ +VOID +EFIAPI +PchPreMemPrintPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + Print whole SI_POLICY_PPI and serial out. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +PchPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get PCH PREMEM config block table total size. + + @retval Size of PCH PREMEM config block table +**/ +UINT16 +EFIAPI +PchGetPreMemConfigBlockTotalSize ( + VOID + ); + +/** + Get PCH config block table total size. + + @retval Size of PCH config block table +**/ +UINT16 +EFIAPI +PchGetConfigBlockTotalSize ( + VOID + ); + +/** + PchAddPreMemConfigBlocks add all PCH config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/** + PchAddConfigBlocks add all PCH config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/* + Apply sample board PCH specific default settings + + @param[in] SiPreMemPolicy The pointer to SI PREMEM Policy PPI instance +*/ +VOID +EFIAPI +PchLoadSamplePreMemPolicy ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ); + +/* + Apply sample board PCH specific default settings + + @param[in] SiPolicyPpi The pointer to SI Policy PPI instance +*/ +VOID +EFIAPI +PchLoadSamplePolicy ( + IN SI_POLICY_PPI *SiPolicy + ); + +#endif // _PEI_PCH_POLICY_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h new file mode 100644 index 0000000000..4a2924f8f6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h @@ -0,0 +1,170 @@ +/** @file + Header file for PchPsfLib. + This is helper library of RC for PSF register programming. + It's not expected to be used in platform code. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PSF_LIB_H_ +#define _PCH_PSF_LIB_H_ + +#include + +/** + This procedure will enable SerialIO device BAR1 at PSF level + + @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2) + + @retval None +**/ +VOID +PsfEnableSerialIoDeviceBar1 ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice + ); + +/** + This procedure will disable SerialIO device BAR1 at PSF level + + @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2) + + @retval None +**/ +VOID +PsfDisableSerialIoDeviceBar1 ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice + ); + +/** + This procedure will disable SerailIO device at PSF level + + @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2) + + @retval None +**/ +VOID +PsfDisableSerialIoDevice ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice + ); + +/** + This procedure will hide SerialIo device PciCfgSpace at PSF level + + @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2) + + @retval None +**/ +VOID +PsfHideSerialIoDevice ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice + ); + +/** + This procedure will reveal SerialIo device PciCfgSpace at PSF level + + @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2) + + @retval None +**/ +VOID +PsfRevealSerialIoDevice ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice + ); + +/** + This procedure will set BARx value for TraceHub ACPI device at PSF level + + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1) + @param[in] BarValue 32bit BAR value + + @retval None +**/ +VOID +PsfSetTraceHubAcpiDeviceBarValue ( + IN UINT8 BarNum, + IN UINT32 BarValue + ); + +/** + This procedure will enable MSE for TraceHub ACPI device at PSF level + + @param[in] None + + @retval None +**/ +VOID +PsfEnableTraceHubAcpiDeviceMemorySpace ( + VOID + ); + +/** + Enable HECI device at PSF level + + @param[in] HeciDevice HECIx Device (HECI1-3) + + @retval None +**/ +VOID +PsfEnableHeciDevice ( + IN UINT8 HeciDevice + ); + +/** + Disable HECI device at PSF level + + @param[in] HeciDevice HECIx Device (HECI1-3) + + @retval None +**/ +VOID +PsfDisableHeciDevice ( + IN UINT8 HeciDevice + ); + +/** + Enable IDER device at PSF level + + @retval None +**/ +VOID +PsfEnableIderDevice ( + VOID + ); + +/** + Disable IDER device at PSF level + + @retval None +**/ +VOID +PsfDisableIderDevice ( + VOID + ); + +/** + Enable SOL device at PSF level + + @retval None +**/ +VOID +PsfEnableSolDevice ( + VOID + ); + +/** + Disable SOL device at PSF level + + @retval None +**/ +VOID +PsfDisableSolDevice ( + VOID + ); +#endif // _PCH_PSF_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h new file mode 100644 index 0000000000..448cd21f50 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h @@ -0,0 +1,30 @@ +/** @file + Header file for PCH RESET Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_RESET_LIB_H_ +#define _PCH_RESET_LIB_H_ + + +/** + Initialize PCH Reset APIs + + @retval EFI_SUCCESS APIs are installed successfully + @retval EFI_OUT_OF_RESOURCES Can't allocate pool +**/ +EFI_STATUS +EFIAPI +PchInitializeReset ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h new file mode 100644 index 0000000000..87d3318260 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h @@ -0,0 +1,162 @@ +/** @file + Header file for PchSbiAccessLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SBI_ACCESS_LIB_H_ +#define _PCH_SBI_ACCESS_LIB_H_ + +/** + PCH SBI Register structure +**/ +typedef struct { + UINT32 SbiAddr; + UINT32 SbiExtAddr; + UINT32 SbiData; + UINT16 SbiStat; + UINT16 SbiRid; +} PCH_SBI_REGISTER_STRUCT; + +/** + PCH SBI opcode definitions +**/ +typedef enum { + MemoryRead = 0x0, + MemoryWrite = 0x1, + PciConfigRead = 0x4, + PciConfigWrite = 0x5, + PrivateControlRead = 0x6, + PrivateControlWrite = 0x7, + GpioLockUnlock = 0x13 +} PCH_SBI_OPCODE; + +/** + PCH SBI response status definitions +**/ +typedef enum { + SBI_SUCCESSFUL = 0, + SBI_UNSUCCESSFUL = 1, + SBI_POWERDOWN = 2, + SBI_MIXED = 3, + SBI_INVALID_RESPONSE +} PCH_SBI_RESPONSE; + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +#endif // _PCH_SBI_ACCESS_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h new file mode 100644 index 0000000000..4ee5a9713e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h @@ -0,0 +1,219 @@ +/** @file + Header file for PCH Serial IO Lib implementation. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SERIAL_IO_LIB_H_ +#define _PCH_SERIAL_IO_LIB_H_ + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSpi0, + PchSerialIoIndexSpi1, + PchSerialIoIndexUart0, + PchSerialIoIndexUart1, + PchSerialIoIndexUart2, + PchSerialIoIndexMax +} PCH_SERIAL_IO_CONTROLLER; + +typedef enum { + PchSerialIoDisabled, + PchSerialIoAcpi, + PchSerialIoPci, + PchSerialIoAcpiHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +} PCH_SERIAL_IO_MODE; + +enum PCH_LP_SERIAL_IO_VOLTAGE_SEL { + PchSerialIoIs33V = 0, + PchSerialIoIs18V +}; +enum PCH_LP_SERIAL_IO_CS_POLARITY { + PchSerialIoCsActiveLow = 0, + PchSerialIoCsActiveHigh = 1 +}; +enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL { + PchSerialIoHwFlowCtrlDisabled = 0, + PchSerialIoHwFlowControlEnabled = 1 +}; + +#define SERIALIO_HID_LENGTH 8 // including null terminator +#define SERIALIO_UID_LENGTH 1 +#define SERIALIO_CID_LENGTH 1 +#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH + +/** + Returns index of the last i2c controller + + @param[in] Number Number of SerialIo controller + + @retval Index of I2C controller +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + VOID + ); + +/** + Returns string with AcpiHID assigned to selected SerialIo controller + + @param[in] Number Number of SerialIo controller + + @retval pointer to 8-byte string +**/ +CHAR8* +GetSerialIoAcpiHID ( + IN PCH_SERIAL_IO_CONTROLLER Number + ); + +/** + Checks if Device with given PciDeviceId is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Number is not updated + + @param[in] PciDevId Device ID + @param[out] Number Number of SerialIo controller + + @retval TRUE Yes it is a SerialIo controller + @retval FALSE No it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoPciDevId ( + IN UINT16 PciDevId, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Checks if Device with given AcpiHID string is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Number is not updated + + @param[in] AcpiHid String + @param[out] Number Number of SerialIo controller + + @retval TRUE yes it is a SerialIo controller + @retval FALSE no it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoAcpiHid ( + IN CHAR8 *AcpiHid, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Configures Serial IO Controller + + @param[in] Controller + @param[in] DeviceMode + + @retval None +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode + ); + +/** + Initializes GPIO pins used by SerialIo I2C devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] I2cVoltage + + @retval None +**/ +VOID +SerialIoI2cGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 I2cVoltage + ); + +/** + Initializes GPIO pins used by SerialIo SPI devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] SpiCsPolarity + + @retval None +**/ +VOID +SerialIoSpiGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 SpiCsPolarity + ); + +/** + Initializes GPIO pins used by SerialIo devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] HardwareFlowControl + + @retval None +**/ +VOID +SerialIoUartGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN HardwareFlowControl + ); + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2 + + @retval SerialIo device number +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2 + + @retval SerialIo funciton number +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work. + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + @param[in] BarNumber 0=BAR0, 1=BAR1 + + @retval SerialIo Bar value +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ); + + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h new file mode 100644 index 0000000000..66c5945a7b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h @@ -0,0 +1,98 @@ +/** @file + Header file for PCH Serial IO UART Lib implementation. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SERIAL_IO_UART_LIB_H_ +#define _PCH_SERIAL_IO_UART_LIB_H_ + +/** + Initialize selected SerialIo UART. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] FifoEnable When TRUE, enables 64-byte FIFOs. + @param[in] BaudRate Baud rate. + @param[in] LineControl Data length, parity, stop bits. + @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data. +**/ +VOID +EFIAPI +PchSerialIoUartInit ( + IN UINT8 UartNumber, + IN BOOLEAN FifoEnable, + IN UINT32 BaudRate, + IN UINT8 LineControl, + IN BOOLEAN HardwareFlowControl + ); + + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval Actual number of bytes writed to serial device. +**/ +UINTN +EFIAPI +PchSerialIoUartOut ( + IN UINT8 UartNumber, + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +); + +/* + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[out] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, function returns as soon as no new characters are available. + + @retval Actual number of bytes raed from serial device. + +**/ +UINTN +EFIAPI +PchSerialIoUartIn ( + IN UINT8 UartNumber, + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes, + IN BOOLEAN WaitUntilBufferFull +); + +/** + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartPoll ( + IN UINT8 UartNumber + ); + + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h new file mode 100644 index 0000000000..cdeeae5e6d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h @@ -0,0 +1,28 @@ +/** @file + Header file for SMM Control PEI Library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SMM_CONTROL_LIB_H_ +#define _PCH_SMM_CONTROL_LIB_H_ + +/** + This function install PEI SMM Control PPI + + @retval EFI_STATUS Results of the installation of the SMM Control PPI +**/ +EFI_STATUS +EFIAPI +PchSmmControlInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h new file mode 100644 index 0000000000..f89e42a546 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h @@ -0,0 +1,113 @@ +/** @file + Library that contains common parts of WdtPei and WdtDxe. Not a standalone module. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_WDT_COMMON_LIB_H_ +#define _PCH_WDT_COMMON_LIB_H_ + +extern UINT8 mAllowExpectedReset; + +/** + Reads LPC bridge to get Watchdog Timer address + + + @retval UINT32 Watchdog's address +**/ +UINT32 +WdtGetAddress ( + VOID + ); + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which + causes the next reset to be treated as watchdog expiration - unless AllowKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +EFI_STATUS +EFIAPI +WdtReloadAndStart ( + IN UINT32 TimeoutValue + ); + +/** + Disables WDT timer. + + +**/ +VOID +EFIAPI +WdtDisable ( + VOID + ); + +/** + Returns WDT failure status. + + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +UINT8 +EFIAPI +WdtCheckStatus ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a failure. + This function allows platform to perform expected reboots with WDT running, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, ReloadAndStart() + must not be called. + + +**/ +VOID +EFIAPI +WdtAllowKnownReset ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application + + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +UINT8 +EFIAPI +IsWdtRequired ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +UINT8 +EFIAPI +IsWdtEnabled ( + VOID + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h new file mode 100644 index 0000000000..ba9586a7a2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h @@ -0,0 +1,27 @@ +/** @file + Header file for SEC PCH Lib. + All function in this library is available for SEC + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SEC_PCH_LIB_H_ +#define _SEC_PCH_LIB_H_ + +/** + This function do the PCH cycle decoding initialization. +**/ +VOID +EFIAPI +EarlyCycleDecoding ( + VOID + ); + +#endif // _SEC_PCH_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h new file mode 100644 index 0000000000..12dfaeb440 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h @@ -0,0 +1,104 @@ +/** @file + The header file includes the common header files, defines + internal structure and functions used by SpiFlashCommonLib. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SPI_FLASH_COMMON_LIB_H__ +#define __SPI_FLASH_COMMON_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ); + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the write. + @param[in,out] NumBytes On input, the number of bytes to write. On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block to be erased. + This library assume that caller garantee that the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h new file mode 100644 index 0000000000..23cb544d67 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h @@ -0,0 +1,49 @@ +/** @file + Header file for TraceHub Init Lib. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _TRACE_HUB_INIT_LIB_H_ +#define _TRACE_HUB_INIT_LIB_H_ + +#include +#include + +/// +/// The PCH_TRACE_HUB_ENABLE_MODE describes the desired TraceHub mode of operation +/// +typedef enum { + TraceHubModeDisabled = 0, ///< Pch TraceHub Disabled + TraceHubModeHostDebugger = 2, ///< Pch TraceHub External Debugger Present + TraceHubModeMax +} TRACE_HUB_ENABLE_MODE; + +/** + This function performs basic initialization for TraceHub + This routine will consume address range 0xFE0C0000 - 0xFE3FFFFF for BARs usage. + Although controller allows access to a 64bit address resource, PEI phase is a 32bit env, + addresses greater than 4G is not allowed by CPU address space. + So, the addresses must be limited to below 4G and UBARs should be set to 0. + If this routine is called by platform code, it is expected EnableMode is passed in as PchTraceHubModeDisabled, + relying on the Intel TH debugger to enable it through the "cratchpad0 bit [24]". + By this practice, it gives the validation team the capability to use single debug BIOS + to validate the early trace functionality and code path that enable/disable Intel TH using BIOS policy. + + @param[in] EnableMode Trace Hub Enable Mode +**/ +VOID +TraceHubInitialize ( + IN UINT8 EnableMode + ); + +#endif // _TRACE_HUB_INIT_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchAccess.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchAccess.h new file mode 100644 index 0000000000..2c457e3a1e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchAccess.h @@ -0,0 +1,71 @@ +/** @file + Macros that simplify accessing PCH devices's PCI registers. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + + +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsystem ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include "Register/PchRegsThermal.h" +#include "Register/PchRegsUsb.h" +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsSerialIo.h" +#include "Register/PchRegsCam.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsScs.h" +#include "Register/PchRegsIsh.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsPsf.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" + +#endif + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchLimits.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchLimits.h new file mode 100644 index 0000000000..905a4778ce --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchLimits.h @@ -0,0 +1,101 @@ +/** @file + Build time limits of PCH resources. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS KBL_PCH_H_PCIE_MAX_ROOT_PORTS +#define SKL_PCH_H_PCIE_MAX_ROOT_PORTS 20 +#define KBL_PCH_H_PCIE_MAX_ROOT_PORTS 24 +#define PCH_LP_PCIE_MAX_ROOT_PORTS 12 + +#define PCH_MAX_PCIE_CONTROLLERS KBL_PCH_H_PCIE_MAX_CONTROLLERS +#define PCH_PCIE_CONTROLLER_PORTS 4u +#define SKL_PCH_H_PCIE_MAX_CONTROLLERS (SKL_PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) +#define KBL_PCH_H_PCIE_MAX_CONTROLLERS (KBL_PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) +#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) + +// +// PCIe clocks limits +// +#define PCH_LP_PCIE_MAX_CLK_REQ 6 +#define PCH_H_PCIE_MAX_CLK_REQ 16 + +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS +#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sata ports in SKL PCH H +#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sata ports in SKL PCH LP +#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS + +#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. +#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. + +#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lanes + Including two ports reserved for USBr +#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lanes + Including two ports reserved for USBr + +#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS + +#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed lanes +#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes + +#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in SKL PCH-LP and SKL PCH-H + +// +// SerialIo limits +// +#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo controllers, this includes I2C, SPI and UART +#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers +#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers for PCH-LP +#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I2C controllers for PCH-H +#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo SPI controllers +#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo UART controllers + +// +// ISH limits +// +#define PCH_ISH_MAX_GP_PINS 8 +#define PCH_ISH_MAX_UART_CONTROLLERS 2 +#define PCH_ISH_MAX_I2C_CONTROLLERS 3 +#define PCH_ISH_MAX_SPI_CONTROLLERS 1 + +// +// SCS limits +// +#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and Communication Subsystem controllers, this includes eMMC, SDIO, SDCARD + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +// +// Number of eSPI slaves +// +#define PCH_ESPI_MAX_SLAVE_ID 2 +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h new file mode 100644 index 0000000000..664f66f296 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h @@ -0,0 +1,54 @@ +/** @file + + Definitions required to create PcieStorageInfoHob + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PCIE_STORAGE_DETECT_HOB_ +#define _PCH_PCIE_STORAGE_DETECT_HOB_ + +#include "PchLimits.h" + +#define PCIE_STORAGE_INFO_HOB_REVISION 1 + +extern EFI_GUID gPchPcieStorageDetectHobGuid; + +typedef enum { + RstLinkWidthX1 = 1, + RstLinkWidthX2 = 2, + RstLinkWidthX4 = 4 +} RST_LINK_WIDTH; + +// +// Stores information about connected PCIe storage devices used later by BIOS setup and RST remapping +// +#pragma pack(1) +typedef struct { + UINT8 Revision; + + // + // Stores the number of root ports occupied by a connected storage device, values from RST_LINK_WIDTH are supported + // + UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Programming interface value for a given device, 0x02 - NVMe or RAID, 0x1 - AHCI storage, 0x0 - no device connected + // + UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Stores information about cycle router number under a given PCIe controller + // + UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS]; +} PCIE_STORAGE_INFO_HOB; +#pragma pack() +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPolicyCommon.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..67b255fe97 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,54 @@ +/** @file + PCH configuration based on PCH policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/PcieRpConfig.h" +#include "ConfigBlock/SataConfig.h" +#include "ConfigBlock/IoApicConfig.h" +#include "ConfigBlock/Cio2Config.h" +#include "ConfigBlock/DmiConfig.h" +#include "ConfigBlock/FlashProtectionConfig.h" +#include "ConfigBlock/HdAudioConfig.h" +#include "ConfigBlock/InterruptConfig.h" +#include "ConfigBlock/IshConfig.h" +#include "ConfigBlock/LanConfig.h" +#include "ConfigBlock/LockDownConfig.h" +#include "ConfigBlock/P2sbConfig.h" +#include "ConfigBlock/PmConfig.h" +#include "ConfigBlock/Port61Config.h" +#include "ConfigBlock/ScsConfig.h" +#include "ConfigBlock/SerialIoConfig.h" +#include "ConfigBlock/SerialIrqConfig.h" +#include "ConfigBlock/SpiConfig.h" +#include "ConfigBlock/ThermalConfig.h" +#include "ConfigBlock/UsbConfig.h" +#include "ConfigBlock/EspiConfig.h" + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h new file mode 100644 index 0000000000..8bd4c9b960 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h @@ -0,0 +1,65 @@ +/** @file + PCH configuration based on PCH policy + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PREMEM_POLICY_COMMON_H_ +#define _PCH_PREMEM_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/DciConfig.h" +#include "ConfigBlock/WatchDogConfig.h" +#include "ConfigBlock/TraceHubConfig.h" +#include "ConfigBlock/HpetConfig.h" +#include "ConfigBlock/SmbusConfig.h" +#include "ConfigBlock/LpcConfig.h" +#include "ConfigBlock/HsioPcieConfig.h" +#include "ConfigBlock/HsioSataConfig.h" +#include "ConfigBlock/HsioConfig.h" + +#pragma pack (push,1) + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an update in the revision number +**/ +#define PCH_PREMEM_POLICY_REVISION 1 + +/** + PCH Policy PPI\n + All PCH config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +typedef struct _PCH_PREMEM_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of AddConfigBlock() +*/ +} PCH_PREMEM_POLICY; + +#pragma pack (pop) + +#endif // _PCH_PREMEM_POLICY_COMMON_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchReservedResources.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchReservedResources.h new file mode 100644 index 0000000000..e5de75c0e3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchReservedResources.h @@ -0,0 +1,62 @@ +/** @file + PCH preserved MMIO resource definitions. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** + PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-------------------------------------------------------------------------+ + | Size | Start | End | Usage | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused | + | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address | + +-------------------------------------------------------------------------+ +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO base address +#define PCH_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB +#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device in ACPI mode +#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR in ACPI mode +#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h new file mode 100644 index 0000000000..c19677cccd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h @@ -0,0 +1,28 @@ +/** @file + PCH Reset Platform Specific definitions. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_ +#define _PCH_RESET_PLATFORM_SPECIFIC_H_ + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) / sizeof (UINT16)) + +extern EFI_GUID gPchGlobalResetGuid; + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_ + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/PchReset.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/PchReset.h new file mode 100644 index 0000000000..951dac00dc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/PchReset.h @@ -0,0 +1,98 @@ +/** @file + PCH Reset PPI + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PPI PCH_RESET_PPI; +typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI; + +// +// Related Definitions +// +// +// PCH Reset Types +// +typedef enum { + PchColdReset = 0, + PchWarmReset = 1, + PchShutdownReset = 2, + PchGlobalReset = 4, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PPI instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, + ShutdownReset, GlobalReset + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_PPI_API) ( + IN PCH_RESET_PPI *This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. Or, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PPI { + PCH_RESET_PPI_API Reset; +}; + +/** + This ppi is used to execute PCH Reset from the host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface + for DXE and PEI environments, respectively. If other drivers need to run their + callback function right before issuing the reset, they can install PCH Reset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PPI { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h new file mode 100644 index 0000000000..cd98f3601c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h @@ -0,0 +1,32 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiService pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Wdt.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Wdt.h new file mode 100644 index 0000000000..b0bb6bccbd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Wdt.h @@ -0,0 +1,33 @@ +/** @file + Watchdog Timer PPI + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PEI_WDT_H_ +#define _PEI_WDT_H_ + +#include +// +// MRC takes a lot of time to execute in debug mode +// +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 60 + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gWdtPpiGuid; + +/// +/// Reuse WDT_PROTOCOL definition +/// +typedef WDT_PROTOCOL WDT_PPI; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h new file mode 100644 index 0000000000..eb08a89f00 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h @@ -0,0 +1,141 @@ +/** @file + APIs of PCH ACPI SMI Dispatch Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH ACPI SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH ACPI SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent ACPI SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH ACPI SMIs Dispatch Protocol + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs. + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow. +**/ +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL. + **/ + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Pme + The event is triggered by hardware when the PME# signal goes active. + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister; + /** + PmeB0 + The event is triggered PCH when any internal device with PCI Power Management + capabilities on bus 0 asserts the equivalent of the PME# signal. + Additionally, the event is only triggered when SCI_EN is not set. + The following are internal devices which can set this bit: + Intel HD Audio, Intel Management Engine "maskable" wake events, Integrated LAN, + SATA, xHCI, Intel SST + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register; + /** + RtcAlarm + The event is triggered by hardware when the RTC generates an alarm + (assertion of the IRQ8# signal). + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister; + /** + TmrOverflow + The event is triggered any time bit 22 of the 24-bit timer goes high + (bits are numbered from 0 to 23). + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 02h, bit 0) is set, + then the setting of the TMROF_STS bit will additionally generate an SMI# + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister; +}; + +/** + PCH ACPI SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_ACPI_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h new file mode 100644 index 0000000000..ad1db3833a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h @@ -0,0 +1,74 @@ +/** @file + PCH eMMC HS400 Tuning Protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_EMMC_TUNING_PROTOCOL_H_ +#define _PCH_EMMC_TUNING_PROTOCOL_H_ + +#define PCH_EMMC_TUNING_PROTOCOL_REVISION 2 +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchEmmcTuningProtocolGuid; + +// +// Forward declaration for PCH_EMMC_TUNING_PROTOCOL +// +typedef struct _PCH_EMMC_TUNING_PROTOCOL PCH_EMMC_TUNING_PROTOCOL; + +/** + This structure decribes the required Emmc info for HS400 tuning +**/ +typedef struct { + EFI_HANDLE PartitionHandle; ///< eMMC partition handle for block read/write + EFI_LBA Lba; ///< Logical Block Address for HS400 Tuning block read/write + UINT32 RelativeDevAddress; ///< Device system address, dynamically assigned by the host during initialization. + UINT8 HS200BusWidth; ///< The value to be programmed for BUS_WIDTH[183] byte +} EMMC_INFO; + +/// +/// This structure describes the return value after HS400 tuning +/// +typedef struct { + UINT8 Hs400DataValid; ///< Set if Hs400 Tuning Data is valid after tuning + UINT8 Hs400RxStrobe1Dll; ///< Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode) + UINT8 Hs400TxDataDll; ///< Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode) + UINT8 Hs400DriverStrength; ///< Hs400 Driver Strength +} EMMC_TUNING_DATA; + +/// +/// EMMC HS400 TUNING INTERFACE +/// +typedef EFI_STATUS (EFIAPI *EMMC_TUNE) ( + IN PCH_EMMC_TUNING_PROTOCOL *This, ///< This pointer to PCH_EMMC_TUNING_PROTOCOL + /** + Revision parameter is used to verify the layout of EMMC_INFO and TUNINGDATA. + If the revision is not matched, means the revision of EMMC_INFO and TUNINGDATA is not matched. + And function will return immediately. + **/ + IN UINT8 Revision, + IN EMMC_INFO *EmmcInfo, ///< Pointer to EMMC_INFO + OUT EMMC_TUNING_DATA *EmmcTuningData ///< Pointer to EMMC_TUNING_DATA +); + +/** + PCH EMMC TUNING PROTOCOL INTERFACE + Platform code uses this protocol to configure Emmc Hs400 mode, by passing the EMMC_INFO information. + PCH will setting EMMC controller based on EMMC_INFO and return EMMC_TUNING_DATA to platform code. + Platform should keep values of EMMC_TUNING_DATA and uses to configure EMMC through policies, to + prevent from doing EMMC tuning every boot. +**/ +struct _PCH_EMMC_TUNING_PROTOCOL { + EMMC_TUNE EmmcTune; ///< Emmc Hs400 Tuning Interface +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h new file mode 100644 index 0000000000..7d7d3a5339 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h @@ -0,0 +1,151 @@ +/** @file + SmmEspiDispatch Protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchEspiSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH eSPI SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. +**/ +typedef +VOID +(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Generic function to register different types of eSPI SMI types + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration successful + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered + @retval others Registration failed +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ESPI_SMI_REGISTER) ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to unregister a callback based on handle + + @param[in] This Not used + @param[in] DispatchHandle Handle acquired during registration + + @retval EFI_SUCCESS Unregister successful + @retval EFI_INVALID_PARAMETER DispatchHandle is null + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has bad pointer + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in database + @retval EFI_ACCESS_DENIED Unregistration is done after end of DXE +**/ + +typedef +EFI_STATUS +(EFIAPI *PCH_ESPI_SMI_UNREGISTER) ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH eSPI SMIs Dispatch Protocol + The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs. + It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserted SMIs +**/ +struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Unregister eSPI SMI events + **/ + PCH_ESPI_SMI_UNREGISTER UnRegister; + /** + Register a BIOS Write Protect event + **/ + PCH_ESPI_SMI_REGISTER BiosWrProtectRegister; + /** + Register a BIOS Write Report event + **/ + PCH_ESPI_SMI_REGISTER BiosWrReportRegister; + /** + Register a Peripheral Channel Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister; + /** + Register a Peripheral Channel Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER PcErrFatalRegister; + /** + Register a Virtual Wire Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister; + /** + Register a Virtual Wire Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER VwErrFatalRegister; + /** + Register a Flash Channel Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister; + /** + Register a Flash Channel Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER FlashErrFatalRegister; + /** + Register a Link Error event + **/ + PCH_ESPI_SMI_REGISTER LnkErrType1Register; + /** + Register a SMI handler for Espi slaver + This routine will also lock down ESPI_SMI_LOCK bit after registration and prevent + this handler from unregistration. + On platform that supports more than 1 device through another chip select (SPT-H), + the SMI handler itself needs to inspect both the eSPI devices' interrupt status registers + (implementation specific for each Slave) in order to identify and service the cause. + After servicing it, it has to clear the Slaves' internal SMI# status registers + **/ + PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister; +}; + +/** + PCH ESPI SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_ESPI_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchGpioUnlockSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchGpioUnlockSmiDispatch.h new file mode 100644 index 0000000000..392733117b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchGpioUnlockSmiDispatch.h @@ -0,0 +1,115 @@ +/** @file + APIs of PCH GPIO UNLOCK SMI Dispatch Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchGpioUnlockSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH GPIO UNLOCK SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_GPIO_UNLOCK_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for specific PCH GPIO UNLOCK SMI dispatch event. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_GPIO_UNLOCK_SMI_DISPATCH_REGISTER) ( + IN PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL *This, + IN PCH_GPIO_UNLOCK_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent GPIO UNLOCK SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_GPIO_UNLOCK_SMI_DISPATCH_UNREGISTER) ( + IN PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH GPIOUNLOCK SMI Dispatch Protocol + The PCH GPIO UNLOCK SMI DISPATCH PROTOCOL provides the ability to dispatch function for + PCH gpio unlock SMIs. +**/ +struct _PCH_GPIO_UNLOCK_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH GPIO UNLOCK SMI DISPATCH PROTOCOL. + **/ + PCH_GPIO_UNLOCK_SMI_DISPATCH_UNREGISTER UnRegister; + /** + GpioUnlock + The event is triggered if the GPIO registers lockdown logic is requesting an SMI#. + **/ + PCH_GPIO_UNLOCK_SMI_DISPATCH_REGISTER Register; +}; + +/** + PCH GPIO UNLOCK SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_GPIO_UNLOCK_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchInfo.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchInfo.h new file mode 100644 index 0000000000..ff81aebddf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchInfo.h @@ -0,0 +1,57 @@ +/** @file + This file defines the PCH Info Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_INFO_H_ +#define _PCH_INFO_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_INFO_PROTOCOL PCH_INFO_PROTOCOL; + +/** + Protocol revision number + Any backwards compatible changes to this protocol will result in an update in the revision number + Major changes will require publication of a new protocol + + Revision 1: Original version + Revision 2: Add PcieControllerCfg6 for KBL PCH-H +**/ +#define PCH_INFO_PROTOCOL_REVISION 2 + +/** + This protocol is used to provide the information of PCH controller. +**/ +struct _PCH_INFO_PROTOCOL { + /** + This member specifies the revision of the PCH Info protocol. This field is used + to indicate backwards compatible changes to the protocol. Platform code that + consumes this protocol must read the correct revision value to correctly interpret + the content of the protocol fields. + **/ + UINT8 Revision; + + UINT8 PcieControllerCfg1; + UINT8 PcieControllerCfg2; + UINT8 PcieControllerCfg3; + UINT8 PcieControllerCfg4; + UINT8 PcieControllerCfg5; + UINT8 PcieControllerCfg6; +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h new file mode 100644 index 0000000000..b80597ae9b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h @@ -0,0 +1,137 @@ +/** @file + APIs of PCH PCIE SMI Dispatch Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +typedef struct { + UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1) + UINT8 BusNum; ///< Root port pci bus number + UINT8 DevNum; ///< Root port pci device number + UINT8 FuncNum; ///< Root port pci function number +} PCH_PCIE_SMI_RP_CONTEXT; + +/** + Callback function for an PCH PCIE RP SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + @param[in] RpContext Pointer of PCH PCIE Root Port context. + +**/ +typedef +VOID +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + Register a child SMI source dispatch function for PCH PCIERP SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] RpIndex Refer to PCH PCIE Root Port index. + 0: RP1, 1: RP2, n: RP(N+1) + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent PCIE SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH PCIE SMIs Dispatch Protocol + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs. + It contains SMI types of HotPlug, LinkActive, and Link EQ. +**/ +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. + **/ + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; + /** + PcieRpXHotPlug + The event is triggered when PCIE root port Hot-Plug Presence Detect. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; + /** + PcieRpXLinkActive + The event is triggered when Hot-Plug Link Active State Changed. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; + /** + PcieRpXLinkEq + The event is triggered when Device Requests Software Link Equalization. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; +}; + +/** + PCH PCIE SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_PCIE_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchReset.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..b39543b36e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchReset.h @@ -0,0 +1,121 @@ +/** @file + PCH Reset Protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_RESET_PROTOCOL_H_ +#define _PCH_RESET_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; +typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +/// +/// PCH Reset Types +/// +typedef enum { + PchColdReset = 0, + PchWarmReset = 1, + PchShutdownReset = 2, + PchGlobalReset = 4, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific reset. +**/ +typedef +VOID * +(EFIAPI *PCH_RESET_GET_RESET_DATA) ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; + PCH_RESET_GET_RESET_DATA GetResetData; +}; + +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes PowerCycle, GlobalReset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE ResetType + ); + +/** + This protocol is used to execute PCH Reset from the host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface + for DXE and PEI environments, respectively. If other drivers need to run their + callback function right before issuing the reset, they can install PCH Reset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PROTOCOL { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h new file mode 100644 index 0000000000..4f0508b238 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h @@ -0,0 +1,139 @@ +/** @file + APIs of PCH SMI Dispatch Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for specific PCH SMI dispatch event. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH specific SMIs Dispatch Protocol + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs. + It contains legacy SMIs and new PCH SMI types like: + SerialIrq, McSmi, Smbus, ... +**/ +struct _PCH_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH SMI DISPATCH PROTOCOL. + **/ + PCH_SMI_DISPATCH_UNREGISTER UnRegister; + /** + SerialIrq + The event is triggered while the SMI# was caused by the SERIRQ decoder. + **/ + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister; + /** + McSmi + The event is triggered if there has been an access to the power management + microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit + in the LPC Bridge I/O Enables configuration register is 1 . + **/ + PCH_SMI_DISPATCH_REGISTER McSmiRegister; + /** + SmBus + The event is triggered while the SMI# was caused by: + 1. The SMBus Slave receiving a message that an SMI# should be caused, or + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the + SMBALERT_DIS bit is cleared, or + 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and + the SMB_SMI_EN bits are set, or + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state. + **/ + PCH_SMI_DISPATCH_REGISTER SmbusRegister; + /** + SPI Asynchronous + When registered, the flash controller will generate an SMI when it blocks a BIOS write or erase. + **/ + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister; +}; + +/** + PCH SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h new file mode 100644 index 0000000000..5d0a4d34cf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h @@ -0,0 +1,72 @@ +/** @file + PCH SMM IO Trap Control Protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ +#define _PCH_SMM_IO_TRAP_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmIoTrapControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume IoTrap callback function. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM IO trap pause and resume protocol + This protocol provides the functions to runtime control the IoTrap SMI enabled/disable. + This applys the capability to the DispatchHandle which returned by IoTrap callback + registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0. + Besides, when S3 resuem, it only restores the state of IoTrap callback registration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { + /** + This runtime pauses a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; + /** + This runtime resumes a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h new file mode 100644 index 0000000000..95c680e75c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h @@ -0,0 +1,72 @@ +/** @file + PCH SMM Periodic Timer Control Protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmPeriodicTimerControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume SMM PERIODIC TIMER function. + + @param[in] This Pointer to the PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) ( + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM PERIODIC TIMER pause and resume protocol + This protocol provides the functions to runtime control the SM periodic timer enabled/disable. + This applies the capability to the DispatchHandle which returned by SMM periodic timer callback + registration. + Besides, when S3 resume, it only restores the state of callback registration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL { + /** + This runtime pauses the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause; + /** + This runtime resumes the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume; +}; + +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h new file mode 100644 index 0000000000..457cdb682c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h @@ -0,0 +1,157 @@ +/** @file + APIs of PCH TCO SMI Dispatch Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH TCO SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH TCO SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent TCO SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH TCO SMIs Dispatch Protocol + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs. + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, and BiowWp. +**/ +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL. + **/ + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Mch + The event is triggered when PCH received a DMI special cycle message using DMI indicating that + it wants to cause an SMI. + The software must read the processor to determine the reason for the SMI. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister; + /** + TcoTimeout + The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reaching 0. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister; + /** + OsTco + The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister; + /** + Nmi + The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherwise have + caused an NMI (because NMI2SMI_EN is set) + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister; + /** + IntruderDectect + The event is triggered by PCH to indicate that an intrusion was detected. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister; + /** + SpiBiosWp + This event is triggered when SMI# was caused by the TCO logic and + SPI flash controller asserted Synchronous SMI by BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister; + /** + LpcBiosWp + This event is triggered when SMI# was caused by the TCO logic and + LPC/eSPI BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister; + /** + NewCentury + This event is triggered when SMI# was caused by the TCO logic and + year of RTC date rolls over a century (99 to 00). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister; +}; + +/** + PCH TCO SMI dispatch revision number + + Revision 1: Initial version + Revision 2: Add NEWCENTURY support +**/ +#define PCH_TCO_SMI_DISPATCH_REVISION 2 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/SerialGpio.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/SerialGpio.h new file mode 100644 index 0000000000..4bc396132d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/SerialGpio.h @@ -0,0 +1,126 @@ +/** @file + This file defines the PCH Serial GPIO Interface Protocol which implements the + Intel(R) Serial Data over GPIO Pin functionality Protocol Interface. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SERIAL_GPIO_PROTOCOL_H_ +#define _PCH_SERIAL_GPIO_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSerialGpioProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SERIAL_GPIO_PROTOCOL PCH_SERIAL_GPIO_PROTOCOL; + +#define SERIAL_GPIO_MAX_DATA_RATE 63 +#define WAIT_TIME 100000 +#define WAIT_PERIOD 10 + +/// +/// Serial GPIO protocol data structures and definitions +/// +typedef enum { + EnumSerialGpioDataByte, + EnumSerialGpioDataWord, + EnumSerialGpioDataUndefined, + EnumSerialGpioDataDword, + EnumSerialGpioDataMax +} SERIAL_GPIO_DATA_WIDTH; + +// +// Protocol member functions +// +/** + Register for one GPIO Pin that will be used as serial GPIO. + For SKL PCH only GPP_D_0-4 will have the capability to be used as serial GPIO. + The caller of this procedure need to be very clear of which GPIO should be used as serial GPIO, + it should not be input, native, conflict with other GPIO, or Index > 4 on the caller's platform. + + @param[in] This Pointer to the PCH_SERIAL_GPIO_PROTOCOL instance. + @param[in] SerialGpioPad The GPIO pad number that will be used as serial GPIO for data sending. + + @retval EFI_SUCCESS Opcode initialization on the SERIAL_GPIO host controller completed. + @retval EFI_ACCESS_DENIED The SERIAL_GPIO configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + @retval EFI_INVALID_PARAMETER SerialGpioPinIndex is out of range +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SERIAL_GPIO_REGISTER) ( + IN PCH_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 SerialGpioPad + ); + +/** + Unregister for one GPIO Pin that has been used as serial GPIO, and recover the registers before + registering. + + @param[in] This Pointer to the PCH_SERIAL_GPIO_PROTOCOL instance. + @param[in] SerialGpioPad The GPIO pad number that will be used as serial GPIO for data sending. + + @retval EFI_SUCCESS Opcode initialization on the SERIAL_GPIO host controller completed. + @retval EFI_ACCESS_DENIED The SERIAL_GPIO configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + @retval EFI_INVALID_PARAMETER Invalid function parameters +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SERIAL_GPIO_UNREGISTER) ( + IN PCH_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 SerialGpioPad + ); + +/** + Execute SERIAL_GPIO commands from the host controller. + + @param[in] This Pointer to the PCH_SERIAL_GPIO_PROTOCOL instance. + @param[in] GpioPad GPIO pad number. + @param[in] DataRate The data rate for serial data transferring. 1 ~ SERIAL_GPIO_MAX_DATA_RATE; 1: 128ns intervals; ...; 8: 8*128 = 1024ns intervals, default value;... + @param[in] DataCountInByte Number of bytes of the data will be transmitted through the GPIO pin. + @param[in, out] Buffer Pointer to caller-allocated buffer containing the data sent through the GPIO pin. + + @retval EFI_SUCCESS Execute succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, GPIO serial data sent failed. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SERIAL_GPIO_SEND_DATA) ( + IN PCH_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 GpioPad, + IN UINT8 DataRate, + IN UINTN DataCountInByte, + IN OUT UINT8 *Buffer + ); +/** + This Protocol allows a platform module to execute the IntelR Serial Data over + GPIO Pin functionality Protocol Interface. + The caller will first call the SerialGpioRegister() function to configure the GPIO + to be used. Then the caller will execute one or more calls to the SerialGpioSendData() + function to perform serial GPIO activities. Finally, the caller will use the + SerialGpioUnRegister() function to un-register and allow other consumers to utilize + the serial GPIO services. + If the serial GPIO capabilities are in use by another caller, the registration + function will return an error. +**/ +struct _PCH_SERIAL_GPIO_PROTOCOL { + PCH_SERIAL_GPIO_REGISTER SerialGpioRegister; ///< Register for one GPIO pin that will be used as serial GPIO. + PCH_SERIAL_GPIO_SEND_DATA SerialGpioSendData; ///< Execute SERIAL_GPIO commands from the host controller. + PCH_SERIAL_GPIO_UNREGISTER SerialGpioUnRegister; ///< Un-register the current GPIO pin used for serial GPIO, and recovers the registers before registering. +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h new file mode 100644 index 0000000000..e4ce8fb472 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h @@ -0,0 +1,299 @@ +/** @file + This file defines the PCH SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSpiProtocolGuid; +extern EFI_GUID gPchSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. Remark: Erase may be needed before write to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data read. + @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations through the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Wdt.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Wdt.h new file mode 100644 index 0000000000..4a65e016e6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Wdt.h @@ -0,0 +1,118 @@ +/** @file + Watchdog Timer protocol + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _DXE_WDT_H_ +#define _DXE_WDT_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gWdtProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _WDT_PROTOCOL WDT_PROTOCOL; + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which + causes the next reset to be treated as watchdog expiration - unless AllowKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +typedef +EFI_STATUS +(EFIAPI *WDT_RELOAD_AND_START) ( + UINT32 TimeoutValue + ); + +/** + Returns WDT failure status. + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +typedef +UINT8 +(EFIAPI *WDT_CHECK_STATUS) ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application. + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_REQUIRED) ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_ENABLED) ( + VOID + ); + +/** + Disables WDT timer. +**/ +typedef +VOID +(EFIAPI *WDT_DISABLE) ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a failure. + This function allows platform to perform expected reboots with WDT running, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, ReloadAndStart() + must not be called. +**/ +typedef +VOID +(EFIAPI *WDT_ALLOW_KNOWN_RESET) ( + VOID + ); + +/** + These protocols and PPI allow a platform module to perform watch dog timer operations + through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI + implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively. + WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they + share the identical data structure. +**/ +struct _WDT_PROTOCOL { + WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it. + WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status. + WDT_DISABLE Disable; ///< Disables WDT timer. + WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures. + IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application. + IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status. +}; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsCam.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsCam.h new file mode 100644 index 0000000000..c4be5c27e7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsCam.h @@ -0,0 +1,151 @@ +/** @file + Register names for Camera block + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_CAM_H_ +#define _PCH_REGS_CAM_H_ + +// +// CIO2 Registers (D20:F3) +// +#define PCI_DEVICE_NUMBER_PCH_CIO2 20 +#define PCI_FUNCTION_NUMBER_PCH_CIO2 3 +#define V_PCH_CIO2_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_LP_CIO2_DEVICE_ID 0x9D32 + +// +// CIO2 PCI Configuration space definitions +// +#define R_PCH_CIO2_CIOLBA 0x10 // Camera IO Controller Lower Base Address +#define R_PCH_CIO2_CIOUBA 0x14 // Camera IO Controller Upper Base Address +#define B_PCH_CIO2_CFG_PMCSR_NSR BIT3 // No Software Reset +#define R_PCH_CIO2_CFG_MID_MMC 0x90 // MSI Capability ID +#define R_PCH_CIO2_CFG_MMLA 0x94 // MSI Message Lower Address +#define R_PCH_CIO2_CFG_MMUA 0x98 // MSI Message Lower Address +#define R_PCH_CIO2_CFG_MMD 0x9C // MSI Message Data +#define R_PCH_CIO2_AFID 0xA0 // Advanced Features Capability Identifiers +#define R_PCH_CIO2_AF_CMD_STS 0xA4 // Adavanced Features Command and Staus Register +#define R_PCH_CIO2_CFG_PID_PC 0xD0 // Power Management Capability Identifiers +#define R_PCH_CIO2_CFG_PMCSR 0xD4 // Power Management Control & Status +#define V_PCH_CIO2_CFG_PMCSR_PS_D3HOT (BIT0 | BIT1) + +// +// CAM_MMIO_CSI2 +// + +// +// CAM_MMIO_PRI +// Camera Pipe Host Controller's MMIO registers in Primary clock domain +// +#define R_PCH_CAM_MMIO_PRI_CIO2_CGC 0x1400 ///< CIO2 Clock Gating Control +#define V_PCH_CAM_MMIO_PRI_CIO2_CGC_CLK_GATING_EN (0x00003D7E) +#define V_PCH_CAM_MMIO_PRI_CIO2_CGC_CLK_GATING_DIS (0x05300000) +#define R_PCH_CAM_MMIO_PRI_CIO2_D0I3C 0x1408 ///< CIO2 D0i3 Control Register +#define B_PCH_CAM_MMIO_PRI_CIO2_D0I3C_I3 BIT2 ///< I3 (D0i3). SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will return the IP to the fully active D0 state (D0i0) +#define R_PCH_CAM_MMIO_PRI_PCE 0x1430 ///< PCE Power Control Enable Register +#define B_PCH_CAM_MMIO_PRI_PCE_D3HE BIT2 ///< D3HE: D3-Hot Enable +#define B_PCH_CAM_MMIO_PRI_PCE_I3E BIT1 ///< I3E: I3 Enable +#define R_PCH_CAM_MMIO_PRI_CIO2_GPR0 0x1434 ///< CIO2 General Purpose register 0 +#define R_PCH_CAM_MMIO_PRI_CIO2_GPR1 0x1438 ///< CIO2 General Purpose register 1 + +// +// CAM_PVT CHC space defininitions +// Private registers description for Camera Pipe Host Controller IP +// MSG IOSF-SB Port 0xA1 (PID_CAM_CHC) +// +#define R_PCH_PCR_CAM_CHC_PVT_FUSVAL 0x00 ///< Fuse Value +#define R_PCH_PCR_CAM_CHC_PVT_ECCLOG 0x04 ///< SRAM Error Count Log +#define R_PCH_PCR_CAM_CHC_PVT_DBGCTL 0x08 ///< Debug Control +#define R_PCH_PCR_CAM_CHC_PVT_FNCFG 0x0C ///< Lock bits +#define B_PCH_PCR_CAM_CHC_PVT_FNCFG_MEM_LOCK BIT8 ///< lock all lockable field in MEM space +#define B_PCH_PCR_CAM_CHC_PVT_FNCFG_BCLD BIT0 ///< lock all lockable fields in CFG space +#define R_PCH_PCR_CAM_CHC_HDEVC 0x10 ///< Hidden Device register +#define R_PCH_PCR_CAM_CHC_PVT_FUSE_DBG 0x14 ///< Hidden Device register + +// +// fls space definitions +// CSI2 host controller's FLIS registers +// MSG IOSF-SB Port 0xAA (PID_CAM_FLS) +// +#define R_PCH_PCR_CAM_FLIS_CSI0_RXCNTRL 0x00 +#define R_PCH_PCR_CAM_FLIS_CSI0_RCCRCOMP 0x01 +#define R_PCH_PCR_CAM_FLIS_CSI0_BSCOMPARE 0x02 +#define R_PCH_PCR_CAM_FLIS_CSI1_RXCNTRL 0x03 +#define R_PCH_PCR_CAM_FLIS_CSI1_RCCRCOMP 0x04 +#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG1 0x05 +#define R_PCH_PCR_CAM_FLIS_CSI1_BSCOMPARE 0x06 +#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG2 0x07 +#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CFG3 0x08 +#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG2 0x09 +#define R_PCH_PCR_CAM_FLIS_CSI2_RXCNTRL 0x0A +#define R_PCH_PCR_CAM_FLIS_CSI2_RCCRCOMP 0x0B +#define R_PCH_PCR_CAM_FLIS_CSI2_BSCOMPARE 0x0C +#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_CMP_STAT 0x0D +#define R_PCH_PCR_CAM_FLIS_CSI0_INTLPBK_ERR_REG 0x0E +#define R_PCH_PCR_CAM_FLIS_CSI_CLKTRIM 0x0F +#define R_PCH_PCR_CAM_FLIS_CSI3_RXCNTRL 0x10 +#define R_PCH_PCR_CAM_FLIS_CSI3_RCCRCOMP 0x11 +#define R_PCH_PCR_CAM_FLIS_CSI3_BSCOMPARE 0x12 +#define R_PCH_PCR_CAM_FLIS_CSI_CFG 0x13 +#define B_PCH_PCR_CAM_FLIS_CSI_CFG_ACIO_LB_EN BIT26 +#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG1 0x14 +#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG2 0x15 +#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CFG3 0x16 +#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG1 0x17 +#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CFG3 0x18 +#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CFG1 0x19 +#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CFG3 0x1A +#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_ERR_REG 0x1B +#define R_PCH_PCR_CAM_FLIS_CSI1_INTLPBK_CMP_STAT 0x1C +#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_ERR_REG 0x1D +#define R_PCH_PCR_CAM_FLIS_CSI2_INTLPBK_CMP_STAT 0x1E +#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_ERR_REG 0x1F +#define R_PCH_PCR_CAM_FLIS_CSI3_INTLPBK_CMP_STAT 0x20 +#define R_PCH_PCR_CAM_FLIS_CSI_RCOMPSTAT_REG 0x21 +#define R_PCH_PCR_CAM_FLIS_CSI_DLLCTL_REG 0x22 +#define R_PCH_PCR_CAM_FLIS_CSI_DATAEYE_REG 0x23 +#define R_PCH_PCR_CAM_FLIS_CSI_DATATRIM 0x24 +#define R_PCH_PCR_CAM_FLIS_CSI_CTLE 0x25 +#define R_PCH_PCR_CAM_FLIS_CSI0_DFT_CFG 0x26 +#define R_PCH_PCR_CAM_FLIS_CSI1_DFT_CFG 0x27 +#define R_PCH_PCR_CAM_FLIS_CSI2_DFT_CFG 0x28 +#define R_PCH_PCR_CAM_FLIS_CSI3_DFT_CFG 0x29 +#define R_PCH_PCR_CAM_FLIS_CSI_AFE_HS_CONTROL 0x2A +#define R_PCH_PCR_CAM_FLIS_CSI_RCOMP_STATUS 0x2B +#define R_PCH_PCR_CAM_FLIS_CSI_RCOMP_CONTROL 0x2C +#define R_PCH_PCR_CAM_FLIS_CSI_DATAEYE1_REG 0x2D +#define R_PCH_PCR_CAM_FLIS_CSI_ALL01 0x2E +#define R_PCH_PCR_CAM_FLIS_CSI_DLLCTL1_REG 0x2F +#define R_PCH_PCR_CAM_FLIS_CSI_DATATRIM1 0x30 + +#endif + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDci.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDci.h new file mode 100644 index 0000000000..d38bd7f0c4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDci.h @@ -0,0 +1,50 @@ +/** @file + Register names for PCH DCI device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable +#define B_PCH_PCR_DCI_ECTRL_HDCIEN_LOCK BIT0 ///< Host DCI Enable Lock +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h new file mode 100644 index 0000000000..942aeda324 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h @@ -0,0 +1,214 @@ +/** @file + Register names for DMI and OP-DMI + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_DMI_H_ +#define _PCH_REGS_DMI_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// VC Configuration (Common) +// +#define R_PCH_PCR_DMI_V0CTL 0x2014 ///< Virtual channel 0 resource control +#define B_PCH_PCR_DMI_V0CTL_EN BIT31 +#define B_PCH_PCR_DMI_V0CTL_ID (7 << 24) ///< Bit[26:24] +#define N_PCH_PCR_DMI_V0CTL_ID 24 +#define V_PCH_PCR_DMI_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V0CTL_TVM_MASK 0x7E +#define R_PCH_PCR_DMI_V0STS 0x201A ///< Virtual channel 0 status +#define B_PCH_PCR_DMI_V0STS_NP BIT1 +#define R_PCH_PCR_DMI_V1CTL 0x2020 ///< Virtual channel 1 resource control +#define B_PCH_PCR_DMI_V1CTL_EN BIT31 +#define B_PCH_PCR_DMI_V1CTL_ID (0x0F << 24) ///< Bit[27:24] +#define N_PCH_PCR_DMI_V1CTL_ID 24 +#define V_PCH_PCR_DMI_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V1CTL_TVM_MASK 0xFE +#define R_PCH_PCR_DMI_V1STS 0x2026 ///< Virtual channel 1 status +#define B_PCH_PCR_DMI_V1STS_NP BIT1 +#define R_PCH_PCR_DMI_VMCTL 0x2040 ///< ME Virtual Channel (VCm) resource control +#define R_PCH_PCR_DMI_VMSTS 0x2046 ///< ME Virtual Channel Resource Status +#define R_PCH_PCR_DMI_UEM 0x2088 ///< Uncorrectable Error Mask +#define R_PCH_PCR_DMI_REC 0x20AC ///< Root Error Command + +// +// Internal Link Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_LCAP 0x21A4 ///< Link Capabilities +#define B_PCH_PCR_DMI_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_PCR_DMI_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_DMI_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI +#define B_PCH_PCR_DMI_LCAP_MLW 0x000003F0 +#define B_PCH_PCR_DMI_LCAP_MLS 0x0000000F +#define R_PCH_PCR_DMI_LCTL 0x21A8 ///< Link Control +#define B_PCH_PCR_DMI_LCTL_ES BIT7 +#define B_PCH_PCR_DMI_LCTL_ASPM (BIT1 | BIT0) ///< Link ASPM +#define R_PCH_PCR_DMI_LSTS 0x21AA ///< Link Status +#define R_PCH_PCR_DMI_LCTL2 0x21B0 ///< Link Control 2 +#define R_PCH_PCR_DMI_LSTS2 0x21B2 ///< Link Status 2 +#define R_PCH_PCR_DMI_L01EC 0x21BC ///< Lane 0 and Lane 1 Equalization Control +#define R_PCH_PCR_DMI_L23EC 0x21C0 ///< Lane 2 and Lane 3 Equalization Control +#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 ///< Upstream Port Lane 1/3 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL13RPH 24 ///< Upstream Port Lane 1/3 Transmitter Preset Hint value offset +#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 ///< Upstream Port Lane 0/2 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL02RPH 8 ///< Upstream Port Lane 0/2 Transmitter Preset Hint value offset +#define V_PCH_PCR_DMI_UPL0RPH 7 ///< Upstream Port Lane 0 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL1RPH 7 ///< Upstream Port Lane 1 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL2RPH 7 ///< Upstream Port Lane 2 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL3RPH 7 ///< Upstream Port Lane 3 Transmitter Preset Hint value + + +// +// North Port Error Injection Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_DMIEN 0x2230 ///< DMI Error Injection Enable + +// +// DMI Control +// +#define R_PCH_PCR_DMI_DMIC 0x2234 ///< DMI Control +#define B_PCH_PCR_DMI_DMIC_SRL BIT31 ///< Secured register lock +#define B_PCH_PCR_DMI_DMIC_ORCE (BIT25 | BIT24) ///< Offset Re-Calibration Enable +#define N_PCH_PCR_DMI_DMIC_ORCE 24 +#define V_PCH_PCR_DMI_DMIC_ORCE_EN_GEN2_GEN3 1 ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only. +#define B_PCH_PCR_DMI_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable +#define R_PCH_PCR_DMI_DMIHWAWC 0x2238 ///< DMI HW Autonomus Width Control +#define R_PCH_PCR_DMI_IOSFSBCS 0x223E ///< IOSF Sideband Control and Status +#define B_PCH_PCR_DMI_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) ///< DMI Clock Gate Enable + +#define R_PCH_PCR_DMI_2300 0x2300 +#define R_PCH_PCR_DMI_2304 0x2304 +#define R_PCH_PCR_DMI_2310 0x2310 +#define R_PCH_PCR_DMI_2314 0x2314 +#define R_PCH_PCR_DMI_2320 0x2320 +#define R_PCH_PCR_DMI_2324 0x2324 +#define R_PCH_PCR_DMI_232C 0x232C +#define R_PCH_PCR_DMI_2334 0x2334 +#define R_PCH_PCR_DMI_2338 0x2338 +#define R_PCH_PCR_DMI_2340 0x2340 +#define R_PCH_PCR_DMI_2344 0x2344 +#define R_PCH_PCR_DMI_2348 0x2348 +#define R_PCH_PCR_DMI_234C 0x234C + +// +// Port Configuration Extension(DMI Only) +// +#define R_PCH_PCR_DMI_EQCFG1 0x2450 +#define B_PCH_PCR_DMI_EQCFG1_RTLEPCEB BIT16 +#define R_PCH_PCR_DMI_LTCO1 0x2470 ///< Local Transmitter Coefficient Override 1 +#define R_PCH_PCR_DMI_LTCO2 0x2474 ///< Local Transmitter Coefficient Override 2 +#define B_PCH_PCR_DMI_L13TCOE BIT25 ///< Lane 1/3 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L02TCOE BIT24 ///< Lane 0/2 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L13TPOSTCO 0x00fc0000 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPOSTCO 18 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L13TPRECO 0x0003f000 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPRECO 12 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPOSTCO 0x00000fc0 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPOSTCO 6 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPRECO 0x0000003f ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPRECO 0 ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset +#define R_PCH_PCR_DMI_G3L0SCTL 0x2478 ///< GEN3 L0s Control + +// +// OP-DMI Specific Registers (OP-DMI Only) +// +#define R_PCH_PCR_OPDMI_LCTL 0x2600 ///< Link Control +#define R_PCH_PCR_OPDMI_STC 0x260C ///< Sideband Timing Control +#define R_PCH_PCR_OPDMI_LPMC 0x2614 ///< Link Power Management Control +#define R_PCH_PCR_OPDMI_LCFG 0x2618 ///< Link Configuration + +// +// DMI Source Decode PCRs (Common) +// +#define R_PCH_PCR_DMI_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable +#define R_PCH_PCR_DMI_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable +#define R_PCH_PCR_DMI_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable +#define R_PCH_PCR_DMI_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable +#define R_PCH_PCR_DMI_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID +#define R_PCH_PCR_DMI_P2SBIOR 0x2720 ///< P2SB IO Range +#define R_PCH_PCR_DMI_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address +#define R_PCH_PCR_DMI_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address +#define R_PCH_PCR_DMI_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1 +#define R_PCH_PCR_DMI_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2 +#define R_PCH_PCR_DMI_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3 +#define R_PCH_PCR_DMI_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4 +#define R_PCH_PCR_DMI_LPCGMR 0x2740 ///< LPC Generic Memory Range +#define R_PCH_PCR_DMI_LPCBDE 0x2744 ///< LPC BIOS Decode Enable +#define R_PCH_PCR_DMI_UCPR 0x2748 ///< uCode Patch Region +#define B_PCH_PCR_DMI_UCPR_UPRE BIT0 ///< uCode Patch Region Enable +#define R_PCH_PCR_DMI_GCS 0x274C ///< Generic Control and Status +#define B_PCH_PCR_DMI_RPRDID 0xFFFF0000 ///< RPR Destination ID +#define B_PCH_PCR_DMI_BBS BIT10 ///< Boot BIOS Strap +#define B_PCH_PCR_DMI_RPR BIT11 ///< Reserved Page Route +#define B_PCH_PCR_DMI_BILD BIT0 ///< BIOS Interface Lock-Down +#define R_PCH_PCR_DMI_IOT1 0x2750 ///< I/O Trap Register 1 +#define R_PCH_PCR_DMI_IOT2 0x2758 ///< I/O Trap Register 2 +#define R_PCH_PCR_DMI_IOT3 0x2760 ///< I/O Trap Register 3 +#define R_PCH_PCR_DMI_IOT4 0x2768 ///< I/O Trap Register 4 +#define R_PCH_PCR_DMI_LPCIOD 0x2770 ///< LPC I/O Decode Ranges +#define R_PCH_PCR_DMI_LPCIOE 0x2774 ///< LPC I/O Enables +#define R_PCH_PCR_DMI_TCOBASE 0x2778 ///< TCO Base Address +#define B_PCH_PCR_DMI_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask +#define R_PCH_PCR_DMI_GPMR1 0x277C ///< General Purpose Memory Range 1 +#define R_PCH_PCR_DMI_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID +#define R_PCH_PCR_DMI_GPMR2 0x2784 ///< General Purpose Memory Range 2 +#define R_PCH_PCR_DMI_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID +#define R_PCH_PCR_DMI_GPMR3 0x278C ///< General Purpose Memory Range 3 +#define R_PCH_PCR_DMI_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID +#define R_PCH_PCR_DMI_GPIOR1 0x2794 ///< General Purpose I/O Range 1 +#define R_PCH_PCR_DMI_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID +#define R_PCH_PCR_DMI_GPIOR2 0x279C ///< General Purpose I/O Range 2 +#define R_PCH_PCR_DMI_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID +#define R_PCH_PCR_DMI_GPIOR3 0x27A4 ///< General Purpose I/O Range 3 +#define R_PCH_PCR_DMI_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID +#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base Address +#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base Control +#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Base Address +#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Base Destination ID + + +// +// Opi PHY registers +// +#define R_PCH_PCR_OPIPHY_0110 0x0110 +#define R_PCH_PCR_OPIPHY_0118 0x0118 +#define R_PCH_PCR_OPIPHY_011C 0x011C +#define R_PCH_PCR_OPIPHY_0354 0x0354 +#define R_PCH_PCR_OPIPHY_B104 0xB104 +#define R_PCH_PCR_OPIPHY_B10C 0xB10C + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsFia.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsFia.h new file mode 100644 index 0000000000..c9e08ca854 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsFia.h @@ -0,0 +1,123 @@ +/** @file + Register definition for FIA component + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_FIA_H_ +#define _PCH_REGS_FIA_H_ + + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PID:FIA +// +#define SKL_PCH_MAX_FIA_DRCRM 3 +#define KBL_PCH_MAX_FIA_DRCRM 4 +#define PCH_MAX_FIA_DRCRM KBL_PCH_MAX_FIA_DRCRM +#define R_PCH_PCR_FIA_CC 0 +#define B_PCH_PCR_FIA_CC_SRL BIT31 +#define B_PCH_PCR_FIA_CC_PTOCGE BIT17 +#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16 +#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15 + +#define R_PCH_PCR_FIA_PLLCTL 0x20 +#define R_PCH_PCR_FIA_DRCRM1 0x100 +#define R_PCH_PCR_FIA_DRCRM2 0x104 +#define R_PCH_PCR_FIA_DRCRM3 0x108 +#define R_PCH_PCR_FIA_DRCRM4 0x10C // KBL-H only +#define N_PCH_PCR_FIA_DRCRM_GBEPCKRQM 23 +#define S_PCH_PCR_FIA_DRCRM_BITS_PER_FIELD 4 // CLKREQ number is encoded in 4 bits +#define S_PCH_PCR_FIA_DRCRM_FIELDS_PER_REG 8 // each DRCRM register contains bitfields for 8 rootports +#define V_PCH_PCR_FIA_DRCRM_NO_CLKREQ 0 // ClkReq not present +#define S_PCH_PCR_FIA_DRCRM 4 +#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28) +#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28 +#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204 +#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208 +#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C +#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210 +#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214 +#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218 +#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C +#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220 +#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250 +#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254 +#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258 +#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C +#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0 +#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1 +#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2 +#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3 +#define V_PCH_PCR_FIA_LANE_OWN_MOBEXP 0x4 +#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5 +#define V_PCH_PCR_FIA_LANE_OWN_CSI3 0x6 +#define V_PCH_PCR_FIA_LANE_OWN_UFS 0x7 +#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L26O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L27O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L28O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L29O (BIT23 | BIT22 | BIT21 | BIT20) +#define PCH_H_FIA_DMILANE_START 14 +#define PCH_H_FIA_DMILANE_END 17 +#define PCH_FIA_MAX_LANES 34 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h new file mode 100644 index 0000000000..a6b2c4a8e5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h @@ -0,0 +1,529 @@ +/** @file + Register names for PCH GPIO + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_GPIO_H_ +#define _PCH_REGS_GPIO_H_ + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_GPIO_GPP_E_PAD_MAX V_PCH_LP_GPIO_GPP_E_PAD_MAX +#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_GPIO_GPP_G_PAD_MAX V_PCH_H_GPIO_GPP_G_PAD_MAX +#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11 +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define V_PCH_GPIO_GROUP_MAX 10 +#define V_PCH_H_GPIO_GROUP_MAX 10 +#define V_PCH_LP_GPIO_GROUP_MAX 8 +#define V_PCH_GPIO_NUM_SUPPORTED_GPIS 204 +#define S_PCH_GPIO_GP_SMI_EN 4 +#define S_PCH_GPIO_GP_SMI_STS 4 + +/// +/// Groups mapped to 2-tier General Purpose Event will all be under +/// one master GPE_111 (0x6F) +/// +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F + + +// +// GPIO Common Private Configuration Registers +// +#define R_PCH_PCR_GPIO_REV_ID 0x00 +#define R_PCH_PCR_GPIO_CAP_LIST 0x04 +#define R_PCH_PCR_GPIO_FAMBAR 0x08 +#define R_PCH_PCR_GPIO_PADBAR 0x0C +#define B_PCH_PCR_GPIO_PADBAR 0x0000FFFF +#define R_PCH_PCR_GPIO_MISCCFG 0x10 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 16 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 12 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 8 +#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3 +#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3 +#define B_PCH_PCR_GPIO_MISCCFG_GPDPCGEN BIT1 +#define B_PCH_PCR_GPIO_MISCCFG_GPDLCGEN BIT0 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14 + +// +// GPIO Community 0 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC +// SKL PCH-H +#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x70 +#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x74 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x90 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x94 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x98 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x9C +// Common +#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0xD0 +#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0xD4 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0120 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0124 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0140 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0160 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0164 +#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 +#define R_PCH_PCR_GPIO_GPP_A_NMI_STS 0x01C0 +#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x01C4 +#define R_PCH_PCR_GPIO_GPP_A_NMI_EN 0x01E0 +#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x01E4 +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 1 Private Configuration Registers +// +//SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40 +#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0 +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4 +//SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x40 +#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x4C +#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x70 +#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x74 +#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x78 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x7C +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x90 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x94 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x98 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x9C +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0xA0 +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xA4 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0xA8 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xAC +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0xB0 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xB4 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0xB8 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0xBC +// Common: +#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0xD0 +#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0xD4 +#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0xD8 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0xDC +#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0xE0 +#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0xE4 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x010C +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0114 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0120 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0124 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0128 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x012C +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0134 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0140 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0148 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x014C +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0150 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0154 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0160 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0164 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0168 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x016C +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0170 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0174 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_SMI_STS 0x018C +#define R_PCH_H_PCR_GPIO_GPP_G_SMI_STS 0x0190 +#define R_PCH_H_PCR_GPIO_GPP_H_SMI_STS 0x0194 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_SMI_EN 0x01AC +#define R_PCH_H_PCR_GPIO_GPP_G_SMI_EN 0x01B0 +#define R_PCH_H_PCR_GPIO_GPP_H_SMI_EN 0x01B4 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x01C0 +#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x01C4 +#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x01C8 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_NMI_STS 0x01CC +#define R_PCH_H_PCR_GPIO_GPP_G_NMI_STS 0x01D0 +#define R_PCH_H_PCR_GPIO_GPP_H_NMI_STS 0x01D4 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x01E0 +#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x01E4 +#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x01E8 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_NMI_EN 0x01EC +#define R_PCH_H_PCR_GPIO_GPP_G_NMI_EN 0x01F0 +#define R_PCH_H_PCR_GPIO_GPP_H_NMI_EN 0x01F4 +// Common: +#define R_PCH_PCR_GPIO_CAP_LIST_1_PWM 0x0200 +#define R_PCH_PCR_GPIO_PWMC 0x0204 +#define R_PCH_PCR_GPIO_CAP_LIST_2_SER_BLINK 0x0208 +#define R_PCH_PCR_GPIO_GP_SER_BLINK 0x020C +#define B_PCH_PCR_GPIO_GP_SER_BLINK 0x1F +#define R_PCH_PCR_GPIO_GP_SER_CMDSTS 0x0210 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS (BIT23 | BIT22) +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS 22 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 0x003F0000 +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 16 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_BUSY BIT8 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_GO BIT0 +#define R_PCH_PCR_GPIO_GP_SER_DATA 0x0210 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GSX 0x218 +#define R_PCH_H_PCR_GPIO_GSX_CAP 0x21C +#define R_PCH_H_PCR_GPIO_GSX_C0CAP_DW0 0x220 +#define R_PCH_H_PCR_GPIO_GSX_C0CAP_DW1 0x224 +#define R_PCH_H_PCR_GPIO_GSX_C0GPILVL_DW0 0x228 +#define R_PCH_H_PCR_GPIO_GSX_C0GPILVL_DW1 0x22C +#define R_PCH_H_PCR_GPIO_GSX_C0GPOLVL_DW0 0x230 +#define R_PCH_H_PCR_GPIO_GSX_C0GPOLVL_DW1 0x234 +#define R_PCH_H_PCR_GPIO_GSX_C0CMD 0x238 +#define R_PCH_H_PCR_GPIO_GSX_C0CTM 0x23C +// Common: +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x5E8 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x6A8 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x768 + +// +// GPIO Community 2 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x70 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x90 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x94 +// Common: +#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0xD0 +#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0120 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0140 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0160 +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 +// +// GPIO Community 3 Private Configuration Registers +// +// SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0 +#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x70 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x90 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x94 +#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0xD0 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0140 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0160 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0180 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x01A0 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x01C0 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x01E0 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400 + +// +// Define Pad Number +// +#define V_GPIO_PAD0 0 +#define V_GPIO_PAD1 1 +#define V_GPIO_PAD2 2 +#define V_GPIO_PAD3 3 +#define V_GPIO_PAD4 4 +#define V_GPIO_PAD5 5 +#define V_GPIO_PAD6 6 +#define V_GPIO_PAD7 7 +#define V_GPIO_PAD8 8 +#define V_GPIO_PAD9 9 +#define V_GPIO_PAD10 10 +#define V_GPIO_PAD11 11 +#define V_GPIO_PAD12 12 +#define V_GPIO_PAD13 13 +#define V_GPIO_PAD14 14 +#define V_GPIO_PAD15 15 +#define V_GPIO_PAD16 16 +#define V_GPIO_PAD17 17 +#define V_GPIO_PAD18 18 +#define V_GPIO_PAD19 19 +#define V_GPIO_PAD20 20 +#define V_GPIO_PAD21 21 +#define V_GPIO_PAD22 22 +#define V_GPIO_PAD23 23 + +// +// Host Software Pad Ownership modes +// +#define V_PCH_PCR_GPIO_HOSTSW_OWN_ACPI 0x00 +#define V_PCH_PCR_GPIO_HOSTSW_OWN_GPIO 0x01 + +// +// Pad Ownership modes +// +#define V_PCH_PCR_GPIO_PAD_OWN_HOST 0x00 +#define V_PCH_PCR_GPIO_PAD_OWN_CSME 0x01 +#define V_PCH_PCR_GPIO_PAD_OWN_ISH 0x02 + +// +// Pad Configuration Register DW0 +// + +//Pad Reset Config +#define B_PCH_GPIO_RST_CONF (BIT31 | BIT30) +#define N_PCH_GPIO_RST_CONF 30 +#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00 +#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01 +#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02 +#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group + +//RX Pad State Select +#define B_PCH_GPIO_RX_PAD_STATE BIT29 +#define N_PCH_GPIO_RX_PAD_STATE 29 +#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00 +#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01 + +//RX Raw Overrride to 1 +#define B_PCH_GPIO_RX_RAW1 BIT28 +#define N_PCH_GPIO_RX_RAW1 28 +#define V_PCH_GPIO_RX_RAW1_DIS 0x00 +#define V_PCH_GPIO_RX_RAW1_EN 0x01 + +//RX Level/Edge Configuration +#define B_PCH_GPIO_RX_LVL_EDG (BIT26 | BIT25) +#define N_PCH_GPIO_RX_LVL_EDG 25 +#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00 +#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01 +#define V_PCH_GPIO_RX_LVL_EDG_0 0x02 +#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03 + +//RX Invert +#define B_PCH_GPIO_RXINV BIT23 +#define N_PCH_GPIO_RXINV 23 +#define V_PCH_GPIO_RXINV_NO 0x00 +#define V_PCH_GPIO_RXINV_YES 0x01 + +//GPIO Input Route IOxAPIC +#define B_PCH_GPIO_RX_APIC_ROUTE BIT20 +#define N_PCH_GPIO_RX_APIC_ROUTE 20 +#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 + +//GPIO Input Route SCI +#define B_PCH_GPIO_RX_SCI_ROUTE BIT19 +#define N_PCH_GPIO_RX_SCI_ROUTE 19 +#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 + +//GPIO Input Route SMI +#define B_PCH_GPIO_RX_SMI_ROUTE BIT18 +#define N_PCH_GPIO_RX_SMI_ROUTE 18 +#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01 + +//GPIO Input Route NMI +#define B_PCH_GPIO_RX_NMI_ROUTE BIT17 +#define N_PCH_GPIO_RX_NMI_ROUTE 17 +#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01 + +//GPIO Pad Mode +#define B_PCH_GPIO_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_PAD_MODE 10 +#define V_PCH_GPIO_PAD_MODE_GPIO 0 +#define V_PCH_GPIO_PAD_MODE_NAT_1 1 +#define V_PCH_GPIO_PAD_MODE_NAT_2 2 +#define V_PCH_GPIO_PAD_MODE_NAT_3 3 +#define V_PCH_GPIO_PAD_MODE_NAT_4 4 // SPT-H only + +//GPIO RX Disable +#define B_PCH_GPIO_RXDIS BIT9 +#define N_PCH_GPIO_RXDIS 9 +#define V_PCH_GPIO_RXDIS_EN 0x00 +#define V_PCH_GPIO_RXDIS_DIS 0x01 + +//GPIO TX Disable +#define B_PCH_GPIO_TXDIS BIT8 +#define N_PCH_GPIO_TXDIS 8 +#define V_PCH_GPIO_TXDIS_EN 0x00 +#define V_PCH_GPIO_TXDIS_DIS 0x01 + +//GPIO RX State +#define B_PCH_GPIO_RX_STATE BIT1 +#define N_PCH_GPIO_RX_STATE 1 +#define V_PCH_GPIO_RX_STATE_LOW 0x00 +#define V_PCH_GPIO_RX_STATE_HIGH 0x01 + +//GPIO TX State +#define B_PCH_GPIO_TX_STATE BIT0 +#define N_PCH_GPIO_TX_STATE 0 +#define V_PCH_GPIO_TX_STATE_LOW 0x00 +#define V_PCH_GPIO_TX_STATE_HIGH 0x01 + +// +// Pad Configuration Register DW1 +// + +//Padtol +#define B_PCH_GPIO_PADTOL BIT25 +#define N_PCH_GPIO_PADTOL 25 +#define V_PCH_GPIO_PADTOL_NONE 0x00 +#define V_PCH_GPIO_PADTOL_CLEAR 0x00 +#define V_PCH_GPIO_PADTOL_SET 0x01 + +//Termination +#define B_PCH_GPIO_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_TERM 10 +#define V_PCH_GPIO_TERM_WPD_NONE 0x00 +#define V_PCH_GPIO_TERM_WPD_5K 0x02 +#define V_PCH_GPIO_TERM_WPD_20K 0x04 +#define V_PCH_GPIO_TERM_WPU_NONE 0x08 +#define V_PCH_GPIO_TERM_WPU_1K 0x09 +#define V_PCH_GPIO_TERM_WPU_2K 0x0B +#define V_PCH_GPIO_TERM_WPU_5K 0x0A +#define V_PCH_GPIO_TERM_WPU_20K 0x0C +#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D +#define V_PCH_GPIO_TERM_NATIVE 0x0F + +//Interrupt number +#define B_PCH_GPIO_INTSEL 0x7F +#define N_PCH_GPIO_INTSEL 0 + +// +// Ownership +// +#define V_PCH_GPIO_OWN_GPIO 0x01 +#define V_PCH_GPIO_OWN_ACPI 0x00 + +// +// GPE +// +#define V_PCH_GPIO_GPE_EN 0x01 +#define V_PCH_GPIO_GPE_DIS 0x00 +// +// SMI +// +#define V_PCH_GPIO_SMI_EN 0x01 +#define V_PCH_GPIO_SMI_DIS 0x00 +// +// NMI +// +#define V_PCH_GPIO_NMI_EN 0x01 +#define V_PCH_GPIO_NMI_DIS 0x00 +// +// Reserved: RSVD1 +// +#define V_PCH_GPIO_RSVD1 0x00 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHda.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHda.h new file mode 100644 index 0000000000..1d5c0e9e76 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHda.h @@ -0,0 +1,201 @@ +/** @file + Register names for PCH High Definition Audio device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// HD-A Controller Registers (D31:F3) +// +// PCI Configuration Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_HDA 31 +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 + +#define R_PCH_HDA_PI 0x09 +#define V_PCH_HDA_PI_ADSP_UAA 0x80 +#define R_PCH_HDA_SCC 0x0A +#define V_PCH_HDA_SCC_ADSP 0x01 +#define R_PCH_HDA_HDALBA 0x10 +#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000 +#define V_PCH_HDA_HDBAR_SIZE (1 << 14) +#define R_PCH_HDA_HDAUBA 0x14 +#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_SROTCGE BIT18 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define R_PCH_HDA_PC 0x52 +#define V_PCH_HDA_PC_PMES 0x18 +#define N_PCH_HDA_PC_PMES 11 +#define R_PCH_HDA_PCS 0x54 +#define B_PCH_HDA_PCS_PMEE BIT8 +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) +#define R_PCH_HDA_MMC 0x62 +#define B_PCH_HDA_MMC_ME BIT0 +#define R_PCH_HDA_DEVC 0x78 +#define B_PCH_HDA_DEVC_NSNPEN BIT11 +#define R_PCH_HDA_SEM1 0xC0 +#define B_PCH_HDA_SEM1_LFLCS BIT24 +#define B_PCH_HDA_SEM1_BLKC3DIS BIT17 +#define B_PCH_HDA_SEM1_TMODE BIT12 +#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9) +#define R_PCH_HDA_SEM2 0xC4 +#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26) +#define V_PCH_HDA_SEM2_BSMT 0x1 +#define N_PCH_HDA_SEM2_BSMT 26 +#define B_PCH_HDA_SEM2_VC0PSNR BIT24 +#define B_PCH_HDA_SEM2_DUM BIT23 +#define R_PCH_HDA_SEM3L 0xC8 +#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2 +#define N_PCH_HDA_SEM3L_ISL1EXT2 20 +#define R_PCH_HDA_SEM4L 0xD0 +#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3 +#define N_PCH_HDA_SEM4L_OSL1EXT2 20 + +// +// Memory Space Registers +// +// +// Resides in 'HD Audio Global Registers' (0000h) +// +#define R_PCH_HDABA_GCAP 0x00 +#define R_PCH_HDABA_GCTL 0x08 +#define B_PCH_HDABA_GCTL_CRST BIT0 + +#define R_PCH_HDABA_OUTPAY 0x04 +#define R_PCH_HDABA_INPAY 0x06 +#define V_PCH_HDABA_INPAY_DEFAULT 0x1C + +#define R_PCH_HDABA_WAKEEN 0x0C +#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3 +#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2 +#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1 +#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0 + +#define R_PCH_HDABA_WAKESTS 0x0E +#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3 +#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2 +#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1 +#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0 + +// +// Resides in 'HD Audio Controller Registers' (0030h) +// +#define R_PCH_HDABA_IC 0x60 +#define R_PCH_HDABA_IR 0x64 +#define R_PCH_HDABA_ICS 0x68 +#define B_PCH_HDABA_ICS_IRV BIT1 +#define B_PCH_HDABA_ICS_ICB BIT0 + +// +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +// +#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe Capability Structure (Memory Space, offset 0800h) +#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04) +#define B_PCH_HDABA_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define V_PCH_HDA_HDALINK_INDEX 0 +#define V_PCH_HDA_IDISPLINK_INDEX 1 + +#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h) +#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_PCH_HDABA_LCTLX_CPA BIT23 +#define B_PCH_HDABA_LCTLX_SPA BIT16 +#define N_PCH_HDABA_LCTLX_SCF 0 +#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0 +#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1 +#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2 +#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3 +#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4 + +// +// Resides in 'HD Audio Vendor Specific Registers' (1000h) +// +#define R_PCH_HDABA_LTRC 0x1048 +#define V_PCH_HDABA_LTRC_GB 0x29 +#define N_PCH_HDABA_LTRC_GB 0 +#define R_PCH_HDABA_PCE 0x104B +#define B_PCH_HDABA_PCE_D3HE BIT2 + +// +// Private Configuration Space Registers +// +// +// Resides in IOSF & Fabric Configuration Registers (000h) +// +#define R_PCH_PCR_HDA_TTCCFG 0xE4 +#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1 + +// +// Resides in PCI & Codec Configuration Registers (500h) +// +#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Configuration Registers (PCR, offset 500h) +#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00 +#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8 +#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x30) +#define B_PCH_PCR_HDA_FNCFG_PGD BIT5 +#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4 +#define B_PCH_PCR_HDA_FNCFG_CGD BIT3 +#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2 +#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0 +#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x34) +#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2 + +// +// Resides in Power Management & EBB Configuration Registers (600h) +// +#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management & EBB Configuration Registers (PCR, offset 600h) +#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG + 0x10) +#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000 +#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG + 0x14) +#define V_PCH_PCR_HDA_APLLP1 0x00001E00 +#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG + 0x18) +#define V_PCH_PCR_HDA_APLLP2 0x0000011D +#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG + 0x1C) +#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8) +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3 +#define N_PCH_PCR_HDA_IOBCTL_OSEL 8 +#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1 +#define R_PCH_PCR_HDA_PTDC (R_PCH_PCR_HDA_PWRMANCFG + 0x28) +#define B_PCH_PCR_HDA_PTDC_SRMIW (BIT6 | BIT5 | BIT4) +#define V_PCH_PCR_HDA_PTDC_SRMIW_256XTAL 0x6 +#define N_PCH_PCR_HDA_PTDC_SRMIW 4 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h new file mode 100644 index 0000000000..faa938e5a5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h @@ -0,0 +1,185 @@ +/** @file + Register definition for HSIO + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_HSIO_H_ +#define _PCH_REGS_HSIO_H_ + +#define B_PCH_HSIO_ACCESS_TYPE (BIT15 | BIT14) +#define N_PCH_HSIO_ACCESS_TYPE 14 +#define V_PCH_HSIO_ACCESS_TYPE_BDCAST (BIT15 | BIT14) +#define V_PCH_HSIO_ACCESS_TYPE_MULCAST BIT15 +#define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_HSIO_FUNCTION_NO (BIT8 | BIT7) +#define N_PCH_HSIO_FUNCTION_NO 7 +#define B_PCH_HSIO_REG_OFFSET (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define V_PCH_HSIO_ACCESS_TYPE_BCAST 0x03 +#define V_PCH_HSIO_ACCESS_TYPE_MCAST 0x02 +#define V_PCH_HSIO_ACCESS_TYPE_UCAST 0x00 + +#define V_PCH_HSIO_LANE_GROUP_NO_CMN_LANE 0x00 + +#define V_PCH_HSIO_FUNCTION_NO_PCS 0x00 +#define V_PCH_HSIO_FUNCTION_NO_TX 0x01 +#define V_PCH_HSIO_FUNCTION_NO_RX 0x02 + +#define V_PCH_HSIO_FUNCTION_NO_CMNDIG 0x00 +#define V_PCH_HSIO_FUNCTION_NO_CMNANA 0x01 +#define V_PCH_HSIO_FUNCTION_NO_PLL 0x02 + +#define R_PCH_HSIO_PCS_DWORD0 0x0 + +#define R_PCH_HSIO_PCS_DWORD1 0x4 + +#define R_PCH_HSIO_PCS_DWORD4 0x10 + +#define R_PCH_HSIO_PCS_DWORD8 0x20 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8 + +#define R_PCH_HSIO_PCS_DWORD9 0x24 +#define B_PCH_HSIO_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29 + +#define R_PCH_HSIO_RX_DWORD8 0x120 +#define B_PCH_HSIO_RX_DWORD8_ICFGDFETAP3_EN BIT10 + +#define R_PCH_HSIO_RX_DWORD9 0x124 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30 + +#define R_PCH_HSIO_RX_DWORD12 0x130 +#define B_PCH_HSIO_RX_DWORD12_O_CFGEWMARGINSEL BIT14 + +#define R_PCH_HSIO_RX_DWORD15 0x13C + +#define R_PCH_HSIO_RX_DWORD20 0x150 +#define B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24 + +#define R_PCH_HSIO_RX_DWORD21 0x154 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0 + +#define R_PCH_HSIO_RX_DWORD23 0x15C +#define B_PCH_HSIO_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2 +#define B_PCH_HSIO_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4 + +#define R_PCH_HSIO_RX_DWORD25 0x164 +#define B_PCH_HSIO_RX_DWORD25_RX_TAP_CFG_CTRL BIT3 +#define B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000 +#define N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16 + +#define R_PCH_HSIO_RX_DWORD26 0x168 +#define B_PCH_HSIO_RX_DWORD26_SATA_EQ_DIS BIT16 + +#define R_PCH_HSIO_RX_DWORD34 0x188 +#define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12) +#define N_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12 + +#define R_PCH_HSIO_RX_DWORD44 0x1B0 +#define B_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000 +#define N_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16 + +#define R_PCH_HSIO_RX_DWORD56 0x1E0 +#define B_PCH_HSIO_RX_DWORD56_ICFGPIDACCFGVALID BIT16 + +#define R_PCH_HSIO_RX_DWORD57 0x1E4 +#define B_PCH_HSIO_RX_DWORD57_JIM_COURSE BIT30 +#define B_PCH_HSIO_RX_DWORD57_JIM_ENABLE BIT29 +#define B_PCH_HSIO_RX_DWORD57_JIMMODE BIT28 +#define B_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000 +#define N_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 24 +#define B_PCH_HSIO_RX_DWORD57_ICFGMARGINEN BIT0 + +#define R_PCH_HSIO_RX_DWORD59 0x1EC +#define R_PCH_HSIO_RX_DWORD60 0x1F0 + +#define R_PCH_HSIO_TX_DWORD5 0x94 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8 + +#define R_PCH_HSIO_TX_DWORD6 0x98 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define R_PCH_HSIO_TX_DWORD8 0xA0 +#define B_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 24 +#define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 16 +#define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 8 + +#define R_PCH_HSIO_TX_DWORD19 0xCC + +#define R_PCH_HSIO_TX_DWORD23 0xDC + +#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020 +#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220 +#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820 +#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020 +#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220 +#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420 +#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620 +#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20 +#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20 + +#define R_PCH_HSIO_CLANE0_CMN_ANA_DWORD2 0x8088 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN BIT5 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDEN BIT3 + +#define R_PCH_HSIO_PLL_SSC_DWORD2 0x8108 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN BIT10 +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN 10 + +#define R_PCH_HSIO_PLL_SSC_DWORD3 0x810C +#define B_PCH_HSIO_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0 + +#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030 +#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0 + +// +// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/write access +// +#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0 +#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000 +#define R_PCH_PCR_MMP0_IMPREG21 0x1050 +#define R_PCH_PCR_MMP0_IMPREG22 0x1054 +#define R_PCH_PCR_MMP0_IMPREG23 0x1058 +#define R_PCH_PCR_MMP0_IMPREG24 0x105C +#define R_PCH_PCR_MMP0_IMPREG25 0x1060 +#define R_PCH_PCR_MMP0_CMNREG4 0xF00C +#define R_PCH_PCR_MMP0_CMNREG15 0xF038 +#define R_PCH_PCR_MMP0_CMNREG16 0xF03C + +#endif //_PCH_REGS_HSIO_H_ + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h new file mode 100644 index 0000000000..687a153f30 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h @@ -0,0 +1,74 @@ +/** @file + Register names for PCH Integrated Sensor Hub (ISH3.0) + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_ISH_H_ +#define _PCH_REGS_ISH_H_ + +// +// ISH Controller Registers (D19:F0) +// +// PCI Configuration Space Registers +#define PCI_DEVICE_NUMBER_PCH_ISH 19 +#define PCI_FUNCTION_NUMBER_PCH_ISH 0 + +#define R_PCH_ISH_BAR0_LOW 0x10 +#define R_PCH_ISH_BAR0_HIGH 0x14 +#define V_PCH_ISH_BAR0_SIZE 0x100000 +#define N_PCH_ISH_BAR0_ALIGNMENT 20 +#define R_PCH_ISH_BAR1_LOW 0x18 +#define R_PCH_ISH_BAR1_HIGH 0x1C +#define V_PCH_ISH_BAR1_SIZE 0x1000 +#define N_PCH_ISH_BAR1_ALIGNMENT 12 + +// +// ISH Private Configuration Space Registers (IOSF2OCP) +// (PID:ISH) +// +#define R_PCH_PCR_ISH_PMCTL 0x1D0 ///< Power Management +#define R_PCH_PCR_ISH_PCICFGCTRL 0x200 ///< PCI Configuration Control +#define B_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_ISH_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin +#define N_PCH_PCR_ISH_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_ISH_PCICFGCTRL_BAR1DIS BIT7 ///< BAR1 Disable + +// +// Number of pins used by ISH controllers +// +#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2 +#define PCH_ISH_PINS_PER_UART_CONTROLLER 4 +#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsItss.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsItss.h new file mode 100644 index 0000000000..21269155b5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsItss.h @@ -0,0 +1,94 @@ +/** @file + Register names for ITSS + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_ITSS_H_ +#define _PCH_REGS_ITSS_H_ + +// +// ITSS PCRs (PID:ITSS) +// +#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100 ///< PIRQA Routing Control register +#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101 ///< PIRQB Routing Control register +#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102 ///< PIRQC Routing Control register +#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103 ///< PIRQD Routing Control register +#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104 ///< PIRQE Routing Control register +#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105 ///< PIRQF Routing Control register +#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 ///< PIRQG Routing Control register +#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 ///< PIRQH Routing Control register +#define B_PCH_PCR_ITSS_PIRQX_ROUT_REN 0x80 ///< Interrupt Routing Enable +#define B_PCH_PCR_ITSS_PIRQX_ROUT_IR 0x0F ///< IRQ Routng +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx to IRQ3 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx to IRQ4 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx to IRQ5 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx to IRQ6 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx to IRQ7 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx to IRQ9 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx to IRQ10 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx to IRQ11 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx to IRQ12 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx to IRQ14 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx to IRQ15 + +#define R_PCH_PCR_ITSS_PIR0 0x3140 ///< PCI Interrupt Route 0 +#define R_PCH_PCR_ITSS_PIR1 0x3142 ///< PCI Interrupt Route 1 +#define R_PCH_PCR_ITSS_PIR2 0x3144 ///< PCI Interrupt Route 2 +#define R_PCH_PCR_ITSS_PIR3 0x3146 ///< PCI Interrupt Route 3 +#define R_PCH_PCR_ITSS_PIR4 0x3148 ///< PCI Interrupt Route 4 +#define R_PCH_PCR_ITSS_PIR5 0x314A ///< PCI Interrupt Route 5 +#define R_PCH_PCR_ITSS_PIR6 0x314C ///< PCI Interrupt Route 6 +#define R_PCH_PCR_ITSS_PIR7 0x314E ///< PCI Interrupt Route 7 +#define R_PCH_PCR_ITSS_PIR8 0x3150 ///< PCI Interrupt Route 8 +#define R_PCH_PCR_ITSS_PIR9 0x3152 ///< PCI Interrupt Route 9 +#define R_PCH_PCR_ITSS_PIR10 0x3154 ///< PCI Interrupt Route 10 +#define R_PCH_PCR_ITSS_PIR11 0x3156 ///< PCI Interrupt Route 11 +#define R_PCH_PCR_ITSS_PIR12 0x3158 ///< PCI Interrupt Route 12 + +#define R_PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control +#define B_PCH_PCR_ITSS_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size +#define B_PCH_PCR_ITSS_GIC_AME BIT17 ///< Alternate Access Mode Enable +#define B_PCH_PCR_ITSS_GIC_SPS BIT16 ///< Shutdown Policy Select +#define R_PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0 +#define R_PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1 +#define R_PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2 +#define R_PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3 +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 ///< ITSS Power Reduction Control +#define B_PCH_PCR_ITSS_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynamic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynamic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE BIT2 ///< 8254 Static Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband Interface Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate Enable + +#define R_PCH_PCR_ITSS_MMC 0x3334 ///< Master Message Control +#define B_PCH_PCR_ITSS_MMC_MSTRMSG_EN BIT0 ///< Master Message Enable + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLan.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLan.h new file mode 100644 index 0000000000..bb4c2c15a9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLan.h @@ -0,0 +1,148 @@ +/** @file + Register names for PCH LAN device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// Gigabit LAN Controller configuration registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LAN 31 +#define PCI_FUNCTION_NUMBER_PCH_LAN 6 + +#define R_PCH_LAN_MBARA 0x10 +#define B_PCH_LAN_MBARA_BA 0xFFFE0000 +#define N_PCH_LAN_MBARA_ALIGN 17 +#define R_PCH_LAN_LTR_CAP 0xA8 +#define R_PCH_LAN_CLIST1 0xC8 +#define B_PCH_LAN_CLIST1_NEXT 0xFF00 +#define B_PCH_LAN_CLIST1_CID 0x00FF +#define R_PCH_LAN_PMC 0xCA +#define B_PCH_LAN_PMC_PMES 0xF800 +#define B_PCH_LAN_PMC_D2S BIT10 +#define B_PCH_LAN_PMC_D1S BIT9 +#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6) +#define B_PCH_LAN_PMC_DSI BIT5 +#define B_PCH_LAN_PMC_PMEC BIT3 +#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) +#define R_PCH_LAN_PMCS 0xCC +#define B_PCH_LAN_PMCS_PMES BIT15 +#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13) +#define B_PCH_LAN_PMCS_DSL 0x1E00 +#define V_PCH_LAN_PMCS_DSL0 0x0000 +#define V_PCH_LAN_PMCS_DSL3 0x0600 +#define V_PCH_LAN_PMCS_DSL4 0x0800 +#define V_PCH_LAN_PMCS_DSL7 0x0E00 +#define V_PCH_LAN_PMCS_DSL8 0x1000 +#define B_PCH_LAN_PMCS_PMEE BIT8 +#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0) +#define V_PCH_LAN_PMCS_PS0 0x00 +#define V_PCH_LAN_PMCS_PS3 0x03 +#define R_PCH_LAN_DR 0xCF +#define B_PCH_LAN_DR 0xFF +#define R_PCH_LAN_CLIST2 0xD0 +#define B_PCH_LAN_CLIST2_NEXT 0xFF00 +#define B_PCH_LAN_CLIST2_CID 0x00FF +#define R_PCH_LAN_MCTL 0xD2 +#define B_PCH_LAN_MCTL_CID BIT7 +#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_LAN_MCTL_MSIE BIT0 +#define R_PCH_LAN_MADDL 0xD4 +#define B_PCH_LAN_MADDL 0xFFFFFFFF +#define R_PCH_LAN_MADDH 0xD8 +#define B_PCH_LAN_MADDH 0xFFFFFFFF +#define R_PCH_LAN_MDAT 0xDC +#define B_PCH_LAN_MDAT 0xFFFFFFFF +#define R_PCH_LAN_FLRCAP 0xE0 +#define B_PCH_LAN_FLRCAP_NEXT 0xFF00 +#define B_PCH_LAN_FLRCAP_CID 0x00FF +#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13 +#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09 +#define R_PCH_LAN_FLRCLV 0xE2 +#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9 +#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8 +#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000 +#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF +#define R_PCH_LAN_DEVCTRL 0xE4 +#define B_PCH_LAN_DEVCTRL BIT0 +#define R_PCH_LAN_CPCE 0x80 +#define B_PCH_LAN_CPCE_HAE BIT5 +#define B_PCH_LAN_CPCE_SE BIT3 +#define B_PCH_LAN_CPCE_D3HE BIT2 +#define B_PCH_LAN_CPCE_I3E BIT1 +#define B_PCH_LAN_CPCE_PCMCRE BIT0 +#define R_PCH_LAN_CD0I3 0x84 +#define B_PCH_LAN_CD0I3_RR BIT3 +#define B_PCH_LAN_CD0I3_D0I3 BIT2 +#define R_PCH_LAN_CLCTL 0x94 +#define R_PCH_LAN_LANDISCTRL 0xA0 +#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0 +#define R_PCH_LAN_LOCKLANDIS 0xA4 +#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0 +// +// Gigabit LAN Capabilities and Status Registers (Memory space) +// +#define R_PCH_LAN_CSR_CTRL 0 +#define B_PCH_LAN_CSR_CTRL_MEHE BIT19 +#define R_PCH_LAN_CSR_STRAP 0x000C +#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11 +#define R_PCH_LAN_CSR_FEXTNVM6 0x0010 +#define R_PCH_LAN_CSR_CTRL_EXT 0x0018 +#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11 +#define R_PCH_LAN_CSR_MDIC 0x0020 +#define B_PCH_LAN_CSR_MDIC_RB BIT28 +#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF +#define R_PCH_LAN_CSR_FEXT 0x002C +#define B_PCH_LAN_CSR_FEXT_WOL BIT30 +#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31 +#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00 +#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5 +#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8 +#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10 +#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6 +#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1 +#define R_PCH_LAN_CSR_F18 0x0F18 +#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31 +#define R_PCH_LAN_CSR_PBECCSTS 0x100C +#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16 +#define R_PCH_LAN_CSR_RAL 0x5400 +#define R_PCH_LAN_CSR_RAH 0x5404 +#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF +#define R_PCH_LAN_CSR_WUC 0x5800 +#define B_PCH_LAN_CSR_WUC_APME BIT0 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h new file mode 100644 index 0000000000..7c6f639260 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h @@ -0,0 +1,610 @@ +/** @file + Register names for PCH LPC/eSPI device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +typedef enum { + PchHB0 = 0x01, + PchHC0, + PchHD0, + PchHD1, + PchLpB0 = 0x23, + PchLpB1, + PchLpC0, + PchLpC1, + KblPchHA0 = 0x40, + PchSteppingMax +} PCH_STEPPING; + +#define SKL_PCH_H_MIN_SUPPORTED_STEPPING PchHB0 +#define KBL_PCH_H_MIN_SUPPORTED_STEPPING KblPchHA0 +#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0 + +#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +// +// +// SKL PCH Server/WS LPC Device IDs +// +#define V_SKL_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Server SKU Intel C236 Chipset +#define V_SKL_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Server SKU Intel C232 Chipset +#define V_SKL_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Server SKU Intel CM236 Chipset +#define V_SKL_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Super SKU Unlocked + +// +// SKL PCH-H Desktop LPC Device IDs +// +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH H Desktop Super SKU unlocked +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH H Desktop Super SKU locked +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH H Desktop H110 +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH H Desktop H170 +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH H Desktop Z170 +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH H Desktop Q170 +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH H Desktop Q150 +#define V_SKL_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH H Desktop B150 +// +// SKL PCH-H Mobile LPC Device IDs +// +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH H Mobile Super SKU unlocked +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH H Mobile QM170 +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH H Mobile HM170 +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_3 0xA151 ///< PCH H Mobile QMS180 (SFF) +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_4 0xA152 ///< KBL PCH H Mobile HM175 +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_5 0xA153 ///< KBL PCH H Mobile QM175 +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_6 0xA154 ///< KBL PCH H Mobile CM238 +#define V_SKL_PCH_H_LPC_DEVICE_ID_MB_8 0xA156 ///< KBL PCH H Mobile QMS185 (SFF) + +// +// SKL PCH-LP LPC Device IDs +// +#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH LP Mobile Super SKU unlocked +#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH LP Mobile Super SKU locked +#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH LP Mobile (U) Base SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH LP Mobile (Y) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH LP Mobile (U) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU_1 0x9D51 ///< KBL PCH LP Mobile Super SKU unlocked +#define V_PCH_LP_LPC_DEVICE_ID_MB_4 0x9D52 ///< KBL PCH LP Mobile Super SKU locked +#define V_PCH_LP_LPC_DEVICE_ID_MB_5 0x9D53 ///< KBL PCH LP Mobile (U) Base SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_6 0x9D56 ///< KBL PCH LP Mobile (Y) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_7 0x9D58 ///< KBL PCH LP Mobile (U) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_8 0x9D4B ///< KBL PCH LP Mobile (Y) iHDCP 2.2 Premium +#define V_PCH_LP_LPC_DEVICE_ID_MB_9 0x9D4E ///< KBL PCH LP Mobile (U) iHDCP 2.2 Premium +#define V_PCH_LP_LPC_DEVICE_ID_MB_10 0x9D50 ///< KBL PCH LP Mobile (U) iHDCP 2.2 Base + + + +// +// KBL PCH Server/WS LPC Device IDs +// +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_ES_SUPER_SKU 0xA2D0 ///< ES Super SKU Unlocked. This is SKL-PCH-H in KBL-PCH-H package +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_SUPER_SKU 0xA2D1 ///< Super SKU Unlocked +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_0 0xA2D2 ///< Server SKU X290 +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_1 0xA2D3 ///< Server SKU C6xx +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_2 0xA2CE ///< Server SKU ES SuperSKU Server +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_3 0xA2CF ///< Server SKU SuperSKU Server +#define V_KBL_PCH_H_LPC_DEVICE_ID_SVR_4 0xA2D4 ///< Server SKU C422B + + +// +// KBL PCH-H Desktop LPC Device IDs +// +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_ES_SUPER_SKU 0xA2C0 ///< PCH H Desktop ES Super SKU unlocked. This is SKL-PCH-H in KBL-PCH-H package +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA2C1 ///< PCH H Desktop Super SKU unlocked +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_H270 0xA2C4 ///< PCH H Desktop H270 +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_Z270 0xA2C5 ///< PCH H Desktop Z270 +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_Q270 0xA2C6 ///< PCH H Desktop Q270 +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_Q250 0xA2C7 ///< PCH H Desktop Q250 +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_B250 0xA2C8 ///< PCH H Desktop B250 + +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_H215 0xA2C3 ///< PCH H Desktop H215 +#define V_KBL_PCH_H_LPC_DEVICE_ID_DT_Z370 0xA2C9 ///< PCH H Desktop Z370 + +#define V_PCH_LPC_RID_0 0x00 +#define V_PCH_LPC_RID_1 0x01 +#define V_PCH_LPC_RID_9 0x09 +#define V_PCH_LPC_RID_10 0x10 +#define V_PCH_LPC_RID_11 0x11 +#define V_PCH_LPC_RID_20 0x20 +#define V_PCH_LPC_RID_21 0x21 +#define V_PCH_LPC_RID_30 0x30 +#define V_PCH_LPC_RID_31 0x31 +#define R_PCH_LPC_SERIRQ_CNT 0x64 +#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80 +#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40 +#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C +#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2 +#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03 +#define N_PCH_LPC_SERIRQ_CNT_SFPW 0 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_PCH_LPC_IOD 0x80 +#define B_PCH_LPC_IOD_FDD 0x1000 +#define N_PCH_LPC_IOD_FDD 12 +#define V_PCH_LPC_IOD_FDD_3F0 0 +#define V_PCH_LPC_IOD_FDD_370 1 +#define B_PCH_LPC_IOD_LPT 0x0300 +#define N_PCH_LPC_IOD_LPT 8 +#define V_PCH_LPC_IOD_LPT_378 0 +#define V_PCH_LPC_IOD_LPT_278 1 +#define V_PCH_LPC_IOD_LPT_3BC 2 +#define B_PCH_LPC_IOD_COMB 0x0070 +#define N_PCH_LPC_IOD_COMB 4 +#define V_PCH_LPC_IOD_COMB_3F8 0 +#define V_PCH_LPC_IOD_COMB_2F8 1 +#define V_PCH_LPC_IOD_COMB_220 2 +#define V_PCH_LPC_IOD_COMB_228 3 +#define V_PCH_LPC_IOD_COMB_238 4 +#define V_PCH_LPC_IOD_COMB_2E8 5 +#define V_PCH_LPC_IOD_COMB_338 6 +#define V_PCH_LPC_IOD_COMB_3E8 7 +#define B_PCH_LPC_IOD_COMA 0x0007 +#define N_PCH_LPC_IOD_COMA 0 +#define V_PCH_LPC_IOD_COMA_3F8 0 +#define V_PCH_LPC_IOD_COMA_2F8 1 +#define V_PCH_LPC_IOD_COMA_220 2 +#define V_PCH_LPC_IOD_COMA_228 3 +#define V_PCH_LPC_IOD_COMA_238 4 +#define V_PCH_LPC_IOD_COMA_2E8 5 +#define V_PCH_LPC_IOD_COMA_338 6 +#define V_PCH_LPC_IOD_COMA_3E8 7 +#define R_PCH_LPC_IOE 0x82 +#define B_PCH_LPC_IOE_ME2 BIT13 ///< Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC +#define B_PCH_LPC_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC. +#define B_PCH_LPC_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC. +#define B_PCH_LPC_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC. +#define B_PCH_LPC_IOE_HGE BIT9 ///< High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC. +#define B_PCH_LPC_IOE_LGE BIT8 ///< Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC. +#define B_PCH_LPC_IOE_FDE BIT3 ///< Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE +#define B_PCH_LPC_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT. +#define B_PCH_LPC_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB. +#define B_PCH_LPC_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA. +#define R_PCH_LPC_GEN1_DEC 0x84 +#define R_PCH_LPC_GEN2_DEC 0x88 +#define R_PCH_LPC_GEN3_DEC 0x8C +#define R_PCH_LPC_GEN4_DEC 0x90 +#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000 +#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC +#define B_PCH_LPC_GENX_DEC_EN 0x00000001 +#define R_PCH_LPC_ULKMC 0x94 +#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15 +#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11 +#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10 +#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9 +#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8 +#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7 +#define B_PCH_LPC_ULKMC_PSTATE BIT6 +#define B_PCH_LPC_ULKMC_A20PASSEN BIT5 +#define B_PCH_LPC_ULKMC_USBSMIEN BIT4 +#define B_PCH_LPC_ULKMC_64WEN BIT3 +#define B_PCH_LPC_ULKMC_64REN BIT2 +#define B_PCH_LPC_ULKMC_60WEN BIT1 +#define B_PCH_LPC_ULKMC_60REN BIT0 +#define R_PCH_LPC_LGMR 0x98 +#define B_PCH_LPC_LGMR_MA 0xFFFF0000 +#define B_PCH_LPC_LGMR_LMRD_EN BIT0 + +#define R_PCH_LPC_FWH_BIOS_SEL 0xD0 +#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000 +#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000 +#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000 +#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000 +#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000 +#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00 +#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0 +#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F +#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4 +#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000 +#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00 +#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0 +#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F +#define R_PCH_LPC_BDE 0xD8 ///< BIOS decode enable +#define B_PCH_LPC_BDE_F8 0x8000 +#define B_PCH_LPC_BDE_F0 0x4000 +#define B_PCH_LPC_BDE_E8 0x2000 +#define B_PCH_LPC_BDE_E0 0x1000 +#define B_PCH_LPC_BDE_D8 0x0800 +#define B_PCH_LPC_BDE_D0 0x0400 +#define B_PCH_LPC_BDE_C8 0x0200 +#define B_PCH_LPC_BDE_C0 0x0100 +#define B_PCH_LPC_BDE_LEG_F 0x0080 +#define B_PCH_LPC_BDE_LEG_E 0x0040 +#define B_PCH_LPC_BDE_70 0x0008 +#define B_PCH_LPC_BDE_60 0x0004 +#define B_PCH_LPC_BDE_50 0x0002 +#define B_PCH_LPC_BDE_40 0x0001 +#define R_PCH_LPC_PCC 0xE0 +#define B_PCH_LPC_PCC_CLKRUN_EN 0x0001 +#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000 +#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400 +#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800 +#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002 +#define R_PCH_LPC_FVEC1 0x01 +#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000 +#define R_PCH_LPC_FVEC2 0x02 +#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability +#define R_PCH_LPC_FVEC3 0x03 +#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 ///< Data Center Manageability Interface (DCMI) Capability +#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 ///< Node Manager Capability + +#define R_PCH_LPC_MDAP 0xC0 +#define B_PCH_LPC_MDAP_POLICY_EN BIT31 +#define B_PCH_LPC_MDAP_PDMA_EN BIT30 +#define B_PCH_LPC_MDAP_VALUE 0x0001FFFF + +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +#define R_PCH_APM_STS 0xB3 + +#define R_PCH_LPC_BC 0xDC ///< Bios Control +#define S_PCH_LPC_BC 1 +#define B_PCH_LPC_BC_BILD BIT7 ///< BIOS Interface Lock-Down +#define B_PCH_LPC_BC_BBS BIT6 ///< Boot BIOS strap +#define N_PCH_LPC_BC_BBS 6 +#define V_PCH_LPC_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_PCH_LPC_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_PCH_LPC_BC_EISS BIT5 ///< Enable InSMM.STS +#define B_PCH_LPC_BC_TS BIT4 ///< Top Swap +#define B_PCH_LPC_BC_LE BIT1 ///< Lock Enable +#define N_PCH_LPC_BC_LE 1 +#define B_PCH_LPC_BC_WPD BIT0 ///< Write Protect Disable + +#define R_PCH_ESPI_PCBC 0xDC ///< Peripheral Channel BIOS Control +#define S_PCH_ESPI_PCBC 4 ///< Peripheral Channel BIOS Control register size +#define B_PCH_ESPI_PCBC_BWRE BIT11 ///< BIOS Write Report Enable +#define N_PCH_ESPI_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position +#define B_PCH_ESPI_PCBC_BWRS BIT10 ///< BIOS Write Report Status +#define N_PCH_ESPI_PCBC_BWRS 10 ///< BIOS Write Report Status bit position +#define B_PCH_ESPI_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status +#define N_PCH_ESPI_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position +#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap +#define B_PCH_ESPI_PCBC_LE BIT1 ///< Lock Enable +#define N_PCH_ESPI_PCBC_LE 1 + +// +// eSPI slave registers +// +#define R_ESPI_SLAVE_CHA_0_CAP_AND_CONF 0x10 ///< Channel 0 Capabilities and Configurations +#define B_ESPI_SLAVE_CHA_0_CAP_AND_CONF_BME BIT2 ///< Bus Master Enable + +// +// Processor interface registers +// +#define R_PCH_NMI_SC 0x61 +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_NMI_EN 0x70 +#define B_PCH_NMI_EN_NMI_EN BIT7 + +// +// Reset Generator I/O Port +// +#define R_PCH_RST_CNT 0xCF9 +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_PCH_RTC_INDEX 0x70 +#define R_PCH_RTC_TARGET 0x71 +#define R_PCH_RTC_EXT_INDEX 0x72 +#define R_PCH_RTC_EXT_TARGET 0x73 +#define R_PCH_RTC_INDEX_ALT 0x74 +#define R_PCH_RTC_TARGET_ALT 0x75 +#define R_PCH_RTC_EXT_INDEX_ALT 0x76 +#define R_PCH_RTC_EXT_TARGET_ALT 0x77 +#define R_PCH_RTC_REGA 0x0A +#define B_PCH_RTC_REGA_UIP 0x80 +#define R_PCH_RTC_REGB 0x0B +#define B_PCH_RTC_REGB_SET 0x80 +#define B_PCH_RTC_REGB_PIE 0x40 +#define B_PCH_RTC_REGB_AIE 0x20 +#define B_PCH_RTC_REGB_UIE 0x10 +#define B_PCH_RTC_REGB_DM 0x04 +#define B_PCH_RTC_REGB_HOURFORM 0x02 +#define R_PCH_RTC_REGC 0x0C +#define R_PCH_RTC_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_PCH_PCR_RTC_CONF 0x3400 ///< RTC Configuration register +#define S_PCH_PCR_RTC_CONF 4 +#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK BIT4 +#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK BIT3 +#define B_PCH_PCR_RTC_CONF_RESERVED BIT31 +#define B_PCH_PCR_RTC_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable +#define R_PCH_PCR_RTC_BUC 0x3414 ///< Backed Up Control +#define B_PCH_PCR_RTC_BUC_TS BIT0 ///< Top Swap +#define R_PCH_PCR_RTC_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control +#define R_PCH_PCR_RTC_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_3F00 0x3F00 +#define R_PCH_PCR_RTC_UIPSMI 0x3F04 ///< RTC Update In Progress SMI Control + +// +// LPC PCR Registers +// +#define R_PCH_PCR_LPC_HVMTCTL 0x3410 +#define R_PCH_PCR_LPC_GCFD 0x3418 +#define R_PCH_PCR_LPC_PRC 0x341C +#define R_PCH_PCR_LPC_PCT 0x3420 +#define R_PCH_PCR_LPC_SCT 0x3424 +#define R_PCH_PCR_LPC_LPCCT 0x3428 +#define R_PCH_PCR_LPC_ULTOR 0x3500 + +// +// eSPI PCR Registers +// +#define R_PCH_PCR_ESPI_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully) +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RD 0 ///< Slave Configuration register read from address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_WR 1 ///< Slave Configuration register write to address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_STS 2 ///< Slave Status register read +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RS 3 ///< In-Band reset +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address +#define R_PCH_PCR_ESPI_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data + +#define R_PCH_PCR_ESPI_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_PCERR_SLV1 0x4024 ///< Peripheral Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_VWERR_SLV1 0x4034 ///< Virtual Wire Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0 +#define B_PCH_PCR_ESPI_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XNFES BIT12 ///< Fatal Error Status +#define B_PCH_PCR_ESPI_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XFES BIT4 ///< Fatal Error Status +#define B_PCH_PCR_ESPI_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected +#define R_PCH_PCR_ESPI_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0 +#define S_PCH_PCR_ESPI_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size +#define B_PCH_PCR_ESPI_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable +#define N_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position +#define V_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status +#define R_PCH_PCR_ESPI_CFG_VAL 0xC00C ///< ESPI Enabled Strap +#define B_PCH_PCR_ESPI_ENABLE_STRAP BIT0 ///< ESPI Enabled Strap bit position + + + +// +// LPC Device ID macros +// +// +// Device IDs that are SKL PCH-H Desktop specific +// +#define IS_SKL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_0) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_1) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_2) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_3) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_4) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_5) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_6) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_ES_SUPER_SKU /* SKL-PCH-H in KBL-PCH-H package */) \ + ) + +// +// Device IDs that are KBL PCH-H Desktop specific +// +#define IS_KBL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_H215) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_Z370) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_H270) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_Z270) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_Q270) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_Q250) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_DT_B250) \ + ) + +// +// Device IDs that are PCH-H Desktop specific +// +#define IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_SKL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) || \ + IS_KBL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +// +// Device IDs that are PCH-H Mobile specific +// + +#define IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_3) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_4) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_5) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_6) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_MB_8) \ + ) + +// +// Device IDs that are PCH-LP Mobile specific +// +#define IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_2) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_3) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU_1) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_4) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_5) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_6) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_7) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_8) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_9) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_10) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +// +// Device IDS that are SKL PCH Server\Workstation specific +// +#define IS_SKL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_ES_SUPER_SKU) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId == V_SKL_PCH_H_LPC_DEVICE_ID_A14B) \ + ) + +// +// Device IDS that are KBL PCH Server\Workstation specific +// +#define IS_KBL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_SUPER_SKU) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_3) || \ + (DeviceId == V_KBL_PCH_H_LPC_DEVICE_ID_SVR_4) \ + ) + + +#define IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_KBL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) || \ + IS_SKL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_SKL_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_SKL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_SKL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_KBL_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_KBL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) || \ + IS_KBL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +#define IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ) + +#define IS_SKL_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_SKL_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) || \ + IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_SKL_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_KBL_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_KBL_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ) +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h new file mode 100644 index 0000000000..b2779ab0ce --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h @@ -0,0 +1,138 @@ +/** @file + Register names for PCH P2SB device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D31:F1) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + +#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_P2SB_SBREG_BAR 0x10 +#define B_PCH_P2SB_SBREG_RBA 0xFF000000 +#define R_PCH_P2SB_SBREG_BARH 0x14 +#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF +#define R_PCH_P2SB_VBDF 0x50 +#define B_PCH_P2SB_VBDF_BUF 0xFF00 +#define B_PCH_P2SB_VBDF_DEV 0x00F8 +#define B_PCH_P2SB_VBDF_FUNC 0x0007 +#define R_PCH_P2SB_ESMBDF 0x52 +#define B_PCH_P2SB_ESMBDF_BUF 0xFF00 +#define B_PCH_P2SB_ESMBDF_DEV 0x00F8 +#define B_PCH_P2SB_ESMBDF_FUNC 0x0007 +#define R_PCH_P2SB_RCFG 0x54 +#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00 +#define B_PCH_P2SB_RCFG_RSE BIT0 +#define R_PCH_P2SB_HPTC 0x60 +#define B_PCH_P2SB_HPTC_AE BIT7 +#define B_PCH_P2SB_HPTC_AS 0x0003 +#define N_PCH_HPET_ADDR_ASEL 12 +#define V_PCH_HPET_BASE0 0xFED00000 +#define V_PCH_HPET_BASE1 0xFED01000 +#define V_PCH_HPET_BASE2 0xFED02000 +#define V_PCH_HPET_BASE3 0xFED03000 +#define R_PCH_P2SB_IOAC 0x64 +#define B_PCH_P2SB_IOAC_AE BIT8 +#define B_PCH_P2SB_IOAC_ASEL 0x00FF +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define R_PCH_IO_APIC_EOI 0xFEC00040 +#define R_PCH_P2SB_IBDF 0x6C +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_80 0x80 +#define R_PCH_P2SB_84 0x84 +#define R_PCH_P2SB_88 0x88 +#define R_PCH_P2SB_8C 0x8C +#define R_PCH_P2SB_90 0x90 +#define R_PCH_P2SB_94 0x94 +#define R_PCH_P2SB_98 0x98 +#define R_PCH_P2SB_9C 0x9C + +#define R_PCH_P2SB_DISPBDF 0xA0 +#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000 +#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00 +#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8 +#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007 +#define R_PCH_P2SB_ICCOS 0xA4 +#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00 +#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF +#define R_PCH_P2SB_EPMASK0 0xB0 +#define R_PCH_P2SB_EPMASK1 0xB4 +#define R_PCH_P2SB_EPMASK2 0xB8 +#define R_PCH_P2SB_EPMASK3 0xBC +#define R_PCH_P2SB_EPMASK4 0xC0 +#define R_PCH_P2SB_EPMASK5 0xC4 +#define R_PCH_P2SB_EPMASK6 0xC8 +#define R_PCH_P2SB_EPMASK7 0xCC + +// +// Definition for SBI +// +#define R_PCH_P2SB_SBIADDR 0xD0 +#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000 +#define B_PCH_P2SB_SBIADDR_RS 0x000F0000 +#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF +#define R_PCH_P2SB_SBIDATA 0xD4 +#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF +#define R_PCH_P2SB_SBISTAT 0xD8 +#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00 +#define B_PCH_P2SB_SBISTAT_POSTED BIT7 +#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006 +#define N_PCH_P2SB_SBISTAT_RESPONSE 1 +#define B_PCH_P2SB_SBISTAT_INITRDY BIT0 +#define R_PCH_P2SB_SBIRID 0xDA +#define B_PCH_P2SB_SBIRID_FBE 0xF000 +#define B_PCH_P2SB_SBIRID_BAR 0x0700 +#define B_PCH_P2SB_SBIRID_FID 0x00FF +#define R_PCH_P2SB_SBIEXTADDR 0xDC +#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_PCH_P2SB_E0 0xE0 +#define R_PCH_P2SB_E4 0xE4 +#define R_PCH_P2SB_E8 0xE8 +#define R_PCH_P2SB_EA 0xEA +#define R_PCH_P2SB_F4 0xF4 +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h new file mode 100644 index 0000000000..704f77c52f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h @@ -0,0 +1,524 @@ +/** @file + Register names for PCH PCI-E root port devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +// +// PCH PCI Express Root Ports (D28:F0..7, D29:F0..7, D27:F0..7) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24 7 + +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express Root Port #1, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express Root Port #2, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express Root Port #3, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express Root Port #4, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express Root Port #5, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express Root Port #6, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express Root Port #7, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express Root Port #8, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express Root Port #9, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express Root Port #10, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express Root Port #11, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express Root Port #12, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express Root Port #13, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express Root Port #14, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express Root Port #15, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express Root Port #16, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express Root Port #17, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express Root Port #18, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express Root Port #19, SKL PCH H +#define V_SKL_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express Root Port #20, SKL PCH H + +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT1 0xA290 ///< PCI Express Root Port #1, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT2 0xA291 ///< PCI Express Root Port #2, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT3 0xA292 ///< PCI Express Root Port #3, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT4 0xA293 ///< PCI Express Root Port #4, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT5 0xA294 ///< PCI Express Root Port #5, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT6 0xA295 ///< PCI Express Root Port #6, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT7 0xA296 ///< PCI Express Root Port #7, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT8 0xA297 ///< PCI Express Root Port #8, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT9 0xA298 ///< PCI Express Root Port #9, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT10 0xA299 ///< PCI Express Root Port #10, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT11 0xA29A ///< PCI Express Root Port #11, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT12 0xA29B ///< PCI Express Root Port #12, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT13 0xA29C ///< PCI Express Root Port #13, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT14 0xA29D ///< PCI Express Root Port #14, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT15 0xA29E ///< PCI Express Root Port #15, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT16 0xA29F ///< PCI Express Root Port #16, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT17 0xA2E7 ///< PCI Express Root Port #17, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT18 0xA2E8 ///< PCI Express Root Port #18, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT19 0xA2E9 ///< PCI Express Root Port #19, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT20 0xA2EA ///< PCI Express Root Port #20, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT21 0xA2EB ///< PCI Express Root Port #21, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT22 0xA2EC ///< PCI Express Root Port #22, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT23 0xA2ED ///< PCI Express Root Port #23, KBL PCH H +#define V_KBL_PCH_H_PCIE_DEVICE_ID_PORT24 0xA2EE ///< PCI Express Root Port #24, KBL PCH H + + +#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express Root Port #1, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express Root Port #2, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express Root Port #3, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express Root Port #4, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express Root Port #5, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express Root Port #6, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express Root Port #7, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express Root Port #8, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express Root Port #9, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express Root Port #10, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express Root Port #11, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express Root Port #12, SKL PCH LP PCIe Device ID + +#define R_PCH_PCIE_CLIST 0x40 +#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PCIE_XCAP_OFFSET) +#define R_PCH_PCIE_DCAP (R_PCH_PCIE_CLIST + R_PCIE_DCAP_OFFSET) +#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PCIE_DCTL_OFFSET) +#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PCIE_DSTS_OFFSET) +#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PCIE_LCAP_OFFSET) +#define B_PCH_PCIE_LCAP_PN 0xFF000000 +#define N_PCH_PCIE_LCAP_PN 24 +#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PCIE_LCTL_OFFSET) +#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET) +#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PCIE_SLCAP_OFFSET) +#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PCIE_SLCTL_OFFSET) +#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PCIE_SLSTS_OFFSET) +#define R_PCH_PCIE_RCTL (R_PCH_PCIE_CLIST + R_PCIE_RCTL_OFFSET) +#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PCIE_RSTS_OFFSET) +#define R_PCH_PCIE_DCAP2 (R_PCH_PCIE_CLIST + R_PCIE_DCAP2_OFFSET) +#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PCIE_DCTL2_OFFSET) +#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PCIE_LCTL2_OFFSET) +#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PCIE_LSTS2_OFFSET) + + +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 + +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define R_PCH_PCIE_SVID 0x94 +#define S_PCH_PCIE_SVID 4 + +#define R_PCH_PCIE_PMCAP 0xA0 +#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PCIE_PMCS_OFFST) +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_MPC2_LSTP BIT6 +#define B_PCH_PCIE_MPC2_IEIME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2) +#define B_PCH_PCIE_MPC2_EOIFD BIT1 + +#define R_PCH_PCIE_MPC 0xD8 +#define S_PCH_PCIE_MPC 4 +#define B_PCH_PCIE_MPC_PMCE BIT31 +#define B_PCH_PCIE_MPC_HPCE BIT30 +#define B_PCH_PCIE_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_MPC_P8XDE BIT26 +#define B_PCH_PCIE_MPC_IRRCE BIT25 +#define B_PCH_PCIE_MPC_SRL BIT23 +#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18) +#define N_PCH_PCIE_MPC_UCEL 18 +#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15) +#define N_PCH_PCIE_MPC_CCEL 15 +#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13) +#define N_PCH_PCIE_MPC_PCIESD 13 +#define V_PCH_PCIE_MPC_PCIESD_GEN1 1 +#define V_PCH_PCIE_MPC_PCIESD_GEN2 2 +#define B_PCH_PCIE_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_MPC_HPME BIT1 +#define N_PCH_PCIE_MPC_HPME 1 +#define B_PCH_PCIE_MPC_PMME BIT0 + +#define R_PCH_PCIE_SMSCS 0xDC +#define S_PCH_PCIE_SMSCS 4 +#define B_PCH_PCIE_SMSCS_PMCS BIT31 +#define N_PCH_PCIE_SMSCS_LERSMIS 5 +#define N_PCH_PCIE_SMSCS_HPLAS 4 +#define N_PCH_PCIE_SMSCS_HPPDM 1 + +#define R_PCH_PCIE_RPDCGEN 0xE1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 + + +#define R_PCH_PCIE_PWRCTL 0xE8 +#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20 +#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17 +#define B_PCH_PCIE_PWRCTL_DBUPI BIT15 +#define B_PCH_PCIE_PWRCTL_TXSWING BIT13 +#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1 +#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0 + +#define R_PCH_PCIE_DC 0xEC +#define B_PCH_PCIE_DC_PCIBEM BIT2 + +#define R_PCH_PCIE_PHYCTL2 0xF5 +#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6) +#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) +#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4 +#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1 +#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0 + +#define R_PCH_PCIE_IOSFSBCS 0xF7 +#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6 +#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2) + +#define R_PCH_PCIE_STRPFUSECFG 0xFC +#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_PCIE_STRPFUSECFG_PXIP 24 +#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2 +#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3 +#define N_PCH_PCIE_STRPFUSECFG_RPC 14 +#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9 +#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8 +#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7 +#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6 +#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5 +#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4 +#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3 +#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header +#define V_PCH_PCIE_EX_AEC_CV 0x1 +#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_PCIE_EX_UEM_OFFSET) // Uncorrectable Error Mask + +#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable Error Status +#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Status +#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status +#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Error Status + + +//CES.RE, CES.BT, CES.BD + +#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended Capability Header +#define V_PCH_PCIE_EX_ACS_CV 0x1 +#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States Extended Capability Header +#define V_PCH_PCIE_EX_L1S_CV 0x1 +#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET) + +#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI Express Extended Capability Header +#define V_PCH_PCIE_EX_SPEECH_CV 0x1 + +#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LES_OFFSET) +#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EX_LECTL_UPTPH 12 +#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00 +#define N_PCH_PCIE_EX_LECTL_UPTP 8 +#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_EX_LECTL_DPTPH 4 +#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F +#define N_PCH_PCIE_EX_LECTL_DPTP 0 + +#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET) +#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET) + +#define R_PCH_PCIE_PCIERTP1 0x300 +#define R_PCH_PCIE_PCIERTP2 0x304 +#define R_PCH_PCIE_PCIENFTS 0x314 +#define R_PCH_PCIE_PCIEL0SC 0x318 + +#define R_PCH_PCIE_PCIECFG2 0x320 +#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30 +#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27 +#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24 +#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23 +#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22 +#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20) +#define V_PCH_PCIE_PCIECFG2_PMET 1 +#define N_PCH_PCIE_PCIECFG2_PMET 20 + +#define R_PCH_PCIE_PCIEDBG 0x324 +#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26) +#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) +#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14 +#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7 +#define B_PCH_PCIE_PCIEDBG_SPCE BIT5 +#define B_PCH_PCIE_PCIEDBG_LR BIT4 + +#define R_PCH_PCIE_PCIESTS1 0x328 +#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F + + +#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19) +#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7 + +#define R_PCH_PCIE_PCIESTS2 0x32C +#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31 +#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30 +#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29 +#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28 +#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000 +#define N_PCH_PCIE_PCIESTS2_CLRE 12 + +#define R_PCH_PCIE_PCIEALC 0x338 +#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29 +#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28 +#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26 +#define R_PCH_PCIE_PHYCTL4 0x408 +#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27 + +#define R_PCH_PCIE_PCIEPMECTL2 0x424 +#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11 +#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8 +#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7 +#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6 +#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5 +#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4 + +#define R_PCH_PCIE_PCE 0x428 +#define B_PCH_PCIE_PCE_HAE BIT5 +#define B_PCH_PCIE_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_EQCFG1 0x450 +#define S_PCH_PCIE_EQCFG1 4 +#define B_PCH_PCIE_EQCFG1_REC 0xFF000000 +#define N_PCH_PCIE_EQCFG1_REC 24 +#define B_PCH_PCIE_EQCFG1_REIFECE BIT23 +#define N_PCH_PCIE_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_EQCFG1_LEP23B BIT18 +#define B_PCH_PCIE_EQCFG1_LEP3B BIT17 +#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13 +#define B_PCH_PCIE_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_RTPCL1 0x454 +#define B_PCH_PCIE_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_RTPCL2 0x458 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_RTPCL3 0x45C +#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_RTPCL4 0x460 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_FOMS 0x464 +#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29) +#define N_PCH_PCIE_FOMS_I 29 +#define B_PCH_PCIE_FOMS_LN 0x1F000000 +#define N_PCH_PCIE_FOMS_LN 24 +#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF +#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF +#define N_PCH_PCIE_FOMS_FOMSV0 0 +#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00 +#define N_PCH_PCIE_FOMS_FOMSV1 8 +#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000 +#define N_PCH_PCIE_FOMS_FOMSV2 16 + +#define R_PCH_PCIE_HAEQ 0x468 +#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28) +#define N_PCH_PCIE_HAEQ_HAPCCPI 28 +#define B_PCH_PCIE_HAEQ_MACFOMC BIT19 + +#define R_PCH_PCIE_LTCO1 0x470 +#define B_PCH_PCIE_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000 +#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18 +#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000 +#define N_PCH_PCIE_LTCO1_L1TPRECO 12 +#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0 +#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6 +#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F +#define N_PCH_PCIE_LTCO1_L0TPRECO 0 + +#define R_PCH_PCIE_LTCO2 0x474 +#define B_PCH_PCIE_LTCO2_L3TCOE BIT25 +#define B_PCH_PCIE_LTCO2_L2TCOE BIT24 +#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F + +#define R_PCH_PCIE_G3L0SCTL 0x478 +#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_EQCFG2 0x47C +#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20) +#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_PCIE_EQCFG2_PCET 16 +#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EQCFG2_HAPCSB 12 +#define B_PCH_PCIE_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_EQCFG2_REWMET 0xFF + +#define R_PCH_PCIE_MM 0x480 +#define B_PCH_PCIE_MM_MSST 0xFFFFFF00 +#define N_PCH_PCIE_MM_MSST 8 +#define B_PCH_PCIE_MM_MSS 0xFF + +// +//PCI Express Extended End Point Capability Registers +// + +#define R_PCH_PCIE_LTRECH_OFFSET 0 +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 + + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF) +// +#define R_PCH_PCR_SPX_PCD 0 ///< Port configuration and disable +#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number +#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 ///< Port 1 config hide +#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number +#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 ///< Port 2 config hide +#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port 3 Function Number +#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 ///< Port 3 config hide +#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number +#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 ///< Port 4 config hide +#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 ///< 4 bits for each RP FN +#define B_PCH_PCR_SPX_PCD_P1D BIT16 ///< Port 1 disable +#define B_PCH_PCR_SPX_PCD_P2D BIT17 ///< Port 2 disable +#define B_PCH_PCR_SPX_PCD_P3D BIT18 ///< Port 3 disable +#define B_PCH_PCR_SPX_PCD_P4D BIT19 ///< Port 4 disable +#define B_PCH_PCR_SPX_PCD_SRL BIT31 ///< Secured Register Lock + +#define R_PCH_PCR_SPX_PCIEHBP 0x0004 ///< PCI Express high-speed bypass +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 ///< PCIe HBP mode enable +#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///< PCIe gen mode override +#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 ///< PCIe transmitter-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 ///< PCIe link recovery override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 ///< PCIe link down override +#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 ///< PCIe SKP suppression mode +#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 ///< PCIe suppress SKP transmission +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///< PCIe HBP port select +#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///< PCIe HBP CRC + + +// +// ICC PCR (PID: ICC) +// +#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 ///< Timing Control SRC Clock Register +#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 ///< Timing Control SRC Clock Register 2 +#define R_PCH_PCR_ICC_MSKCKRQ 0x100C ///< Mask Control CLKREQ + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h new file mode 100644 index 0000000000..eac209a149 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h @@ -0,0 +1,111 @@ +/** @file + Register names for PCH private chipset register + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/// +/// Definition for PCR base address (defined in PchReservedResources.h) +/// +//#define PCH_PCR_BASE_ADDRESS 0xFD000000 +//#define PCH_PCR_MMIO_SIZE 0x01000000 +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(Pid) << 16) | (UINT16)(Offset)) + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), Buffer, Buffer, 1, 1); + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataOr, 1, 1); + + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well. +**/ +#define PID_DMI 0xEF +#define PID_ESPISPI 0xEE +#define PID_OPIPHY 0xEC +#define PID_MODPHY0 0xEA +#define PID_MODPHY1 0xE9 +#define PID_OTG 0xE5 +#define PID_SPF 0xC9 // Available only in KBL PCH H +#define PID_SPE 0xE4 // Reserved in SKL PCH LP +#define PID_SPD 0xE3 // Reserved in SKL PCH LP +#define PID_SPC 0xE2 +#define PID_SPB 0xE1 +#define PID_SPA 0xE0 +#define PID_ICC 0xDC +#define PID_DSP 0xD7 +#define PID_FIA 0xCF +#define PID_SERIALIO 0xCB +#define PID_USB2 0xCA +#define PID_LPC 0xC7 +#define PID_SMB 0xC6 +#define PID_ITSS 0xC4 +#define PID_RTC 0xC3 +#define PID_SCS 0xC0 // Reserved in SKL PCH H +#define PID_ISHBR 0xBF +#define PID_ISH 0xBE +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_DCI 0xB8 +#define PID_MMP0 0xB0 // for SKL-LP only +#define PID_MODPHY4 0xB0 // for KBL-H only +#define PID_GPIOCOM0 0xAF +#define PID_GPIOCOM1 0xAE +#define PID_GPIOCOM2 0xAD +#define PID_GPIOCOM3 0xAC +#define PID_CAM_FLS 0xAA +#define PID_MODPHY2 0xA9 +#define PID_MODPHY3 0xA8 +#define PID_CAM_CHC 0xA1 +#define PID_CSME12 0x9C +#define PID_CSME0 0x90 +#define PID_CSME_PSF 0x8F +#define PID_PSTH 0x89 + +typedef UINT8 PCH_SBI_PID; + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h new file mode 100644 index 0000000000..d4c048ffe3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h @@ -0,0 +1,652 @@ +/** @file + Register names for PCH PMC device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +// PMC Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_PMC 31 +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 + +#define R_PCH_PMC_PM_DATA_BAR 0x10 +#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000 +#define R_PCH_PMC_ACPI_BASE 0x40 +#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC +#define R_PCH_PMC_ACPI_CNT 0x44 +#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM enable +#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 ///< ACPI eanble +#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7 +#define R_PCH_PMC_PWRM_BASE 0x48 +#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode. +#define R_PCH_PMC_GEN_PMCON_A 0xA0 +#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30 +#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29 +#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28 +#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27 +#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23 +#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21 +#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18 +#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT13 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12 +#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10 +#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5 +#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4 +#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 ///< ESPI SMI lock +#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003 +#define R_PCH_PMC_GEN_PMCON_B 0xA4 +#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at 0x40, only cleared by reset when set +#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16 +#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15 +#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 +#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13 +#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00 +#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9 +#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3 +#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 +#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1 +#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0 +#define R_PCH_PMC_BM_CX_CNF 0xA8 +#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31 +#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30 +#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24 +#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19 +#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17 +#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16 +#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15 +#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 +#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11 +#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10 +#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9 +#define R_PCH_PMC_ETR3 0xAC +#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown +#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21 +#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset +#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19 +#define B_PCH_PMC_ETR3_CWORWRE BIT18 + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define S_PCH_ACPI_PM1_STS 2 +#define B_PCH_ACPI_PM1_STS_WAK BIT15 +#define B_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS BIT14 +#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 +#define B_PCH_ACPI_PM1_STS_RTC BIT10 +#define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 +#define B_PCH_ACPI_PM1_STS_GBL BIT5 +#define B_PCH_ACPI_PM1_STS_BM BIT4 +#define B_PCH_ACPI_PM1_STS_TMROF BIT0 +#define N_PCH_ACPI_PM1_STS_WAK 15 +#define N_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS 14 +#define N_PCH_ACPI_PM1_STS_PRBTNOR 11 +#define N_PCH_ACPI_PM1_STS_RTC 10 +#define N_PCH_ACPI_PM1_STS_PWRBTN 8 +#define N_PCH_ACPI_PM1_STS_GBL 5 +#define N_PCH_ACPI_PM1_STS_BM 4 +#define N_PCH_ACPI_PM1_STS_TMROF 0 + +#define R_PCH_ACPI_PM1_EN 0x02 +#define S_PCH_ACPI_PM1_EN 2 +#define B_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS BIT14 +#define B_PCH_ACPI_PM1_EN_RTC BIT10 +#define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 +#define B_PCH_ACPI_PM1_EN_GBL BIT5 +#define B_PCH_ACPI_PM1_EN_TMROF BIT0 +#define N_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS 14 +#define N_PCH_ACPI_PM1_EN_RTC 10 +#define N_PCH_ACPI_PM1_EN_PWRBTN 8 +#define N_PCH_ACPI_PM1_EN_GBL 5 +#define N_PCH_ACPI_PM1_EN_TMROF 0 + +#define R_PCH_ACPI_PM1_CNT 0x04 +#define S_PCH_ACPI_PM1_CNT 4 +#define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) +#define V_PCH_ACPI_PM1_CNT_S0 0 +#define V_PCH_ACPI_PM1_CNT_S1 BIT10 +#define V_PCH_ACPI_PM1_CNT_S3 (BIT12 | BIT10) +#define V_PCH_ACPI_PM1_CNT_S4 (BIT12 | BIT11) +#define V_PCH_ACPI_PM1_CNT_S5 (BIT12 | BIT11 | BIT10) +#define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 +#define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1 +#define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0 + +#define R_PCH_ACPI_PM1_TMR 0x08 +#define V_PCH_ACPI_TMR_FREQUENCY 3579545 +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow + +#define R_PCH_SMI_EN 0x30 +#define S_PCH_SMI_EN 4 +#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 +#define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 +#define B_PCH_SMI_EN_PERIODIC BIT14 +#define B_PCH_SMI_EN_TCO BIT13 +#define B_PCH_SMI_EN_MCSMI BIT11 +#define B_PCH_SMI_EN_BIOS_RLS BIT7 +#define B_PCH_SMI_EN_SWSMI_TMR BIT6 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_ON_SLP_EN BIT4 +#define B_PCH_SMI_EN_LEGACY_USB BIT3 +#define B_PCH_SMI_EN_BIOS BIT2 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 +#define N_PCH_SMI_EN_LEGACY_USB3 31 +#define N_PCH_SMI_EN_ESPI 28 +#define N_PCH_SMI_EN_GPIO_UNLOCK 27 +#define N_PCH_SMI_EN_INTEL_USB2 18 +#define N_PCH_SMI_EN_LEGACY_USB2 17 +#define N_PCH_SMI_EN_PERIODIC 14 +#define N_PCH_SMI_EN_TCO 13 +#define N_PCH_SMI_EN_MCSMI 11 +#define N_PCH_SMI_EN_BIOS_RLS 7 +#define N_PCH_SMI_EN_SWSMI_TMR 6 +#define N_PCH_SMI_EN_APMC 5 +#define N_PCH_SMI_EN_ON_SLP_EN 4 +#define N_PCH_SMI_EN_LEGACY_USB 3 +#define N_PCH_SMI_EN_BIOS 2 +#define N_PCH_SMI_EN_EOS 1 +#define N_PCH_SMI_EN_GBL_SMI 0 + +#define R_PCH_SMI_STS 0x34 +#define S_PCH_SMI_STS 4 +#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 +#define B_PCH_SMI_STS_GPIO_UNLOCK BIT27 +#define B_PCH_SMI_STS_SPI BIT26 +#define B_PCH_SMI_STS_MONITOR BIT21 +#define B_PCH_SMI_STS_PCI_EXP BIT20 +#define B_PCH_SMI_STS_PATCH BIT19 +#define B_PCH_SMI_STS_INTEL_USB2 BIT18 +#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 +#define B_PCH_SMI_STS_SMBUS BIT16 +#define B_PCH_SMI_STS_SERIRQ BIT15 +#define B_PCH_SMI_STS_PERIODIC BIT14 +#define B_PCH_SMI_STS_TCO BIT13 +#define B_PCH_SMI_STS_DEVMON BIT12 +#define B_PCH_SMI_STS_MCSMI BIT11 +#define B_PCH_SMI_STS_GPIO_SMI BIT10 +#define B_PCH_SMI_STS_GPE0 BIT9 +#define B_PCH_SMI_STS_PM1_STS_REG BIT8 +#define B_PCH_SMI_STS_SWSMI_TMR BIT6 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_STS_ON_SLP_EN BIT4 +#define B_PCH_SMI_STS_LEGACY_USB BIT3 +#define B_PCH_SMI_STS_BIOS BIT2 +#define N_PCH_SMI_STS_LEGACY_USB3 31 +#define N_PCH_SMI_STS_ESPI 28 +#define N_PCH_SMI_STS_GPIO_UNLOCK 27 +#define N_PCH_SMI_STS_SPI 26 +#define N_PCH_SMI_STS_MONITOR 21 +#define N_PCH_SMI_STS_PCI_EXP 20 +#define N_PCH_SMI_STS_PATCH 19 +#define N_PCH_SMI_STS_INTEL_USB2 18 +#define N_PCH_SMI_STS_LEGACY_USB2 17 +#define N_PCH_SMI_STS_SMBUS 16 +#define N_PCH_SMI_STS_SERIRQ 15 +#define N_PCH_SMI_STS_PERIODIC 14 +#define N_PCH_SMI_STS_TCO 13 +#define N_PCH_SMI_STS_DEVMON 12 +#define N_PCH_SMI_STS_MCSMI 11 +#define N_PCH_SMI_STS_GPIO_SMI 10 +#define N_PCH_SMI_STS_GPE0 9 +#define N_PCH_SMI_STS_PM1_STS_REG 8 +#define N_PCH_SMI_STS_SWSMI_TMR 6 +#define N_PCH_SMI_STS_APM 5 +#define N_PCH_SMI_STS_ON_SLP_EN 4 +#define N_PCH_SMI_STS_LEGACY_USB 3 +#define N_PCH_SMI_STS_BIOS 2 + +#define R_PCH_ACPI_GPE_CNTL 0x40 +#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 + +#define R_PCH_DEVACT_STS 0x44 +#define S_PCH_DEVACT_STS 2 +#define B_PCH_DEVACT_STS_MASK 0x13E1 +#define B_PCH_DEVACT_STS_KBC BIT12 +#define B_PCH_DEVACT_STS_PIRQDH BIT9 +#define B_PCH_DEVACT_STS_PIRQCG BIT8 +#define B_PCH_DEVACT_STS_PIRQBF BIT7 +#define B_PCH_DEVACT_STS_PIRQAE BIT6 +#define B_PCH_DEVACT_STS_D0_TRP BIT0 +#define N_PCH_DEVACT_STS_KBC 12 +#define N_PCH_DEVACT_STS_PIRQDH 9 +#define N_PCH_DEVACT_STS_PIRQCG 8 +#define N_PCH_DEVACT_STS_PIRQBF 7 +#define N_PCH_DEVACT_STS_PIRQAE 6 + +#define R_PCH_ACPI_PM2_CNT 0x50 +#define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0 + +#define R_PCH_OC_WDT_CTL 0x54 +#define B_PCH_OC_WDT_CTL_RLD BIT31 +#define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_PCH_OC_WDT_CTL_EN BIT14 +#define B_PCH_OC_WDT_CTL_ICCSURV BIT13 +#define B_PCH_OC_WDT_CTL_LCK BIT12 +#define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_PCH_OC_WDT_CTL_STATUS_OK 0 + +#define R_PCH_ACPI_GPE0_STS_31_0 0x80 +#define R_PCH_ACPI_GPE0_STS_63_32 0x84 +#define R_PCH_ACPI_GPE0_STS_95_64 0x88 +#define R_PCH_ACPI_GPE0_STS_127_96 0x8C +#define S_PCH_ACPI_GPE0_STS_127_96 4 +#define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_STS_127_96_PME 11 +#define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_STS_127_96_RI 8 +#define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7 +#define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0_EN_31_0 0x90 +#define R_PCH_ACPI_GPE0_EN_63_32 0x94 +#define R_PCH_ACPI_GPE0_EN_95_64 0x98 +#define R_PCH_ACPI_GPE0_EN_127_96 0x9C +#define S_PCH_ACPI_GPE0_EN_127_96 4 +#define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_EN_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_EN_127_96_USB3 12 +#define N_PCH_ACPI_GPE0_EN_127_96_PME 11 +#define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_EN_127_96_RI 8 +#define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1 + + +// +// TCO register I/O map +// +#define R_PCH_TCO_RLD 0x0 +#define R_PCH_TCO_DAT_IN 0x2 +#define R_PCH_TCO_DAT_OUT 0x3 +#define R_PCH_TCO1_STS 0x04 +#define S_PCH_TCO1_STS 2 +#define B_PCH_TCO1_STS_DMISERR BIT12 +#define B_PCH_TCO1_STS_DMISMI BIT10 +#define B_PCH_TCO1_STS_DMISCI BIT9 +#define B_PCH_TCO1_STS_BIOSWR BIT8 +#define B_PCH_TCO1_STS_NEWCENTURY BIT7 +#define B_PCH_TCO1_STS_TIMEOUT BIT3 +#define B_PCH_TCO1_STS_TCO_INT BIT2 +#define B_PCH_TCO1_STS_SW_TCO_SMI BIT1 +#define B_PCH_TCO1_STS_NMI2SMI BIT0 +#define N_PCH_TCO1_STS_DMISMI 10 +#define N_PCH_TCO1_STS_BIOSWR 8 +#define N_PCH_TCO1_STS_NEWCENTURY 7 +#define N_PCH_TCO1_STS_TIMEOUT 3 +#define N_PCH_TCO1_STS_SW_TCO_SMI 1 +#define N_PCH_TCO1_STS_NMI2SMI 0 + +#define R_PCH_TCO2_STS 0x06 +#define S_PCH_TCO2_STS 2 +#define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_PCH_TCO2_STS_BAD_BIOS BIT3 +#define B_PCH_TCO2_STS_BOOT BIT2 +#define B_PCH_TCO2_STS_SECOND_TO BIT1 +#define B_PCH_TCO2_STS_INTRD_DET BIT0 +#define N_PCH_TCO2_STS_INTRD_DET 0 + +#define R_PCH_TCO1_CNT 0x08 +#define S_PCH_TCO1_CNT 2 +#define B_PCH_TCO_CNT_LOCK BIT12 +#define B_PCH_TCO_CNT_TMR_HLT BIT11 +#define B_PCH_TCO_CNT_NMI2SMI_EN BIT9 +#define B_PCH_TCO_CNT_NMI_NOW BIT8 +#define N_PCH_TCO_CNT_NMI2SMI_EN 9 + +#define R_PCH_TCO2_CNT 0x0A +#define S_PCH_TCO2_CNT 2 +#define B_PCH_TCO2_CNT_OS_POLICY 0x0030 +#define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_PCH_TCO2_CNT_INTRD_SEL 0x0006 +#define N_PCH_TCO2_CNT_INTRD_SEL 2 + +#define R_PCH_TCO_MESSAGE1 0x0C +#define R_PCH_TCO_MESSAGE2 0x0D +#define R_PCH_TCO_WDCNT 0x0E +#define R_PCH_TCO_SW_IRQ_GEN 0x10 +#define B_PCH_TCO_IRQ12_CAUSE BIT1 +#define B_PCH_TCO_IRQ1_CAUSE BIT0 +#define R_PCH_TCO_TMR 0x12 + +// +// PWRM Registers +// +#define R_PCH_WADT_AC 0x0 ///< Wake Alarm Device Timer: AC +#define R_PCH_WADT_DC 0x4 ///< Wake Alarm Device Timer: DC +#define R_PCH_WADT_EXP_AC 0x8 ///< Wake Alarm Device Expired Timer: AC +#define R_PCH_WADT_EXP_DC 0xC ///< Wake Alarm Device Expired Timer: DC +#define R_PCH_PWRM_PRSTS 0x10 ///< Power and Reset Status +#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status +#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4 +#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0 +#define R_PCH_PWRM_14 0x14 +#define R_PCH_PWRM_CFG 0x18 ///< Power Management Configuration +#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown +#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 Core Power Gating +#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable +#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width +#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds +#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 second +#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms) +#define V_PCH_PWRM_CFG_SSMAW_0S 0 ///< 0 second +#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width +#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds +#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms +#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 ///< 4 seconds +#define V_PCH_PWRM_CFG_SAMAW_0S 0 ///< 0 second +#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration +#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds +#define V_PCH_PWRM_CFG_RPCD_2S BIT9 ///< 2-3 seconds +#define V_PCH_PWRM_CFG_RPCD_3S BIT8 ///< 3-4 seconds +#define V_PCH_PWRM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default) +#define R_PCH_PWRM_PCH_PM_STS 0x1C ///< Contains misc. fields used to record PCH power management events +#define B_PCH_PWRM_PCH_PM_STS_PMC_MSG_FULL_STS BIT24 ///< MTPMC transport mechanism full indication +#define R_PCH_PWRM_MTPMC 0x20 ///< Message to PMC +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE ///< Command to override lanes 0-15 power gating +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF ///< Command to override lanes 16-31 power gating +#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 ///< Data part of PowerGate Message to PMC +#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16 +#define R_PCH_PWRM_PCH_PM_STS2 0x24 ///< PCH Power Management Status +#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 ///< S3 Power Gating Policies +#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 ///< Deep S3 Enable in DC Mode +#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 ///< Deep S3 Enable in AC Mode +#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C ///< Deep S4 Power Policies +#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 ///< Deep S4 Enable in DC Mode +#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 ///< Deep S4 Enable in AC Mode +#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 ///< Deep S5 Power Policies +#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S5 Enable in DC Mode +#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S5 Enable in AC Mode +#define R_PCH_PWRM_DSX_CFG 0x34 ///< Deep SX Configuration +#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable +#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT pin pulldown in DeepSx disable +#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable +#define R_PCH_PWRM_CFG2 0x3C ///< Power Management Configuration Reg 2 +#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP) +#define N_PCH_PWRM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP) +#define B_PCH_PWRM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS) +#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM RESET# control +#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 ///< Enable Snoop Request to SLOW_RING +#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C ///< Enable Snoop Request to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_SN_SA 0x50 ///< Enable Snoop Request to SA +#define R_PCH_PWRM_EN_SN_SA2 0x54 ///< Enable Snoop Request to SA 2nd Reg +#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 ///< Enable Snoop Request to SLOW_RING_CF +#define R_PCH_PWRM_EN_NS_SA 0x68 ///< Enable Non-Snoop Request to SA +#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 ///< Enable Clock Wake to SLOW_RING +#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 ///< Enable Clock Wake to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_CW_SA 0x88 ///< Enable Clock Wake to SA +#define R_PCH_PWRM_EN_CW_SA2 0x8C ///< Enable Clock Wake to SA 2nd Reg +#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 ///< Enable Clock Wake to SLOW_RING_CF +#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 ///< Enable Pegged Active to SLOW_RING +#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC ///< Enable Pegged Active to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_PA_SA 0xB0 ///< Enable Pegged Active to SA +#define R_PCH_PWRM_EN_PA_SA2 0xB4 ///< Enable Pegged Active to SA 2nd Reg +#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 ///< Enable Misc PM_SYNC Events +#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4 +#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) +#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24 +#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1 +#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8 +#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock +#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11 +#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10 +#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 ///< PM_SYNC State Hysteresis +#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 ///< PM_SYNC Pin Mode +#define R_PCH_PWRM_CFG3 0xE0 ///< Power Management Configuration Reg 3 +#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable +#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable +#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 ///< Lock power gating override messages +#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION +#define R_PCH_PWRM_CFG4 0xE8 ///< Power Management Configuration Reg 4 +#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable +#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0] +#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018 +#define R_PCH_PWRM_CPU_EPOC 0xEC +#define R_PCH_PWRM_VR_MISC_CTL 0x100 +#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3 +#define R_PCH_PWRM_GPIO_CFG 0x120 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0 +#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 ///< PM_SYNC Pin Mode in C0 +#define R_PCH_PWRM_ACPI_TMR_CTL 0xFC +#define B_PCH_PWRM_ACPI_TMR_DIS BIT1 +#define R_PCH_PWRM_124 0x124 +#define R_PCH_PWRM_SLP_S0_RESIDENCY_COUNTER 0x13C +#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200 +#define R_PCH_PWRM_MODPHY_PM_CFG1_MLSXSWPGP 0xFFFF +#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< ModPHY Power Management Configuration Reg 2 +#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable +#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< Enable ModPHY FET Control +#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time +#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24 +#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A +#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< UFS ModPHY SPD SPD Override +#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< ModPHY Power Management Configuration Reg 3 +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request +#define R_PCH_PWRM_30C 0x30C +#define R_PCH_PWRM_OBFF_CFG 0x314 ///< OBFF Configuration +#define R_PCH_PWRM_31C 0x31C +#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 ///< CPPM Miscellaneous Configuration +#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 ///< CPPM Clock Gating Policy Reg 1 +#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 ///< CPPM Clock Gating Policy Reg 3 +#define R_PCH_PWRM_34C 0x34C +#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 ///< CPPM Clock Gating Policy Reg 5 +#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group X +#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0] +#define R_PCH_PWRM_3D0 0x3D0 +#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 ///< CPPM ModPHY Gating Policy Reg 1A +#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0] +#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 ///< Clock Source Shutdown Control Reg 1 +#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20 +#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0 +#define R_PCH_PWRM_CS_SD_CTL2 0x3EC ///< Clock Source Shutdown Control Reg 2 +#define R_PCH_PWRM_HSWPGCR1 0x5D0 +#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31 +#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0 +#define R_PCH_PWRM_600 0x600 +#define R_PCH_PWRM_604 0x604 +#define R_PCH_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Static PG Related Function Disable Register 1 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC) +#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Static Function Disable Control Register 2 +#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Static Function Disable Control Register 2 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< SerialIo Controller UART Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< SerialIo Controller UART Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< SerialIo Controller UART Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< SerialIo Controller I2C Device 5 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Device 4 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< SerialIo Controller I2C Device 3 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< SerialIo Controller I2C Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< SerialIo Controller I2C Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< SerialIo Controller I2C Device 0 Function Disable +#define R_PCH_PWRM_NST_PG_FDIS_1 0x628 +#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDCI Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADSP Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SATA Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCIe Controller C Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCIe Controller C Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCIe Controller C Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCIe Controller B Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCIe Controller B Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCIe Controller B Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCIe Controller B Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCIe Controller A Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCIe Controller A Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCIe Controller A Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHCI Function Disable +#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fuse Disable Read 1 Register +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCIe Controller E Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCIe Controller E Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCIe Controller E Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCIe Controller D Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCIe Controller C Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCIe Controller C Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCIe Controller C Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCIe Controller B Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCIe Controller B Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCIe Controller B Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCIe Controller B Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCIe Controller A Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCIe Controller A Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCIe Controller A Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHCI Fuse Disable +#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fuse Disable Read 2 Register +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PSTH Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHCI Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRSB Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITSS Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< SerialIo Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Camera Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable +#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Static PG Fuse and Soft Strap Disable Read Register 3 +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNCRA3 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNCRA2 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNCRA1 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNCRA Fuse or Soft Strap Disable + + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h new file mode 100644 index 0000000000..c52f1e721d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h @@ -0,0 +1,364 @@ +/** @file + Register definition for PSF component + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_PSF_H_ +#define _PCH_REGS_PSF_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PSFx segment registers +// +#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 ///< PSF Segment Global Configuration Register +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4 +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3 +#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4010 ///< PSF Segment Rootspace Configuration Register +#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS1 0x4014 +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RSX_ENADDRP2P BIT1 +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RSX_VTDEN BIT0 +#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4018 ///< PSF Segment Port Configuration Register + +#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4 +#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4 +#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F +#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F + +// +// PSFx PCRs definitions +// +#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 ///< PCI BAR0 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 ///< PCI BAR1 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 ///< PCI BAR2 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C ///< PCI BAR3 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 ///< PCI BAR4 +#define R_PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 ///< Disable BAR0 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 ///< Disable BAR1 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 ///< Disable BAR2 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 ///< Disable BAR3 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 ///< Disable BAR4 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 ///< Disable BAR5 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable +#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 ///< PCI power management configuration +#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) ///< Power status +#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 ///< PCI configuration disable +#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 ///< config disable + +#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable + +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 ///< device number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4 +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | BIT1) ///< function number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1 + +#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00 +#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00 + +// +// PSF1 PCRs +// +// PSF1 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 ///< D31F6 PSF base address (GBE) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 ///< D20F3 PSF base address (CAM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 ///< D22F4 PSF base address (CSME: HECI3) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 ///< D22F1 PSF base address (CSME: HECI2) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 ///< D22F0 PSF base address (CSME: HECI1) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 ///< D22F3 PSF base address (CSME: KT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 ///< D22F2 PSF base address (CSME: IDER) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 ///< D18F1 PSF base address (CSME: CLINK) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 ///< D18F0 PSF base address (CSME: KVM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 ///< PCH-LP D23F0 PSF base address (SATA) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 ///< PCH-LP D29F3 PSF base address (PCIE PORT 12) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 ///< PCH-LP D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 ///< PCH-LP D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 ///< PCH-LP D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 ///< PCH-LP D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 ///< PCH-LP D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 ///< PCH-LP D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 ///< PCH-LP D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 ///< PCH-LP D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 ///< PCH-LP D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 ///< PCH-LP D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 ///< PCH-LP D28F0 PSF base address (PCIE PORT 01) + +// PSF1 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 ///< SPT-H D22F4 PSF base address (CSME: HECI3) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 ///< SPT-H D22F1 PSF base address (CSME: HECI2) +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 ///< SPT-H D22F0 PSF base address (CSME: HECI1) +#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 ///< SPT-H D22F3 PSF base address (CSME: KT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 ///< SPT-H D22F2 PSF base address (CSME: IDER) +#define R_PCH_H_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0900 ///< D18F1 PSF base address (CSME: CLINK) +#define R_PCH_H_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0A00 ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0B00 ///< D18F0 PSF base address (CSME: KVM) +#define R_PCH_H_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x0C00 ///< PCH-H D23F0 PSF base address (SATA) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 ///< PCH-H D27F3 PSF base address (PCIE PORT 20) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 ///< PCH-H D27F2 PSF base address (PCIE PORT 19) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 ///< PCH-H D27F1 PSF base address (PCIE PORT 18) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 ///< PCH-H D27F0 PSF base address (PCIE PORT 17) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 ///< PCH-H D29F7 PSF base address (PCIE PORT 16) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 ///< PCH-H D29F6 PSF base address (PCIE PORT 15) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 ///< PCH-H D29F5 PSF base address (PCIE PORT 14) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 ///< PCH-H D29F4 PSF base address (PCIE PORT 13) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 ///< PCH-H D29F3 PSF base address (PCIE PORT 10) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 ///< PCH-H D29F2 PSF base address (PCIE PORT 11) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 ///< PCH-H D29F1 PSF base address (PCIE PORT 10) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 ///< PCH-H D29F0 PSF base address (PCIE PORT 09) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 ///< PCH-H D28F7 PSF base address (PCIE PORT 08) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 ///< PCH-H D28F6 PSF base address (PCIE PORT 07) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 ///< PCH-H D28F5 PSF base address (PCIE PORT 06) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 ///< PCH-H D28F4 PSF base address (PCIE PORT 05) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 ///< PCH-H D28F3 PSF base address (PCIE PORT 04) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 ///< PCH-H D28F2 PSF base address (PCIE PORT 03) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 ///< PCH-H D28F1 PSF base address (PCIE PORT 02) +#define R_SKL_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 ///< PCH-H D28F0 PSF base address (PCIE PORT 01) + +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE24_REG_BASE 0x2000 ///< PCH-H D27F7 PSF base address (PCIE PORT 24) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE23_REG_BASE 0x2100 ///< PCH-H D27F6 PSF base address (PCIE PORT 23) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE22_REG_BASE 0x2200 ///< PCH-H D27F5 PSF base address (PCIE PORT 22) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE21_REG_BASE 0x2300 ///< PCH-H D27F4 PSF base address (PCIE PORT 21) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2400 ///< PCH-H D27F3 PSF base address (PCIE PORT 20) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2500 ///< PCH-H D27F2 PSF base address (PCIE PORT 19) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2600 ///< PCH-H D27F1 PSF base address (PCIE PORT 18) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2700 ///< PCH-H D27F0 PSF base address (PCIE PORT 17) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2800 ///< PCH-H D29F7 PSF base address (PCIE PORT 16) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2900 ///< PCH-H D29F6 PSF base address (PCIE PORT 15) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2A00 ///< PCH-H D29F5 PSF base address (PCIE PORT 14) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2B00 ///< PCH-H D29F4 PSF base address (PCIE PORT 13) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2C00 ///< PCH-H D29F3 PSF base address (PCIE PORT 10) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2D00 ///< PCH-H D29F2 PSF base address (PCIE PORT 11) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2E00 ///< PCH-H D29F1 PSF base address (PCIE PORT 10) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2F00 ///< PCH-H D29F0 PSF base address (PCIE PORT 09) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x3000 ///< PCH-H D28F7 PSF base address (PCIE PORT 08) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x3100 ///< PCH-H D28F6 PSF base address (PCIE PORT 07) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x3200 ///< PCH-H D28F5 PSF base address (PCIE PORT 06) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x3300 ///< PCH-H D28F4 PSF base address (PCIE PORT 05) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3400 ///< PCH-H D28F3 PSF base address (PCIE PORT 04) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3500 ///< PCH-H D28F2 PSF base address (PCIE PORT 03) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3600 ///< PCH-H D28F1 PSF base address (PCIE PORT 02) +#define R_KBL_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3700 ///< PCH-H D28F0 PSF base address (PCIE PORT 01) + + +// Other PSF1 PCRs definition +#define R_PCH_H_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x4038 ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050 ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060 ///< Destination ID +#define R_SKL_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4048 ///< Multicast Control Register +#define R_SKL_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4058 ///< Destination ID +#define R_KBL_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x404C ///< Multicast Control Register +#define R_KBL_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x405C ///< Destination ID + + +//PSF 1 Multicast Message Configuration + +#define R_PCH_PCR_PSF1_RC_OWNER_RS0 0x4008 ///< Destination ID + +#define B_PCH_PCR_PSF1_TARGET_CHANNELID 0xFF +#define B_PCH_PCR_PSF1_TARGET_PORTID 0x7F00 +#define N_PCH_PCR_PSF1_TARGET_PORTID 8 +#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID BIT15 +#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID 15 +#define B_PCH_PCR_PSF1_TARGET_PSFID 0xFF0000 +#define N_PCH_PCR_PSF1_TARGET_PSFID 16 +#define B_PCH_PCR_PSF1_TARGET_CHANMAP BIT31 + +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID 10 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM 1 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPSTREAM 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWNSTREAM 1 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 1 + +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4058 ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x409C ///< Destination ID +#define R_SKL_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4050 ///< Multicast Control Register +#define R_SKL_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x40B4 ///< Destination ID +#define R_KBL_PCH_H_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4054 ///< Multicast Control Register +#define R_KBL_PCH_H_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x40C8 ///< Destination ID + +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN BIT0 +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 0xFE +#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI 0 + + + +// +// controls the PCI configuration header of a PCI function +// +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 ///< SPC + +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x41C0 ///< SPA +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x41C4 ///< SPA +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41C8 ///< SPA +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41CC ///< SPA +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41D0 ///< SPB +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41D4 ///< SPB +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41D8 ///< SPB +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41DC ///< SPB +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41E0 ///< SPC +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41E4 ///< SPC +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41E8 ///< SPC +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41EC ///< SPC +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F4 0x41F0 ///< SPD +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F5 0x41F4 ///< SPD +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F6 0x41F8 ///< SPD +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F7 0x41FC ///< SPD +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F0 0x4200 ///< SPE +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F1 0x4204 ///< SPE +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F2 0x4208 ///< SPE +#define R_SKL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F3 0x420C ///< SPE + +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4274 ///< SPA +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x4278 ///< SPA +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x427C ///< SPA +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x4280 ///< SPA +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x4284 ///< SPB +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x4288 ///< SPB +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x428C ///< SPB +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x4290 ///< SPB +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x4294 ///< SPC +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x4298 ///< SPC +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x429C ///< SPC +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x42A0 ///< SPC +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F4 0x42A4 ///< SPD +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F5 0x42A8 ///< SPD +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F6 0x42AC ///< SPD +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPD_D29_F7 0x42B0 ///< SPD +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F0 0x42B4 ///< SPE +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F1 0x42B8 ///< SPE +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F2 0x42BC ///< SPE +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPE_D27_F3 0x42C0 ///< SPE +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPF_D27_F4 0x42C4 ///< SPF +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPF_D27_F5 0x42C8 ///< SPF +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPF_D27_F6 0x42CC ///< SPF +#define R_KBL_PCH_H_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPF_D27_F7 0x42D0 ///< SPF + +// +// PSF1 grant count registers +// +#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC +#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0 + +#define R_SKL_PCH_H_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x4214 +#define R_KBL_PCH_H_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x42D8 +#define R_SKL_PCH_H_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x46DC +#define R_KBL_PCH_H_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x4834 + +// +// PSF2 PCRs (PID:PSF2) +// +#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 ///< D20F2 PSF base address (Thermal). // LP&H +// PSF2 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 ///< D30F7 PSF base address (SCC: UFS) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 ///< D30F6 PSF base address (SCC: SDCard) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 ///< D30F5 PSF base address (SCC: SDIO) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 ///< D30F4 PSF base address (SCC: eMMC) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 ///< D20F0 PSF base address (XHCI) +// PSF2 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 ///< D20F0 PSF base address (XHCI) + +// +// PSF3 PCRs (PID:PSF3) +// +#define R_PCH_PCR_PSF3_T0_SHDW_P2SB_REG_BASE 0x0100 ///< D31F1 PSF base address (P2SB) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_ACPI_REG_BASE 0x0200 ///< D20F4 PSF base address (TraceHub ACPI) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_TRACE_HUB_REG_BASE 0x0300 ///< D31F7 PSF base address (TraceHub PCI) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_LPC_REG_BASE 0x0400 ///< D31F0 PSF base address (LPC) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_SMBUS_REG_BASE 0x0500 ///< D31F4 PSF base address (SMBUS) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_PMC_REG_BASE 0x0700 ///< D31F2 PSF base address (PMC) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_ISH_REG_BASE 0x0800 ///< D19F0 PSF base address (ISH) // LP&H +#define R_PCH_PCR_PSF3_T0_SHDW_AUD_REG_BASE 0x1900 ///< D31F3 PSF base address (HDA, ADSP) // LP&H +// PSF3 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C4_REG_BASE 0x0900 ///< D25F2 PSF base address (SerialIo: I2C4) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_SPI1_REG_BASE 0x0A00 ///< D30F3 PSF base address (SerialIo: SPI1) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_SPI0_REG_BASE 0x0B00 ///< D30F2 PSF base address (SerialIo: SPI0) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_UART1_REG_BASE 0x0C00 ///< D30F1 PSF base address (SerialIo: UART1) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_UART0_REG_BASE 0x0D00 ///< D30F0 PSF base address (SerialIo: UART0) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C5_REG_BASE 0x0E00 ///< D25F1 PSF base address (SerialIo: I2C5) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_UART2_REG_BASE 0x0F00 ///< D25F0 PSF base address (SerialIo: UART2) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C3_REG_BASE 0x1000 ///< D21F3 PSF base address (SerialIo: I2C3) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C2_REG_BASE 0x1100 ///< D21F2 PSF base address (SerialIo: I2C2) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C1_REG_BASE 0x1200 ///< D21F1 PSF base address (SerialIo: I2C1) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_I2C0_REG_BASE 0x1300 ///< D21F0 PSF base address (SerialIo: I2C0) +#define R_PCH_LP_PCR_PSF3_T0_SHDW_SPI_SPI_REG_BASE 0x1600 ///< D31F5 PSF base address (SPI SPI) +// PSF3 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF3_T0_SHDW_SPI1_REG_BASE 0x0900 ///< D30F3 PSF base address (SerialIo: SPI1) +#define R_PCH_H_PCR_PSF3_T0_SHDW_SPI0_REG_BASE 0x0A00 ///< D30F2 PSF base address (SerialIo: SPI0) +#define R_PCH_H_PCR_PSF3_T0_SHDW_UART1_REG_BASE 0x0B00 ///< D30F1 PSF base address (SerialIo: UART1) +#define R_PCH_H_PCR_PSF3_T0_SHDW_UART0_REG_BASE 0x0C00 ///< D30F0 PSF base address (SerialIo: UART0) +#define R_PCH_H_PCR_PSF3_T0_SHDW_UART2_REG_BASE 0x0D00 ///< D25F0 PSF base address (SerialIo: UART2) +#define R_PCH_H_PCR_PSF3_T0_SHDW_I2C3_REG_BASE 0x0E00 ///< D21F3 PSF base address (SerialIo: I2C3) +#define R_PCH_H_PCR_PSF3_T0_SHDW_I2C2_REG_BASE 0x0F00 ///< D21F2 PSF base address (SerialIo: I2C2) +#define R_PCH_H_PCR_PSF3_T0_SHDW_I2C1_REG_BASE 0x1000 ///< D21F1 PSF base address (SerialIo: I2C1) +#define R_PCH_H_PCR_PSF3_T0_SHDW_I2C0_REG_BASE 0x1100 ///< D21F0 PSF base address (SerialIo: I2C0) +#define R_PCH_H_PCR_PSF3_T0_SHDW_SPI_SPI_REG_BASE 0x1400 ///< D31F5 PSF base address (SPI SPI) +#define R_PCH_H_PCR_PSF3_T0_SHDW_GBE_REG_BASE 0x1700 ///< D31F6 PSF base address (GBE) + +#define R_PCH_PCR_PSF3_PSF_MC_CONTROL_MCAST0_EOI 0x404C ///< Multicast Control Register // LP&H +#define R_PCH_PCR_PSF3_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4054 ///< Destination ID // LP&H + +#define R_PCH_H_PCR_PSF3_PSF_PORT_CONFIG_PG1_PORT1 0x4020 ///< PSF Port Configuration Register + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h new file mode 100644 index 0000000000..b312f7100e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h @@ -0,0 +1,72 @@ +/** @file + Register definition for PSTH component + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_PSTH_H_ +#define _PCH_REGS_PSTH_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PSTH and IO Trap PCRs (PID:PSTH) +// +#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH control register +#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable +#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap status regsiter +#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask +#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped cycle +#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write +#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables +#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address +#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped write data +#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data +#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp 0 register +#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp 1 register +#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp 2 register +#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp 3 register +#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask +#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write +#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field +#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32) +#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask +#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte enable +#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask +#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Address +#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap and SMI# Enable + + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSata.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSata.h new file mode 100644 index 0000000000..88d066ea28 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSata.h @@ -0,0 +1,720 @@ +/** @file + Register names for PCH SATA controllers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller Registers (D23:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SATA 23 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 +#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +// +// SKL PCH-LP SATA Device ID's +// +#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controller (AHCI) - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controller (RAID 0/1/5/10) - premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controller (RAID 1/RRT Only) - Mobile + +// +// PCH-H SATA Device ID's +// +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controller (RAID 0/1/5/10) - premium - Alternate ID +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controller (RAID 0/1/5/10) - RSTe of Server SKU + +// +// SKL PCH-H SATA Device ID's +// +#define V_SKL_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controller (AHCI) +#define V_SKL_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controller (AHCI) - SPTH A0 +#define V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controller (RAID 0/1/5/10) - NOT premium +#define V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controller (RAID 0/1/5/10) - premium +#define V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controller (RAID 1/RRT Only) + +// +// KBL PCH-H SATA Device ID's +// +#define V_KBL_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA282 ///< SATA Controller (AHCI) +#define V_KBL_PCH_H_SATA_DEVICE_ID_D_RAID 0xA284 ///< SATA Controller (RAID 0/1/5/10) - NOT premium +#define V_KBL_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA286 ///< SATA Controller (RAID 0/1/5/10) - premium +#define V_KBL_PCH_H_SATA_DEVICE_ID_D_OPTANE 0xA28E ///< SATA Controller (RAID 1/RRT Only) + + +// +// SATA Controller common Registers +// +#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06 +#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04 +#define R_PCH_SATA_AHCI_BAR 0x24 +#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11 +#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19 +#define B_PCH_SATA_AHCI_BAR_PF BIT3 +#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_PCH_SATA_AHCI_BAR_RTE BIT0 +#define R_PCH_SATA_PID 0x70 +#define B_PCH_SATA_PID_NEXT 0xFF00 +#define V_PCH_SATA_PID_NEXT_0 0xB000 +#define V_PCH_SATA_PID_NEXT_1 0xA800 +#define B_PCH_SATA_PID_CID 0x00FF +#define R_PCH_SATA_PC 0x72 +#define S_PCH_SATA_PC 2 +#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) +#define V_PCH_SATA_PC_PME_0 0x0000 +#define V_PCH_SATA_PC_PME_1 0x4000 +#define B_PCH_SATA_PC_D2_SUP BIT10 +#define B_PCH_SATA_PC_D1_SUP BIT9 +#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_SATA_PC_DSI BIT5 +#define B_PCH_SATA_PC_PME_CLK BIT3 +#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_SATA_PMCS 0x74 +#define B_PCH_SATA_PMCS_PMES BIT15 +#define B_PCH_SATA_PMCS_PMEE BIT8 +#define B_PCH_SATA_PMCS_NSFRST BIT3 +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 +#define R_PCH_SATA_MID 0x80 +#define B_PCH_SATA_MID_NEXT 0xFF00 +#define B_PCH_SATA_MID_CID 0x00FF +#define R_PCH_SATA_MC 0x82 +#define B_PCH_SATA_MC_C64 BIT7 +#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_PCH_SATA_MC_MME_4 0x04 +#define V_PCH_SATA_MC_MME_2 0x02 +#define V_PCH_SATA_MC_MME_1 0x01 +#define V_PCH_SATA_MC_MME_0 0x00 +#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_PCH_SATA_MC_MMC_4 0x04 +#define V_PCH_SATA_MC_MMC_0 0x00 +#define B_PCH_SATA_MC_MSIE BIT0 +#define V_PCH_SATA_MC_MSIE_1 0x01 +#define V_PCH_SATA_MC_MSIE_0 0x00 +#define R_PCH_SATA_MA 0x84 +#define B_PCH_SATA_MA 0xFFFFFFFC +#define R_PCH_SATA_MD 0x88 +#define B_PCH_SATA_MD_MSIMD 0xFFFF + +// +// Sata Register for PCH-LP +// +#define R_PCH_LP_SATA_MAP 0x90 +#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8) +#define N_PCH_LP_SATA_MAP_SPD 8 +#define B_PCH_LP_SATA_MAP_SPD2 BIT10 +#define B_PCH_LP_SATA_MAP_SPD1 BIT9 +#define B_PCH_LP_SATA_MAP_SPD0 BIT8 +#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6 +#define N_PCH_LP_SATA_MAP_SMS_MASK 6 +#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0 +#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1 +#define R_PCH_LP_SATA_PCS 0x92 +#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15 +#define B_PCH_LP_SATA_PCS_P2P BIT10 +#define B_PCH_LP_SATA_PCS_P1P BIT9 +#define B_PCH_LP_SATA_PCS_P0P BIT8 +#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0) +#define B_PCH_LP_SATA_PCS_P2E BIT2 +#define B_PCH_LP_SATA_PCS_P1E BIT1 +#define B_PCH_LP_SATA_PCS_P0E BIT0 +#define R_PCH_LP_SATA_SCLKGC 0x94 +#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24) +#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26 +#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25 +#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24 +#define R_PCH_LP_SATA_98 0x98 + +// +// Sata Register for PCH-H +// +#define R_PCH_H_SATA_MAP 0x90 +#define B_PCH_H_SATA_MAP_SPD 0xFF0000 +#define N_PCH_H_SATA_MAP_SPD 16 +#define B_PCH_H_SATA_MAP_SPD7 BIT23 +#define B_PCH_H_SATA_MAP_SPD6 BIT22 +#define B_PCH_H_SATA_MAP_SPD5 BIT21 +#define B_PCH_H_SATA_MAP_SPD4 BIT20 +#define B_PCH_H_SATA_MAP_SPD3 BIT19 +#define B_PCH_H_SATA_MAP_SPD2 BIT18 +#define B_PCH_H_SATA_MAP_SPD1 BIT17 +#define B_PCH_H_SATA_MAP_SPD0 BIT16 +#define B_PCH_H_SATA_MAP_PCD 0xFF +#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7 +#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6 +#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5 +#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4 +#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3 +#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2 +#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1 +#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0 +#define R_PCH_H_SATA_PCS 0x94 +#define B_PCH_H_SATA_PCS_P7P BIT23 +#define B_PCH_H_SATA_PCS_P6P BIT22 +#define B_PCH_H_SATA_PCS_P5P BIT21 +#define B_PCH_H_SATA_PCS_P4P BIT20 +#define B_PCH_H_SATA_PCS_P3P BIT19 +#define B_PCH_H_SATA_PCS_P2P BIT18 +#define B_PCH_H_SATA_PCS_P1P BIT17 +#define B_PCH_H_SATA_PCS_P0P BIT16 +#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF +#define B_PCH_H_SATA_PCS_P7E BIT7 +#define B_PCH_H_SATA_PCS_P6E BIT6 +#define B_PCH_H_SATA_PCS_P5E BIT5 +#define B_PCH_H_SATA_PCS_P4E BIT4 +#define B_PCH_H_SATA_PCS_P3E BIT3 +#define B_PCH_H_SATA_PCS_P2E BIT2 +#define B_PCH_H_SATA_PCS_P1E BIT1 +#define B_PCH_H_SATA_PCS_P0E BIT0 + +#define R_PCH_SATA_SATAGC 0x9C +#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16 +#define N_PCH_H_SATA_SATAGC_SMS_MASK 16 +#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0 +#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1 +#define B_PCH_SATA_SATAGC_AIE BIT7 +#define B_PCH_SATA_SATAGC_AIES BIT6 +#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3) +#define V_PCH_SATA_SATAGC_MSS_8K 0x2 +#define N_PCH_SATA_SATAGC_MSS 3 +#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) + +#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0 +#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1 +#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2 +#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3 +#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4 +#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5 +#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6 + +#define R_PCH_SATA_SIRI 0xA0 +#define R_PCH_SATA_STRD 0xA4 +#define R_PCH_SATA_SIR_0C 0x0C +#define R_PCH_SATA_SIR_50 0x50 +#define R_PCH_SATA_SIR_54 0x54 +#define R_PCH_SATA_SIR_58 0x58 +#define R_PCH_SATA_SIR_5C 0x5C +#define R_PCH_SATA_SIR_60 0x60 +#define R_PCH_SATA_SIR_64 0x64 +#define R_PCH_SATA_SIR_68 0x68 +#define R_PCH_SATA_SIR_6C 0x6C +#define R_PCH_SATA_SIR_70 0x70 +#define R_PCH_SATA_SIR_80 0x80 +#define R_PCH_SATA_SIR_84 0x84 +#define R_PCH_SATA_SIR_8C 0x8C +#define R_PCH_SATA_SIR_90 0x90 +#define R_PCH_SATA_SIR_98 0x98 +#define R_PCH_SATA_SIR_9C 0x9C +#define R_PCH_SATA_SIR_A0 0xA0 +#define R_PCH_SATA_SIR_A4 0xA4 +#define R_PCH_SATA_SIR_A8 0xA8 +#define R_PCH_SATA_SIR_C8 0xC8 +#define R_PCH_SATA_SIR_CC 0xCC +#define R_PCH_SATA_SIR_D0 0xD0 +#define R_PCH_SATA_SIR_D4 0xD4 +#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF +#define R_PCH_SATA_CR0 0xA8 +#define B_PCH_SATA_CR0_MAJREV 0x00F00000 +#define B_PCH_SATA_CR0_MINREV 0x000F0000 +#define B_PCH_SATA_CR0_NEXT 0x0000FF00 +#define B_PCH_SATA_CR0_CAP 0x000000FF +#define R_PCH_SATA_CR1 0xAC +#define B_PCH_SATA_CR1_BAROFST 0xFFF0 +#define B_PCH_SATA_CR1_BARLOC 0x000F +#define R_PCH_SATA_FLR_CID 0xB0 +#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 +#define B_PCH_SATA_FLR_CID 0x00FF +#define V_PCH_SATA_FLR_CID_1 0x0009 +#define V_PCH_SATA_FLR_CID_0 0x0013 +#define R_PCH_SATA_FLR_CLV 0xB2 +#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_PCH_SATA_FLRC 0xB4 +#define B_PCH_SATA_FLRC_TXP BIT8 +#define B_PCH_SATA_FLRC_INITFLR BIT0 +#define R_PCH_SATA_SP 0xC0 +#define B_PCH_SATA_SP 0xFFFFFFFF +#define R_PCH_SATA_MXID 0xD0 +#define N_PCH_SATA_MXID_NEXT 8 + +#define R_PCH_SATA_BFCS 0xE0 +#define B_PCH_SATA_BFCS_P7BFI BIT17 +#define B_PCH_SATA_BFCS_P6BFI BIT16 +#define B_PCH_SATA_BFCS_P5BFI BIT15 +#define B_PCH_SATA_BFCS_P4BFI BIT14 +#define B_PCH_SATA_BFCS_P3BFI BIT13 +#define B_PCH_SATA_BFCS_P2BFI BIT12 +#define B_PCH_SATA_BFCS_P2BFS BIT11 +#define B_PCH_SATA_BFCS_P2BFF BIT10 +#define B_PCH_SATA_BFCS_P1BFI BIT9 +#define B_PCH_SATA_BFCS_P0BFI BIT8 +#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7 +#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6 +#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5 +#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4 +#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3 +#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 +#define R_PCH_SATA_BFTD1 0xE4 +#define B_PCH_SATA_BFTD1 0xFFFFFFFF +#define R_PCH_SATA_BFTD2 0xE8 +#define B_PCH_SATA_BFTD2 0xFFFFFFFF + +#define R_PCH_SATA_VS_CAP 0xA4 +#define B_PCH_SATA_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable +#define B_PCH_SATA_VS_CAP_MSL 0x1FFE ///< Memory Space Limit +#define N_PCH_SATA_VS_CAP_MSL 1 +#define V_PCH_SATA_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value +#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 ///< NVM Remapped Memory Offset +#define N_PCH_SATA_VS_CAP_NRMO 16 +#define V_PCH_SATA_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value + +// +// RST PCIe Storage Remapping Registers +// +#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 ///< Remap Capability Register +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) ///< Number of Remapping Supported +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1) +#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C ///< Scratch Pad Register +#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 ///< CR#1 Device Class Code +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8 +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16 +#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 ///< Device Type +#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 ///< Remapped Configuration for RST PCIe Storage Cycle Router #n +#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 ///< Remapped Root Port Offset Value +#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 ///< Port Configuration Register + +// +// AHCI BAR Area related Registers +// +#define R_PCH_SATA_AHCI_CAP 0x0 +#define B_PCH_SATA_AHCI_CAP_S64A BIT31 +#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 +#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 +#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock Switch +#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up +#define B_PCH_SATA_AHCI_CAP_SALP BIT26 +#define B_PCH_SATA_AHCI_CAP_SAL BIT25 +#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override +#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support +#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 +#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 +#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 +#define B_PCH_SATA_AHCI_CAP_SAM BIT18 +#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier +#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block +#define B_PCH_SATA_AHCI_CAP_SSC BIT14 +#define B_PCH_SATA_AHCI_CAP_PSC BIT13 +#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 +#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 +#define B_PCH_SATA_AHCI_CAP_EMS BIT6 +#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is supported +#define B_PCH_SATA_AHCI_CAP_NPS 0x001F + +#define R_PCH_SATA_AHCI_GHC 0x04 +#define B_PCH_SATA_AHCI_GHC_AE BIT31 +#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 +#define B_PCH_SATA_AHCI_GHC_IE BIT1 +#define B_PCH_SATA_AHCI_GHC_HR BIT0 + +#define R_PCH_SATA_AHCI_IS 0x08 +#define B_PCH_SATA_AHCI_IS_PORT7 BIT7 +#define B_PCH_SATA_AHCI_IS_PORT6 BIT6 +#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 +#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 +#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 +#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 +#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 +#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 +#define R_PCH_SATA_AHCI_PI 0x0C +#define B_PCH_H_SATA_PORT_MASK 0xFF +#define B_PCH_LP_SATA_PORT_MASK 0x03 +#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7 +#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6 +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 +#define R_PCH_SATA_AHCI_VS 0x10 +#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 +#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_LOC 0x1C +#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_CTRL 0x20 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 +#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 +#define R_PCH_SATA_AHCI_CAP2 0x24 +#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 +#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 +#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 +#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions +#define R_PCH_SATA_AHCI_VSP 0xA0 +#define B_PCH_SATA_AHCI_VSP_SLPD BIT0 +#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabilities +#define B_PCH_SATA_AHCI_RSTF_OMA BIT13 +#define B_PCH_SATA_AHCI_RSTF_LEGACY BIT12 +#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10) +#define N_PCH_SATA_AHCI_RSTF_OUD 10 +#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9 +#define B_PCH_SATA_AHCI_RSTF_IROES BIT8 +#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7 +#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6 +#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5 +#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4 +#define B_PCH_SATA_AHCI_RSTF_R5E BIT3 +#define B_PCH_SATA_AHCI_RSTF_R10E BIT2 +#define B_PCH_SATA_AHCI_RSTF_R1E BIT1 +#define B_PCH_SATA_AHCI_RSTF_R0E BIT0 +#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF +#define R_PCH_SATA_AHCI_P0CLB 0x100 +#define R_PCH_SATA_AHCI_P1CLB 0x180 +#define R_PCH_SATA_AHCI_P2CLB 0x200 +#define R_PCH_SATA_AHCI_P3CLB 0x280 +#define R_PCH_SATA_AHCI_P4CLB 0x300 +#define R_PCH_SATA_AHCI_P5CLB 0x380 +#define R_PCH_SATA_AHCI_P6CLB 0x400 +#define R_PCH_SATA_AHCI_P7CLB 0x480 +#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 +#define R_PCH_SATA_AHCI_P0CLBU 0x104 +#define R_PCH_SATA_AHCI_P1CLBU 0x184 +#define R_PCH_SATA_AHCI_P2CLBU 0x204 +#define R_PCH_SATA_AHCI_P3CLBU 0x284 +#define R_PCH_SATA_AHCI_P4CLBU 0x304 +#define R_PCH_SATA_AHCI_P5CLBU 0x384 +#define R_PCH_SATA_AHCI_P6CLBU 0x404 +#define R_PCH_SATA_AHCI_P7CLBU 0x484 +#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0FB 0x108 +#define R_PCH_SATA_AHCI_P1FB 0x188 +#define R_PCH_SATA_AHCI_P2FB 0x208 +#define R_PCH_SATA_AHCI_P3FB 0x288 +#define R_PCH_SATA_AHCI_P4FB 0x308 +#define R_PCH_SATA_AHCI_P5FB 0x388 +#define R_PCH_SATA_AHCI_P6FB 0x408 +#define R_PCH_SATA_AHCI_P7FB 0x488 +#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 +#define R_PCH_SATA_AHCI_P0FBU 0x10C +#define R_PCH_SATA_AHCI_P1FBU 0x18C +#define R_PCH_SATA_AHCI_P2FBU 0x20C +#define R_PCH_SATA_AHCI_P3FBU 0x28C +#define R_PCH_SATA_AHCI_P4FBU 0x30C +#define R_PCH_SATA_AHCI_P5FBU 0x38C +#define R_PCH_SATA_AHCI_P6FBU 0x40C +#define R_PCH_SATA_AHCI_P7FBU 0x48C +#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0IS 0x110 +#define R_PCH_SATA_AHCI_P1IS 0x190 +#define R_PCH_SATA_AHCI_P2IS 0x210 +#define R_PCH_SATA_AHCI_P3IS 0x290 +#define R_PCH_SATA_AHCI_P4IS 0x310 +#define R_PCH_SATA_AHCI_P5IS 0x390 +#define R_PCH_SATA_AHCI_P6IS 0x410 +#define R_PCH_SATA_AHCI_P7IS 0x490 +#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 +#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 +#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 +#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 +#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 +#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 +#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 +#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 +#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 +#define B_PCH_SATA_AHCI_PXIS_DIS BIT7 +#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 +#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 +#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 +#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 +#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 +#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 +#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 +#define R_PCH_SATA_AHCI_P0IE 0x114 +#define R_PCH_SATA_AHCI_P1IE 0x194 +#define R_PCH_SATA_AHCI_P2IE 0x214 +#define R_PCH_SATA_AHCI_P3IE 0x294 +#define R_PCH_SATA_AHCI_P4IE 0x314 +#define R_PCH_SATA_AHCI_P5IE 0x394 +#define R_PCH_SATA_AHCI_P6IE 0x414 +#define R_PCH_SATA_AHCI_P7IE 0x494 +#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 +#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 +#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 +#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 +#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 +#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 +#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 +#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 +#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 +#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 +#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 +#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 +#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 +#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 +#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 +#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 +#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 +#define R_PCH_SATA_AHCI_P0CMD 0x118 +#define R_PCH_SATA_AHCI_P1CMD 0x198 +#define R_PCH_SATA_AHCI_P2CMD 0x218 +#define R_PCH_SATA_AHCI_P3CMD 0x298 +#define R_PCH_SATA_AHCI_P4CMD 0x318 +#define R_PCH_SATA_AHCI_P5CMD 0x398 +#define R_PCH_SATA_AHCI_P6CMD 0x418 +#define R_PCH_SATA_AHCI_P7CMD 0x498 +#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18) +#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 +#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 +#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 +#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 +#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 +#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 +#define R_PCH_SATA_AHCI_P2DEVSLP 0x244 +#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4 +#define R_PCH_SATA_AHCI_P4DEVSLP 0x344 +#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4 +#define R_PCH_SATA_AHCI_P6DEVSLP 0x444 +#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4 +#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 +#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device +#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port +#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 +#define B_PCH_SATA_AHCI_PxCMD_FR BIT14 +#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13 +#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 +#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4 +#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 +#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 +#define R_PCH_SATA_AHCI_P0TFD 0x120 +#define R_PCH_SATA_AHCI_P1TFD 0x1A0 +#define R_PCH_SATA_AHCI_P2TFD 0x220 +#define R_PCH_SATA_AHCI_P3TFD 0x2A0 +#define R_PCH_SATA_AHCI_P4TFD 0x320 +#define R_PCH_SATA_AHCI_P5TFD 0x3A0 +#define R_PCH_SATA_AHCI_P6TFD 0x420 +#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF +#define R_PCH_SATA_AHCI_P0SIG 0x124 +#define R_PCH_SATA_AHCI_P1SIG 0x1A4 +#define R_PCH_SATA_AHCI_P2SIG 0x224 +#define R_PCH_SATA_AHCI_P3SIG 0x2A4 +#define R_PCH_SATA_AHCI_P4SIG 0x324 +#define R_PCH_SATA_AHCI_P5SIG 0x3A4 +#define R_PCH_SATA_AHCI_P6SIG 0x424 +#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF +#define R_PCH_SATA_AHCI_P0SSTS 0x128 +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 +#define R_PCH_SATA_AHCI_P2SSTS 0x228 +#define R_PCH_SATA_AHCI_P3SSTS 0x2A8 +#define R_PCH_SATA_AHCI_P4SSTS 0x328 +#define R_PCH_SATA_AHCI_P5SSTS 0x3A8 +#define R_PCH_SATA_AHCI_P6SSTS 0x428 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SCTL 0x12C +#define R_PCH_SATA_AHCI_P1SCTL 0x1AC +#define R_PCH_SATA_AHCI_P2SCTL 0x22C +#define R_PCH_SATA_AHCI_P3SCTL 0x2AC +#define R_PCH_SATA_AHCI_P4SCTL 0x32C +#define R_PCH_SATA_AHCI_P5SCTL 0x3AC +#define R_PCH_SATA_AHCI_P6SCTL 0x42C +#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F +#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SERR 0x130 +#define R_PCH_SATA_AHCI_P1SERR 0x1B0 +#define R_PCH_SATA_AHCI_P2SERR 0x230 +#define R_PCH_SATA_AHCI_P3SERR 0x2B0 +#define R_PCH_SATA_AHCI_P4SERR 0x330 +#define R_PCH_SATA_AHCI_P5SERR 0x3B0 +#define R_PCH_SATA_AHCI_P6SERR 0x430 +#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1 +#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0 +#define R_PCH_SATA_AHCI_P0SACT 0x134 +#define R_PCH_SATA_AHCI_P1SACT 0x1B4 +#define R_PCH_SATA_AHCI_P2SACT 0x234 +#define R_PCH_SATA_AHCI_P3SACT 0x2B4 +#define R_PCH_SATA_AHCI_P4SACT 0x334 +#define R_PCH_SATA_AHCI_P5SACT 0x3B4 +#define R_PCH_SATA_AHCI_P6SACT 0x434 +#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0CI 0x138 +#define R_PCH_SATA_AHCI_P1CI 0x1B8 +#define R_PCH_SATA_AHCI_P2CI 0x238 +#define R_PCH_SATA_AHCI_P3CI 0x2B8 +#define R_PCH_SATA_AHCI_P4CI 0x338 +#define R_PCH_SATA_AHCI_P5CI 0x3B8 +#define R_PCH_SATA_AHCI_P6CI 0x438 +#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_SKL_PCH_H_SATA_DEVICE_ID_D_AHCI_A0) || \ + (DeviceId == V_SKL_PCH_H_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_KBL_PCH_H_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ) + +// +// SATA RAID Device ID macros +// +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE) || \ + (DeviceId == V_SKL_PCH_H_SATA_DEVICE_ID_D_RAID_RRT) || \ + (DeviceId == V_KBL_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_KBL_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) \ + ) + + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ) +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ) + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsScs.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsScs.h new file mode 100644 index 0000000000..b1872adbe6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsScs.h @@ -0,0 +1,202 @@ +/** @file + Register names for PCH Storage and Communication Subsystem + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_SCS_H_ +#define _PCH_REGS_SCS_H_ + +// +// SCS eMMC Controller Registers (D30:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SCS_EMMC 30 +#define PCI_FUNCTION_NUMBER_PCH_SCS_EMMC 4 +#define V_PCH_SCS_EMMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_SCS_EMMC_DEVICE_ID 0x9D2B + +// +// SCS SDIO Controller Registers (D30:F5) +// +#define PCI_DEVICE_NUMBER_PCH_SCS_SDIO 30 +#define PCI_FUNCTION_NUMBER_PCH_SCS_SDIO 5 +#define V_PCH_SCS_SDIO_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_SCS_SDIO_DEVICE_ID 0x9D2C + +// +// SCS SDCARD Controller Registers (D30:F6) +// +#define PCI_DEVICE_NUMBER_PCH_SCS_SDCARD 30 +#define PCI_FUNCTION_NUMBER_PCH_SCS_SDCARD 6 +#define V_PCH_SCS_SDCARD_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_SCS_SDCARD_DEVICE_ID 0x9D2D + +// +// SCS Devices PCI Config Space Registers +// +#define R_PCH_SCS_DEV_PCS 0x84 ///< PME Control Status +#define B_PCH_SCS_DEV_PCS_PMESTS BIT15 ///< PME Status +#define B_PCH_SCS_DEV_PCS_PMEEN BIT8 ///< PME Enable +#define B_PCH_SCS_DEV_PCS_NSS BIT3 ///< No Soft Reset +#define B_PCH_SCS_DEV_PCS_PS (BIT1 | BIT0) ///< Power State +#define B_PCH_SCS_DEV_PCS_PS_D3HOT (BIT1 | BIT0) ///< Power State: D3Hot State +#define R_PCH_SCS_DEV_PG_CONFIG 0xA2 ///< PG Config +#define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 ///< Sleep Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 ///< PG Enable +#define B_PCH_SCS_DEV_PG_CONFIG_I3E BIT1 ///< I3 Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PMCRE BIT0 ///< PMC Request Enable +#define V_PCH_SCS_DEV_BAR0_SIZE 0x1000 ///< BAR0 size +// +// SCS Devices MMIO Space Register +// +#define R_PCH_SCS_DEV_MEM_DMAADR 0x00 +#define R_PCH_SCS_DEV_MEM_BLKSZ 0x04 +#define R_PCH_SCS_DEV_MEM_BLKCNT 0x06 +#define R_PCH_SCS_DEV_MEM_CMDARG 0x08 +#define R_PCH_SCS_DEV_MEM_XFRMODE 0x0C +#define B_PCH_SCS_DEV_MEM_XFRMODE_DMA_EN BIT0 +#define B_PCH_SCS_DEV_MEM_XFRMODE_BLKCNT_EN BIT1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3) +#define V_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD12_EN 1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_DATA_TRANS_DIR BIT4 ///< 1: Read (Card to Host), 0: Write (Host to Card) +#define B_PCH_SCS_DEV_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 ///< 1: Multiple Block, 0: Single Block +#define R_PCH_SCS_DEV_MEM_SDCMD 0x0E +#define B_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1) +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4 +#define B_PCH_SCS_DEV_MEM_SDCMD_DATA_PRESENT_SEL BIT5 +#define R_PCH_SCS_DEV_MEM_RESP 0x10 +#define R_PCH_SCS_DEV_MEM_BUFDATAPORT 0x20 +#define R_PCH_SCS_DEV_MEM_PSTATE 0x24 +#define B_PCH_SCS_DEV_MEM_PSTATE_DAT0 BIT20 +#define R_PCH_SCS_DEV_MEM_PWRCTL 0x29 +#define R_PCH_SCS_DEV_MEM_CLKCTL 0x2C +#define R_PCH_SCS_DEV_MEM_TIMEOUT_CTL 0x2E ///< Timeout Control +#define B_PCH_SCS_DEV_MEM_TIMEOUT_CTL_DTCV 0x0F ///< Data Timeout Counter Value +#define R_PCH_SCS_DEV_MEM_SWRST 0x2F +#define B_PCH_SCS_DEV_MEM_SWRST_CMDLINE BIT1 +#define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2 +#define R_PCH_SCS_DEV_MEM_NINTSTS 0x30 +#define B_PCH_SCS_DEV_MEM_NINTSTS_MASK 0xFFFF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CLEAR_MASK 0x60FF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CMD_COMPLETE BIT0 +#define B_PCH_SCS_DEV_MEM_NINTSTS_TRANSFER_COMPLETE BIT1 +#define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3 +#define B_PCH_SCS_DEV_MEM_NINTSTS_BUF_READ_READY_INTR BIT5 +#define R_PCH_SCS_DEV_MEM_ERINTSTS 0x32 +#define B_PCH_SCS_DEV_MEM_ERINTSTS_MASK 0x13FF +#define B_PCH_SCS_DEV_MEM_ERINTSTS_CLEAR_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTEN 0x34 +#define B_PCH_SCS_DEV_MEM_NINTEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTEN 0x36 +#define B_PCH_SCS_DEV_MEM_ERINTEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTSIGNEN 0x38 +#define B_PCH_SCS_DEV_MEM_NINTSIGNEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTSIGNEN 0x3A +#define B_PCH_SCS_DEV_MEM_ERINTSIGNEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_HOST_CTL2 0x3E +#define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2) +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_HS400 5 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_DDR50 4 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR104 3 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR25 1 +#define R_PCH_SCS_DEV_MEM_CAP1 0x40 +#define R_PCH_SCS_DEV_MEM_CAP2 0x44 +#define B_PCH_SCS_DEV_MEM_CAP2_HS400_SUPPORT BIT31 +#define B_PCH_SCS_DEV_MEM_CAP2_SDR104_SUPPORT BIT1 +#define R_PCH_SCS_DEV_MEM_CESHC2 0x3C ///< Auto CMD12 Error Status Register & Host Control 2 +#define B_PCH_SCS_DEV_MEM_CESHC2_ASYNC_INT BIT30 ///< Asynchronous Interrupt Enable +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL 0x810 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL_EN 0x5A +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1 0x814 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_EMMC_DEFAULTS 0x3C80EB1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDIO_DEFAULTS 0x1C80EF1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDCARD_DEFAULTS 0x1C80E75C +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_HS400 BIT29 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 22 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 0x1 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20 | BIT19 | BIT18 | BIT17) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE (BIT12 | BIT11) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE 11 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE_EMBEDDED 0x1 +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2 0x818 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_EMMC_DEFAULTS 0x040040C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDIO_DEFAULTS 0x040000C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDCARD_DEFAULTS 0x040000C8 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL1 0x820 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL2 0x80C +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL1 0x824 +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL2 0x828 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C +#define R_PCH_SCS_DEV_MEM_RX_STROBE_DLL_CNTL 0x830 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2 0x834 +#define N_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_BEFORE 0x1 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AFTER 0x0 + +// +// SCS Private Configuration Space Registers +// +#define R_PCH_PCR_SCS_IOSFCTL 0x00 ///< IOSF Control +#define B_PCH_PCR_SCS_IOSFCTL_NSNPDIS BIT7 ///< Non-Snoop Disable +#define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream pending reads +#define R_PCH_PCR_SCS_OCPCTL 0x10 ///< OCP Control +#define B_PCH_PCR_SCS_OCPCTL_NPEN BIT0 ///< Downstream non-posted memory write capability +#define R_PCH_PCR_SCS_PMCTL 0x1D0 ///< Power Management Control +#define R_PCH_PCR_SCS_PCICFGCTR_EMMC 0x200 ///< PCI Configuration Control 1 - eMMC +#define R_PCH_PCR_SCS_PCICFGCTR_SDIO 0x204 ///< PCI Configuration Control 2 - SDIO +#define R_PCH_PCR_SCS_PCICFGCTR_SDCARD 0x208 ///< PCI Configuration Control 3 - SD Card +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_SCS_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin +#define N_PCH_PCR_SCS_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_SCS_PCICFGCTR_BAR1DIS BIT7 ///< BAR 1 Disable +#define B_PCH_PCR_SCS_PCICFGCTR_PS 0x7C ///< PME Support +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_INT_EN BIT1 ///< ACPI Interrupt Enable +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_CFG_DIS BIT0 ///< PCI Configuration Space Disable + +#define R_PCH_PCR_SCS_GPPRVRW1 0x600 ///< Clock Gating Control +#define R_PCH_PCR_SCS_GPPRVRW2 0x604 ///< Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_EMMC_DIS BIT1 ///< eMMC Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 ///< 1: SDIO Host Controller Disable, 0: SDCARD Host Controller Disable +#define R_PCH_PCR_SCS_GPPRVRW6 0x614 ///< 1.8V Signal Select Delay Control +#define V_PCH_PCR_SCS_GPPRVRW6_1P8_SEL_DELAY 0x7F ///< Rcomp SDCARD 10ms delay during switch + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h new file mode 100644 index 0000000000..461b935fde --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h @@ -0,0 +1,325 @@ +/** @file + Register names for PCH Serial IO Controllers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_SERIAL_IO_ +#define _PCH_REGS_SERIAL_IO_ + + +// +// Serial IO I2C0 Controller Registers (D21:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0 +#define V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID 0x9D60 +#define V_SKL_PCH_H_SERIAL_IO_I2C0_DEVICE_ID 0xA160 +#define V_KBL_PCH_H_SERIAL_IO_I2C0_DEVICE_ID 0xA2E0 + +// +// Serial IO I2C1 Controller Registers (D21:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1 +#define V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID 0x9D61 +#define V_SKL_PCH_H_SERIAL_IO_I2C1_DEVICE_ID 0xA161 +#define V_KBL_PCH_H_SERIAL_IO_I2C1_DEVICE_ID 0xA2E1 + +// +// Serial IO I2C2 Controller Registers (D21:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2 +#define V_PCH_LP_SERIAL_IO_I2C2_DEVICE_ID 0x9D62 +#define V_SKL_PCH_H_SERIAL_IO_I2C2_DEVICE_ID 0xA162 +#define V_KBL_PCH_H_SERIAL_IO_I2C2_DEVICE_ID 0xA2E2 + +// +// Serial IO I2C3 Controller Registers (D21:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3 +#define V_PCH_LP_SERIAL_IO_I2C3_DEVICE_ID 0x9D63 +#define V_SKL_PCH_H_SERIAL_IO_I2C3_DEVICE_ID 0xA163 +#define V_KBL_PCH_H_SERIAL_IO_I2C3_DEVICE_ID 0xA2E3 + +// +// Serial IO I2C4 Controller Registers (D25:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 2 +#define V_PCH_LP_SERIAL_IO_I2C4_DEVICE_ID 0x9D64 + +// +// Serial IO I2C5 Controller Registers (D25:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1 +#define V_PCH_LP_SERIAL_IO_I2C5_DEVICE_ID 0x9D65 + +// +// Serial IO SPI0 Controller Registers (D30:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2 +#define V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID 0x9D29 +#define V_SKL_PCH_H_SERIAL_IO_SPI0_DEVICE_ID 0xA129 +#define V_KBL_PCH_H_SERIAL_IO_SPI0_DEVICE_ID 0xA2A9 + +// +// Serial IO SPI1 Controller Registers (D30:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3 +#define V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID 0x9D2A +#define V_SKL_PCH_H_SERIAL_IO_SPI1_DEVICE_ID 0xA129 +#define V_KBL_PCH_H_SERIAL_IO_SPI1_DEVICE_ID 0xA2AA + +// +// Serial IO UART0 Controller Registers (D30:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0 +#define V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID 0x9D27 +#define V_SKL_PCH_H_SERIAL_IO_UART0_DEVICE_ID 0xA127 +#define V_KBL_PCH_H_SERIAL_IO_UART0_DEVICE_ID 0xA2A7 + +// +// Serial IO UART1 Controller Registers (D30:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1 +#define V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID 0x9D28 +#define V_SKL_PCH_H_SERIAL_IO_UART1_DEVICE_ID 0xA128 +#define V_KBL_PCH_H_SERIAL_IO_UART1_DEVICE_ID 0xA2A8 + +// +// Serial IO UART2 Controller Registers (D25:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 0 +#define V_PCH_LP_SERIAL_IO_UART2_DEVICE_ID 0x9D66 +#define V_SKL_PCH_H_SERIAL_IO_UART2_DEVICE_ID 0xA166 +#define V_KBL_PCH_H_SERIAL_IO_UART2_DEVICE_ID 0xA2E6 + +#define V_PCH_SERIAL_IO_DEV_MIN_FUN 0 +#define V_PCH_SERIAL_IO_DEV_MAX_FUN 5 + +// +// Serial IO Controllers General PCI Configuration Registers +// registers accessed using PciD21FxRegBase + offset +// +#define R_PCH_SERIAL_IO_BAR0_LOW 0x10 +#define B_PCH_SERIAL_IO_BAR0_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR0_HIGH 0x14 +#define R_PCH_SERIAL_IO_BAR1_LOW 0x18 +#define B_PCH_SERIAL_IO_BAR1_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR1_HIGH 0x1C +#define V_PCH_SERIAL_IO_BAR_SIZE (4 * 1024) +#define N_PCH_SERIAL_IO_BAR_ALIGNMENT 12 + +#define R_PCH_SERIAL_IO_PME_CTRL_STS 0x84 +#define B_PCH_SERIAL_IO_PME_CTRL_STS_PWR_ST (BIT1| BIT0) + +#define R_PCH_SERIAL_IO_D0I3MAXDEVPG 0xA0 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PMCRE BIT16 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_I3E BIT17 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PGE BIT18 + +#define R_PCH_SERIAL_IO_INTERRUPTREG 0x3C +#define B_PCH_SERIAL_IO_INTERRUPTREG_INTLINE 0x000000FF + +// +// Serial IO Controllers Private Registers +// registers accessed : BAR0 + offset +// +#define R_PCH_SERIAL_IO_SSCR1 0x4 +#define B_PCH_SERIAL_IO_SSCR1_IFS BIT16 + +#define R_PCH_SERIAL_IO_PPR_CLK 0x200 +#define B_PCH_SERIAL_IO_PPR_CLK_EN BIT0 +#define B_PCH_SERIAL_IO_PPR_CLK_UPDATE BIT31 +#define V_PCH_SERIAL_IO_PPR_CLK_M_DIV 0x30 +#define V_PCH_SERIAL_IO_PPR_CLK_N_DIV 0xC35 + +#define R_PCH_SERIAL_IO_PPR_RESETS 0x204 +#define B_PCH_SERIAL_IO_PPR_RESETS_FUNC BIT0 +#define B_PCH_SERIAL_IO_PPR_RESETS_APB BIT1 +#define B_PCH_SERIAL_IO_PPR_RESETS_IDMA BIT2 + +#define R_PCH_SERIAL_IO_ACTIVE_LTR 0x210 +#define R_PCH_SERIAL_IO_IDLE_LTR 0x214 +#define B_PCH_SERIAL_IO_LTR_SNOOP_VALUE 0x000003FF +#define B_PCH_SERIAL_IO_LTR_SNOOP_SCALE 0x00001C00 +#define B_PCH_SERIAL_IO_LTR_SNOOP_REQUIREMENT BIT15 + +#define R_PCH_SERIAL_IO_SPI_CS_CONTROL 0x224 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_STATE BIT1 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_MODE BIT0 + +#define R_PCH_SERIAL_IO_REMAP_ADR_LOW 0x240 +#define R_PCH_SERIAL_IO_REMAP_ADR_HIGH 0x244 + +#define R_PCH_SERIAL_IO_I2C_SDA_HOLD 0x7C +#define V_PCH_SERIAL_IO_I2C_SDA_HOLD_VALUE 0x002C002C + +// +// I2C Controller +// Registers accessed through BAR0 + offset +// +#define R_IC_CON 0x00 // I2c Control +#define B_IC_MASTER_MODE BIT0 +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_IC_SPEED_STANDARD 0x02 +#define V_IC_SPEED_FAST 0x04 +#define V_IC_SPEED_HIGH 0x06 + +#define R_IC_TAR 0x04 // I2c Target Address +#define B_IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buffer and Command +#define B_IC_CMD_READ BIT8 // 1 = read, 0 = write +#define B_IC_CMD_STOP BIT9 // 1 = STOP +#define B_IC_CMD_RESTART BIT10 // 1 = IC_RESTART_EN +#define V_IC_WRITE_CMD_MASK 0xFF + +#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c Clock SCL High Count +#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c Clock SCL Low Count +#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Clock SCL High Count +#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Clock SCL Low Count +#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Clock SCL High Count +#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Clock SCL Low Count +#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status +#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask +#define B_IC_INTR_GEN_CALL BIT11 // General call received +#define B_IC_INTR_START_DET BIT10 +#define B_IC_INTR_STOP_DET BIT9 +#define B_IC_INTR_ACTIVITY BIT8 +#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK +#define B_IC_INTR_TX_EMPTY BIT4 +#define B_IC_INTR_TX_OVER BIT3 +#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold +#define B_IC_INTR_RX_OVER BIT1 +#define B_IC_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt Status +#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO Threshold +#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO Threshold +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt +#define R_IC_ENABLE ( 0x6C) // I2c Enable + +#define R_IC_STATUS 0x70 // I2c Status +#define B_IC_STATUS_RFF BIT4 // RX FIFO is completely full +#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not empty +#define B_IC_STATUS_TFE BIT2 // TX FIFO is completely empty +#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not full +#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activity Status. + +#define R_IC_TXFL R ( 0x74) // Transmit FIFO Level Register +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register +#define R_IC_SDA_HOLD ( 0x7C) +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort Status Register +#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address + +#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Register +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Call Register +#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status Register +#define B_IC_EN BIT0 // I2c enable status + +#define R_IC_CLK_GATE (0xC0) +#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID +#define R_IC_COMP_TYPE ( 0xFC) // Component Type + + + +// +// Bridge Private Configuration Registers +// accessed only through SB messaging. SB access = SerialIo IOSF2OCP Bridge Port ID + offset +// +#define R_PCH_PCR_SERIAL_IO_PMCTL 0x1D0 +#define V_PCH_PCR_SERIAL_IO_PMCTL_PWR_GATING 0x3F + +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRLx 0x200 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_N_OFFS 0x04 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL1 0x200 //I2C0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL2 0x204 //I2C1 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL3 0x208 //I2C2 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL4 0x20C //I2C3 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL5 0x210 //I2C4 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL6 0x214 //I2C5 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL9 0x218 //UA00 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL10 0x21C //UA01 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL11 0x220 //UA02 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL13 0x224 //SPI0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL14 0x228 //SPI1 + +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_CFG_DIS BIT0 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_INTR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_BAR1_DIS BIT7 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN 8 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTA 0x01 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTB 0x02 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTC 0x03 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTD 0x04 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 20 + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW2 0x604 +#define V_PCH_PCR_SERIAL_IO_GPPRVRW2_CLK_GATING (BIT11 | BIT1) + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW7 0x618 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2 + +// +// Number of pins used by SerialIo controllers +// +#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 +#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h new file mode 100644 index 0000000000..9682040879 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h @@ -0,0 +1,149 @@ +/** @file + Register names for PCH Smbus Device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 +#define R_PCH_SMBUS_BASE 0x20 +#define V_PCH_SMBUS_BASE_SIZE (1 << 5) +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SPDWD BIT4 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +#define R_PCH_SMBUS_TCOBASE 0x50 +#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_TCOCTL 0x54 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 +#define R_PCH_SMBUS_64 0x64 +#define R_PCH_SMBUS_80 0x80 + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL) +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 +#define B_PCH_SMBUS_SMB_CMD 0x1C +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_PCH_SMBUS_LAST_BYTE 0x20 +#define B_PCH_SMBUS_START 0x40 +#define B_PCH_SMBUS_PEC_EN 0x80 +#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W +#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W +#define B_PCH_SMBUS_RW_SEL 0x01 +#define B_PCH_SMBUS_READ 0x01 // RW +#define B_PCH_SMBUS_WRITE 0x00 // RW +#define B_PCH_SMBUS_ADDRESS 0xFE +#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W +#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W +#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F +#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W +#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC +#define B_PCH_SMBUS_CRCE 0x01 +#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode +#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W +#define B_PCH_SMBUS_AAC 0x01 +#define B_PCH_SMBUS_E32B 0x02 +#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W +#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 +#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 +#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 +#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W +#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 +#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 +#define B_PCH_SMBUS_SMBCLK_CTL 0x04 +#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 +#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 +#define B_PCH_SMBUS_SMBALERT_DIS 0x04 +#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE +#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO +#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO + +// +// SMBus Private Config Registers +// (PID:SMB) +// +#define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register +#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable +#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled +#define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode +#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter +#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch +#define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode +#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up +#define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control +#define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable +#define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot +#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h new file mode 100644 index 0000000000..f43c676797 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h @@ -0,0 +1,309 @@ +/** @file + Register names for PCH SPI device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Registers (D31:F5) +// + +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 + +#define R_PCH_SPI_BAR0 0x10 +#define B_PCH_SPI_BAR0_MASK 0x0FFF + +#define R_PCH_SPI_BDE 0xD8 +#define B_PCH_SPI_BDE_F8 0x8000 +#define B_PCH_SPI_BDE_F0 0x4000 +#define B_PCH_SPI_BDE_E8 0x2000 +#define B_PCH_SPI_BDE_E0 0x1000 +#define B_PCH_SPI_BDE_D8 0x0800 +#define B_PCH_SPI_BDE_D0 0x0400 +#define B_PCH_SPI_BDE_C8 0x0200 +#define B_PCH_SPI_BDE_C0 0x0100 +#define B_PCH_SPI_BDE_LEG_F 0x0080 +#define B_PCH_SPI_BDE_LEG_E 0x0040 +#define B_PCH_SPI_BDE_70 0x0008 +#define B_PCH_SPI_BDE_60 0x0004 +#define B_PCH_SPI_BDE_50 0x0002 +#define B_PCH_SPI_BDE_40 0x0001 + +#define R_PCH_SPI_BC 0xDC +#define S_PCH_SPI_BC 4 +#define N_PCH_SPI_BC_ASE_BWP 11 +#define B_PCH_SPI_BC_ASE_BWP BIT11 +#define N_PCH_SPI_BC_ASYNC_SS 10 +#define B_PCH_SPI_BC_ASYNC_SS BIT10 +#define B_PCH_SPI_BC_OSFH BIT9 ///< OS Function Hide +#define N_PCH_SPI_BC_SYNC_SS 8 +#define B_PCH_SPI_BC_SYNC_SS BIT8 +#define B_PCH_SPI_BC_BILD BIT7 +#define B_PCH_SPI_BC_BBS BIT6 ///< Boot BIOS strap +#define N_PCH_SPI_BC_BBS 6 +#define V_PCH_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_PCH_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_PCH_SPI_BC_EISS BIT5 ///< Enable InSMM.STS +#define B_PCH_SPI_BC_TSS BIT4 +#define B_PCH_SPI_BC_SRC (BIT3 | BIT2) +#define N_PCH_SPI_BC_SRC 2 +#define V_PCH_SPI_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetching and Caching enabled +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefetching, but caching enabled +#define B_PCH_SPI_BC_LE BIT1 ///< Lock Enable +#define N_PCH_SPI_BC_BLE 1 +#define B_PCH_SPI_BC_WPD BIT0 ///< Write Protect Disable + +// +// BIOS Flash Program Registers (based on SPI_BAR0) +// +#define R_PCH_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1 +#define B_PCH_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit mask +#define N_PCH_SPI_BFPR_PRL 16 ///< BIOS Flash Primary Region Limit bit position +#define B_PCH_SPI_BFPR_PRB 0x00007FFF ///< BIOS Flash Primary Region Base mask +#define N_PCH_SPI_BFPR_PRB 0 ///< BIOS Flash Primary Region Base bit position +#define R_PCH_SPI_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_PCH_SPI_HSFSC_FSMIE BIT31 ///< Flash SPI SMI# Enable +#define B_PCH_SPI_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. +#define N_PCH_SPI_HSFSC_FDBC 24 +#define B_PCH_SPI_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle. +#define N_PCH_SPI_HSFSC_CYCLE 17 +#define V_PCH_SPI_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read +#define V_PCH_SPI_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write +#define V_PCH_SPI_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase +#define V_PCH_SPI_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase +#define V_PCH_SPI_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP +#define V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID +#define V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status +#define V_PCH_SPI_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status +#define B_PCH_SPI_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go. +#define B_PCH_SPI_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down +#define B_PCH_SPI_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs +#define B_PCH_SPI_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status +#define B_PCH_SPI_HSFSC_PRR34_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down +#define B_PCH_SPI_HSFSC_SAF_CE BIT8 ///< SAF ctype error +#define B_PCH_SPI_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC +#define B_PCH_SPI_HSFSC_SAF_LE BIT6 ///< SAF link error +#define B_PCH_SPI_HSFSC_SCIP BIT5 ///< SPI cycle in progress +#define B_PCH_SPI_HSFSC_SAF_DLE BIT4 ///< SAF Data length error +#define B_PCH_SPI_HSFSC_SAF_ERROR BIT3 ///< SAF Error +#define B_PCH_SPI_HSFSC_AEL BIT2 ///< Access Error Log +#define B_PCH_SPI_HSFSC_FCERR BIT1 ///< Flash Cycle Error +#define B_PCH_SPI_HSFSC_FDONE BIT0 ///< Flash Cycle Done +#define R_PCH_SPI_FADDR 0x08 ///< SPI Flash Address +#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit) +#define R_PCH_SPI_DLOCK 0x0C ///< Discrete Lock Bits +#define B_PCH_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN +#define R_PCH_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits) +#define R_PCH_SPI_FDATA01 0x14 ///< SPI Data 01 +#define R_PCH_SPI_FDATA02 0x18 ///< SPI Data 02 +#define R_PCH_SPI_FDATA03 0x1C ///< SPI Data 03 +#define R_PCH_SPI_FDATA04 0x20 ///< SPI Data 04 +#define R_PCH_SPI_FDATA05 0x24 ///< SPI Data 05 +#define R_PCH_SPI_FDATA06 0x28 ///< SPI Data 06 +#define R_PCH_SPI_FDATA07 0x2C ///< SPI Data 07 +#define R_PCH_SPI_FDATA08 0x30 ///< SPI Data 08 +#define R_PCH_SPI_FDATA09 0x34 ///< SPI Data 09 +#define R_PCH_SPI_FDATA10 0x38 ///< SPI Data 10 +#define R_PCH_SPI_FDATA11 0x3C ///< SPI Data 11 +#define R_PCH_SPI_FDATA12 0x40 ///< SPI Data 12 +#define R_PCH_SPI_FDATA13 0x44 ///< SPI Data 13 +#define R_PCH_SPI_FDATA14 0x48 ///< SPI Data 14 +#define R_PCH_SPI_FDATA15 0x4C ///< SPI Data 15 +#define R_PCH_SPI_FRAP 0x50 ///< Flash Region Access Permisions Register +#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData +#define N_PCH_SPI_FRAP_BRWA 8 ///< BIOS Region Write Access bit position +#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData +#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant +#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant +#define R_PCH_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits) +#define R_PCH_SPI_FREG1_BIOS 0x58 ///< Flash Region 1(BIOS)(32bits) +#define R_PCH_SPI_FREG2_ME 0x5C ///< Flash Region 2(ME)(32bits) +#define R_PCH_SPI_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits) +#define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4(Platform Data)(32bits) +#define R_PCH_SPI_FREG5_DER 0x68 ///< Flash Region 5(Device Expansion Region)(32bits) +#define S_PCH_SPI_FREGX 4 ///< Size of Flash Region register +#define B_PCH_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh +#define N_PCH_SPI_FREGX_LIMIT 16 ///< Region limit bit position +#define N_PCH_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position +#define B_PCH_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12] +#define N_PCH_SPI_FREGX_BASE 0 ///< Region base bit position +#define N_PCH_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position +#define R_PCH_SPI_PR0 0x84 ///< Protected Region 0 Register +#define R_PCH_SPI_PR1 0x88 ///< Protected Region 1 Register +#define R_PCH_SPI_PR2 0x8C ///< Protected Region 2 Register +#define R_PCH_SPI_PR3 0x90 ///< Protected Region 3 Register +#define R_PCH_SPI_PR4 0x94 ///< Protected Region 4 Register +#define S_PCH_SPI_PRX 4 ///< Protected Region X Register size +#define B_PCH_SPI_PRX_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] +#define N_PCH_SPI_PRX_PRL 16 ///< Protected Range Limit bit position +#define B_PCH_SPI_PRX_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] +#define N_PCH_SPI_PRX_PRB 0 ///< Protected Range Base bit position +#define R_PCH_SPI_SFRAP 0xB0 ///< Secondary Flash Regions Access Permisions Register +#define R_PCH_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits) +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select +#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map +#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 ///< Component +#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 ///< Region +#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master +#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps +#define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index +#define R_PCH_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits) +#define R_PCH_SPI_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_PCH_SPI_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid +#define B_PCH_SPI_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock +#define B_PCH_SPI_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_EO_4K BIT28 ///< 4k Erase valid (EO_4k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_RPMC BIT27 ///< RPMC Supported +#define B_PCH_SPI_SFDPX_VSCCX_DPD BIT26 ///< Deep Powerdown Supported +#define B_PCH_SPI_SFDPX_VSCCX_SUSRES BIT25 ///< Suspend/Resume Supported +#define B_PCH_SPI_SFDPX_VSCCX_SOFTRES BIT24 ///< Soft Reset Supported +#define B_PCH_SPI_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 ///< 64k Erase Opcode (EO_64k) +#define B_PCH_SPI_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 ///< 4k Erase Opcode (EO_4k) +#define B_PCH_SPI_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) ///< Quad Enable Requirements +#define B_PCH_SPI_SFDPX_VSCCX_WEWS BIT4 ///< Write Enable on Write Status +#define B_PCH_SPI_SFDPX_VSCCX_WSR BIT3 ///< Write Status Required +#define B_PCH_SPI_SFDPX_VSCCX_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define R_PCH_SPI_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits) +#define R_PCH_SPI_PINTX 0xCC ///< Parameter Table Index +#define N_PCH_SPI_PINTX_SPT 14 +#define V_PCH_SPI_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table +#define V_PCH_SPI_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table +#define N_PCH_SPI_PINTX_HORD 12 +#define V_PCH_SPI_PINTX_HORD_SFDP 0x0 ///< SFDP Header +#define V_PCH_SPI_PINTX_HORD_PT 0x1 ///< Parameter Table Header +#define V_PCH_SPI_PINTX_HORD_DATA 0x2 ///< Data +#define R_PCH_SPI_PTDATA 0xD0 ///< Parameter Table Data +#define R_PCH_SPI_SBRS 0xD4 ///< SPI Bus Requester Status +#define R_PCH_SPI_SSML 0xF0 ///< Set Strap Msg Lock +#define B_PCH_SPI_SSML_SSL BIT0 ///< Set_Strap Lock +#define R_PCH_SPI_SSMC 0xF4 ///< Set Strap Msg Control +#define B_PCH_SPI_SSMC_SSMS BIT0 ///< Set_Strap Mux Select +#define R_PCH_SPI_SSMD 0xF8 ///< Set Strap Msg Data +// +// @todo Follow up with EDS owner if it should be 3FFF or FFFF. +// +#define B_PCH_SPI_SRD_SSD 0x0000FFFF ///< Set_Strap Data +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature +#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A +#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04 +#define B_PCH_SPI_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address +#define B_PCH_SPI_FDBAR_NC 0x00000300 ///< Number Of Components +#define N_PCH_SPI_FDBAR_NC 8 ///< Number Of Components +#define V_PCH_SPI_FDBAR_NC_1 0x00000000 +#define V_PCH_SPI_FDBAR_NC_2 0x00000100 +#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address +#define B_PCH_SPI_FDBAR_NR 0x07000000 ///< Number Of Regions +#define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08 +#define B_PCH_SPI_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address +#define B_PCH_SPI_FDBAR_NM 0x00000700 ///< Number Of Masters +#define B_PCH_SPI_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4] +#define N_PCH_SPI_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position +#define N_PCH_SPI_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position +#define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords +#define N_PCH_SPI_FDBAR_PCHSL 24 ///< PCH Strap Length bit position +#define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C +#define B_PCH_SPI_FDBAR_FCPUSBA 0x000000FF ///< CPU Strap Base Address, [7:0] represents [11:4] +#define N_PCH_SPI_FDBAR_FCPUSBA 0 ///< CPU Strap Base Address bit position +#define N_PCH_SPI_FDBAR_FCPUSBA_REPR 4 ///< CPU Strap Base Address bit represents position +#define B_PCH_SPI_FDBAR_CPUSL 0x0000FF00 ///< CPU Strap Length, [15:8] represents number of Dwords +#define N_PCH_SPI_FDBAR_CPUSL 8 ///< CPU Strap Length bit position +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_PCH_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register +#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency +#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency +#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency +#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 ///< Fast Read Support. +#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency. +#define V_PCH_SPI_FLCOMP_FREQ_48MHZ 0x02 +#define V_PCH_SPI_FLCOMP_FREQ_30MHZ 0x04 +#define V_PCH_SPI_FLCOMP_FREQ_17MHZ 0x06 +#define B_PCH_SPI_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK +#define N_PCH_SPI_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position +#define B_PCH_SPI_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK +#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_PCH_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1 +#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address +#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length + +#define R_PCH_SPI_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register +#define S_PCH_SPI_VTBA_JID0 0x04 +#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF +#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00 +#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000 +#define N_PCH_SPI_VTBA_JID0_DID0 0x08 +#define N_PCH_SPI_VTBA_JID0_DID1 0x10 +#define R_PCH_SPI_VTBA_VSCC0 0x04 +#define S_PCH_SPI_VTBA_VSCC0 0x04 + + +// +// SPI Private Configuration Space Registers +// +#define R_PCH_PCR_SPI_CLK_CTL 0xC004 +#define R_PCH_PCR_SPI_PWR_CTL 0xC008 +#define R_PCH_PCR_SPI_ESPI_SOFTSTRAPS 0xC210 +#define B_PCH_PCR_SPI_ESPI_SOFTSTRAPS_SLAVE BIT12 + +// +// MMP0 +// +#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap offset +#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap bit + + +#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP +#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enable +#define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output Read Enable +#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enable +#define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read Enable + +// +// Descriptor Record 0 +// +#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0 +#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsThermal.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsThermal.h new file mode 100644 index 0000000000..fe43d210ab --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsThermal.h @@ -0,0 +1,107 @@ +/** @file + Register names for PCH Thermal Device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D20:2) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 20 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2 + +#define R_PCH_THERMAL_TBAR 0x10 +#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBAR_ALIGNMENT 12 +#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000 +#define R_PCH_THERMAL_TBARH 0x14 +#define R_PCH_THERMAL_TBARB 0x40 +#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBARB_ALIGNMENT 12 +#define B_PCH_THERMAL_SPTYPEN BIT0 +#define R_PCH_THERMAL_TBARBH 0x44 +#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000 + +// +// Thermal TBAR MMIO registers +// +#define R_PCH_TBAR_TSC 0x04 +#define B_PCH_TBAR_TSC_PLD BIT7 +#define B_PCH_TBAR_TSC_CPDE BIT0 +#define R_PCH_TBAR_TSS 0x06 +#define R_PCH_TBAR_TSEL 0x08 +#define B_PCH_TBAR_TSEL_PLD BIT7 +#define B_PCH_TBAR_TSEL_ETS BIT0 +#define R_PCH_TBAR_TSREL 0x0A +#define R_PCH_TBAR_TSMIC 0x0C +#define B_PCH_TBAR_TSMIC_PLD BIT7 +#define B_PCH_TBAR_TSMIC_SMIE BIT0 +#define R_PCH_TBAR_CTT 0x10 +#define R_PCH_TBAR_TAHV 0x14 +#define R_PCH_TBAR_TALV 0x18 +#define R_PCH_TBAR_TSPM 0x1C +#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_TBAR_TSPM_LTT 0x0C8 +#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9) +#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9) +#define B_PCH_TBAR_TSPM_MINTSST BIT12 +#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13 +#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14 +#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15 +#define R_PCH_TBAR_TL 0x40 +#define B_PCH_TBAR_TL_LOCK BIT31 +#define B_PCH_TBAR_TL_TTEN BIT29 +#define R_PCH_TBAR_TL2 0x50 +#define R_PCH_TBAR_TL2_LOCK BIT15 +#define R_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_PHL 0x60 +#define B_PCH_TBAR_PHLE BIT15 +#define R_PCH_TBAR_PHLC 0x62 +#define B_PCH_TBAR_PHLC_LOCK BIT0 +#define R_PCH_TBAR_TAS 0x80 +#define R_PCH_TBAR_TSPIEN 0x82 +#define R_PCH_TBAR_TSGPEN 0x84 +#define B_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_A4 0xA4 +#define R_PCH_TBAR_C0 0xC0 +#define R_PCH_TBAR_C4 0xC4 +#define R_PCH_TBAR_C8 0xC8 +#define R_PCH_TBAR_CC 0xCC +#define R_PCH_TBAR_D0 0xD0 +#define R_PCH_TBAR_E0 0xE0 +#define R_PCH_TBAR_E4 0xE4 +#define R_PCH_TBAR_E8 0xE8 +#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal controller function disable +#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal controller disable + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h new file mode 100644 index 0000000000..513b022f08 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h @@ -0,0 +1,140 @@ +/** @file + Register names for PCH TraceHub device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_TRACE_HUB_H_ +#define _PCH_REGS_TRACE_HUB_H_ + +// +// TraceHub Registers (D31:F7) +// +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31 +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7 + +#define R_PCH_TRACE_HUB_CSR_MTB_LBAR 0x10 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAL 0xFFF00000 +#define R_PCH_TRACE_HUB_CSR_MTB_UBAR 0x14 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_SW_LBAR 0x18 +#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000 +#define R_PCH_TRACE_HUB_SW_UBAR 0x1C +#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20 +#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00 +#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24 +#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_MSICID 0x40 +#define R_PCH_TRACE_HUB_MSINCP 0x41 +#define R_PCH_TRACE_HUB_MSIMC 0x42 +#define R_PCH_TRACE_HUB_MSILMA 0x44 +#define R_PCH_TRACE_HUB_MSIUMA 0x48 +#define R_PCH_TRACE_HUB_MSIMD 0x4C +#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000 +#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_DSC 0x80 +#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub Bypass +#define R_PCH_TRACE_HUB_DSS 0x81 +#define R_PCH_TRACE_HUB_ISTOT 0x84 +#define R_PCH_TRACE_HUB_ICTOT 0x88 +#define R_PCH_TRACE_HUB_IPAD 0x8C +#define R_PCH_TRACE_HUB_DSD 0x90 + +// +// Offsets from CSR_MTB_BAR +// +#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15 +#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A +#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08 +#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00 +#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0 +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10 +#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F +#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14 +#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18 +#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100 +#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3 +#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8) +#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4) +#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4 +#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2 +#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1 +#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0 +#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4 +#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8 +#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7 +#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108 +#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C +#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208 +#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C +#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000 +#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28 +#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00 +#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0 +#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16) +#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT20) +#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0 +#define R_PCH_TRACE_HUB_MTB_SCR 0xC8 +#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC +#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40 +#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14 +#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0 +#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80 +#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20 +#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000 +#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0 + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsUsb.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsUsb.h new file mode 100644 index 0000000000..7dfe90815f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/PchRegsUsb.h @@ -0,0 +1,490 @@ +/** @file + Register names for PCH USB devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without [generation_name] inserted. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +// +// USB3 (XHCI) related definitions +// +#define PCI_BUS_NUMBER_PCH_XHCI 0 +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// XHCI PCI Config Space registers +// +#define R_PCH_XHCI_MEM_BASE 0x10 +#define R_PCH_XHCI_MEM_BASE_2 0x14 +#define V_PCH_XHCI_MEM_LENGTH 0x10000 +#define N_PCH_XHCI_MEM_SHIFT 32 +#define N_PCH_XHCI_MEM_ALIGN 16 +#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF + +#define R_PCH_XHCI_XHCC1 0x40 +#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 +#define B_PCH_XHCI_XHCC1_RMTASERR BIT24 +#define B_PCH_XHCI_XHCC1_URD BIT23 +#define B_PCH_XHCI_XHCC1_URRE BIT22 +#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 +#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 +#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 +#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 +#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) +#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) +#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) +#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) + +#define R_PCH_XHCI_XHCC2 0x44 +#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 +#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11 +#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 +#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) +#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) +#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) + +#define R_PCH_XHCI_XHCLKGTEN 0x50 +#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 +#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 +#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 +#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 +#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 +#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 +#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 +#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) +#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) +#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) +#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 +#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 +#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 +#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 +#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 + +#define R_PCH_XHCI_USB_RELNUM 0x60 +#define B_PCH_XHCI_USB_RELNUM 0xFF +#define R_PCH_XHCI_FL_ADJ 0x61 +#define B_PCH_XHCI_FL_ADJ 0x3F +#define R_PCH_XHCI_PWR_CAPID 0x70 +#define B_PCH_XHCI_PWR_CAPID 0xFF +#define R_PCH_XHCI_NXT_PTR1 0x71 +#define B_PCH_XHCI_NXT_PTR1 0xFF +#define R_PCH_XHCI_PWR_CAP 0x72 +#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_XHCI_PWR_CAP_DSI BIT5 +#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) +#define R_PCH_XHCI_MSI_MCTL 0x82 +#define R_PCH_XHCI_HSCFG2 0xA4 +#define R_PCH_XHCI_SSCFG1 0xA8 +#define R_PCH_XHCI_HSCFG1 0xAC +#define R_PCH_XHCI_U2OCM 0xB0 +#define R_PCH_XHCI_U3OCM 0xD0 +#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8 + +#define R_PCH_XHCI_FUS 0xE0 +#define B_PCH_XHCI_FUS_USBR (BIT5) +#define V_PCH_XHCI_FUS_USBR_EN 0 +#define V_PCH_XHCI_FUS_USBR_DIS (BIT5) + +#define R_PCH_XHCI_FC 0xFC + +#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) +#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) + +#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) +#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) + +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 + +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF + +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F + +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF + +// +// xHCI MMIO registers +// + +// +// 0x00 - 0x1F - Capability Registers +// +#define R_PCH_XHCI_CAPLENGTH 0x00 +#define R_PCH_XHCI_HCIVERSION 0x02 +#define R_PCH_XHCI_HCSPARAMS1 0x04 +#define R_PCH_XHCI_HCSPARAMS2 0x08 +#define R_PCH_XHCI_HCSPARAMS3 0x0C +#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 +#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF +#define R_PCH_XHCI_HCCPARAMS 0x10 +#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 +#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 +#define R_PCH_XHCI_DBOFF 0x14 +#define R_PCH_XHCI_RTSOFF 0x18 + +// +// 0x80 - 0xBF - Operational Registers +// +#define R_PCH_XHCI_USBCMD 0x80 +#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop +#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST +#define R_PCH_XHCI_USBSTS 0x84 +#define B_PCH_XHCI_USBSTS_HCH BIT0 +#define B_PCH_XHCI_USBSTS_CNR BIT11 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_LP_XHCI_PORTSC01USB2 0x480 +#define R_PCH_LP_XHCI_PORTSC02USB2 0x490 +#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_LP_XHCI_PORTSC09USB2 0x500 +#define R_PCH_LP_XHCI_PORTSC10USB2 0x510 + +#define R_PCH_LP_XHCI_PORTSC11USBR 0x520 +#define R_PCH_LP_XHCI_PORTSC12USBR 0x530 + +#define R_PCH_LP_XHCI_PORTSC01USB3 0x540 +#define R_PCH_LP_XHCI_PORTSC02USB3 0x550 +#define R_PCH_LP_XHCI_PORTSC03USB3 0x560 +#define R_PCH_LP_XHCI_PORTSC04USB3 0x570 +#define R_PCH_LP_XHCI_PORTSC05USB3 0x580 +#define R_PCH_LP_XHCI_PORTSC06USB3 0x590 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_H_XHCI_PORTSC01USB2 0x480 +#define R_PCH_H_XHCI_PORTSC02USB2 0x490 +#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_H_XHCI_PORTSC09USB2 0x500 +#define R_PCH_H_XHCI_PORTSC10USB2 0x510 +#define R_PCH_H_XHCI_PORTSC11USB2 0x520 +#define R_PCH_H_XHCI_PORTSC12USB2 0x530 +#define R_PCH_H_XHCI_PORTSC13USB2 0x540 +#define R_PCH_H_XHCI_PORTSC14USB2 0x550 + +#define R_PCH_H_XHCI_PORTSC15USBR 0x560 +#define R_PCH_H_XHCI_PORTSC16USBR 0x570 + +#define R_PCH_H_XHCI_PORTSC01USB3 0x580 +#define R_PCH_H_XHCI_PORTSC02USB3 0x590 +#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0 +#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0 +#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0 +#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0 +#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0 +#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0 +#define R_PCH_H_XHCI_PORTSC09USB3 0x600 +#define R_PCH_H_XHCI_PORTSC10USB3 0x610 + +#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe +#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 +#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State +#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status +#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) +#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control + +#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB3_LWS BIT16 ///< Port Link State Write Strobe +#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power +#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_DISABLED 0x00000080 ///< Link is in the RxDetect State +#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) +// +// 0x2000 - 0x21FF - Runtime Registers +// 0x3000 - 0x307F - Doorbell Registers +// +#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008 +#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028 +#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094 +#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C +#define R_PCH_XHCI_PMCTRL 0x80A4 +#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control +#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg +#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2 +#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables +#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports +#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports +#define R_PCH_XHCI_AUX_CTRL_REG 0x80C0 ///< AUX_CTRL_REG - AUX Reset Control +#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8 +#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC +#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0 +#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2 +#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2 +#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0 +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1 +#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control +#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control +#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control +#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control +#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control +#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control +#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control +#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control +#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle +#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count +#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register +#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control + +// +// SKL PCH LP FUSE +// +#define R_PCH_XHCI_LP_FUSE1 0x8410 +#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1) +#define B_PCH_XHCI_LP_FUS_USBR (BIT5) +#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap +#define B_PCH_XHCI_STRAP2_USB3_SSIC_MODE (BIT1 | BIT0) ///< USB3/SSIC Mode +#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable +#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable + +// +// Extended Capability Registers +// +#define R_PCH_XHCI_USB2PDO 0x84F8 +#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports +#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports +#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 + +#define R_PCH_XHCI_USB3PDO 0x84FC +#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports +#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports +#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 + +// +// Debug Capability Descriptor Parameters +// +#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// xDCI (OTG) PCI Config Space Registers +// +#define R_PCH_XDCI_MEM_BASE 0x10 +#define V_PCH_XDCI_MEM_LENGTH 0x200000 +#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register +#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1 +#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable +#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4 +#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register + +// +// xDCI (OTG) MMIO registers +// +#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl +#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable +#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register +#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY +#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0 +#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px +#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810 +#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818 +#define R_PCH_XDCI_APBFC_U3PMU_CFG5 0x10F81C +#define R_PCH_XDCI_APBFC_U3PMU_CFG6 0x10F820 + +// +// xDCI (OTG) Private Configuration Registers +// (PID:OTG) +// +#define R_PCH_PCR_OTG_IOSF_A2 0xA2 +#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0 +#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20 +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00 +#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8 +#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080 +#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001 + +// +// USB2 Private Configuration Registers +// USB2 HIP design featured +// (PID:USB2) +// +#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT +#define R_PCH_PCR_USB2_400C 0x400C +#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address +#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00 +#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08 +#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26 +#define R_PCH_PCR_USB2_402A 0x402A +#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG +#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2 +#define R_PCH_PCR_USB2_7034 0x7034 +#define R_PCH_PCR_USB2_7038 0x7038 +#define R_PCH_PCR_USB2_703C 0x703C +#define R_PCH_PCR_USB2_7040 0x7040 +#define R_PCH_PCR_USB2_7044 0x7044 +#define R_PCH_PCR_USB2_7048 0x7048 +#define R_PCH_PCR_USB2_704C 0x704C +#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG + +// +// xHCI SSIC registers +// +#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2 +#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31 +#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38 + +#endif -- cgit v1.2.3