From 0c4229f0c041ae2f5990b9fce1bbf8e1bb842845 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Sat, 17 Mar 2018 07:40:05 +0800 Subject: LewisBurgPkg: Initial version. Cc: Isaac W Oram Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Isaac W Oram --- .../LewisburgPkg/Include/Register/PchRegsDci.h | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h (limited to 'Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h') diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h new file mode 100644 index 0000000000..a3dd6ed148 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable + +#endif -- cgit v1.2.3