From 6c816b0e41758c4a75d0367afa7324bddf8151df Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 16 Apr 2018 12:57:04 +0200 Subject: Silicon/Socionext/SynQuacer: update PHY reference clock rate As reported by Kojima-san, the PHY reference clock value we use in our ACPI and DT descriptions is out of sync with the hardware. Replace 125 MHz with 250 MHz throughout. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl') diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index b6f6c43600..3f73c191d4 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, Package (2) { "max-speed", 1000 }, Package (2) { "max-frame-size", 9000 }, - Package (2) { "socionext,phy-clock-frequency", 125000000 }, + Package (2) { "socionext,phy-clock-frequency", 250000000 }, } }) } -- cgit v1.2.3