From ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 8 Mar 2018 15:13:24 +0000 Subject: Silicon/SynQuacer: add cache topology information to device tree Add a DT description of the size and geometry of the various levels of caches that are present in the SynQuacer SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi') diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index fdaccb9844..6e93c6ae16 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2017, Linaro Limited. All rights reserved. + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials are licensed and made * available under the terms and conditions of the BSD License which @@ -575,3 +575,5 @@ #size-cells = <0>; }; }; + +#include "SynQuacerCaches.dtsi" -- cgit v1.2.3