From 6c816b0e41758c4a75d0367afa7324bddf8151df Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 16 Apr 2018 12:57:04 +0200 Subject: Silicon/Socionext/SynQuacer: update PHY reference clock rate As reported by Kojima-san, the PHY reference clock value we use in our ACPI and DT descriptions is out of sync with the hardware. Replace 125 MHz with 250 MHz throughout. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- .../SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h') diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h index 1caf64e306..f6ec9b30ec 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h @@ -16,8 +16,8 @@ #ifndef OGMA_CONFIG_H #define OGMA_CONFIG_H -#define OGMA_CONFIG_CLK_HZ 125000000UL -#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL +#define OGMA_CONFIG_CLK_HZ 250000000UL +#define OGMA_CONFIG_GMAC_CLK_HZ 250000000UL #define OGMA_CONFIG_CHECK_CLK_SUPPLY #define OGMA_CONFIG_USE_READ_GMAC_STAT -- cgit v1.2.3