From 7961f156e4197fd7ce8294d76a496b498a0dfeeb Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Fri, 8 Dec 2017 15:57:35 +0100 Subject: Marvell/Drivers: Modify MvPhyDxe location MvPhyDxe driver nesting into additional Phy directory under Silicon/Marvell/Drivers/Net is redundant. Align its level with MvMdioDxe and Pp2Dxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 +- Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c | 460 +++++++++++++++++++++ Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.h | 100 +++++ Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 73 ++++ .../Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 460 --------------------- .../Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 100 ----- .../Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 73 ---- 7 files changed, 634 insertions(+), 634 deletions(-) create mode 100644 Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c create mode 100644 Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.h create mode 100644 Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf delete mode 100644 Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c delete mode 100644 Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h delete mode 100644 Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf (limited to 'Silicon') diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index 0de86214b5..ed3dba609d 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -428,7 +428,7 @@ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf - Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf + Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c new file mode 100644 index 0000000000..dd2edaec36 --- /dev/null +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c @@ -0,0 +1,460 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "MvPhyDxe.h" + +#define TIMEOUT 500 + +STATIC MARVELL_MDIO_PROTOCOL *Mdio; + +// +// Table with available Mdio controllers +// +STATIC UINT8 * CONST MdioDeviceTable = PcdGetPtr (PcdMdioControllersEnabled); +// +// Table with PHY to Mdio controller mappings +// +STATIC UINT8 * CONST Phy2MdioController = PcdGetPtr (PcdPhy2MdioController); +// +// Table with PHYs' SMI addresses +// +STATIC UINT8 * CONST PhySmiAddresses = PcdGetPtr (PcdPhySmiAddresses); + +STATIC MV_PHY_DEVICE MvPhyDevices[] = { + { MV_PHY_DEVICE_1512, MvPhyInit1512 }, + { 0, NULL } +}; + +EFI_STATUS +MvPhyStatus ( + IN CONST MARVELL_PHY_PROTOCOL *This, + IN PHY_DEVICE *PhyDev + ); + +EFI_STATUS +MvPhyReset ( + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Reg = 0; + INTN timeout = TIMEOUT; + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); + Reg |= BMCR_RESET; + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); + + while ((Reg & BMCR_RESET) && timeout--) { + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); + gBS->Stall(1000); + } + + if (Reg & BMCR_RESET) { + DEBUG((DEBUG_ERROR, "PHY reset timed out\n")); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/* Marvell 88E1111S */ +EFI_STATUS +MvPhyM88e1111sConfig ( + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Reg; + + if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_ID) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) { + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg); + + if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) { + Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) { + Reg &= ~MIIM_88E1111_TX_DELAY; + Reg |= MIIM_88E1111_RX_DELAY; + } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) { + Reg &= ~MIIM_88E1111_RX_DELAY; + Reg |= MIIM_88E1111_TX_DELAY; + } + + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg); + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); + + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + + if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) + Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; + else + Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; + + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + if (PhyDev->Connection == PHY_CONNECTION_SGMII) { + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); + + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + if (PhyDev->Connection == PHY_CONNECTION_RTBI) { + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg); + Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg); + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); + + /* Soft reset */ + MvPhyReset (PhyDev); + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | + MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); + Reg |= (BMCR_ANENABLE | BMCR_ANRESTART); + Reg &= ~BMCR_ISOLATE; + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); + + /* Soft reset */ + MvPhyReset (PhyDev); + + MvPhyReset (PhyDev); + + return EFI_SUCCESS; +} + +EFI_STATUS +MvPhyParseStatus ( + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + UINT32 Speed; + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data); + + if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) && + !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + INTN i = 0; + + DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link")); + while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + DEBUG((DEBUG_ERROR," TIMEOUT !\n")); + PhyDev->LinkUp = FALSE; + break; + } + + if ((i++ % 1000) == 0) + DEBUG((DEBUG_ERROR, ".")); + gBS->Stall(1000); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data); + } + DEBUG((DEBUG_ERROR," done\n")); + gBS->Stall(500000); + } else { + if (Data & MIIM_88E1xxx_PHYSTAT_LINK) { + DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, ")); + PhyDev->LinkUp = TRUE; + } else { + DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, ")); + PhyDev->LinkUp = FALSE; + } + } + + if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) { + DEBUG((DEBUG_ERROR, "full duplex, ")); + PhyDev->FullDuplex = TRUE; + } else { + DEBUG((DEBUG_ERROR, "half duplex, ")); + PhyDev->FullDuplex = FALSE; + } + + Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED; + + switch (Speed) { + case MIIM_88E1xxx_PHYSTAT_GBIT: + DEBUG((DEBUG_ERROR, "speed 1000\n")); + PhyDev->Speed = SPEED_1000; + break; + case MIIM_88E1xxx_PHYSTAT_100: + DEBUG((DEBUG_ERROR, "speed 100\n")); + PhyDev->Speed = SPEED_100; + break; + default: + DEBUG((DEBUG_ERROR, "speed 10\n")); + PhyDev->Speed = SPEED_10; + break; + } + + return EFI_SUCCESS; +} + +STATIC +VOID +MvPhy1512WriteBits ( + IN PHY_DEVICE *PhyDev, + IN UINT8 RegNum, + IN UINT16 Offset, + IN UINT16 Len, + IN UINT16 Data) +{ + UINT32 Reg, Mask; + + if ((Len + Offset) >= 16) + Mask = 0 - (1 << Offset); + else + Mask = (1 << (Len + Offset)) - (1 << Offset); + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, &Reg); + + Reg &= ~Mask; + Reg |= Data << Offset; + + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, Reg); +} + +STATIC +EFI_STATUS +MvPhyInit1512 ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN OUT PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + INTN i; + + if (PhyDev->Connection == PHY_CONNECTION_SGMII) { + /* Select page 0xff and update configuration registers according to + * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0, + * Errata Section 3.1 - needed in SGMII mode. + */ + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x00ff); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x214B); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2144); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x0C28); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2146); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xB233); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x214D); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xCC0C); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2159); + + /* Reset page selection and select page 0x12 */ + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0012); + + /* Write HWCFG_MODE = SGMII to Copper */ + MvPhy1512WriteBits(PhyDev, 20, 0, 3, 1); + + /* Phy reset - necessary after changing mode */ + MvPhy1512WriteBits(PhyDev, 20, 15, 1, 1); + + /* Reset page selection */ + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); + gBS->Stall(100); + } + + MvPhyM88e1111sConfig (PhyDev); + + /* autonegotiation on startup is not always required */ + if (!PcdGetBool (PcdPhyStartupAutoneg)) + return EFI_SUCCESS; + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + + if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) { + + DEBUG((DEBUG_ERROR, "MvPhyDxe: Waiting for PHY auto negotiation... ")); + for (i = 0; !(Data & BMSR_ANEGCOMPLETE); i++) { + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + DEBUG((DEBUG_ERROR, "timeout\n")); + PhyDev->LinkUp = FALSE; + return EFI_TIMEOUT; + } + + gBS->Stall(1000); /* 1 ms */ + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + } + PhyDev->LinkUp = TRUE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); + } else { + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + + if (Data & BMSR_LSTATUS) { + PhyDev->LinkUp = TRUE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); + } else { + PhyDev->LinkUp = FALSE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link down\n")); + } + } + MvPhyParseStatus (PhyDev); + + return EFI_SUCCESS; +} + +EFI_STATUS +MvPhyInit ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN UINT32 PhyIndex, + IN PHY_CONNECTION PhyConnection, + IN OUT PHY_DEVICE **OutPhyDev + ) +{ + EFI_STATUS Status; + PHY_DEVICE *PhyDev; + UINT8 *DeviceIds; + UINT8 MdioIndex; + INTN i; + + Status = gBS->LocateProtocol ( + &gMarvellMdioProtocolGuid, + NULL, + (VOID **) &Mdio + ); + if (EFI_ERROR(Status)) + return Status; + + MdioIndex = Phy2MdioController[PhyIndex]; + + /* Verify correctness of PHY <-> MDIO assignment */ + if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >= Mdio->ControllerCount) { + DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment for PHY#%d", PhyIndex)); + return EFI_INVALID_PARAMETER; + } + + /* perform setup common for all PHYs */ + PhyDev = AllocateZeroPool (sizeof (PHY_DEVICE)); + PhyDev->Addr = PhySmiAddresses[PhyIndex]; + PhyDev->Connection = PhyConnection; + DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n", + PhyDev->Addr, PhyConnection)); + *OutPhyDev = PhyDev; + + DeviceIds = PcdGetPtr (PcdPhyDeviceIds); + for (i = 0; i < PcdGetSize (PcdPhyDeviceIds); i++) { + /* find MvPhyDevices fitting entry */ + if (MvPhyDevices[i].DevId == DeviceIds[i]) { + ASSERT (MvPhyDevices[i].DevInit != NULL); + /* proceed with PHY-specific initialization */ + return MvPhyDevices[i].DevInit (Snp, PhyDev); + } + } + + /* if we are here, no matching DevId was found */ + Status = EFI_INVALID_PARAMETER; + FreePool (PhyDev); + return Status; +} + +EFI_STATUS +MvPhyStatus ( + IN CONST MARVELL_PHY_PROTOCOL *This, + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + + if ((Data & BMSR_LSTATUS) == 0) { + PhyDev->LinkUp = FALSE; + } else { + PhyDev->LinkUp = TRUE; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvPhyDxeInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + MARVELL_PHY_PROTOCOL *Phy; + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + + Phy = AllocateZeroPool (sizeof (MARVELL_PHY_PROTOCOL)); + Phy->Status = MvPhyStatus; + Phy->Init = MvPhyInit; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gMarvellPhyProtocolGuid, Phy, + NULL + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to install interfaces\n")); + return Status; + } + DEBUG((DEBUG_ERROR, "Succesfully installed protocol interfaces\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.h b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.h new file mode 100644 index 0000000000..66974bba4b --- /dev/null +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.h @@ -0,0 +1,100 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_PHY_DXE_H__ +#define __MV_PHY_DXE_H__ + +#define MII_BMCR 0x00 /* Basic mode control Register */ +#define MII_BMSR 0x01 /* Basic mode status Register */ + +/* BMCR */ +#define BMCR_ANRESTART 0x0200 /* 1 = Restart autonegotiation */ +#define BMCR_ISOLATE 0x0400 /* 0 = Isolate PHY */ +#define BMCR_ANENABLE 0x1000 /* 1 = Enable autonegotiation */ +#define BMCR_RESET 0x8000 /* 1 = Reset the PHY */ + +/* BSMR */ +#define BMSR_LSTATUS 0x0004 /* 1 = Link up */ +#define BMSR_ANEGCAPABLE 0x0008 /* 1 = Able to perform auto-neg */ +#define BMSR_ANEGCOMPLETE 0x0020 /* 1 = Auto-neg complete */ + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1xxx_PHY_STATUS 0x11 +#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1xxx_PHYSTAT_100 0x4000 +#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 + +/* 88E1111 Extended PHY Specific Control Register */ +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_RX_DELAY 0x80 +#define MIIM_88E1111_TX_DELAY 0x02 + +/* 88E1111 Extended PHY Specific Status Register */ +#define MIIM_88E1111_PHY_EXT_SR 0x1b +#define MIIM_88E1111_HWCFG_MODE_MASK 0xf +#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb +#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 +#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 +#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 + +typedef enum { + MV_PHY_DEVICE_1512 +} MV_PHY_DEVICE_ID; + +typedef +EFI_STATUS +(*MV_PHY_DEVICE_INIT) ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN OUT PHY_DEVICE *PhyDev + ); + +typedef struct { + MV_PHY_DEVICE_ID DevId; + MV_PHY_DEVICE_INIT DevInit; +} MV_PHY_DEVICE; + +STATIC +EFI_STATUS +MvPhyInit1512 ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN OUT PHY_DEVICE *PhyDev + ); + +#endif diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf new file mode 100644 index 0000000000..fe0f55478b --- /dev/null +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf @@ -0,0 +1,73 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MvPhyDxe + FILE_GUID = 5aac3843-d8d4-40ba-ae07-38967138509c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MvPhyDxeInitialise + +[Sources.common] + MvPhyDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gMarvellMdioProtocolGuid + gMarvellPhyProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled + gMarvellTokenSpaceGuid.PcdPhy2MdioController + gMarvellTokenSpaceGuid.PcdPhyDeviceIds + gMarvellTokenSpaceGuid.PcdPhySmiAddresses + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + +[Depex] + TRUE diff --git a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c deleted file mode 100644 index dd2edaec36..0000000000 --- a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c +++ /dev/null @@ -1,460 +0,0 @@ -/******************************************************************************** -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "MvPhyDxe.h" - -#define TIMEOUT 500 - -STATIC MARVELL_MDIO_PROTOCOL *Mdio; - -// -// Table with available Mdio controllers -// -STATIC UINT8 * CONST MdioDeviceTable = PcdGetPtr (PcdMdioControllersEnabled); -// -// Table with PHY to Mdio controller mappings -// -STATIC UINT8 * CONST Phy2MdioController = PcdGetPtr (PcdPhy2MdioController); -// -// Table with PHYs' SMI addresses -// -STATIC UINT8 * CONST PhySmiAddresses = PcdGetPtr (PcdPhySmiAddresses); - -STATIC MV_PHY_DEVICE MvPhyDevices[] = { - { MV_PHY_DEVICE_1512, MvPhyInit1512 }, - { 0, NULL } -}; - -EFI_STATUS -MvPhyStatus ( - IN CONST MARVELL_PHY_PROTOCOL *This, - IN PHY_DEVICE *PhyDev - ); - -EFI_STATUS -MvPhyReset ( - IN PHY_DEVICE *PhyDev - ) -{ - UINT32 Reg = 0; - INTN timeout = TIMEOUT; - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); - Reg |= BMCR_RESET; - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); - - while ((Reg & BMCR_RESET) && timeout--) { - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); - gBS->Stall(1000); - } - - if (Reg & BMCR_RESET) { - DEBUG((DEBUG_ERROR, "PHY reset timed out\n")); - return EFI_TIMEOUT; - } - - return EFI_SUCCESS; -} - -/* Marvell 88E1111S */ -EFI_STATUS -MvPhyM88e1111sConfig ( - IN PHY_DEVICE *PhyDev - ) -{ - UINT32 Reg; - - if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || - (PhyDev->Connection == PHY_CONNECTION_RGMII_ID) || - (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) || - (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) { - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg); - - if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || - (PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) { - Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); - } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) { - Reg &= ~MIIM_88E1111_TX_DELAY; - Reg |= MIIM_88E1111_RX_DELAY; - } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) { - Reg &= ~MIIM_88E1111_RX_DELAY; - Reg |= MIIM_88E1111_TX_DELAY; - } - - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg); - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); - - Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); - - if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) - Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; - else - Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; - - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); - } - - if (PhyDev->Connection == PHY_CONNECTION_SGMII) { - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); - - Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); - Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; - Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); - } - - if (PhyDev->Connection == PHY_CONNECTION_RTBI) { - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, &Reg); - Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_CR, Reg); - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); - Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | - MIIM_88E1111_HWCFG_FIBER_COPPER_RES); - Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); - - /* Soft reset */ - MvPhyReset (PhyDev); - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, &Reg); - Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | - MIIM_88E1111_HWCFG_FIBER_COPPER_RES); - Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | - MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EXT_SR, Reg); - } - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); - Reg |= (BMCR_ANENABLE | BMCR_ANRESTART); - Reg &= ~BMCR_ISOLATE; - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); - - /* Soft reset */ - MvPhyReset (PhyDev); - - MvPhyReset (PhyDev); - - return EFI_SUCCESS; -} - -EFI_STATUS -MvPhyParseStatus ( - IN PHY_DEVICE *PhyDev - ) -{ - UINT32 Data; - UINT32 Speed; - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data); - - if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) && - !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { - INTN i = 0; - - DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link")); - while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - DEBUG((DEBUG_ERROR," TIMEOUT !\n")); - PhyDev->LinkUp = FALSE; - break; - } - - if ((i++ % 1000) == 0) - DEBUG((DEBUG_ERROR, ".")); - gBS->Stall(1000); - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STATUS, &Data); - } - DEBUG((DEBUG_ERROR," done\n")); - gBS->Stall(500000); - } else { - if (Data & MIIM_88E1xxx_PHYSTAT_LINK) { - DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, ")); - PhyDev->LinkUp = TRUE; - } else { - DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, ")); - PhyDev->LinkUp = FALSE; - } - } - - if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) { - DEBUG((DEBUG_ERROR, "full duplex, ")); - PhyDev->FullDuplex = TRUE; - } else { - DEBUG((DEBUG_ERROR, "half duplex, ")); - PhyDev->FullDuplex = FALSE; - } - - Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED; - - switch (Speed) { - case MIIM_88E1xxx_PHYSTAT_GBIT: - DEBUG((DEBUG_ERROR, "speed 1000\n")); - PhyDev->Speed = SPEED_1000; - break; - case MIIM_88E1xxx_PHYSTAT_100: - DEBUG((DEBUG_ERROR, "speed 100\n")); - PhyDev->Speed = SPEED_100; - break; - default: - DEBUG((DEBUG_ERROR, "speed 10\n")); - PhyDev->Speed = SPEED_10; - break; - } - - return EFI_SUCCESS; -} - -STATIC -VOID -MvPhy1512WriteBits ( - IN PHY_DEVICE *PhyDev, - IN UINT8 RegNum, - IN UINT16 Offset, - IN UINT16 Len, - IN UINT16 Data) -{ - UINT32 Reg, Mask; - - if ((Len + Offset) >= 16) - Mask = 0 - (1 << Offset); - else - Mask = (1 << (Len + Offset)) - (1 << Offset); - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, &Reg); - - Reg &= ~Mask; - Reg |= Data << Offset; - - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, Reg); -} - -STATIC -EFI_STATUS -MvPhyInit1512 ( - IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN OUT PHY_DEVICE *PhyDev - ) -{ - UINT32 Data; - INTN i; - - if (PhyDev->Connection == PHY_CONNECTION_SGMII) { - /* Select page 0xff and update configuration registers according to - * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0, - * Errata Section 3.1 - needed in SGMII mode. - */ - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x00ff); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x214B); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2144); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x0C28); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2146); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xB233); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x214D); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xCC0C); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2159); - - /* Reset page selection and select page 0x12 */ - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0012); - - /* Write HWCFG_MODE = SGMII to Copper */ - MvPhy1512WriteBits(PhyDev, 20, 0, 3, 1); - - /* Phy reset - necessary after changing mode */ - MvPhy1512WriteBits(PhyDev, 20, 15, 1, 1); - - /* Reset page selection */ - Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); - gBS->Stall(100); - } - - MvPhyM88e1111sConfig (PhyDev); - - /* autonegotiation on startup is not always required */ - if (!PcdGetBool (PcdPhyStartupAutoneg)) - return EFI_SUCCESS; - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); - - if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) { - - DEBUG((DEBUG_ERROR, "MvPhyDxe: Waiting for PHY auto negotiation... ")); - for (i = 0; !(Data & BMSR_ANEGCOMPLETE); i++) { - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - DEBUG((DEBUG_ERROR, "timeout\n")); - PhyDev->LinkUp = FALSE; - return EFI_TIMEOUT; - } - - gBS->Stall(1000); /* 1 ms */ - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); - } - PhyDev->LinkUp = TRUE; - DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); - } else { - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); - - if (Data & BMSR_LSTATUS) { - PhyDev->LinkUp = TRUE; - DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); - } else { - PhyDev->LinkUp = FALSE; - DEBUG((DEBUG_INFO, "MvPhyDxe: link down\n")); - } - } - MvPhyParseStatus (PhyDev); - - return EFI_SUCCESS; -} - -EFI_STATUS -MvPhyInit ( - IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyIndex, - IN PHY_CONNECTION PhyConnection, - IN OUT PHY_DEVICE **OutPhyDev - ) -{ - EFI_STATUS Status; - PHY_DEVICE *PhyDev; - UINT8 *DeviceIds; - UINT8 MdioIndex; - INTN i; - - Status = gBS->LocateProtocol ( - &gMarvellMdioProtocolGuid, - NULL, - (VOID **) &Mdio - ); - if (EFI_ERROR(Status)) - return Status; - - MdioIndex = Phy2MdioController[PhyIndex]; - - /* Verify correctness of PHY <-> MDIO assignment */ - if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >= Mdio->ControllerCount) { - DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment for PHY#%d", PhyIndex)); - return EFI_INVALID_PARAMETER; - } - - /* perform setup common for all PHYs */ - PhyDev = AllocateZeroPool (sizeof (PHY_DEVICE)); - PhyDev->Addr = PhySmiAddresses[PhyIndex]; - PhyDev->Connection = PhyConnection; - DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n", - PhyDev->Addr, PhyConnection)); - *OutPhyDev = PhyDev; - - DeviceIds = PcdGetPtr (PcdPhyDeviceIds); - for (i = 0; i < PcdGetSize (PcdPhyDeviceIds); i++) { - /* find MvPhyDevices fitting entry */ - if (MvPhyDevices[i].DevId == DeviceIds[i]) { - ASSERT (MvPhyDevices[i].DevInit != NULL); - /* proceed with PHY-specific initialization */ - return MvPhyDevices[i].DevInit (Snp, PhyDev); - } - } - - /* if we are here, no matching DevId was found */ - Status = EFI_INVALID_PARAMETER; - FreePool (PhyDev); - return Status; -} - -EFI_STATUS -MvPhyStatus ( - IN CONST MARVELL_PHY_PROTOCOL *This, - IN PHY_DEVICE *PhyDev - ) -{ - UINT32 Data; - - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); - Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); - - if ((Data & BMSR_LSTATUS) == 0) { - PhyDev->LinkUp = FALSE; - } else { - PhyDev->LinkUp = TRUE; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -MvPhyDxeInitialise ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - MARVELL_PHY_PROTOCOL *Phy; - EFI_STATUS Status; - EFI_HANDLE Handle = NULL; - - Phy = AllocateZeroPool (sizeof (MARVELL_PHY_PROTOCOL)); - Phy->Status = MvPhyStatus; - Phy->Init = MvPhyInit; - - Status = gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gMarvellPhyProtocolGuid, Phy, - NULL - ); - - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "Failed to install interfaces\n")); - return Status; - } - DEBUG((DEBUG_ERROR, "Succesfully installed protocol interfaces\n")); - - return EFI_SUCCESS; -} diff --git a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h deleted file mode 100644 index 66974bba4b..0000000000 --- a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h +++ /dev/null @@ -1,100 +0,0 @@ -/******************************************************************************** -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ -#ifndef __MV_PHY_DXE_H__ -#define __MV_PHY_DXE_H__ - -#define MII_BMCR 0x00 /* Basic mode control Register */ -#define MII_BMSR 0x01 /* Basic mode status Register */ - -/* BMCR */ -#define BMCR_ANRESTART 0x0200 /* 1 = Restart autonegotiation */ -#define BMCR_ISOLATE 0x0400 /* 0 = Isolate PHY */ -#define BMCR_ANENABLE 0x1000 /* 1 = Enable autonegotiation */ -#define BMCR_RESET 0x8000 /* 1 = Reset the PHY */ - -/* BSMR */ -#define BMSR_LSTATUS 0x0004 /* 1 = Link up */ -#define BMSR_ANEGCAPABLE 0x0008 /* 1 = Able to perform auto-neg */ -#define BMSR_ANEGCOMPLETE 0x0020 /* 1 = Auto-neg complete */ - -#define PHY_AUTONEGOTIATE_TIMEOUT 5000 - -/* 88E1011 PHY Status Register */ -#define MIIM_88E1xxx_PHY_STATUS 0x11 -#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 -#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 -#define MIIM_88E1xxx_PHYSTAT_100 0x4000 -#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 -#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 -#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 - -/* 88E1111 Extended PHY Specific Control Register */ -#define MIIM_88E1111_PHY_EXT_CR 0x14 -#define MIIM_88E1111_RX_DELAY 0x80 -#define MIIM_88E1111_TX_DELAY 0x02 - -/* 88E1111 Extended PHY Specific Status Register */ -#define MIIM_88E1111_PHY_EXT_SR 0x1b -#define MIIM_88E1111_HWCFG_MODE_MASK 0xf -#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb -#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 -#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 -#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 -#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 -#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 - -typedef enum { - MV_PHY_DEVICE_1512 -} MV_PHY_DEVICE_ID; - -typedef -EFI_STATUS -(*MV_PHY_DEVICE_INIT) ( - IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN OUT PHY_DEVICE *PhyDev - ); - -typedef struct { - MV_PHY_DEVICE_ID DevId; - MV_PHY_DEVICE_INIT DevInit; -} MV_PHY_DEVICE; - -STATIC -EFI_STATUS -MvPhyInit1512 ( - IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN OUT PHY_DEVICE *PhyDev - ); - -#endif diff --git a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf b/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf deleted file mode 100644 index fe0f55478b..0000000000 --- a/Silicon/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (C) 2016 Marvell International Ltd. -# -# Marvell BSD License Option -# -# If you received this File from Marvell, you may opt to use, redistribute and/or -# modify this File under the following licensing terms. -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# * Neither the name of Marvell nor the names of its contributors may be -# used to endorse or promote products derived from this software without -# specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = MvPhyDxe - FILE_GUID = 5aac3843-d8d4-40ba-ae07-38967138509c - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = MvPhyDxeInitialise - -[Sources.common] - MvPhyDxe.c - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - IoLib - PcdLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiLib - -[Protocols] - gMarvellMdioProtocolGuid - gMarvellPhyProtocolGuid - -[Pcd] - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled - gMarvellTokenSpaceGuid.PcdPhy2MdioController - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg - -[Depex] - TRUE -- cgit v1.2.3