From f204d37aca86f4f321a3a8301e847b125005c6de Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Fri, 23 Dec 2016 12:57:11 +0800 Subject: BroxtonSiPkg: Add Include and Library Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../BroxtonSiPkg/SouthCluster/Include/CEATA.h | 105 + .../BroxtonSiPkg/SouthCluster/Include/CmosMap.h | 177 ++ .../SouthCluster/Include/ConfigBlock/DciConfig.h | 52 + .../Include/ConfigBlock/FlashProtectionConfig.h | 59 + .../SouthCluster/Include/ConfigBlock/GmmConfig.h | 52 + .../Include/ConfigBlock/HdAudioConfig.h | 114 + .../SouthCluster/Include/ConfigBlock/HpetConfig.h | 51 + .../Include/ConfigBlock/IoApicConfig.h | 46 + .../SouthCluster/Include/ConfigBlock/IshConfig.h | 37 + .../Include/ConfigBlock/LockDownConfig.h | 41 + .../SouthCluster/Include/ConfigBlock/LpcConfig.h | 43 + .../SouthCluster/Include/ConfigBlock/LpssConfig.h | 81 + .../SouthCluster/Include/ConfigBlock/P2sbConfig.h | 42 + .../Include/ConfigBlock/PcieRpConfig.h | 238 ++ .../SouthCluster/Include/ConfigBlock/PmConfig.h | 55 + .../SouthCluster/Include/ConfigBlock/SataConfig.h | 79 + .../Include/ConfigBlock/ScGeneralConfig.h | 41 + .../Include/ConfigBlock/ScInterruptAssign.h | 72 + .../SouthCluster/Include/ConfigBlock/ScsConfig.h | 122 ++ .../Include/ConfigBlock/SerialIrqConfig.h | 50 + .../SouthCluster/Include/ConfigBlock/SmbusConfig.h | 44 + .../SouthCluster/Include/ConfigBlock/UsbConfig.h | 107 + .../SouthCluster/Include/ConfigBlock/VtdConfig.h | 40 + .../BroxtonSiPkg/SouthCluster/Include/Dbg2t.h | 68 + .../BroxtonSiPkg/SouthCluster/Include/Dbgp.h | 58 + .../SouthCluster/Include/DmaRemappingTable.h | 106 + .../SouthCluster/Include/Guid/BxtVariable.h | 22 + .../SouthCluster/Include/Guid/SataControllerGuid.h | 26 + .../SouthCluster/Include/Guid/ScInitVar.h | 47 + .../SouthCluster/Include/Guid/SmbusArpMap.h | 27 + .../SouthCluster/Include/IndustryStandard/CeAta.h | 102 + .../SouthCluster/Include/IndustryStandard/Mmc.h | 338 +++ .../SouthCluster/Include/IndustryStandard/SdCard.h | 133 ++ .../Include/Library/DxeRuntimePciLibPciExpress.h | 54 + .../SouthCluster/Include/Library/DxeVtdLib.h | 78 + .../SouthCluster/Include/Library/HsioLib.h | 87 + .../SouthCluster/Include/Library/I2CLib.h | 227 ++ .../SouthCluster/Include/Library/PeiMmcMainLib.h | 36 + .../SouthCluster/Include/Library/PeiScPolicyLib.h | 125 ++ .../SouthCluster/Include/Library/PeiVtdLib.h | 47 + .../SouthCluster/Include/Library/ScInfoLib.h | 52 + .../SouthCluster/Include/Library/ScPcrLib.h | 208 ++ .../SouthCluster/Include/Library/ScPlatformLib.h | 805 +++++++ .../SouthCluster/Include/Library/ScSerialIoLib.h | 174 ++ .../Include/Library/ScSerialIoUartLib.h | 106 + .../BroxtonSiPkg/SouthCluster/Include/MMC.h | 272 +++ .../SouthCluster/Include/MediaDeviceDriver.h | 632 ++++++ .../SouthCluster/Include/Ppi/BlockIoPei.h | 275 +++ .../SouthCluster/Include/Ppi/PeiBlockIo.h | 236 ++ .../SouthCluster/Include/Ppi/ScPcieDeviceTable.h | 54 + .../SouthCluster/Include/Ppi/ScPolicy.h | 37 + .../SouthCluster/Include/Ppi/ScPolicyPreMem.h | 35 + .../Include/Private/Guid/ScPolicyHobGuid.h | 26 + .../Include/Private/Library/DxeScHdaNhlt.h | 132 ++ .../Library/PeiDxeSmmScPciExpressHelpersLib.h | 376 ++++ .../Include/Private/Library/ScHdaLib.h | 67 + .../Include/Private/Library/ScInitCommonLib.h | 119 + .../Include/Private/Library/ScSmbusCommonLib.h | 183 ++ .../Include/Private/Library/UsbCommonLib.h | 161 ++ .../Include/Private/Protocol/PcieIoTrap.h | 46 + .../SouthCluster/Include/Private/Protocol/ScNvs.h | 37 + .../Include/Private/Protocol/ScNvsArea.h | 211 ++ .../SouthCluster/Include/Private/ScHdaEndpoints.h | 131 ++ .../Include/Private/ScPmcFunctionDisableResetHob.h | 37 + .../Include/Protocol/EmmcCardInfoProtocol.h | 38 + .../Include/Protocol/HwWatchdogTimer.h | 234 ++ .../SouthCluster/Include/Protocol/MmcHostIo.h | 384 ++++ .../Include/Protocol/ScExtendedReset.h | 56 + .../SouthCluster/Include/Protocol/ScInfo.h | 42 + .../Include/Protocol/ScPcieSmiDispatch.h | 125 ++ .../SouthCluster/Include/Protocol/ScReset.h | 104 + .../SouthCluster/Include/Protocol/ScS3Support.h | 112 + .../Include/Protocol/ScSmmIoTrapControl.h | 62 + .../Include/Protocol/SmmIchnDispatchEx.h | 150 ++ .../SouthCluster/Include/Protocol/TcoReset.h | 68 + .../BroxtonSiPkg/SouthCluster/Include/ScAccess.h | 264 +++ .../BroxtonSiPkg/SouthCluster/Include/ScLimits.h | 68 + .../SouthCluster/Include/ScPolicyCommon.h | 69 + .../SouthCluster/Include/ScPreMemPolicyCommon.h | 34 + .../SouthCluster/Include/ScRegs/RegsGpio.h | 61 + .../SouthCluster/Include/ScRegs/RegsHda.h | 562 +++++ .../SouthCluster/Include/ScRegs/RegsIsh.h | 105 + .../SouthCluster/Include/ScRegs/RegsItss.h | 138 ++ .../SouthCluster/Include/ScRegs/RegsLpc.h | 278 +++ .../SouthCluster/Include/ScRegs/RegsLpss.h | 191 ++ .../SouthCluster/Include/ScRegs/RegsP2sb.h | 139 ++ .../SouthCluster/Include/ScRegs/RegsPcie.h | 307 +++ .../SouthCluster/Include/ScRegs/RegsPcr.h | 54 + .../SouthCluster/Include/ScRegs/RegsPcu.h | 1043 +++++++++ .../SouthCluster/Include/ScRegs/RegsPmc.h | 64 + .../SouthCluster/Include/ScRegs/RegsSata.h | 542 +++++ .../SouthCluster/Include/ScRegs/RegsScc.h | 233 ++ .../SouthCluster/Include/ScRegs/RegsSmbus.h | 225 ++ .../SouthCluster/Include/ScRegs/RegsSpi.h | 439 ++++ .../SouthCluster/Include/ScRegs/RegsUsb.h | 571 +++++ .../SouthCluster/Include/ScReservedResources.h | 30 + .../BroxtonSiPkg/SouthCluster/Include/SdCard.h | 138 ++ .../BroxtonSiPkg/SouthCluster/Include/SdHostIo.h | 317 +++ .../DxeRuntimePciLibPciExpress.c | 2284 ++++++++++++++++++++ .../DxeRuntimePciLibPciExpress.h | 30 + .../DxeRuntimePciLibPciExpress.inf | 47 + .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.c | 683 ++++++ .../SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf | 62 + .../PeiDxeSmmPchSerialIoLib.c | 293 +++ .../PeiDxeSmmPchSerialIoLib.inf | 41 + .../PeiDxeSmmPchSerialIoUartLib.c | 348 +++ .../PeiDxeSmmPchSerialIoUartLib.inf | 40 + .../Library/PeiScPolicyLib/PeiScPolicyLib.c | 862 ++++++++ .../Library/PeiScPolicyLib/PeiScPolicyLib.inf | 77 + .../Library/PeiScPolicyLib/PeiScPolicyLibrary.h | 51 + .../Library/PeiScPolicyLib/PeiScPreMemPolicyLib.c | 201 ++ .../Library/PeiScPolicyLib/ScPrintPolicy.c | 699 ++++++ .../Library/PeiScPolicyLib/ScPrintPolicyPreMem.c | 75 + .../Library/Private/DxeScHdaLib/DxeScHdaLib.inf | 46 + .../Library/Private/DxeScHdaLib/ScHdaEndpoints.c | 497 +++++ .../Library/Private/DxeScHdaLib/ScHdaLib.c | 807 +++++++ .../PeiDxeSmmScPciExpressHelpersLib.inf | 45 + .../ScPciExpressHelpersLibrary.c | 2096 ++++++++++++++++++ .../ScPciExpressHelpersLibrary.h | 48 + .../PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf | 53 + .../Private/PeiDxeUsbCommonLib/UsbCommonLib.c | 1172 ++++++++++ .../Library/ScPlatformLib/ScCycleDecoding.c | 739 +++++++ .../Library/ScPlatformLib/ScPlatformLib.inf | 46 + .../Library/ScPlatformLib/ScPlatformLibrary.c | 843 ++++++++ .../Library/ScPlatformLib/ScPlatformLibrary.h | 32 + .../Library/ScPlatformLib/ScSbiAccess.c | 297 +++ 126 files changed, 27502 insertions(+) create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CEATA.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CmosMap.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Dbg2t.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Dbgp.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/DmaRemappingTable.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/BxtVariable.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SataControllerGuid.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/ScInitVar.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SmbusArpMap.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/CeAta.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/Mmc.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/SdCard.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MMC.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MediaDeviceDriver.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/BlockIoPei.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/PeiBlockIo.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPcieDeviceTable.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicy.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicyPreMem.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Guid/ScPolicyHobGuid.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/DxeScHdaNhlt.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/PeiDxeSmmScPciExpressHelpersLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScHdaLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScInitCommonLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScSmbusCommonLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/UsbCommonLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/PcieIoTrap.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvs.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvsArea.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScHdaEndpoints.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScPmcFunctionDisableResetHob.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/HwWatchdogTimer.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/MmcHostIo.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScExtendedReset.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScInfo.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScPcieSmiDispatch.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScReset.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScS3Support.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScSmmIoTrapControl.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/TcoReset.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScAccess.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScLimits.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPolicyCommon.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPreMemPolicyCommon.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsGpio.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsHda.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsIsh.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsItss.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpc.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsP2sb.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcie.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcr.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcu.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPmc.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSata.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsScc.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSmbus.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsUsb.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScReservedResources.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdCard.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdHostIo.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLibrary.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPreMemPolicyLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicy.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicyPreMem.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/DxeScHdaLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaEndpoints.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/PeiDxeSmmScPciExpressHelpersLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScCycleDecoding.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLib.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScSbiAccess.c (limited to 'Silicon') diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CEATA.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CEATA.h new file mode 100644 index 0000000000..c286b6e8c6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CEATA.h @@ -0,0 +1,105 @@ +/** @file + Header file for chipset CE-AT spec. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CE_ATA_H +#define _CE_ATA_H + +#pragma pack(1) + +#define DATA_UNIT_SIZE 512 +#define CMD60 60 +#define CMD61 61 + +#define RW_MULTIPLE_REGISTER CMD60 +#define RW_MULTIPLE_BLOCK CMD61 + +#define CE_ATA_SIG_CE 0xCE +#define CE_ATA_SIG_AA 0xAA + +#define Reg_Features_Exp 01 +#define Reg_SectorCount_Exp 02 +#define Reg_LBALow_Exp 03 +#define Reg_LBAMid_Exp 04 +#define Reg_LBAHigh_Exp 05 +#define Reg_Control 06 +#define Reg_Features_Error 09 +#define Reg_SectorCount 10 +#define Reg_LBALow 11 +#define Reg_LBAMid 12 +#define Reg_LBAHigh 13 +#define Reg_Device_Head 14 +#define Reg_Command_Status 15 + +#define Reg_scrTempC 0x80 +#define Reg_scrTempMaxP 0x84 +#define Reg_scrTempMinP 0x88 +#define Reg_scrStatus 0x8C +#define Reg_scrReallocsA 0x90 +#define Reg_scrERetractsA 0x94 +#define Reg_scrCapabilities 0x98 +#define Reg_scrControl 0xC0 + +typedef struct { + UINT8 Reserved0; + UINT8 Features_Exp; + UINT8 SectorCount_Exp; + UINT8 LBALow_Exp; + UINT8 LBAMid_Exp; + UINT8 LBAHigh_Exp; + UINT8 Control; + UINT8 Reserved1[2]; + UINT8 Features_Error; + UINT8 SectorCount; + UINT8 LBALow; + UINT8 LBAMid; + UINT8 LBAHigh; + UINT8 Device_Head; + UINT8 Command_Status; +} TASK_FILE; + +// +// Reduced ATA command set +// +#define IDENTIFY_DEVICE 0xEC +#define READ_DMA_EXT 0x25 +#define WRITE_DMA_EXT 0x35 +#define STANDBY_IMMEDIATE 0xE0 +#define FLUSH_CACHE_EXT 0xEA + +typedef struct { + UINT16 Reserved0[10]; + UINT16 SerialNumber[10]; + UINT16 Reserved1[3]; + UINT16 FirmwareRevision[4]; + UINT16 ModelNumber[20]; + UINT16 Reserved2[33]; + UINT16 MajorVersion; + UINT16 Reserved3[19]; + UINT16 MaximumLBA[4]; + UINT16 Reserved4[2]; + UINT16 Sectorsize; + UINT16 Reserved5; + UINT16 DeviceGUID[4]; + UINT16 Reserved6[94]; + UINT16 Features; + UINT16 MaxWritesPerAddress; + UINT16 Reserved7[47]; + UINT16 IntegrityWord; +} IDENTIFY_DEVICE_DATA; + +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CmosMap.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CmosMap.h new file mode 100644 index 0000000000..4c9a3df88b --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/CmosMap.h @@ -0,0 +1,177 @@ +/** @file + This header file provides platform specific definitions used by other modules + for platform specific initialization. + + This is not suitable for consumption by ASL or VRF files. + + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CMOSMAP_H_ +#define _CMOSMAP_H_ + +#define CmosIo_70 0x70 +#define CmosIo_71 0x71 +#define CmosIo_72 0x72 +#define CmosIo_73 0x73 + +// +// PLATFORM SPECIFIC USAGE +// +#define CPU_HT_POLICY 0x50 +#define CPU_HT_POLICY_ENABLED 0x01 + +#define TPM_POLICY 0x60 +#define TPM_POLICY_ENABLED 0x01 + +#define CMOS_LCDPANELTYPE_REG 0x61 +#define CMOS_LCDPANELSCALING_REG 0x62 +#define CMOS_IGDBOOTTYPE_REG 0x63 +#define CMOS_BACKLIGHT_REG 0x64 +#define CMOS_LFP_PANEL_COLOR_DEPTH_REG 0x65 +#define CMOS_EDP_ACTIVE_LFP_CONFIG_REG 0x66 +#define CMOS_PRIMARY_DISPLAY_REG 0x67 +#define CMOS_IGD_DISPLAY_PIPE_B_REG 0x68 +#define CMOS_SDVOPANELTYPE_REG 0x69 +#define CMOS_CPV_STATE 0x6A +#define CMOS_PLATFORM_RESET_OS 0x80 +#define CMOS_CPU_BSP_SELECT 0x90 +#define CMOS_CPU_RATIO_OFFSET 0x92 +#define CMOS_ICH_PORT80_OFFSET 0x97 + +#define CMOS_DATA_PORT 0x71 +#define CMOS_ADDR_PORT 0x70 +#define CMOS_BAD_REG 0xe + +#define CMOS_MAXRATIO_CONFIG_REG 0xEF + +#define CMOS_BOOT_REGISTER_REG 0x47 +#define RTC_ADDRESS_CENTURY 0x32 +#define RTC_ADDRESS_CENTURY_DEFAULT 0x20 ///<20th Century.BCD value + +// +// Post Code value to be break at +// +#define CMOS_POST_CODE_BREAK_REG 0x48 +#define CMOS_POST_CODE_BREAK_1_REG 0x49 +#define CMOS_POST_CODE_BREAK_2_REG 0x4A +#define CMOS_POST_CODE_BREAK_3_REG 0x4B + +// +// Debug Mask saved in CMOS +// +#define CMOS_DEBUG_PRINT_LEVEL_REG 0x4C +#define CMOS_DEBUG_PRINT_LEVEL_1_REG 0x4D +#define CMOS_DEBUG_PRINT_LEVEL_2_REG 0x4E +#define CMOS_DEBUG_PRINT_LEVEL_3_REG 0x4F + +// +// CMOS usage Upper CMOS bank offsets: +// +#define CMOS_CPU_UP_MODE 0x11 +#define CMOS_CPU_CORE_HT_OFFSET 0x13 +#define CMOS_EFI_DEBUG 0x14 +#define CMOS_CPU_BIST_OFFSET 0x15 +#define CMOS_CPU_VMX_OFFSET 0x16 +#define CMOS_PORT80_OFFSET 0x17 +#define CMOS_PLATFORM_DESIGNATOR 0x18 +#define CMOS_VALIDATION_TEST_BYTE 0x19 +#define CMOS_SERIAL_BAUD_RATE 0x1A +#define CMOS_DCU_MODE_OFFSET 0x1B +#define CMOS_VR11_SET_OFFSET 0x1C +#define CMOS_SBSP_TO_AP_COMM 0x20 +#define TCG_CMOS_AREA_OFFSET 0x60 + +#define TCG_CMOS_MOR_AREA_OFFSET (TCG_CMOS_AREA_OFFSET + 0x05) + +#define EFI_CMOS_START_ADDRESS 0x40 +#define EFI_CMOS_END_ADDRESS 0x7F + +#define EFI_CMOS_CHECKSUM_ADDRESS 0x4F +#define EFI_CMOS_HYPERBOOT_FLAGS 0x50 +#define B_CMOS_FIRST_BOOT 0x01 +#define B_CMOS_BOOT_SUCCESS 0x02 +#define B_CMOS_HYPERBOOT_STATUS 0x04 +#define B_CMOS_HYPERBOOT_RECOVERY 0x08 +#define B_CMOS_BOOT_FAILED 0x10 +#define B_CMOS_BOOT_LOCK 0x20 +#define EFI_CMOS_BOOT_CFG_FLAGS 0x51 +#define B_CMOS_BOOT_CFG_EXIST 0x01 +#define B_CMOS_BOOT_CFG_BOOT_MENU 0x02 +#define B_CMOS_BOOT_CFG_BOOT_CD 0x04 +#define B_CMOS_BOOT_CFG_BOOT_FDD 0x08 +#define B_CMOS_BOOT_CFG_BOOT_PXE 0x10 +#define B_CMOS_BOOT_CFG_BOOT_USB 0x20 +#define B_CMOS_BOOT_CFG_USB_FIRST 0x40 +#define B_CMOS_BOOT_CFG_BOOT_UEFI 0x80 + +#define EFI_CMOS_CRASHDUMP_ADDR_0 0x68 +#define EFI_CMOS_CRASHDUMP_ADDR_1 0x69 +#define EFI_CMOS_CRASHDUMP_ADDR_2 0x6A +#define EFI_CMOS_CRASHDUMP_ADDR_3 0x6B +#define EFI_CMOS_CRASHDUMP_TRIGGERED 0x6C + +#define EFI_CMOS_PENDING_ME_BIOS_ACTION 0x6D +#define EFI_CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E +#define EFI_CMOS_XP_FLAG_ADDRESS 0x6F +#define EFI_CMOS_CAPSULE_ADDRESS_1 0x70 +#define EFI_CMOS_CAPSULE_ADDRESS_2 0x71 +#define EFI_CMOS_CAPSULE_ADDRESS_3 0x72 +#define EFI_CMOS_CAPSULE_ADDRESS_4 0x73 +#define EFI_CMOS_PERFORMANCE_FLAGS 0x74 +#define B_CMOS_MEMORY_INIT 0x01 +#define B_CMOS_FORCED_REBOOT 0x02 +#define B_CMOS_ALLOW_RESET 0x04 +#define B_CMOS_WD_RUNNING_FROM_OS 0x08 +#define B_CMOS_WD_FAILURE_STATUS_TO_OS 0x10 +#define B_CMOS_BIOS_RESET_PERF_SETTINGS_TO_OS 0x20 +#define B_CMOS_TCO_WDT_RESET 0x40 +#define EFI_ACPI_TPM_REQUEST 0x75 +#define EFI_ACPI_TPM_LAST_REQUEST 0x76 +#define EFI_ACPI_TPM_MORD 0x77 +#define EFI_CMOS_UCLK_DEFAULT 0x78 +#define EFI_CMOS_CCLK_DEFAULT 0x79 +#define EFI_CMOS_QCLK_DEFAULT 0x7A +#define EFI_CMOS_BURN_IN_MODE_FLAGS 0x7C +#define B_CMOS_BIM_HANG 0x01 +#define EFI_CMOS_ACPI_TABLE_FLAG_ADDRESS 0x7D +#define B_CMOS_HPET_ENABLED 0x01 +#define EFI_CMOS_BOOT_FLAG_ADDRESS 0x7E +#define B_CMOS_THERMAL_TRIP 0x01 +#define B_CMOS_FORCE_ENTER_SETUP 0x02 +#define B_CMOS_FORCE_NETWORK_BOOT 0x04 +#define B_CMOS_TPM_ENABLED 0x08 +#define EFI_CMOS_SX_STATE_FLAG_ADDRESS 0x7F +#define B_CMOS_S5_SHUTDOWN 0x01 +#define EFI_CMOS_BATTERY_CHARGING 0xF0 +#define EFI_CMOS_CLEAN_RESET 0xFE +#define B_MAGIC_CLEAN_RESET_VALUE 0xDD +#define B_MAGIC_INIT_VALUE 0xBB + +#define EFI_CMOS_EOL 0xFFFF +#define EFI_CMOS_CHECKSUM_EXCLUDES {EFI_CMOS_CHECKSUM_ADDRESS, \ + EFI_CMOS_XP_FLAG_ADDRESS, \ + EFI_ACPI_TPM_REQUEST, \ + EFI_ACPI_TPM_LAST_REQUEST, \ + EFI_ACPI_TPM_MORD, \ + EFI_CMOS_BOOT_FLAG_ADDRESS, \ + EFI_CMOS_S4_WAKEUP_FLAG_ADDRESS, \ + EFI_CMOS_ACPI_TABLE_FLAG_ADDRESS, \ + EFI_CMOS_SX_STATE_FLAG_ADDRESS, \ + EFI_CMOS_PERFORMANCE_FLAGS, \ + EFI_CMOS_BURN_IN_MODE_FLAGS, \ + EFI_CMOS_HYPERBOOT_FLAGS, \ + EFI_CMOS_BOOT_CFG_FLAGS, \ + EFI_CMOS_EOL } + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h new file mode 100644 index 0000000000..25217d846e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/DciConfig.h @@ -0,0 +1,52 @@ +/** @file + DCI policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DCI_CONFIG_H_ +#define _DCI_CONFIG_H_ + +#define DCI_CONFIG_REVISION 1 + +extern EFI_GUID gDciConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to Direct Connection Interface (DCI). + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the host control is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature. + 0:Disabled; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + (Test) When set to Auto detect mode, it detects CCA being connected during BIOS post time. + This policy only applies when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, 1: Enable AUTO mode + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} SC_DCI_CONFIG; + +#pragma pack (pop) + +#endif // _DCI_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h new file mode 100644 index 0000000000..904f7d6ced --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/FlashProtectionConfig.h @@ -0,0 +1,59 @@ +/** @file + Flash Protection policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FLASH_PROTECTION_CONFIG_H_ +#define _FLASH_PROTECTION_CONFIG_H_ + +#define FLASH_PROTECTION_CONFIG_REVISION 1 + +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) + +/** + The SC provides a method for blocking writes and reads to specific ranges + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by ScGetSpiRegionAddresses routine, + and set the limit and base accordingly. + +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + PROTECTED_RANGE ProtectRange[SC_FLASH_PROTECTED_RANGES]; +} SC_FLASH_PROTECTION_CONFIG; + +#pragma pack (pop) + +#endif // _FLASH_PROTECTION_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h new file mode 100644 index 0000000000..0f9ce312b1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/GmmConfig.h @@ -0,0 +1,52 @@ +/** @file + GMM(Gaussian Mixture Model) scoring accelerator policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GMM_CONFIG_H_ +#define _GMM_CONFIG_H_ + +#define GMM_CONFIG_REVISION 1 + +extern EFI_GUID gGmmConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to GMM. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< 1: Enable, 0: Disable + UINT32 ClkGatingPgcbClkTrunk : 1; ///< GMM Clock Gating - PGCB Clock Trunk: 0: Disable, 1: Enable; + UINT32 ClkGatingSb : 1; ///< GMM Clock Gating - Sideband: 0: Disable, 1: Enable; + UINT32 ClkGatingSbClkTrunk : 1; ///< GMM Clock Gating - Sideband Clock Trunk: 0: Disable, 1: Enable; + UINT32 ClkGatingSbClkPartition : 1; ///< GMM Clock Gating - Sideband Clock Partition: 0: Disable, 1: Enable; + UINT32 ClkGatingCore : 1; ///< GMM Clock Gating - Core: 0: Disable, 1: Enable; + UINT32 ClkGatingDma : 1; ///< GMM Clock Gating - DMA: 0: Disable, 1: Enable; + UINT32 ClkGatingRegAccess : 1; ///< GMM Clock Gating - Register Access: 0: Disable, 1: Enable; + UINT32 ClkGatingHost : 1; ///< GMM Clock Gating - Host: 0: Disable, 1: Enable; + UINT32 ClkGatingPartition : 1; ///< GMM Clock Gating - Partition: 0: Disable, 1: Enable; + UINT32 ClkGatingTrunk : 1; ///< GMM Clock Gating - Trunk: 0: Disable, 1: Enable; + UINT32 SvPwrGatingHwAutoEnable : 1; ///< GMM Power Gating - HW Autonomous Enabled: 0: Disable, 1: Enable; + UINT32 SvPwrGatingD3HotEnable : 1; ///< GMM Power Gating - D3 Hot Enabled: 0: Disable, 1: Enable; + UINT32 SvPwrGatingI3Enable : 1; ///< GMM Power Gating - I3 Enabled: 0: Disable, 1: Enable; + UINT32 SvPwrGatingPmcReqEnable : 1; ///< GMM Power Gating - PMC Request Enabled: 0: Disable, 1: Enable; + UINT32 RsvdBits : 17; ///< Reserved bits +} SC_GMM_CONFIG; + +#pragma pack (pop) + +#endif // _GMM_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h new file mode 100644 index 0000000000..9d7281e8aa --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HdAudioConfig.h @@ -0,0 +1,114 @@ +/** @file + HD-Audio policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _HDAUDIO_CONFIG_H_ +#define _HDAUDIO_CONFIG_H_ + +#define HDAUDIO_CONFIG_REVISION 3 + +extern EFI_GUID gHdAudioConfigGuid; + +#pragma pack (push,1) + +typedef struct { + UINT32 VendorDeviceId; ///< Codec Vendor/Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNo; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs following the header. +} HDA_VERB_TABLE_HEADER; + +typedef struct { + HDA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 VerbTableData[]; +} HDAUDIO_VERB_TABLE; + +// +// The SC_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature. +// +enum SC_HDAUDIO_IO_BUFFER_OWNERSHIP { + ScHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers. + ScHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers. + ScHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers. +}; + +enum SC_HDAUDIO_IO_BUFFER_VOLTAGE { + ScHdaIoBuf33V = 0, + ScHdaIoBuf18V = 1 +}; + +enum SC_HDAUDIO_DMIC_TYPE { + ScHdaDmicDisabled = 0, + ScHdaDmic2chArray = 1, + ScHdaDmic4chArray = 2 +}; + +enum SC_HDAUDIO_VC_TYPE { + ScHdaVc0 = 0, + ScHdaVc1 = 1, + ScHdaVc2 = 2 +}; + +typedef enum { + ScHdaLinkFreq6MHz = 0, + ScHdaLinkFreq12MHz = 1, + ScHdaLinkFreq24MHz = 2, + ScHdaLinkFreq48MHz = 3, + ScHdaLinkFreq96MHz = 4, + ScHdaLinkFreqInvalid +} SC_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + ScHdaIDispMode2T = 0, + ScHdaIDispMode1T = 1 +} SC_HDAUDIO_IDISP_TMODE; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; 1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Disable; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: 0: HD-A Link; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: 0: 3.3V; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (SC_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (SC_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (SC_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T + UINT32 RsvdBits0 : 15; ///< Reserved bits + UINT32 DspEndpointDmic : 2; ///< DMIC Select (SC_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: Disable; 1: Enable + UINT32 DspEndpointI2sSkp : 1; ///< I2S SHK enablement: 0: Disable; 1: Enable + UINT32 DspEndpointI2sHp : 1; ///< I2S HP enablement: 0: Disable; 1: Enable + UINT32 AudioCtlPwrGate : 1; ///< Deprecated + UINT32 AudioDspPwrGate : 1; ///< Deprecated + UINT32 Mmt : 1; ///< CSME Memory Transfers : 0: VC0, 1: VC2 + UINT32 Hmt : 1; ///< Host Memory Transfers : 0: VC0, 1: VC2 + UINT32 BiosCfgLockDown : 1; ///< BIOS Configuration Lock Down : 0: Disable, 1: Enable + UINT32 PwrGate : 1; ///< Power Gating : 0: Disable, 1: Enable + UINT32 ClkGate : 1; ///< Clock Gating : 0: Disable, 1: Enable + UINT32 RsvdBits1 : 20; ///< Reserved bits + UINT32 DspFeatureMask; + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< < (Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 300. + UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4 + UINT32 RsvdBits3 : 2; + UINT32 RsvdBits2 : 30; ///< Reserved bits + UINT8 VerbTableEntryNum; + UINT32 VerbTablePtr; +} SC_HDAUDIO_CONFIG; + +#pragma pack (pop) + +#endif // _HDAUDIO_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h new file mode 100644 index 0000000000..d5dbf8fda1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/HpetConfig.h @@ -0,0 +1,51 @@ +/** @file + HPET policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _HPET_CONFIG_H_ +#define _HPET_CONFIG_H_ + +#define HPET_CONFIG_REVISION 1 + +extern EFI_GUID gHpetConfigGuid; + +#pragma pack (push,1) + +/** + The SC_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determines if enable HPET timer. 0: Disable; 1: Enable. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halted. + **/ + UINT32 Enable : 1; ///< Determines if enable HPET function + UINT32 BdfValid : 1; ///< Whether the BDF value is valid. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is 0xFA. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is 0x00. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Default is 0xFED00000. +} SC_HPET_CONFIG; + +#pragma pack (pop) + +#endif // _HPET_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h new file mode 100644 index 0000000000..8213f54255 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IoApicConfig.h @@ -0,0 +1,46 @@ +/** @file + Io Apic policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IOAPIC_CONFIG_H_ +#define _IOAPIC_CONFIG_H_ + +#define IOAPIC_CONFIG_REVISION 1 + +extern EFI_GUID gIoApicConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to IO Apic. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, SC code will not program these fields if this bit is not TRUE. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0xFA. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x0F. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable IOAPIC Entry 24-119 + UINT32 RsvdBits1 : 7; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC ID. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is 0 + UINT8 Rsvd0[2]; ///< Reserved bytes +} SC_IOAPIC_CONFIG; + +#pragma pack (pop) + +#endif // _IOAPIC_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h new file mode 100644 index 0000000000..fc2bc43f54 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/IshConfig.h @@ -0,0 +1,37 @@ +/** @file + ISH policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _ISH_CONFIG_H_ +#define _ISH_CONFIG_H_ + +#define ISH_CONFIG_REVISION 1 + +extern EFI_GUID gIshConfigGuid; + +#pragma pack (push,1) + +// +// The SC_ISH_CONFIG block describes Integrated Sensor Hub device. +// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< ISH Controler 0: Disable; 1: Enable. + UINT32 RsvdBits0: 31; ///< Reserved Bits +} SC_ISH_CONFIG; + +#pragma pack (pop) + +#endif // _ISH_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h new file mode 100644 index 0000000000..cacf48bb62 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LockDownConfig.h @@ -0,0 +1,41 @@ +/** @file + Lock down policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _LOCK_DOWN_CONFIG_H_ +#define _LOCK_DOWN_CONFIG_H_ + +#define LOCK_DOWN_CONFIG_REVISION 2 + +extern EFI_GUID gLockDownConfigGuid; + +#pragma pack (push,1) + +typedef struct { + + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 GlobalSmi : 1; + UINT32 BiosInterface : 1; + UINT32 RtcLock : 1; + UINT32 BiosLock : 1; + UINT32 SpiEiss : 1; + UINT32 BiosLockSwSmiNumber: 8; + UINT32 TcoLock : 1; + UINT32 RsvdBits0 : 18; ///< Reserved bits +} SC_LOCK_DOWN_CONFIG; + +#pragma pack (pop) + +#endif // _LOCK_DOWN_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h new file mode 100644 index 0000000000..1034b99b39 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,43 @@ +/** @file + Lpc policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _LPC_CONFIG_H_ +#define _LPC_CONFIG_H_ + +#define LPC_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gLpcPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} SC_LPC_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _LPC_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h new file mode 100644 index 0000000000..09adde126e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/LpssConfig.h @@ -0,0 +1,81 @@ +/** @file + LPSS policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _LPSS_CONFIG_H_ +#define _LPSS_CONFIG_H_ + +#define LPSS_CONFIG_REVISION 2 + +extern EFI_GUID gLpssConfigGuid; + +#pragma pack (push,1) + +#define LPSS_I2C_DEVICE_NUM 8 +#define LPSS_HSUART_DEVICE_NUM 4 +#define LPSS_SPI_DEVICE_NUM 3 + +/** + The SC_LPSS_CONFIG block describes Low Power Sub System (LPSS) settings for SC. + @note: the order defined below is per the PCI BDF sequence, and MUST not change. + Items defined will be accessed by its index in ScInit module + +**/ +typedef struct { + /** + Revision 1: Init version + Revision 2: Deprecated ExiEnable + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determine if I2C_n is enabled. + 0: Disabled; 1: PCI Mode; 2: ACPI Mode; + **/ + SC_DEV_MODE I2c0Enable; + SC_DEV_MODE I2c1Enable; + SC_DEV_MODE I2c2Enable; + SC_DEV_MODE I2c3Enable; + SC_DEV_MODE I2c4Enable; + SC_DEV_MODE I2c5Enable; + SC_DEV_MODE I2c6Enable; + SC_DEV_MODE I2c7Enable; + /** + Determine if UART_n is enabled. + 0: Disabled; 1: PCI Mode; 2: ACPI Mode; + **/ + SC_DEV_MODE Hsuart0Enable; + SC_DEV_MODE Hsuart1Enable; + SC_DEV_MODE Hsuart2Enable; + SC_DEV_MODE Hsuart3Enable; + /** + Determine if SPI_n is enabled. + 0: Disabled; 1: PCI Mode; 2: ACPI Mode; + **/ + SC_DEV_MODE Spi0Enable; + SC_DEV_MODE Spi1Enable; + SC_DEV_MODE Spi2Enable; + UINT32 Uart2KernelDebugBaseAddress; + UINT8 I2cClkGateCfg[LPSS_I2C_DEVICE_NUM]; + UINT8 HsuartClkGateCfg[LPSS_HSUART_DEVICE_NUM]; + UINT8 SpiClkGateCfg[LPSS_SPI_DEVICE_NUM]; + UINT32 S0ixEnable : 1; ///< 0: Disabled; 1: Enabled + UINT32 OsDbgEnable : 1; ///< 0: Disabled; 1: Enabled + UINT32 ExiEnable : 1; ///< @deprecated, please use DciEn from SC_DCI_CONFIG + UINT32 RsvdBits : 29; +} SC_LPSS_CONFIG; + +#pragma pack (pop) + +#endif // _LPSS_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h new file mode 100644 index 0000000000..600357d6ff --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/P2sbConfig.h @@ -0,0 +1,42 @@ +/** @file + P2SB policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _P2SB_CONFIG_H_ +#define _P2SB_CONFIG_H_ + +#define P2SB_CONFIG_REVISION 1 + +extern EFI_GUID gP2sbConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to P2SB Interface. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) P2SB + 0:Hide; 1:UnHide + **/ + UINT32 P2sbUnhide : 1; + UINT32 RsvdBytes :31; ///< Reserved bytes +} SC_P2SB_CONFIG; + +#pragma pack (pop) + +#endif // _P2SB_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h new file mode 100644 index 0000000000..a41fe76d7e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PcieRpConfig.h @@ -0,0 +1,238 @@ +/** @file + PCIe root port policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PCIE_CONFIG_H_ +#define _SC_PCIE_CONFIG_H_ + +#define PCIE_RP_PREMEM_CONFIG_REVISION 2 +#define PCIE_RP_CONFIG_REVISION 4 + +extern EFI_GUID gPcieRpPreMemConfigGuid; +extern EFI_GUID gPcieRpConfigGuid; + +#pragma pack (push,1) + +/** + The SC_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each SC PCIe root port. + +**/ +typedef struct { + UINT32 Perst; ///< PCIe reset# pin GPIO pad offset. + UINT32 Clock; ///< PCIe clock# ping GPIO pad offset. +} SC_PCIE_ROOT_PORT_PREMEM_CONFIG; + +/** + The SC_PCIE_PREMEM_CONFIG block describes the expected configuration of the SC PCI Express controllers + +**/ +typedef struct { + /** + Revision 1: Init version + + Revision 2: Add StartTimerTickerOfPerstAssert. + + Revision 3: Add Clock in Root Port. + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + These members describe the configuration of each PCH PCIe root port. + **/ + SC_PCIE_ROOT_PORT_PREMEM_CONFIG RootPort[SC_MAX_PCIE_ROOT_PORTS]; + /** + The Start Timer Ticker of PFET be asserted. + This policy item is primary for responsiveness improvement. + BIOS can utilize this policy item to reduce the delay time in ScConfigurePciePowerSequence() + **/ + UINTN StartTimerTickerOfPfetAssert; +} SC_PCIE_PREMEM_CONFIG; + +// +// SW SMI values which are used by SC Policy +// +#define SW_SMI_PCIE_ASPM_OVERRIDE 0xAA + +enum SC_PCIE_SPEED { + ScPcieAuto, + ScPcieGen1, + ScPcieGen2, + ScPcieGen3 +}; + +typedef enum { + ScPcieAspmDisabled, + ScPcieAspmL0s, + ScPcieAspmL1, + ScPcieAspmL0sL1, + ScPcieAspmAutoConfig, + ScPcieAspmMax +} SC_PCIE_ASPM_CONTROL; + +typedef enum { + ScPcieL1SubstatesDisabled, + ScPcieL1SubstatesL1_1, + ScPcieL1SubstatesL1_2, + ScPcieL1SubstatesL1_1_2, + ScPcieL1SubstatesMax +} SC_PCIE_L1SUBSTATES_CONTROL; + +enum SC_PCIE_COMPLETION_TIMEOUT { + ScPcieCompletionTO_Default, + ScPcieCompletionTO_50_100us, + ScPcieCompletionTO_1_10ms, + ScPcieCompletionTO_16_55ms, + ScPcieCompletionTO_65_210ms, + ScPcieCompletionTO_260_900ms, + ScPcieCompletionTO_1_3P5s, + ScPcieCompletionTO_4_13s, + ScPcieCompletionTO_17_64s, + ScPcieCompletionTO_Disabled +}; + +/** + The SC_PCIE_CONFIG block describes the expected configuration of the PCI Express controllers + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 2; ///< Root Port enabling, 0: Disable; 1: Enable; 2: Auto. + UINT32 Hide : 1; ///< Whether or not to hide the configuration space of this port. + UINT32 SlotImplemented : 1; ///< Indicates whether the root port is connected to a slot. + UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. + UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. + UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled + + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts + to verify CLKREQ# signal is connected by testing pad state before enabling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. + UINT32 PmeInterrupt : 1; ///< Indicate whether the PME Interrupt is enabled. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. + UINT32 Rsvdbits1 : 3; ///< Reserved fields for future expansion w/o protocol change + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: SC_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. + UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: SC_PCIE_COMPLETION_TIMEOUT) + UINT8 Reserved0; ///< Reserved byte + UINT32 PtmEnable : 1; ///< PTM enabling, 0: Disable; 1: Enable. + /** + Selectable De-emphasis enabling. + When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component. + 1b: -3.5 dB, 0b:-6 dB + 0: Disable; 1: Enable. + **/ + UINT32 SelectableDeemphasis : 1; + UINT32 Rsvdbits2 : 30; ///< Reserved Bits + UINT32 Reserved1[1]; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configuration of the root port (see: SC_PCIE_ASPM_CONTROL) + UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: SC_PCIE_L1SUBSTATES_CONTROL) + UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. + UINT8 LtrConfigLock; ///< 0: Disable; 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Latency Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Latency Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Specifies upper limit on power supplie by slot. Leave as 0 to set to default. + UINT32 Rsvdbits3 : 18; ///< Reserved Bits + UINT32 Reserved2[16]; ///< Reserved bytes + UINT8 PcieRootRsvd0; +} SC_PCIE_ROOT_PORT_CONFIG; + +/** + The SC_PCIE_CONFIG block describes the expected configuration of the SC PCI Express controllers + +**/ +typedef struct { + /** + Revision 1: Init version + Revision 2: Add ComplianceTestMode. + Revision 3: Add SelectableDeemphasis + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + These members describe the configuration of each SC PCIe root port. + **/ + SC_PCIE_ROOT_PORT_CONFIG RootPort[SC_MAX_PCIE_ROOT_PORTS]; + /** + This member describes whether PCIE root port Port 8xh Decode is enabled + **/ + UINT32 EnablePort8xhDecode : 1; + /** + The Index of PCIe Port that is selected for Port8xh Decode (0 Based) + **/ + UINT32 ScPciePort8xhDecodePortIndex : 5; + /** + This member describes whether the PCI Express Clock Gating for each root port + is enabled by platform modules. It is enabled by default. + **/ + UINT32 DisableRootPortClockGating : 1; + /** + This member describes whether Peer Memroy Writes are enabled on the platform + **/ + UINT32 EnablePeerMemoryWrite : 1; + /** + This member describes the SwSmi value for override PCIe ASPM table. Default is 0xAA + **/ + UINT32 AspmSwSmiNumber : 8; + /** + Compliance Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + UINT32 Rsvdbits : 15; + + UINT32 PcieRsvdBits0 : 2; + UINT32 SvRsvdbits : 30; + UINT32 Reserved[3]; ///< Reserved bytes +} SC_PCIE_CONFIG; + +#pragma pack (pop) + +#endif // _SC_PCIE_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h new file mode 100644 index 0000000000..6a9fe614bf --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/PmConfig.h @@ -0,0 +1,55 @@ +/** @file + Power Management policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PM_CONFIG_H_ +#define _PM_CONFIG_H_ + +#define PM_CONFIG_REVISION 2 + +extern EFI_GUID gPmConfigGuid; + +#pragma pack (push,1) + +/** + This structure allows to customize wake up capability from wake events. + +**/ +typedef struct { + UINT32 PmeB0S5Dis : 1; + UINT32 Rsvdbits : 31; +} SC_WAKE_CONFIG; + +/** + The SC_PM_CONFIG block describes expected miscellaneous power management settings. + The PowerResetStatusClear field would clear the Power/Reset status bits, please + set the bits if you want PCH Init driver to clear it, if you want to check the + status later then clear the bits. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + SC_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy + UINT32 PciClockRun : 1; + UINT32 Timer8254ClkGateEn : 1; + UINT32 PwrBtnOverridePeriod : 3; + UINT32 DisableNativePowerButton : 1; + UINT32 PowerButterDebounceMode : 1; + UINT32 Rsvdbits :25; +} SC_PM_CONFIG; + +#pragma pack (pop) + +#endif // _PM_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h new file mode 100644 index 0000000000..5e0a234b2a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SataConfig.h @@ -0,0 +1,79 @@ +/** @file + SATA policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SATA_CONFIG_H_ +#define _SATA_CONFIG_H_ + +#define SATA_CONFIG_REVISION 1 + +extern EFI_GUID gSataConfigGuid; + +#pragma pack (push,1) + +typedef enum { + ScSataModeAhci, + ScSataModeRaid, + ScSataModeMax +} SC_SATA_MODE; + +typedef enum { + ScSataSpeedDefault, + ScSataSpeedGen1, + ScSataSpeedGen2, + ScSataSpeedGen3 +} SC_SATA_SPEED; + +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable + UINT32 HotPlug : 1; ///< 0: Disable; 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; 1: Enable + UINT32 External : 1; ///< 0: Disable; 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: SSD + UINT32 DevSlp : 1; ///< 0: Disable; 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. Default is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is 625. + UINT32 Rsvdbits0 : 10; ///< Reserved fields for future expansion w/o protocol change +} SC_SATA_PORT_CONFIG; + +// +// The SC_SATA_CONFIG block describes the expected configuration of the SATA controllers. +// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + // + // This member describes whether or not the SATA controllers should be enabled. + // + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test) 0: Disable; 1: Allow entrance to the SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disable; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable SATA Power Optimizer on SC side. + UINT32 eSATASpeedLimit : 1; + UINT32 Rsvdbits : 27; ///< Reserved bits + SC_SATA_MODE SataMode; + SC_SATA_SPEED SpeedLimit; + // + // This member configures the features, property, and capability for each SATA port. + // + SC_SATA_PORT_CONFIG PortSettings[SC_MAX_SATA_PORTS]; + UINT32 Reserved; ///< Reserved bytes + UINT32 Reserved1[3]; ///< Reserved fields for future expansion +} SC_SATA_CONFIG; + +#pragma pack (pop) + +#endif // _SATA_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h new file mode 100644 index 0000000000..4c919f6a64 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScGeneralConfig.h @@ -0,0 +1,41 @@ +/** @file + SC General policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_GENERAL_CONFIG_H_ +#define _SC_GENERAL_CONFIG_H_ + +#define SC_GENERAL_CONFIG_REVISION 1 + +extern EFI_GUID gScGeneralConfigGuid; + +#pragma pack (push,1) + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the SC devices. Default is 0x8086 + UINT16 SubSystemId; ///< Default Subsystem ID of the SC devices. Default is 0x7270 + UINT16 AcpiBase; ///< Power management I/O base address. Default is 0x400. + UINT32 PmcBase; ///< PMC Base Address. Default is 0xD1001000. + UINT32 P2sbBase; ///< P2SB base Address. Default is 0xD0000000. + UINT32 Crid : 1; + UINT32 S0ixSupport : 1; + UINT32 ResetSelect : 4; + UINT32 RsvdBits0 : 26; ///< Reserved bits +} SC_GENERAL_CONFIG; + +#pragma pack (pop) + +#endif // _SC_GENERAL_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h new file mode 100644 index 0000000000..895ea00b18 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScInterruptAssign.h @@ -0,0 +1,72 @@ +/** @file + IoApic policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _INTERRUPT_CONFIG_H_ +#define _INTERRUPT_CONFIG_H_ + +#define INTERRUPT_CONFIG_REVISION 1 + +extern EFI_GUID gInterruptConfigGuid; + +#pragma pack (push,1) + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef struct { + UINT8 Port; + UINT16 PciCfgOffset; + UINT8 PciIrqNumber; + UINT8 IrqPin; +} PRIVATE_PCICFGCTRL; + +typedef enum { + ScNoInt, ///< No Interrupt Pin + ScIntA, + ScIntB, + ScIntC, + ScIntD +} SC_INT_PIN; + +// +// The SC_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for SC device. +// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SC_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SC_DEVICE_INTERRUPT_CONFIG; + +#define SC_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all SC devices +#define SC_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS +#define SC_MAX_DIRECT_IRQ_CONFIG 25 ///< Number of direct Irq Table + +// +// The SC_INTERRUPT_CONFIG block describes interrupt settings for SC. +// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table + UINT8 NumOfDirectIrqTable; + PRIVATE_PCICFGCTRL DirectIrqTable[SC_MAX_DIRECT_IRQ_CONFIG]; + SC_DEVICE_INTERRUPT_CONFIG DevIntConfig[SC_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores SC devices interrupts settings + UINT8 PxRcRouting[SC_MAX_PXRC_CONFIG]; +} SC_INTERRUPT_CONFIG; + +#pragma pack (pop) + +#endif // _INTERRUPT_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h new file mode 100644 index 0000000000..2a8c72c110 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/ScsConfig.h @@ -0,0 +1,122 @@ +/** @file + Scs policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SCS_CONFIG_H_ +#define _SCS_CONFIG_H_ + +#define SCS_CONFIG_REVISION 3 + +extern EFI_GUID gScsConfigGuid; + +#pragma pack (push,1) + +// +// Device Operating Mode +// +typedef enum { + ScDisabled = 0, + ScPciMode = 1, + ScAcpiMode = 2, + ScDevModeMax +} SC_DEV_MODE; + +// +// SCC eMMC Host Speed +// +enum SCC_EMMC_MODE { + SccEmmcHs400 = 0, + SccEmmcHs200 = 1, + SccEmmcDdr50 = 2, +}; + +/** + The SDIO_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC. + @note: the order defined below is for SDIO DLL registers settings, and MUST not change. + Items defined will be accessed by its index in ConfigureSdioDll module + +**/ +typedef struct { + UINT32 TxCmdCntl; + UINT32 TxDataCntl1; + UINT32 TxDataCntl2; + UINT32 RxCmdDataCntl1; + UINT32 RxCmdDataCntl2; +} SDIO_REG_CONFIG; + +/** + The SDCARD_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC. + @note: the order defined below is for SDCARD DLL registers settings, and MUST not change. + Items defined will be accessed by its index in ConfigureSdioDll module + +**/ +typedef struct { + UINT32 TxCmdCntl; + UINT32 TxDataCntl1; + UINT32 TxDataCntl2; + UINT32 RxCmdDataCntl1; + UINT32 RxStrobeCntl; + UINT32 RxCmdDataCntl2; +} SDCARD_REG_CONFIG; + +/** + The EMMC_REG_CONFIG block is the structure defined in SC_SCS_CONFIG for SC. + @note: the order defined below is for EMMC DLL registers settings, and MUST not change. + Items defined will be accessed by its index in ConfigureSdioDll module +**/ +typedef struct { + UINT32 TxCmdCntl; + UINT32 TxDataCntl1; + UINT32 TxDataCntl2; + UINT32 RxCmdDataCntl1; + UINT32 RxStrobeCntl; + UINT32 RxCmdDataCntl2; + UINT32 MasterSwCntl; +} EMMC_REG_CONFIG; + +// +// SCC eMMC Trace Length +// +#define SCC_EMMC_LONG_TRACE_LEN 0 +#define SCC_EMMC_SHORT_TRACE_LEN 1 + +/** + The SC_SCS_CONFIG block describes Storage and Communication Subsystem (SCS) settings for SC. + @note: the order defined below is per the PCI BDF sequence, and MUST not change. + Items defined will be accessed by its index in ScInit module +**/ +typedef struct { +/** + Revision 1: Init version + Revision 2: Add SccEmmcTraceLength + Revision 3: Add SDIO_REG_CONFIG and SDCARD_REG_CONFIG and EMMC_REG_CONFIG structures. +**/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header //ChangeLog, Revision 1: Init version, Revision 2: Add SccEmmcTraceLength + SC_DEV_MODE SdcardEnable; ///< Determine if SD Card is enabled - 0: Disabled, 1: Enabled. Default is ScPciMode + SC_DEV_MODE EmmcEnable; ///< Determine if eMMC is enabled - 0: Disabled, 1: Enabled. Default is ScPciMode + SC_DEV_MODE UfsEnable; ///< Determine if UFS is enabled - 0: Disabled, 1: Enabled. + SC_DEV_MODE SdioEnable; ///< Determine if SDIO is enabled - 0: Disabled, 1: Enabled. Default is ScPciMode + UINT32 EmmcHostMaxSpeed : 2; ///< Determine eMMC Mode. Default is 0: HS400, 1: HS200, 2:DDR50 + UINT32 GppLock : 1; ///< Determine if GPP is locked 0: Disabled; 1: Enabled + UINT32 SccEmmcTraceLength : 2; ///< Determine EMMC Trace length - 0: Longer Trace, Validated on Rvp 1: Shorter trace, Validated on FFD. Default is SCC_EMMC_LONG_TRACE_LEN + UINT32 RsvdBits : 27; ///< Reserved bits + SDIO_REG_CONFIG SdioRegDllConfig; ///< SDIO DLL Configure structure + SDCARD_REG_CONFIG SdcardRegDllConfig; ///< SDCARD DLL Configure structure + EMMC_REG_CONFIG EmmcRegDllConfig; ///< eMMC DLL Configure structure +} SC_SCS_CONFIG; + +#pragma pack (pop) + +#endif // _SCS_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h new file mode 100644 index 0000000000..59c57e6aaf --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SerialIrqConfig.h @@ -0,0 +1,50 @@ +/** @file + Serial IRQ policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SERIAL_IRQ_CONFIG_H_ +#define _SERIAL_IRQ_CONFIG_H_ + +#define SERIAL_IRQ_CONFIG_REVISION 1 + +extern EFI_GUID gSerialIrqConfigGuid; + +#pragma pack (push,1) + +typedef enum { + ScQuietMode, + ScContinuousMode +} SC_SIRQ_MODE; + +typedef enum { + ScSfpw4Clk, + ScSfpw6Clk, + ScSfpw8Clk +} SC_START_FRAME_PULSE; + +// +// The SC_LPC_SIRQ_CONFIG block describes the expected configuration for Serial IRQ. +// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; 1: Enable. + UINT32 SirqMode : 2; ///< Serial IRQ Mode Select. Refer to SC_SIRQ_MODE for each value. 0: quiet mode 1: continuous mode. + UINT32 StartFramePulse : 3; ///< Start Frame Pulse Width. Refer to SC_START_FRAME_PULSE for each value. Default is ScSfpw4Clk. + UINT32 RsvdBits0 : 26; ///< Reserved bits +} SC_LPC_SIRQ_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IRQ_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h new file mode 100644 index 0000000000..4cc1788fd8 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/SmbusConfig.h @@ -0,0 +1,44 @@ +/** @file + Smbus policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SMBUS_CONFIG_H_ +#define _SMBUS_CONFIG_H_ + +#define SMBUS_CONFIG_REVISION 1 + +extern EFI_GUID gSmbusConfigGuid; + +#pragma pack (push,1) + +#define SC_MAX_SMBUS_RESERVED_ADDRESS 128 + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable or Enable Smbus dynamic power gating. + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable. + UINT8 RsvdSmbusAddressTable[SC_MAX_SMBUS_RESERVED_ADDRESS]; + UINT32 SpdRsvd : 2; + UINT32 SvRsvdbits : 30; +} SC_SMBUS_CONFIG; + +#pragma pack (pop) + +#endif // _SMBUS_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..a29f8cc205 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,107 @@ +/** @file + USB policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _USB_CONFIG_H_ +#define _USB_CONFIG_H_ + +#define USB_CONFIG_REVISION 2 + +extern EFI_GUID gUsbConfigGuid; + +#pragma pack (push,1) + +typedef enum { + ScUsbOverCurrentPin0 = 0, + ScUsbOverCurrentPin1, + ScUsbOverCurrentPinSkip, + ScUsbOverCurrentPinMax +} SC_USB_OVERCURRENT_PIN; + +#define XHCI_MODE_OFF 0 +#define XHCI_MODE_ON 1 + +typedef struct { + UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto + UINT8 Rsvdbits : 4; +} SC_USB30_CONTROLLER_SETTINGS; + +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + UINT32 Rsvd1[1]; ///< Reserved bytes +} SC_USB20_PORT_CONFIG; + +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; ///< Reserved bits + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4 + UINT32 Rsvd1[2]; ///< Reserved bytes +} SC_USB30_PORT_CONFIG; + +typedef struct { + UINT32 Enable : 2; + UINT32 RsvdBits : 30; ///< Reserved bits +} SC_XDCI_CONFIG; + +typedef struct { + UINT32 Enable : 1; + UINT32 RsvdBits : 31; +} SC_XHCI_HSIC_PORT; + +/** + These members describe some settings which are related to the SSIC ports. + +**/ +typedef struct { + SC_XHCI_HSIC_PORT HsicPort[XHCI_MAX_HSIC_PORTS]; +} SC_HSIC_CONFIG; + +typedef enum { + XhciSsicRateA = 1, + XhciSsicRateB +} SC_XHCI_SSIC_PORT_RATE; + +typedef struct { + UINT32 Enable : 1; + UINT32 Rate : 2; + UINT32 RsvdBits : 29; +} SC_XHCI_SSIC_PORT; + +typedef struct { + SC_XHCI_SSIC_PORT SsicPort[XHCI_MAX_SSIC_PORTS]; + UINT32 DlanePwrGating : 1; + UINT32 RsvdBits : 31; +} SC_SSIC_CONFIG; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DisableComplianceMode : 1; + UINT32 UsbPerPortCtl : 1; ///< @deprecated since revision 2 + UINT32 RsvdBits : 30; + SC_USB30_CONTROLLER_SETTINGS Usb30Settings; + SC_USB20_PORT_CONFIG PortUsb20[SC_MAX_USB2_PORTS]; + SC_USB30_PORT_CONFIG PortUsb30[SC_MAX_USB3_PORTS]; + SC_XDCI_CONFIG XdciConfig; + SC_HSIC_CONFIG HsicConfig; + SC_SSIC_CONFIG SsicConfig; +} SC_USB_CONFIG; + +#pragma pack (pop) + +#endif // _USB_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h new file mode 100644 index 0000000000..e6fb1a24ec --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ConfigBlock/VtdConfig.h @@ -0,0 +1,40 @@ +/** @file + VT-d policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _VTD_CONFIG_H_ +#define _VTD_CONFIG_H_ + +#define VTD_CONFIG_REVISION 1 + +extern EFI_GUID gVtdConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to VT-d. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 VtdEnable : 1; ///< 1: Enable, 0: Disable VT-d + UINT8 x2ApicEnabled : 1; + UINT32 RsvdBits : 30; ///< Reserved bits + UINT64 RmrrUsbBaseAddr; + UINT64 RmrrUsbLimit; +} SC_VTD_CONFIG; + +#pragma pack (pop) + +#endif // _VTD_CONFIG_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Dbg2t.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Dbg2t.h new file mode 100644 index 0000000000..38f1e89813 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Dbg2t.h @@ -0,0 +1,68 @@ +/** @file + Required by Microsoft Windows to report the available debug ports on the platform. + + Copyright (c) 1996 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DBG2_H +#define _DBG2_H + +#include + +// +// Definitions +// +#define EFI_ACPI_CREATOR_REVISION 0x0100000D + +// +// DBG2 Definitions +// +#define EFI_ACPI_OEM_DBG2_TABLE_REVISION 0x00000000 +#define NUMBER_DBG_DEVICE_INFO 1 +#define DEBUG_DEVICE_INFORMATION_REVISION 0x00 +#define NAMESPACE_STRING_MAX_LENGTH 32 +#define EFI_ACPI_OEM_TABLE_ID_2 SIGNATURE_64('I','N','T','L','D','B','G','2') /// + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DBGP_H_ +#define _DBGP_H_ + +// +// Statements that include other files +// + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// Debug Port Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 InterfaceType; + UINT8 Reserved_37[3]; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; +} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE; + +#pragma pack() + + +#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01 + +// +// Interface Type +// +#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550 0 +#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 1 + +// +// DBGP Definitions +// +#define EFI_ACPI_DBGP_TABLE_REVISION 0x00000001 +#define EFI_ACPI_OEM_DBGP_REVISION 0x00000000 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/DmaRemappingTable.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/DmaRemappingTable.h new file mode 100644 index 0000000000..fd5cae5a0f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/DmaRemappingTable.h @@ -0,0 +1,106 @@ +/** @file + This code defines ACPI DMA Remapping table related definitions. + See the System Agent BIOS specification for definition of the table. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DMA_REMAPPING_TABLE_H_ +#define _DMA_REMAPPING_TABLE_H_ + +#include +#include +#include + +#pragma pack(1) + +/// +/// DMAR table signature +/// +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR" +#define EFI_ACPI_DMAR_TABLE_REVISION 1 +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10 +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18 +#define MAX_PCI_DEPTH 5 + +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT8 EnumId; + UINT8 StartBusNumber; + UINT8 PciPath[2]; ///< device, function +} EFI_ACPI_DEV_SCOPE_STRUCTURE; + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT8 Flags; + UINT8 Reserved; + UINT16 SegmentNum; + EFI_PHYSICAL_ADDRESS RegisterBaseAddress; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; +} EFI_ACPI_DRHD_ENGINE1_STRUCT; + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT8 Flags; + UINT8 Reserved; + UINT16 SegmentNum; + EFI_PHYSICAL_ADDRESS RegisterBaseAddress; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_DRHD_ENGINE2_STRUCT; + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 Reserved; + UINT16 SegmentNum; + EFI_PHYSICAL_ADDRESS RmrBaseAddress; + EFI_PHYSICAL_ADDRESS RmrLimitAddress; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_RMRR_USB_STRUC; + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 Reserved; + UINT16 SegmentNum; + EFI_PHYSICAL_ADDRESS RmrBaseAddress; + EFI_PHYSICAL_ADDRESS RmrLimitAddress; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; ///< IGD +} EFI_ACPI_RMRR_IGD_STRUC; + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT8 Reserved[3]; + UINT8 AcpiDeviceNumber; + UINT8 AcpiObjectName[20]; +} EFI_ACPI_ANDD_STRUC; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 HostAddressWidth; + UINT8 Flags; + UINT8 Reserved[10]; + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1; + EFI_ACPI_DRHD_ENGINE2_STRUCT DrhdEngine2; + EFI_ACPI_RMRR_USB_STRUC RmrrUsb; + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd; +} EFI_ACPI_DMAR_TABLE; + +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/BxtVariable.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/BxtVariable.h new file mode 100644 index 0000000000..2981be2895 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/BxtVariable.h @@ -0,0 +1,22 @@ +/** @file + GUID used to define Broxton variable. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BXT_VARIABLE_GUID_H_ +#define _BXT_VARIABLE_GUID_H_ + +extern EFI_GUID gEfiBxtVariableGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SataControllerGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SataControllerGuid.h new file mode 100644 index 0000000000..036d540a6a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SataControllerGuid.h @@ -0,0 +1,26 @@ +/** @file + GUID for use in describing SataController. + + Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SERIAL_ATA_CONTROLLER_GUID_H_ +#define _SERIAL_ATA_CONTROLLER_GUID_H_ + +#define SATA_CONTROLLER_DRIVER_GUID \ + {\ + 0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \} + +extern EFI_GUID gSataControllerDriverGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/ScInitVar.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/ScInitVar.h new file mode 100644 index 0000000000..e8e04bd1ac --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/ScInitVar.h @@ -0,0 +1,47 @@ +/** @file + This file defines variable shared between SC Init DXE driver and SC + Init S3 Resume PEIM. + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_INIT_VAR_H_ +#define _SC_INIT_VAR_H_ + +// +// Define the SC Init Var GUID +// +#define INIT_VARIABLE_GUID {0xe6c2f70a, 0xb604, 0x4877,{0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}} + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gScInitVariableGuid; + +#define INIT_VARIABLE_NAME L"PchInit" + +// +// Define the SC Init Variable structure +// +typedef struct { + UINT32 StorePosition; + UINT32 ExecutePosition; +} SC_S3_PARAMETER_HEADER; + +#pragma pack(1) +typedef struct _SC_INIT_VARIABLE { + SC_S3_PARAMETER_HEADER *ScS3Parameter; +} SC_INIT_VARIABLE; +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SmbusArpMap.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SmbusArpMap.h new file mode 100644 index 0000000000..73d8ee7ee2 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Guid/SmbusArpMap.h @@ -0,0 +1,27 @@ +/** @file + GUID for use in describing SMBus devices that were ARPed during PEI. + + Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_ +#define _EFI_SMBUS_ARP_MAP_GUID_H_ + +#define EFI_SMBUS_ARP_MAP_GUID \ + { \ + 0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \ + } + +extern EFI_GUID gEfiSmbusArpMapGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/CeAta.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/CeAta.h new file mode 100644 index 0000000000..874e478cbd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/CeAta.h @@ -0,0 +1,102 @@ +/** @file + Header file for chipset CE-AT spec. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CE_ATA_H +#define _CE_ATA_H + +#pragma pack(1) + +#define DATA_UNIT_SIZE 512 +#define CMD60 60 +#define CMD61 61 +#define RW_MULTIPLE_REGISTER CMD60 +#define RW_MULTIPLE_BLOCK CMD61 +#define CE_ATA_SIG_CE 0xCE +#define CE_ATA_SIG_AA 0xAA +#define Reg_Features_Exp 01 +#define Reg_SectorCount_Exp 02 +#define Reg_LBALow_Exp 03 +#define Reg_LBAMid_Exp 04 +#define Reg_LBAHigh_Exp 05 +#define Reg_Control 06 +#define Reg_Features_Error 09 +#define Reg_SectorCount 10 +#define Reg_LBALow 11 +#define Reg_LBAMid 12 +#define Reg_LBAHigh 13 +#define Reg_Device_Head 14 +#define Reg_Command_Status 15 + +#define Reg_scrTempC 0x80 +#define Reg_scrTempMaxP 0x84 +#define Reg_scrTempMinP 0x88 +#define Reg_scrStatus 0x8C +#define Reg_scrReallocsA 0x90 +#define Reg_scrERetractsA 0x94 +#define Reg_scrCapabilities 0x98 +#define Reg_scrControl 0xC0 + +typedef struct { + UINT8 Reserved0; + UINT8 Features_Exp; + UINT8 SectorCount_Exp; + UINT8 LBALow_Exp; + UINT8 LBAMid_Exp; + UINT8 LBAHigh_Exp; + UINT8 Control; + UINT8 Reserved1[2]; + UINT8 Features_Error; + UINT8 SectorCount; + UINT8 LBALow; + UINT8 LBAMid; + UINT8 LBAHigh; + UINT8 Device_Head; + UINT8 Command_Status; +} TASK_FILE; + +// +//Reduced ATA command set +// +#define IDENTIFY_DEVICE 0xEC +#define READ_DMA_EXT 0x25 +#define WRITE_DMA_EXT 0x35 +#define STANDBY_IMMEDIATE 0xE0 +#define FLUSH_CACHE_EXT 0xEA + +typedef struct { + UINT16 Reserved0[10]; + UINT16 SerialNumber[10]; + UINT16 Reserved1[3]; + UINT16 FirmwareRevision[4]; + UINT16 ModelNumber[20]; + UINT16 Reserved2[33]; + UINT16 MajorVersion; + UINT16 Reserved3[19]; + UINT16 MaximumLBA[4]; + UINT16 Reserved4[2]; + UINT16 Sectorsize; + UINT16 Reserved5; + UINT16 DeviceGUID[4]; + UINT16 Reserved6[94]; + UINT16 Features; + UINT16 MaxWritesPerAddress; + UINT16 Reserved7[47]; + UINT16 IntegrityWord; +} IDENTIFY_DEVICE_DATA; + +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/Mmc.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/Mmc.h new file mode 100644 index 0000000000..82e6767468 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/Mmc.h @@ -0,0 +1,338 @@ +/** @file + Header file for Industry MMC 4.2 spec. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MMC_H +#define _MMC_H + +#pragma pack(1) + +// +// Command definition +// +#define CMD0 0 +#define CMD1 1 +#define CMD2 2 +#define CMD3 3 +#define CMD4 4 +#define CMD6 6 +#define CMD7 7 +#define CMD8 8 +#define CMD9 9 +#define CMD10 10 +#define CMD11 11 +#define CMD12 12 +#define CMD13 13 +#define CMD14 14 +#define CMD15 15 +#define CMD16 16 +#define CMD17 17 +#define CMD18 18 +#define CMD19 19 +#define CMD20 20 +#define CMD23 23 +#define CMD24 24 +#define CMD25 25 +#define CMD26 26 +#define CMD27 27 +#define CMD28 28 +#define CMD29 29 +#define CMD30 30 +#define CMD31 31 +#define CMD35 35 +#define CMD36 36 +#define CMD38 38 +#define CMD39 39 +#define CMD40 40 +#define CMD42 42 +#define CMD55 55 +#define CMD56 56 + +#define GO_IDLE_STATE CMD0 +#define SEND_OP_COND CMD1 +#define ALL_SEND_CID CMD2 +#define SET_RELATIVE_ADDR CMD3 +#define SET_DSR CMD4 +#define SWITCH CMD6 +#define SELECT_DESELECT_CARD CMD7 +#define SEND_EXT_CSD CMD8 +#define SEND_CSD CMD9 +#define SEND_CID CMD10 +#define READ_DAT_UNTIL_STOP CMD11 +#define STOP_TRANSMISSION CMD12 +#define SEND_STATUS CMD13 +#define BUSTEST_R CMD14 +#define GO_INACTIVE_STATE CMD15 +#define SET_BLOCKLEN CMD16 +#define READ_SINGLE_BLOCK CMD17 +#define READ_MULTIPLE_BLOCK CMD18 +#define BUSTEST_W CMD19 +#define WRITE_DAT_UNTIL_STOP CMD20 +#define SET_BLOCK_COUNT CMD23 +#define WRITE_BLOCK CMD24 +#define WRITE_MULTIPLE_BLOCK CMD25 +#define PROGRAM_CID CMD26 +#define PROGRAM_CSD CMD27 +#define SET_WRITE_PROT CMD28 +#define CLR_WRITE_PROT CMD29 +#define SEND_WRITE_PROT CMD30 +#define SEND_WRITE_PROT_TYPE CMD31 +#define ERASE_GROUP_START CMD35 +#define ERASE_GROUP_END CMD36 +#define ERASE CMD38 +#define FAST_IO CMD39 +#define GO_IRQ_STATE CMD40 +#define LOCK_UNLOCK CMD42 +#define APP_CMD CMD55 +#define GEN_CMD CMD56 + +#define B_PERM_WP_DIS 0x10 +#define B_PWR_WP_EN 0x01 +#define US_PERM_WP_DIS 0x10 +#define US_PWR_WP_EN 0x01 + +#define FREQUENCY_OD (400 * 1000) +#define FREQUENCY_MMC_DEFAULT (25 * 1000 * 1000) +#define FREQUENCY_MMC_PP (26 * 1000 * 1000) +#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000) +#define FREQUENCY_MMC_HS (200 * 1000 * 1000) + +#define DEFAULT_DSR_VALUE 0x404 + +// +// Registers definition +// +typedef struct { + UINT32 Reserved0: 7; // 0 + UINT32 V170_V195: 1; // 1.70V - 1.95V + UINT32 V200_V260: 7; // 2.00V - 2.60V + UINT32 V270_V360: 9; // 2.70V - 3.60V + UINT32 Reserved1: 5; // 0 + UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) + UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine +} OCR; + +typedef struct { + UINT8 NotUsed: 1; ///< 1 + UINT8 CRC: 7; ///< CRC7 checksum + UINT8 MDT; ///< Manufacturing date + UINT32 PSN; ///< Product serial number + UINT8 PRV; ///< Product revision + UINT8 PNM[6]; ///< Product name + UINT16 OID; ///< OEM/Application ID + UINT8 MID; ///< Manufacturer ID +} CID; + +typedef struct { + UINT8 NotUsed: 1; ///< 1 [0:0] + UINT8 CRC: 7; ///< CRC [7:1] + UINT8 ECC: 2; ///< ECC code [9:8] + UINT8 FILE_FORMAT: 2; ///< File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; ///< Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; ///< Permanent write protection [13:13] + UINT8 COPY: 1; ///< Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; ///< File format group [15:15] + UINT16 CONTENT_PROT_APP: 1; ///< Content protection application [16:16] + UINT16 Reserved0: 4; ///< 0 [20:17] + UINT16 WRITE_BL_PARTIAL: 1; ///< Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; ///< Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; ///< Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; ///< Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; ///< Write protect group enable [31:31] + UINT32 WP_GRP_SIZE: 5; ///< Write protect group size [36:32] + UINT32 ERASE_GRP_MULT: 5; ///< Erase group size multiplier [41:37] + UINT32 ERASE_GRP_SIZE: 5; ///< Erase group size [46:42] + UINT32 C_SIZE_MULT: 3; ///< Device size multiplier [49:47] + UINT32 VDD_W_CURR_MAX: 3; ///< Max. write current @ VDD max [52:50] + UINT32 VDD_W_CURR_MIN: 3; ///< Max. write current @ VDD min [55:53] + UINT32 VDD_R_CURR_MAX: 3; ///< Max. read current @ VDD max [58:56] + UINT32 VDD_R_CURR_MIN: 3; ///< Max. read current @ VDD min [61:59] + UINT32 C_SIZELow2: 2; ///< Device size [73:62] + UINT32 C_SIZEHigh10: 10;///< Device size [73:62] + UINT32 Reserved1: 2; ///< 0 [75:74] + UINT32 DSR_IMP: 1; ///< DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; ///< Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; ///< Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; ///< Partial blocks for read allowed [79:79] + UINT32 READ_BL_LEN: 4; ///< Max. read data block length [83:80] + UINT32 CCC: 12;///< Card command classes [95:84] + UINT8 TRAN_SPEED ; ///< Max. bus clock frequency [103:96] + UINT8 NSAC ; ///< Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; ///< Data read access-time 1 [119:112] + UINT8 Reserved2: 2; ///< 0 [121:120] + UINT8 SPEC_VERS: 4; ///< System specification version [125:122] + UINT8 CSD_STRUCTURE: 2; ///< CSD structure [127:126] +} CSD; + +typedef struct { + UINT8 Reserved133_0[134]; ///< [133:0] 0 + UINT8 SEC_BAD_BLOCK_MGMNT; ///< [134] Bad Block Management mode + UINT8 Reserved135; ///< [135] 0 + UINT8 ENH_START_ADDR[4]; ///< [139:136] Enhanced User Data Start Address + UINT8 ENH_SIZE_MULT[3]; ///< [142:140] Enhanced User Data Start Size + UINT8 GP_SIZE_MULT_1[3]; ///< [145:143] GPP1 Size + UINT8 GP_SIZE_MULT_2[3]; ///< [148:146] GPP2 Size + UINT8 GP_SIZE_MULT_3[3]; ///< [151:149] GPP3 Size + UINT8 GP_SIZE_MULT_4[3]; ///< [154:152] GPP4 Size + UINT8 PARTITION_SETTING_COMPLETED; ///< [155] Partitioning Setting + UINT8 PARTITIONS_ATTRIBUTES; ///< [156] Partitions attributes + UINT8 MAX_ENH_SIZE_MULT[3]; ///< [159:157] GPP4 Start Size + UINT8 PARTITIONING_SUPPORT; ///< [160] Partitioning Support + UINT8 HPI_MGMT; ///< [161] HPI management + UINT8 RST_n_FUNCTION; ///< [162] H/W reset function + UINT8 BKOPS_EN; ///< [163] Enable background operations handshake + UINT8 BKOPS_START; ///< [164] Manually start background operations + UINT8 Reserved165; ///< [165] 0 + UINT8 WR_REL_PARAM; ///< [166] Write reliability parameter register + UINT8 WR_REL_SET; ///< [167] Write reliability setting register + UINT8 RPMB_SIZE_MULT; ///< [168] RPMB Size + UINT8 FW_CONFIG; ///< [169] FW configuration + UINT8 Reserved170; ///< [170] 0 + UINT8 USER_WP; ///< [171] User area write protection + UINT8 Reserved172; ///< [172] 0 + UINT8 BOOT_WP; ///< [173] Boot area write protection + UINT8 BOOT_WP_STATUS; ///< [174] BOOT_WP_STATUS + UINT8 ERASE_GROUP_DEF; ///< [175] High density erase group definition + UINT8 Reserved176; ///< [176] 0 + UINT8 BOOT_BUS_WIDTH; ///< [177] Boot bus width + UINT8 BOOT_CONFIG_PROT; ///< [178] Boot config protection + UINT8 PARTITION_CONFIG; ///< [179] Partition config + UINT8 Reserved180; ///< [180] 0 + UINT8 ERASED_MEM_CONT; ///< [181] Erased Memory Content + UINT8 Reserved182; ///< [182] 0 + UINT8 BUS_WIDTH; ///< [183] Bus Width Mode + UINT8 Reserved184; ///< [184] 0 + UINT8 HS_TIMING; ///< [185] High Speed Interface Timing + UINT8 Reserved186; ///< [186] 0 + UINT8 POWER_CLASS; ///< [187] Power Class + UINT8 Reserved188; ///< [188] 0 + UINT8 CMD_SET_REV; ///< [189] Command Set Revision + UINT8 Reserved190; ///< [190] 0 + UINT8 CMD_SET; ///< [191] Command Set + UINT8 EXT_CSD_REV; ///< [192] Extended CSD Revision + UINT8 Reserved193; ///< [193] 0 + UINT8 CSD_STRUCTURE; ///< [194] CSD Structure Version + UINT8 Reserved195; ///< [195] 0 + UINT8 CARD_TYPE; ///< [196] Card Type + UINT8 DRIVER_STRENGTH; ///< [197] Driver Strength + UINT8 OUT_OF_INTERRUPT_TIME; ///< [198] Out-of-interrupt busy timing + UINT8 PARTITION_SWITCH_TIME; ///< [199] Partition switching timing + UINT8 PWR_CL_52_195; ///< [200] Power Class for 52MHz @ 1.95V + UINT8 PWR_CL_26_195; ///< [201] Power Class for 26MHz @ 1.95V + UINT8 PWR_CL_52_360; ///< [202] Power Class for 52MHz @ 3.6V + UINT8 PWR_CL_26_360; ///< [203] Power Class for 26MHz @ 3.6V + UINT8 Reserved204; ///< [204] 0 + UINT8 MIN_PERF_R_4_26; ///< [205] Minimum Read Performance for 4bit @26MHz + UINT8 MIN_PERF_W_4_26; ///< [206] Minimum Write Performance for 4bit @26MHz + UINT8 MIN_PERF_R_8_26_4_52; ///< [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz + UINT8 MIN_PERF_W_8_26_4_52; ///< [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz + UINT8 MIN_PERF_R_8_52; ///< [209] Minimum Read Performance for 8bit @52MHz + UINT8 MIN_PERF_W_8_52; ///< [210] Minimum Write Performance for 8bit @52MHz + UINT8 Reserved211; ///< [211] 0 + UINT8 SEC_COUNT[4]; ///< [215:212] Sector Count + UINT8 Reserved216; ///< [216] 0 + UINT8 S_A_TIMEOUT; ///< [217] Sleep/awake timeout + UINT8 Reserved218; ///< [218] 0 + UINT8 S_C_VCCQ; ///< [219] Sleep current (VCCQ) + UINT8 S_C_VCC; ///< [220] Sleep current (VCC) + UINT8 HC_WP_GRP_SIZE; ///< [221] High-capacity write protect group size + UINT8 REL_WR_SEC_C; ///< [222] Reliable write sector count + UINT8 ERASE_TIMEOUT_MULT; ///< [223] High-capacity erase timeout + UINT8 HC_ERASE_GRP_SIZE; ///< [224] High-capacity erase unit size + UINT8 ACC_SIZE; ///< [225] Access size + UINT8 BOOT_SIZE_MULTI; ///< [226] Boot partition size + UINT8 Reserved227; ///< [227] 0 + UINT8 BOOT_INFO; ///< [228] Boot information + UINT8 SEC_TRIM_MULT; ///< [229] Secure TRIM Multiplier + UINT8 SEC_ERASE_MULT; ///< [230] Secure Erase Multiplier + UINT8 SEC_FEATURE_SUPPORT; ///< [231] Secure Feature support + UINT8 TRIM_MULT; ///< [232] TRIM Multiplier + UINT8 Reserved233; ///< [233] 0 + UINT8 MIN_PERF_DDR_R_8_52; ///< [234] Min Read Performance for 8-bit @ 52MHz + UINT8 MIN_PERF_DDR_W_8_52; ///< [235] Min Write Performance for 8-bit @ 52MHz + UINT8 Reserved237_236[2]; ///< [237:236] 0 + UINT8 PWR_CL_DDR_52_195; ///< [238] Power class for 52MHz, DDR at 1.95V + UINT8 PWR_CL_DDR_52_360; ///< [239] Power class for 52MHz, DDR at 3.6V + UINT8 Reserved240; ///< [240] 0 + UINT8 INI_TIMEOUT_AP; ///< [241] 1st initialization time after partitioning + UINT8 CORRECTLY_PRG_SECTORS_NUM[4];///< [245:242] Number of correctly programmed sectors + UINT8 BKOPS_STATUS; ///< [246] Background operations status + UINT8 Reserved501_247[255]; ///< [501:247] 0 + UINT8 BKOPS_SUPPORT; ///< [502] Background operations support + UINT8 HPI_FEATURES; ///< [503] HPI features + UINT8 S_CMD_SET; ///< [504] Sector Count + UINT8 Reserved511_505[7]; ///< [511:505] Sector Count +} EXT_CSD; + +// +// Card Status definition +// +typedef struct { + UINT32 Reserved0: 2; ///< Reserved for Manufacturer Test Mode + UINT32 Reserved1: 2; ///< Reserved for Application Specific commands + UINT32 Reserved2: 1; ///< + UINT32 SAPP_CMD: 1; ///< + UINT32 Reserved3: 1; ///< Reserved + UINT32 SWITCH_ERROR: 1; ///< + UINT32 READY_FOR_DATA: 1; ///< + UINT32 CURRENT_STATE: 4; ///< + UINT32 ERASE_RESET: 1; ///< + UINT32 Reserved4: 1; ///< Reserved + UINT32 WP_ERASE_SKIP: 1; ///< + UINT32 CID_CSD_OVERWRITE: 1; ///< + UINT32 OVERRUN: 1; ///< + UINT32 UNDERRUN: 1; ///< + UINT32 ERROR: 1; ///< + UINT32 CC_ERROR: 1; ///< + UINT32 CARD_ECC_FAILED: 1; ///< + UINT32 ILLEGAL_COMMAND: 1; ///< + UINT32 COM_CRC_ERROR: 1; ///< + UINT32 LOCK_UNLOCK_FAILED: 1; ///< + UINT32 CARD_IS_LOCKED: 1; ///< + UINT32 WP_VIOLATION: 1; ///< + UINT32 ERASE_PARAM: 1; ///< + UINT32 ERASE_SEQ_ERROR: 1; ///< + UINT32 BLOCK_LEN_ERROR: 1; ///< + UINT32 ADDRESS_MISALIGN: 1; ///< + UINT32 ADDRESS_OUT_OF_RANGE:1; ///< +} CARD_STATUS; + +typedef struct { + UINT32 CmdSet: 3; + UINT32 Reserved0: 5; + UINT32 Value: 8; + UINT32 Index: 8; + UINT32 Access: 2; + UINT32 Reserved1: 6; +} SWITCH_ARGUMENT; + +#define CommandSet_Mode 0 +#define SetBits_Mode 1 +#define ClearBits_Mode 2 +#define WriteByte_Mode 3 + +#define Idle_STATE 0 +#define Ready_STATE 1 +#define Ident_STATE 2 +#define Stby_STATE 3 +#define Tran_STATE 4 +#define Data_STATE 5 +#define Rcv_STATE 6 +#define Prg_STATE 7 +#define Dis_STATE 8 +#define Btst_STATE 9 + +#pragma pack() +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/SdCard.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/SdCard.h new file mode 100644 index 0000000000..736ce5c609 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/IndustryStandard/SdCard.h @@ -0,0 +1,133 @@ +/** @file + Header file for Industry SD Card 2.0 spec. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SD_CARD_H +#define _SD_CARD_H + +#include + +#pragma pack(1) + +#define CHECK_PATTERN 0xAA ///< Physical Layer Simplified Specification Version 3.01 recommended 0xAA + +#define ACMD6 6 +#define ACMD13 13 +#define ACMD23 23 +#define ACMD41 41 +#define ACMD42 42 +#define ACMD51 51 + +#define SWITCH_FUNC CMD6 +#define SEND_IF_COND CMD8 +#define SET_BUS_WIDTH ACMD6 +#define SD_STATUS ACMD13 +#define SET_WR_BLK_ERASE_COUNT ACMD23 +#define SD_SEND_OP_COND ACMD41 +#define SET_CLR_CARD_DETECT ACMD42 +#define SEND_SCR ACMD51 +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 +#define FREQUENCY_SD_PP (25 * 1000 * 1000) +#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000) +#define SD_SPEC_10 0 +#define SD_SPEC_11 1 +#define SD_SPEC_20 2 + +#define VOLTAGE_27_36 0x1 + +typedef struct { + UINT8 NotUsed: 1; ///< 1 [0:0] + UINT8 CRC: 7; ///< CRC [7:1] + UINT8 ECC: 2; ///< ECC code [9:8] + UINT8 FILE_FORMAT: 2; ///< File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; ///< Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; ///< Permanent write protection [13:13] + UINT8 COPY: 1; ///< Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; ///< File format group [15:15] + UINT16 Reserved0: 5; ///< 0 [20:16] + UINT16 WRITE_BL_PARTIAL: 1; ///< Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; ///< Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; ///< Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; ///< Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; ///< Write protect group enable [31:31] + UINT16 WP_GRP_SIZE: 7; ///< Write protect group size [38:32] + UINT16 SECTOR_SIZE: 7; ///< Erase sector size [45:39] + UINT16 ERASE_BLK_EN: 1; ///< Erase single block enable [46:46] + UINT16 Reserved1: 1; ///< 0 [47:47] + UINT32 C_SIZE: 22; ///< Device size [69:48] + UINT32 Reserved2: 6; ///< 0 [75:70] + UINT32 DSR_IMP: 1; ///< DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; ///< Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; ///< Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; ///< Partial blocks for read allowed [79:79] + UINT16 READ_BL_LEN: 4; ///< Max. read data block length [83:80] + UINT16 CCC: 12; ///< Card command classes [95:84] + UINT8 TRAN_SPEED ; ///< Max. bus clock frequency [103:96] + UINT8 NSAC ; ///< Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; ///< Data read access-time 1 [119:112] + UINT8 Reserved3: 6; ///< 0 [125:120] + UINT8 CSD_STRUCTURE: 2; ///< CSD structure [127:126] +} CSD_SDV2; + +typedef struct { + UINT32 Reserved0; + UINT32 Reserved1: 16; + UINT32 SD_BUS_WIDTH: 4; + UINT32 SD_SECURITY: 3; + UINT32 DATA_STAT_AFTER_ERASE: 1; + UINT32 SD_SPEC: 4; + UINT32 SCR_STRUCT: 4; +} SCR; + +typedef struct { + UINT8 Reserved0[50]; + UINT8 ERASE_OFFSET: 2; + UINT8 ERASE_TIMEOUT: 6; + UINT16 ERASE_SIZE; + UINT8 Reserved1: 4; + UINT8 AU_SIZE: 4; + UINT8 PERFORMANCE_MOVE; + UINT8 SPEED_CLASS; + UINT32 SIZE_OF_PROTECTED_AREA; + UINT32 SD_CARD_TYPE: 16; + UINT32 Reserved2: 13; + UINT32 SECURED_MODE: 1; + UINT32 DAT_BUS_WIDTH: 2; +} SD_STATUS_REG; + +typedef struct { + UINT8 Reserved0[34]; + UINT16 Group1BusyStatus; + UINT16 Group2BusyStatus; + UINT16 Group3BusyStatus; + UINT16 Group4BusyStatus; + UINT16 Group5BusyStatus; + UINT16 Group6BusyStatus; + UINT8 DataStructureVersion; + UINT8 Group21Status; + UINT8 Group43Status; + UINT8 Group65Status; + UINT16 Group1Function; + UINT16 Group2Function; + UINT16 Group3Function; + UINT16 Group4Function; + UINT16 Group5Function; + UINT16 Group6Function; + UINT16 MaxCurrent; +} SWITCH_STATUS; + +#pragma pack() +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h new file mode 100644 index 0000000000..2d3dc46574 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeRuntimePciLibPciExpress.h @@ -0,0 +1,54 @@ +/** @file + Header file for the Dxe Runtime PCI library. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_ +#define _DXE_RUNTIME_PCI_LIB_PCIEXPRESS_H_ + + +/** + Constructor for Pci library. Register VirtualAddressNotifyEvent() notify function + It will ASSERT() if that operation fails + + @param[in] None + + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +PciLibConstructor ( + VOID + ); + +/** + Register memory space + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If SmPciLibAddressMapIndex) > PCI_LIB_ADDRESS_MAP_MAX_ITEM, then ASSERT(). + + @param[in] Address Starting address of the memory space + @param[in] Length Length of the memory space + + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +PciLibRegisterMemory ( + IN UINTN Address, + IN UINTN Length + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h new file mode 100644 index 0000000000..bf88f5b220 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/DxeVtdLib.h @@ -0,0 +1,78 @@ +/** @file + Prototype of Intel VT-d (Virtualization Technology for Directed I/O). + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _VT_D_DXE_H_ +#define _VT_D_DXE_H_ + +// +// Include files +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VTD_ECAP_REG 0x10 +#define IR BIT3 +#define VTD_RMRR_USB_LENGTH 0x20000 + +#define EFI_MSR_XAPIC_BASE 0x1B +#define R_SA_MCHBAR 0x48 +// +// VT-d Engine base address. +// +#define R_SA_MCHBAR_VTD1_OFFSET 0x6C88 ///< DMA Remapping HW UNIT1 for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x6C80 ///< DMA Remapping HW UNIT2 for all other - PEG, USB, SATA etc + +/** + Locate the VT-d ACPI tables data file and update it based on current configuration and capabilities. + + @retval EFI_SUCCESS VT-d initialization complete + @retval EFI_UNSUPPORTED VT-d is disabled by policy or not supported + +**/ +EFI_STATUS +VtdInit ( + VOID + ); + +/** + ReadyToBoot callback routine to update DMAR. + +**/ +VOID +UpdateDmarOnReadyToBoot ( + BOOLEAN VtEnable + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h new file mode 100644 index 0000000000..d68143efef --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/HsioLib.h @@ -0,0 +1,87 @@ +/** @file + Header file for ScHsioLib. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_HSIO_LIB_H_ +#define _SC_HSIO_LIB_H_ + +/** + The function returns the Port Id and lane owner for the specified lane. + + @param[in] LaneNum Lane number that needs to be checked + @param[out] PortId Common Lane End Point ID + @param[out] LaneOwner Lane Owner + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid lane number + +**/ +EFI_STATUS +EFIAPI +ScGetLaneInfo ( + IN UINT32 LaneNum, + OUT UINT8 *PortId, + OUT UINT8 *LaneOwner + ); + +/** + Determine the lane number of a specified port. + + @param[in] PcieLaneIndex PCIE Root Port Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port + +**/ +EFI_STATUS +ScGetPcieLaneNum ( + IN UINT32 PcieLaneIndex, + OUT UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port. + + @param[in] SataLaneIndex Sata Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port + +**/ +EFI_STATUS +ScGetSataLaneNum ( + IN UINT32 SataLaneIndex, + OUT UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port. + + @param[in] Usb3LaneIndex USB3 Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port + +**/ +EFI_STATUS +ScGetUsb3LaneNum ( + IN UINT32 Usb3LaneIndex, + OUT UINT8 *LaneNum + ); + +#endif // _SC_HSIO_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h new file mode 100644 index 0000000000..b593620106 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h @@ -0,0 +1,227 @@ +/** @file + Register Definitions for I2C Library. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _I2C_LIB_H_ +#define _I2C_LIB_H_ + +#include +#include + +// +// FIFO write workaround value. +// +#define FIFO_WRITE_DELAY 2 + +// +// MMIO Register Definitions +// +#define R_IC_CON (0x00) ///< I2C Control +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_SPEED_STANDARD 0x02 +#define V_SPEED_FAST 0x04 +#define V_SPEED_HIGH 0x06 +#define B_MASTER_MODE BIT0 + +#define R_IC_TAR (0x04) ///< I2C Target Address +#define IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_SAR (0x08) ///< I2C Slave Address +#define R_IC_HS_MADDR (0x0C) ///< I2C HS MasterMode Code Address +#define R_IC_DATA_CMD (0x10) ///< I2C Rx/Tx Data Buffer and Command + +#define B_READ_CMD BIT8 ///< 1 = read, 0 = write +#define B_CMD_STOP BIT9 ///< 1 = STOP +#define B_CMD_RESTART BIT10 ///< 1 = IC_RESTART_EN + +#define V_WRITE_CMD_MASK (0xFF) + +#define R_IC_SS_SCL_HCNT (0x14) ///< Standard Speed I2C Clock SCL High Count +#define R_IC_SS_SCL_LCNT (0x18) ///< Standard Speed I2C Clock SCL Low Count +#define R_IC_FS_SCL_HCNT (0x1C) ///< Full Speed I2C Clock SCL High Count +#define R_IC_FS_SCL_LCNT (0x20) ///< Full Speed I2C Clock SCL Low Count +#define R_IC_HS_SCL_HCNT (0x24) ///< High Speed I2C Clock SCL High Count +#define R_IC_HS_SCL_LCNT (0x28) ///< High Speed I2C Clock SCL Low Count +#define R_IC_INTR_STAT (0x2C) ///< I2C Inetrrupt Status +#define R_IC_INTR_MASK (0x30) ///< I2C Interrupt Mask +#define I2C_INTR_GEN_CALL BIT11 ///< General call received +#define I2C_INTR_START_DET BIT10 +#define I2C_INTR_STOP_DET BIT9 +#define I2C_INTR_ACTIVITY BIT8 +#define I2C_INTR_TX_ABRT BIT6 ///< Set on NACK +#define I2C_INTR_TX_EMPTY BIT4 +#define I2C_INTR_TX_OVER BIT3 +#define I2C_INTR_RX_FULL BIT2 ///< Data bytes in RX FIFO over threshold +#define I2C_INTR_RX_OVER BIT1 +#define I2C_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT (0x34) ///< I2C Raw Interrupt Status +#define R_IC_RX_TL (0x38) ///< I2C Receive FIFO Threshold +#define R_IC_TX_TL (0x3C) ///< I2C Transmit FIFO Threshold +#define R_IC_CLR_INTR (0x40) ///< Clear Combined and Individual Interrupts +#define R_IC_CLR_RX_UNDER (0x44) ///< Clear RX_UNDER Interrupt +#define R_IC_CLR_RX_OVER (0x48) ///< Clear RX_OVERinterrupt +#define R_IC_CLR_TX_OVER (0x4C) ///< Clear TX_OVER interrupt +#define R_IC_CLR_RD_REQ (0x50) ///< Clear RD_REQ interrupt +#define R_IC_CLR_TX_ABRT (0x54) ///< Clear TX_ABRT interrupt +#define R_IC_CLR_RX_DONE (0x58) ///< Clear RX_DONE interrupt +#define R_IC_CLR_ACTIVITY (0x5C) ///< Clear ACTIVITY interrupt +#define R_IC_CLR_STOP_DET (0x60) ///< Clear STOP_DET interrupt +#define R_IC_CLR_START_DET (0x64) ///< Clear START_DET interrupt +#define R_IC_CLR_GEN_CALL (0x68) ///< Clear GEN_CALL interrupt +#define R_IC_ENABLE (0x6C) ///< I2C Enable +#define R_IC_STATUS (0x70) ///< I2C Status + +#define R_IC_SDA_HOLD (0x7C) ///< I2C IC_DEFAULT_SDA_HOLD//16bits + +#define STAT_MST_ACTIVITY BIT5 ///< Master FSM Activity Status. +#define STAT_RFF BIT4 ///< RX FIFO is completely full +#define STAT_RFNE BIT3 ///< RX FIFO is not empty +#define STAT_TFE BIT2 ///< TX FIFO is completely empty +#define STAT_TFNF BIT1 ///< TX FIFO is not full + +#define R_IC_TXFLR (0x74) ///< Transmit FIFO Level Register +#define R_IC_RXFLR (0x78) ///< Receive FIFO Level Register +#define R_IC_TX_ABRT_SOURCE (0x80) ///< I2C Transmit Abort Status Register +#define R_IC_SLV_DATA_NACK_ONLY (0x84) ///< Generate SLV_DATA_NACK Register +#define R_IC_DMA_CR (0x88) ///< DMA Control Register +#define R_IC_DMA_TDLR (0x8C) ///< DMA Transmit Data Level +#define R_IC_DMA_RDLR (0x90) ///< DMA Receive Data Level +#define R_IC_SDA_SETUP (0x94) ///< I2C SDA Setup Register +#define R_IC_ACK_GENERAL_CALL (0x98) ///< I2C ACK General Call Register +#define R_IC_ENABLE_STATUS (0x9C) ///< I2C Enable Status Register +#define R_IC_COMP_PARAM (0xF4) ///< Component Parameter Register +#define R_IC_COMP_VERSION (0xF8) ///< Component Version ID +#define R_IC_COMP_TYPE (0xFC) ///< Component Type + +#define R_IC_CLK_GATE (0xC0) ///< Clock Gate + +#define IC_TAR_10BITADDR_MASTER BIT12 +#define FIFO_SIZE 32 + + +/** + Program LPSS I2C PCI controller's BAR0 and enable memory decode. + + @param[in] BusNo I2C Bus number to which the I2C device has been connected + + @retval EFI_SUCCESS I2C controller's BAR0 is programmed and memory decode enabled. + @retval EFI_NOT_READY I2C controller's is not exist or its function has been disabled. + +**/ +EFI_STATUS +ProgramPciLpssI2C ( + IN UINT8 BusNo + ); + +/** + Read bytes from I2C Device + This is actual I2C hardware operation function. + + @param[in] BusNo I2C Bus number to which the I2C device has been connected + @param[in] SlaveAddress Slave address of the I2C device + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to be stored + @param[in] Start It controls whether a RESTART is issued before the byte is sent or received. + @param[in] End It controls whether a STOP is issued after the byte is sent or received. + + @retval EFI_SUCCESS The byte value read successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to read a byte via I2C + +**/ +EFI_STATUS +ByteReadI2C_Basic ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer, + IN UINT8 Start, + IN UINT8 End + ); + +/** + Write bytes to I2C Device + This is actual I2C hardware operation function. + + @param[in] BusNo I2C Bus number to which the I2C device has been connected + @param[in] SlaveAddress Slave address of the I2C device + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to be written + @param[in] Start It controls whether a RESTART is issued before the byte is sent or received. + @param[in] End It controls whether a STOP is issued after the byte is sent or received. + + @retval EFI_SUCCESS The byte value written successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to write a byte via I2C + +**/ +EFI_STATUS +ByteWriteI2C_Basic ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT8 Start, + IN UINT8 End + ); + +/** + Read bytes from I2C Device + + @param[in] BusNo I2C Bus number to which the I2C device has been connected + @param[in] SlaveAddress Slave address of the I2C device + @param[in] Offset Register offset from which the data has to be read + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to be stored + + @retval EFI_SUCCESS Read bytes from I2C device successfully + @retval Others Return status depends on ByteReadI2C_Basic + +**/ +EFI_STATUS +ByteReadI2C ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer + ); + +/** + Write bytes to I2C Device + + @param[in] BusNo I2C Bus number to which the I2C device has been connected + @param[in] SlaveAddress Slave address of the I2C device + @param[in] Offset Register offset from which the data has to be read + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to be written + + @retval EFI_SUCCESS Write bytes to I2C device successfully + @retval Others Return status depends on ByteWriteI2C_Basic + +**/ +EFI_STATUS +ByteWriteI2C ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer + ); + +#endif // _I2C_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h new file mode 100644 index 0000000000..7a4172daa5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiMmcMainLib.h @@ -0,0 +1,36 @@ +/** @file + Mmc Main PEI Library header. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_MMC_MAIN_LIB_H_ +#define _PEI_MMC_MAIN_LIB_H_ + +/** + Entry point for EFI drivers. + + @param[in] PeiServices EFI_PEI_SERVICES + + @retval EFI_SUCCESS Success + @retval EFI_DEVICE_ERROR Fail + +**/ +EFI_STATUS +EFIAPI +MmcMainEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h new file mode 100644 index 0000000000..84ed7b1dfd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiScPolicyLib.h @@ -0,0 +1,125 @@ +/** @file + Prototype of the PeiScPolicy library. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_SC_POLICY_LIBRARY_H_ +#define _PEI_SC_POLICY_LIBRARY_H_ + +#include +#include + +/** + Print whole SC_PREMEM_POLICY_PPI and serial out. + + @param[in] ScPreMemPolicyPpi The RC Policy PPI instance + +**/ +VOID +EFIAPI +ScPreMemPrintPolicyPpi ( + IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi + ); + +/** + Print whole SC_POLICY_PPI and serial out. + + @param[in] ScPolicy The SC Policy Ppi instance + +**/ +VOID +EFIAPI +ScPrintPolicyPpi ( + IN SC_POLICY_PPI *ScPolicy + ); + +/** + CreatePreMemConfigBlocks generates the config blocks of SC Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] ScPreMemPolicyPpi The pointer to get SC PREMEM Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScCreatePreMemConfigBlocks ( + OUT SC_PREMEM_POLICY_PPI **ScPreMemPolicyPpi + ); + +/** + ScInstallPreMemPolicyPpi installs ScPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] ScPreMemPolicyPpi The pointer to SC PREMEM Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScInstallPreMemPolicyPpi ( + IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi + ); + +/** + Get SC config block table total size. + + @retval Size of SC config block table + +**/ +UINT32 +EFIAPI +ScGetConfigBlockTotalSize ( + VOID + ); + +/** + ScCreateConfigBlocks generates the config blocks of SC Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] ScPolicyPpi The pointer to get SC Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScCreateConfigBlocks ( + OUT SC_POLICY_PPI **ScPolicyPpi + ); + +/** + ScInstallPolicyPpi installs ScPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] ScPolicyPpi The pointer to SC Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScInstallPolicyPpi ( + IN SC_POLICY_PPI *ScPolicyPpi + ); + +#endif // _PEI_SC_POLICY_LIBRARY_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h new file mode 100644 index 0000000000..614a6c0d1a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/PeiVtdLib.h @@ -0,0 +1,47 @@ +/** @file + Prototype of Intel VT-d (Virtualization Technology for Directed I/O). + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _VT_D_PEI_H_ +#define _VT_D_PEI_H_ + +#include + +#define VTD_ECAP_REG 0x10 +#define IR BIT3 +#define R_SA_MCHBAR 0x48 + +// +// VT-d Engine base address. +// +#define R_SA_MCHBAR_VTD1_OFFSET 0x6C88 ///< DMA Remapping HW UNIT1 for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x6C80 ///< DMA Remapping HW UNIT2 for all other - PEG, USB, SATA etc + +#define SA_VTD_ENGINE_NUMBER 2 + +/** + Configure VT-d Base and capabilities. + + @param[in] ScPolicyPpi The SC Policy PPI instance + + @retval EFI_SUCCESS VT-d initialization complete + @retval EFI_UNSUPPORTED VT-d is disabled by policy or not supported + +**/ +EFI_STATUS +VtdInit ( + IN SC_POLICY_PPI *ScPolicyPpi + ); +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h new file mode 100644 index 0000000000..2a2d4ac8dc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScInfoLib.h @@ -0,0 +1,52 @@ +/** @file + Header file for PchInfoLib. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include + +typedef enum { + PchH = 1, + PchLp, + PchUnknownSeries +} PCH_SERIES; + +/** + Return Pch Series. + + @retval PCH_SERIES Pch Series + +**/ +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number. + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number + +**/ +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ); + +#endif // _PCH_INFO_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h new file mode 100644 index 0000000000..a192e27276 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPcrLib.h @@ -0,0 +1,208 @@ +/** @file + Header file for PchPcrLib. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +#endif // _PCH_PCR_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h new file mode 100644 index 0000000000..896cb05ca5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScPlatformLib.h @@ -0,0 +1,805 @@ +/** @file + Header file for ScPlatform Lib. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PLATFORM_LIB_H_ +#define _SC_PLATFORM_LIB_H_ + +#include +#include + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCIE_CONTROLLER_INFO; + +/** + Get Sc Maximum Pcie Root Port Number. + + @retval UINT8 Sc Maximum Pcie Root Port Number + +**/ +UINT8 +EFIAPI +GetScMaxPciePortNum ( + VOID + ); + +/** + Delay for at least the request number of microseconds. + This function would be called by runtime driver, please do not use any MMIO marco here. + + @param[in] Microseconds Number of microseconds to delay. + +**/ +VOID +EFIAPI +ScPmTimerStall ( + IN UINTN Microseconds + ); + +/** + Check whether SPI is in descriptor mode. + + @param[in] SpiBase The SC SPI Base Address + + @retval TRUE SPI is in descriptor mode + @retval FALSE SPI is not in descriptor mode + +**/ +BOOLEAN +EFIAPI +ScIsSpiDescriptorMode ( + IN UINTN SpiBase + ); + +/** + Determine if SC is supported. + + @retval TRUE SC is supported + @retval FALSE SC is not supported + +**/ +BOOLEAN +IsScSupported ( + VOID + ); + +/** + This function can be called to poll for certain value within a time given. + + @param[in] MmioAddress The Mmio Address. + @param[in] BitMask Bits to be masked. + @param[in] BitValue Value to be polled. + @param[in] DelayTime Delay time in terms of 100 micro seconds. + + @retval EFI_SUCCESS Successfully polled the value. + @retval EFI_TIMEOUT Timeout while polling the value. + +**/ +EFI_STATUS +EFIAPI +ScMmioPoll32 ( + IN UINTN MmioAddress, + IN UINT32 BitMask, + IN UINT32 BitValue, + IN UINT16 DelayTime + ); + +/** + Get SC Pcie Root Port Device and Function Number by Root Port physical Number. + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid + +**/ +EFI_STATUS +EFIAPI +GetScPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Root Port physical Number by SC Pcie Root Port Device and Function Number. + + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding Root port physical number. + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port + +**/ +EFI_STATUS +EFIAPI +GetScPcieRpNumber ( + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ); + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ); + +/** + Reads an 4-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 4-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads an 2-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 2-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads an 1-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 1-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controller. + + @retval EFI_SUCCESS Always return success. + +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ); + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not after. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controller. + @param[out] OrgStatus Original P2SB hidding/unhidden status + + @retval EFI_SUCCESS Always return success. + +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ); + +// +// implemented in PchSbiAccess.c +// + +/** + PCH SBI Register structure + +**/ +typedef struct { + UINT32 SbiAddr; + UINT32 SbiExtAddr; + UINT32 SbiData; + UINT16 SbiStat; + UINT16 SbiRid; +} PCH_SBI_REGISTER_STRUCT; + +/** + PCH SBI opcode definitions + +**/ +typedef enum { + MemoryRead = 0x0, + MemoryWrite = 0x1, + PciConfigRead = 0x4, + PciConfigWrite = 0x5, + PrivateControlRead = 0x6, + PrivateControlWrite = 0x7, + GpioLockUnlock = 0x13 +} PCH_SBI_OPCODE; + +/** + PCH SBI response status definitions + +**/ +typedef enum { + SBI_SUCCESSFUL = 0, + SBI_UNSUCCESSFUL = 1, + SBI_POWERDOWN = 2, + SBI_MIXED = 3, + SBI_INVALID_RESPONSE +} PCH_SBI_RESPONSE; + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN SC_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN SC_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. + +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. + +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +// +// implemented in PchCycleDecoding.c +// +// +// structure of LPC general IO range register +// It contains base address, address mask, and enable status. +// +typedef struct { + UINT32 BaseAddr :16; + UINT32 Length :15; + UINT32 Enable : 1; +} PCH_LPC_GEN_IO_RANGE; + +#define PCH_LPC_GEN_IO_RANGE_MAX 4 + +// +// structure of LPC general IO range register list +// It lists all LPC general IO ran registers supported by PCH. +// +typedef struct { + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX]; +} PCH_LPC_GEN_IO_RANGE_LIST; + +/** + Set PCH LPC generic IO range. + For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length aligned. + This function basically checks the address and length, which should not overlap with all other generic ranges. + If no more generic range register available, it returns out of resource error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ); + +/** + Get PCH LPC generic IO range list. + This function returns a list of base address, length, and enable for all LPC generic IO range regsiters. + + @param[in] LpcGenIoRangeList Return all LPC generic IO range register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + IN PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + ); + +/** + Set PCH LPC memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first before changing base address. + 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + ); + +/** + Get PCH LPC memory range decoding address. + + @param[in] Address Address of LPC memory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + IN UINT32 *Address + ); + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable. + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC IO enable decoding. + Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ); + +/** + Enable VTd support in PSF. + + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +PchPsfEnableVtd ( + VOID + ); + +/** + Get Sc Maximum Usb2 Port Number of XHCI Controller. + + @retval UINT8 Sc Maximum Usb2 Port Number of XHCI Controller + +**/ +UINT8 +EFIAPI +GetScXhciMaxUsb2PortNum ( + VOID + ); + +/** + Get Sc Maximum Usb3 Port Number of XHCI Controller. + + @retval UINT8 Sc Maximum Usb3 Port Number of XHCI Controller + +**/ +UINT8 +EFIAPI +GetScXhciMaxUsb3PortNum ( + VOID + ); + +/** + Get SPI linear Base address of descriptor region section. + + @param[in] RegNum FLREG number of region section defined in the descriptor + + @retval UINT32 Base address of the FLREG + +**/ +UINT32 +GetSpiFlashRegionBase ( + IN UINTN RegNum + ); + +/** + return SPI linear Base address of descriptor region section. + + @param[in] RegNum FLREG number of region section defined in the descriptor + + @retval UINTN Base address of the FLREG + +**/ +UINT32 +GetSpiFlashRegionLimit ( + UINTN RegNum + ); + +typedef enum { + PcieP1, + PcieP2, + PcieP3, + PcieP4, + PcieP5, + PcieP6, + SataP0, + SataP1, + UsbP0, + UsbP1, + UsbP2, + UsbP3, + UsbP4, + UsbP5, + UsbP6, + UsbP7 +} SC_DEVICE_PORT; + + +/** + Set TCO base address for legacy Smbus. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +SetTcoBase ( + IN UINT16 Address + ); + +/** + Get TCO base address. + + @param[in] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. + +**/ +EFI_STATUS +EFIAPI +GetTcoBase ( + IN UINT16 *Address + ); +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h new file mode 100644 index 0000000000..df6f4f5ba7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoLib.h @@ -0,0 +1,174 @@ +/** @file + Header file for PCH Serial IO Lib implementation. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SERIAL_IO_LIB_H_ +#define _PCH_SERIAL_IO_LIB_H_ + +typedef enum { + PchSerialIoIndexUart0, + PchSerialIoIndexUart1, + PchSerialIoIndexUart2, + PchSerialIoIndexUart3, + PchSerialIoIndexMax +} PCH_SERIAL_IO_CONTROLLER; + +typedef enum { + PchSerialIoDisabled, + PchSerialIoAcpi, + PchSerialIoPci, + PchSerialIoAcpiHidden, + PchSerialIoLegacyUart +} PCH_SERIAL_IO_MODE; + +enum PCH_LP_SERIAL_IO_VOLTAGE_SEL { + PchSerialIoIs33V = 0, + PchSerialIoIs18V +}; +enum PCH_LP_SERIAL_IO_CS_POLARITY { + PchSerialIoCsActiveLow = 0, + PchSerialIoCsActiveHigh = 1 +}; +enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL { + PchSerialIoHwFlowCtrlDisabled = 0, + PchSerialIoHwFlowControlEnabled = 1 +}; + +#define SERIALIO_HID_LENGTH 8 // including null terminator +#define SERIALIO_UID_LENGTH 1 +#define SERIALIO_CID_LENGTH 1 +#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH + +/** + Returns index of the last i2c controller. + + @retval Value Index of I2C controller + +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + VOID + ); + +/** + Configures Serial IO Controller. + + @param[in] Controller 0=I2C0, ..., 11=UART2 + @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE + @param[in] SerialIoSafeRegister D0i3 Max Power On Latency and Device PG config + +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode +#ifdef PCH_PO_FLAG + , IN UINT32 SerialIoSafeRegister +#endif + ); + +#if 0 +/** + Initializes GPIO pins used by SerialIo I2C devices. + + @param[in] Controller 0=I2C0, ..., 11=UART2 + @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE + @param[in] I2cVoltage Select I2C voltage, 1.8V or 3.3V + +**/ +VOID +SerialIoI2cGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 I2cVoltage + ); + +/** + Initializes GPIO pins used by SerialIo SPI devices. + + @param[in] Controller 0=I2C0, ..., 11=UART2 + @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE + @param[in] SpiCsPolarity SPI CS polarity + +**/ +VOID +SerialIoSpiGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 SpiCsPolarity + ); + +/** + Initializes GPIO pins used by SerialIo devices. + + @param[in] Controller 0=I2C0, ..., 11=UART2 + @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE + @param[in] HardwareFlowControl Hardware flow control method + +**/ +VOID +SerialIoUartGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN HardwareFlowControl + ); +#endif + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable. + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + + @retval UINT8 SerialIo device number + +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable. + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + + @retval UINT8 SerialIo funciton number + +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work. + If the SerialIo device is in PCI mode, a request for BAR1 will return its PCI CFG space instead. + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + @param[in] BarNumber 0=BAR0, 1=BAR1 + + @retval UINTN SerialIo Bar value + +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ); + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h new file mode 100644 index 0000000000..68c04695ac --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/ScSerialIoUartLib.h @@ -0,0 +1,106 @@ +/** @file + Header file for PCH Serial IO UART Lib implementation. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SERIAL_IO_UART_LIB_H_ +#define _PCH_SERIAL_IO_UART_LIB_H_ + +/** + Initialize selected SerialIo UART. + This init function MUST be used prior any SerialIo UART functions to init serial io controller if platform is going use serialio UART as debug output. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] FifoEnable When TRUE, enables 64-byte FIFOs. + @param[in] BaudRate Baud rate. + @param[in] LineControl Data length, parity, stop bits. + @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data. + + @retval BOOLEAN Initilization succeeded. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartInit ( + IN UINT8 UartNumber, + IN BOOLEAN FifoEnable, + IN UINT32 BaudRate, + IN UINT8 LineControl, + IN BOOLEAN HardwareFlowControl + ); + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval UINTN Actual number of bytes writed to serial device. + +**/ +UINTN +EFIAPI +PchSerialIoUartOut ( + IN UINT8 UartNumber, + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + +/** + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[out] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, + function returns as soon as no new characters are available. + + @retval UINTN Actual number of bytes raed to serial device. + +**/ +UINTN +EFIAPI +PchSerialIoUartIn ( + IN UINT8 UartNumber, + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes, + IN BOOLEAN WaitUntilBufferFull + ); + +/** + Polls a serial device to see if there is any data waiting to be read. + + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartPoll ( + IN UINT8 UartNumber + ); + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MMC.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MMC.h new file mode 100644 index 0000000000..8ab8f1315f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MMC.h @@ -0,0 +1,272 @@ +/** @file + Header file for Industry MMC 4.2 spec. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MMC_H +#define _MMC_H + +#pragma pack(1) + +// +// Command definition +// +#define CMD0 0 +#define CMD1 1 +#define CMD2 2 +#define CMD3 3 +#define CMD4 4 +#define CMD6 6 +#define CMD7 7 +#define CMD8 8 +#define CMD9 9 +#define CMD10 10 +#define CMD11 11 +#define CMD12 12 +#define CMD13 13 +#define CMD14 14 +#define CMD15 15 +#define CMD16 16 +#define CMD17 17 +#define CMD18 18 +#define CMD19 19 +#define CMD20 20 +#define CMD23 23 +#define CMD24 24 +#define CMD25 25 +#define CMD26 26 +#define CMD27 27 +#define CMD28 28 +#define CMD29 29 +#define CMD30 30 +#define CMD35 35 +#define CMD36 36 +#define CMD38 38 +#define CMD39 39 +#define CMD40 40 +#define CMD42 42 +#define CMD55 55 +#define CMD56 56 + +#define GO_IDLE_STATE CMD0 +#define SEND_OP_COND CMD1 +#define ALL_SEND_CID CMD2 +#define SET_RELATIVE_ADDR CMD3 +#define SET_DSR CMD4 +#define SWITCH CMD6 +#define SELECT_DESELECT_CARD CMD7 +#define SEND_EXT_CSD CMD8 +#define SEND_CSD CMD9 +#define SEND_CID CMD10 +#define READ_DAT_UNTIL_STOP CMD11 +#define STOP_TRANSMISSION CMD12 +#define SEND_STATUS CMD13 +#define BUSTEST_R CMD14 +#define GO_INACTIVE_STATE CMD15 +#define SET_BLOCKLEN CMD16 +#define READ_SINGLE_BLOCK CMD17 +#define READ_MULTIPLE_BLOCK CMD18 +#define BUSTEST_W CMD19 +#define WRITE_DAT_UNTIL_STOP CMD20 +#define SET_BLOCK_COUNT CMD23 +#define WRITE_BLOCK CMD24 +#define WRITE_MULTIPLE_BLOCK CMD25 +#define PROGRAM_CID CMD26 +#define PROGRAM_CSD CMD27 +#define SET_WRITE_PROT CMD28 +#define CLR_WRITE_PROT CMD29 +#define SEND_WRITE_PROT CMD30 +#define ERASE_GROUP_START CMD35 +#define ERASE_GROUP_END CMD36 +#define ERASE CMD38 +#define FAST_IO CMD39 +#define GO_IRQ_STATE CMD40 +#define LOCK_UNLOCK CMD42 +#define APP_CMD CMD55 +#define GEN_CMD CMD56 + +#define CMD_INDEX_MASK 0x3F +#define AUTO_CMD12_ENABLE BIT6 +#define AUTO_CMD23_ENABLE BIT7 + +#define FREQUENCY_OD (400 * 1000) +#define FREQUENCY_MMC_PP (26 * 1000 * 1000) +#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000) + +#define DEFAULT_DSR_VALUE 0x404 + +// +// Registers definition +// + +typedef struct { + UINT32 Reserved0: 7; // 0 + UINT32 V170_V195: 1; // 1.70V - 1.95V + UINT32 V200_V260: 7; // 2.00V - 2.60V + UINT32 V270_V360: 9; // 2.70V - 3.60V + UINT32 Reserved1: 5; // 0 + UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) + UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine +} OCR; + +typedef struct { + UINT8 NotUsed: 1; // 1 + UINT8 CRC: 7; // CRC7 checksum + UINT8 MDT; // Manufacturing date + UINT32 PSN; // Product serial number + UINT8 PRV; // Product revision + UINT8 PNM[6]; // Product name + UINT16 OID; // OEM/Application ID + UINT8 MID; // Manufacturer ID +} CID; + +typedef struct { + UINT8 NotUsed: 1; // 1 [0:0] + UINT8 CRC: 7; // CRC [7:1] + UINT8 ECC: 2; // ECC code [9:8] + UINT8 FILE_FORMAT: 2; // File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] + UINT8 COPY: 1; // Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] + UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16] + UINT16 Reserved0: 4; // 0 [20:17] + UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] + UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32] + UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37] + UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42] + UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47] + UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50] + UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53] + UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56] + UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59] + UINT32 C_SIZELow2: 2;// Device size [73:62] + UINT32 C_SIZEHigh10: 10;// Device size [73:62] + UINT32 Reserved1: 2; // 0 [75:74] + UINT32 DSR_IMP: 1; // DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] + UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] + UINT32 CCC: 12;// Card command classes [95:84] + UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] + UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; // Data read access-time 1 [119:112] + UINT8 Reserved2: 2; // 0 [121:120] + UINT8 SPEC_VERS: 4; // System specification version [125:122] + UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] +} CSD; + +typedef struct { + UINT8 Reserved0[181]; // 0 [0:180] + UINT8 ERASED_MEM_CONT; // Erased Memory Content [181] + UINT8 Reserved2; // Erased Memory Content [182] + UINT8 BUS_WIDTH; // Bus Width Mode [183] + UINT8 Reserved3; // 0 [184] + UINT8 HS_TIMING; // High Speed Interface Timing [185] + UINT8 Reserved4; // 0 [186] + UINT8 POWER_CLASS; // Power Class [187] + UINT8 Reserved5; // 0 [188] + UINT8 CMD_SET_REV; // Command Set Revision [189] + UINT8 Reserved6; // 0 [190] + UINT8 CMD_SET; // Command Set [191] + UINT8 EXT_CSD_REV; // Extended CSD Revision [192] + UINT8 Reserved7; // 0 [193] + UINT8 CSD_STRUCTURE; // CSD Structure Version [194] + UINT8 Reserved8; // 0 [195] + UINT8 CARD_TYPE; // Card Type [196] + UINT8 Reserved9[3]; // 0 [199:197] + UINT8 PWR_CL_52_195; // Power Class for 52MHz @ 1.95V [200] + UINT8 PWR_CL_26_195; // Power Class for 26MHz @ 1.95V [201] + UINT8 PWR_CL_52_360; // Power Class for 52MHz @ 3.6V [202] + UINT8 PWR_CL_26_360; // Power Class for 26MHz @ 3.6V [203] + UINT8 Reserved10; // 0 [204] + UINT8 MIN_PERF_R_4_26; // Minimum Read Performance for 4bit @26MHz [205] + UINT8 MIN_PERF_W_4_26; // Minimum Write Performance for 4bit @26MHz [206] + UINT8 MIN_PERF_R_8_26_4_52; // Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207] + UINT8 MIN_PERF_W_8_26_4_52; // Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208] + UINT8 MIN_PERF_R_8_52; // Minimum Read Performance for 8bit @52MHz [209] + UINT8 MIN_PERF_W_8_52; // Minimum Write Performance for 8bit @52MHz [210] + UINT8 Reserved11; // 0 [211] + UINT8 SEC_COUNT[4]; // Sector Count [215:212] + UINT8 Reserved12[288]; // 0 [503:216] + UINT8 S_CMD_SET; // Sector Count [504] + UINT8 Reserved13[7]; // Sector Count [511:505] +} EXT_CSD; + +// +// Card Status definition +// +typedef struct { + UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode + UINT32 Reserved1: 2; //Reserved for Application Specific commands + UINT32 Reserved2: 1; // + UINT32 SAPP_CMD: 1; // + UINT32 Reserved3: 1; //Reserved + UINT32 SWITCH_ERROR: 1; // + UINT32 READY_FOR_DATA: 1; // + UINT32 CURRENT_STATE: 4; // + UINT32 ERASE_RESET: 1; // + UINT32 Reserved4: 1; //Reserved + UINT32 WP_ERASE_SKIP: 1; // + UINT32 CID_CSD_OVERWRITE: 1; // + UINT32 OVERRUN: 1; // + UINT32 UNDERRUN: 1; // + UINT32 ERROR: 1; // + UINT32 CC_ERROR: 1; // + UINT32 CARD_ECC_FAILED: 1; // + UINT32 ILLEGAL_COMMAND: 1; // + UINT32 COM_CRC_ERROR: 1; // + UINT32 LOCK_UNLOCK_FAILED: 1; // + UINT32 CARD_IS_LOCKED: 1; // + UINT32 WP_VIOLATION: 1; // + UINT32 ERASE_PARAM: 1; // + UINT32 ERASE_SEQ_ERROR: 1; // + UINT32 BLOCK_LEN_ERROR: 1; // + UINT32 ADDRESS_MISALIGN: 1; // + UINT32 ADDRESS_OUT_OF_RANGE:1; // +} CARD_STATUS; + +typedef struct { + UINT32 CmdSet: 3; + UINT32 Reserved0: 5; + UINT32 Value: 8; + UINT32 Index: 8; + UINT32 Access: 2; + UINT32 Reserved1: 6; +} SWITCH_ARGUMENT; + +#define CommandSet_Mode 0 +#define SetBits_Mode 1 +#define ClearBits_Mode 2 +#define WriteByte_Mode 3 + +#define Idle_STATE 0 +#define Ready_STATE 1 +#define Ident_STATE 2 +#define Stby_STATE 3 +#define Tran_STATE 4 +#define Data_STATE 5 +#define Rcv_STATE 6 +#define Prg_STATE 7 +#define Dis_STATE 8 +#define Btst_STATE 9 + +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MediaDeviceDriver.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MediaDeviceDriver.h new file mode 100644 index 0000000000..243ee9adbd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/MediaDeviceDriver.h @@ -0,0 +1,632 @@ +/** @file + Media Device Driver header. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MEDIA_DEVICE_DRIVER_H +#define _MEDIA_DEVICE_DRIVER_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Driver Consumed Protocol Prototypes +// +#include +#include + +// +// Driver Produced Protocol Prototypes +// +#include +#include +#include +#include + +extern EFI_COMPONENT_NAME_PROTOCOL gMediaDeviceComponentName; +extern EFI_DRIVER_BINDING_PROTOCOL gMediaDeviceDriverBinding; +extern EFI_COMPONENT_NAME2_PROTOCOL gMmcMediaDeviceName2; + +extern UINT32 gMediaDeviceDebugLevel; + +extern EFI_GUID gEfiEmmcBootPartitionProtocolGuid; + +#define CARD_DATA_SIGNATURE SIGNATURE_32 ('c', 'a', 'r', 'd') +#define CARD_PARTITION_SIGNATURE SIGNATURE_32 ('c', 'p', 'a', 'r') + +#define CARD_PARTITION_DATA_FROM_THIS(a) \ + CR(a, MMC_PARTITION_DATA, BlockIo, CARD_PARTITION_SIGNATURE) + +#define CARD_DATA_FROM_THIS(a) \ + ((CARD_PARTITION_DATA_FROM_THIS(a))->CardData) + +#define CARD_DATA_PARTITION_NUM(p) \ + ((((UINTN) p) - ((UINTN) &(p->CardData->Partitions))) / sizeof (*p)) + +// +// Partition Number +// +#define NO_ACCESS_TO_BOOT_PARTITION 0x00 +#define BOOT_PARTITION_1 0x01 +#define BOOT_PARTITION_2 0x02 +#define REPLAY_PROTECTED_MEMORY_BLOCK 0x03 +#define GENERAL_PURPOSE_PARTITION_1 0x04 +#define GENERAL_PURPOSE_PARTITION_2 0x05 +#define GENERAL_PURPOSE_PARTITION_3 0x06 +#define GENERAL_PURPOSE_PARTITION_4 0x07 +// +// Command timeout will be max 100 ms +// +#define TIMEOUT_COMMAND 100 +#define TIMEOUT_DATA 5000 + +typedef enum { + UnknownCard = 0, + MMCCard, ///< MMC card + CEATACard, ///< CE-ATA device + SdMemoryCard, ///< SD 1.1 card + SdMemoryCard2, ///< SD 2.0 or above standard card + SdMemoryCard2High ///< SD 2.0 or above high capacity card +} CARD_TYPE; + +typedef struct _CARD_DATA CARD_DATA; + +typedef struct { + // + // BlockIO + // + UINT32 Signature; + EFI_HANDLE Handle; + BOOLEAN Present; + EFI_DEVICE_PATH_PROTOCOL *DevPath; + EFI_BLOCK_IO_PROTOCOL BlockIo; + EFI_BLOCK_IO_MEDIA BlockIoMedia; + CARD_DATA *CardData; +} MMC_PARTITION_DATA; + +#define MAX_NUMBER_OF_PARTITIONS 8 + +struct _CARD_DATA { + // + // BlockIO + // + UINT32 Signature; + EFI_HANDLE Handle; + MMC_PARTITION_DATA Partitions[MAX_NUMBER_OF_PARTITIONS]; + EFI_MMC_HOST_IO_PROTOCOL *MmcHostIo; + EFI_UNICODE_STRING_TABLE *ControllerNameTable; + CARD_TYPE CardType; + UINT8 CurrentBusWidth; + BOOLEAN DualVoltage; + BOOLEAN NeedFlush; + UINT8 Reserved[3]; + UINT16 Address; + UINT32 BlockLen; + UINT32 MaxFrequency; + UINT64 BlockNumber; + // + // Common used + // + CARD_STATUS CardStatus; + OCR OCRRegister; + CID CIDRegister; + CSD CSDRegister; + EXT_CSD ExtCSDRegister; + UINT8 *RawBufferPointer; + UINT8 *AlignedBuffer; + // + // CE-ATA specific + // + TASK_FILE TaskFile; + IDENTIFY_DEVICE_DATA IndentifyDeviceData; + // + // SD specific + // + SCR SCRRegister; + SD_STATUS_REG SdSattus; + SWITCH_STATUS SwitchStatus; +}; + +/** + MediaDeviceDriverEntryPoint + + @param[in] ImageHandle + @param[in] SystemTable + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + MediaDeviceDriverInstallBlockIo + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +MediaDeviceDriverInstallBlockIo ( + IN CARD_DATA *CardData + ); + +/** + MediaDeviceDriverUninstallBlockIo + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +MediaDeviceDriverUninstallBlockIo ( + IN CARD_DATA *CardData + ); + +/** + MediaDeviceComponentNameGetDriverName + + @param[in] This + @param[in] Language + @param[out] DriverName + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceComponentNameGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +/** + MediaDeviceComponentNameGetControllerName + + @param[in] This + @param[in] ControllerHandle + @param[in] ChildHandle + @param[in] Language + @param[out] ControllerName + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceComponentNameGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle, OPTIONAL + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/** + MediaDeviceDriverBindingSupported + + @param[in] This + @param[in] Controller + @param[in] RemainingDevicePath + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + MediaDeviceDriverBindingStart + + @param[in] This + @param[in] Controller + @param[in] RemainingDevicePath + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + MediaDeviceDriverBindingStop + + @param[in] This + @param[in] Controller + @param[in] NumberOfChildren + @param[in] ChildHandleBuffer + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +MediaDeviceDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ); + +/** + MMCSDCardInit + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +MMCSDCardInit ( + IN CARD_DATA *CardData + ); + +/** + MMCSDBlockIoInit + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +MMCSDBlockIoInit ( + IN CARD_DATA *CardData + ); + +/** + SendCommand + + @param[in] This + @param[in] CommandIndex + @param[in] Argument + @param[in] DataType + @param[in] Buffer + @param[in] BufferSize + @param[in] ResponseType + @param[in] TimeOut + @param[out] ResponseData + + @retval EFI_STATUS + +**/ +EFI_STATUS +SendCommand ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData + ); + +/** + FastIO + + @param[in] CardData + @param[in] RegisterAddress + @param[in, out] RegisterData + @param[in] Write + + @retval EFI_STATUS + +**/ +EFI_STATUS +FastIO ( + IN CARD_DATA *CardData, + IN UINT8 RegisterAddress, + IN OUT UINT8 *RegisterData, + IN BOOLEAN Write + ); + +/** + IsCEATADevice + + @param[in] CardData + + @retval EFI_STATUS + +**/ +BOOLEAN +IsCEATADevice ( + IN CARD_DATA *CardData + ); + +/** + CEATABlockIoInit + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +CEATABlockIoInit ( + IN CARD_DATA *CardData + ); + +/** + IndentifyDevice + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +IndentifyDevice ( + IN CARD_DATA *CardData + ); + +/** + FlushCache + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +FlushCache ( + IN CARD_DATA *CardData + ); + +/** + StandByImmediate + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +StandByImmediate ( + IN CARD_DATA *CardData + ); + +/** + ReadDMAExt + + @param[in] CardData + @param[in] LBA + @param[in] Buffer + @param[in] SectorCount + + @retval EFI_STATUS + +**/ +EFI_STATUS +ReadDMAExt ( + IN CARD_DATA *CardData, + IN EFI_LBA LBA, + IN UINT8 *Buffer, + IN UINT16 SectorCount + ); + +/** + WriteDMAExt + + @param[in] CardData + @param[in] LBA + @param[in] Buffer + @param[in] SectorCount + + @retval EFI_STATUS + +**/ +EFI_STATUS +WriteDMAExt ( + IN CARD_DATA *CardData, + IN EFI_LBA LBA, + IN UINT8 *Buffer, + IN UINT16 SectorCount + ); + +/** + SoftwareReset + + @param[in] CardData + + @retval EFI_STATUS + +**/ +EFI_STATUS +SoftwareReset ( + IN CARD_DATA *CardData + ); + +/** + SendAppCommand + + @param[in] CardData + @param[in] CommandIndex + @param[in] Argument + @param[in] DataType + @param[in] Buffer + @param[in] BufferSize + @param[in] ResponseType + @param[in] TimeOut + @param[out] ResponseData + + @retval EFI_STATUS + +**/ +EFI_STATUS +SendAppCommand ( + IN CARD_DATA *CardData, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData + ); + +/** + MmcGetExtCsd8 + + @param[in] CardData + @param[in] Offset + + @retval UINT32 + +**/ +UINT32 +MmcGetExtCsd8 ( + IN CARD_DATA *CardData, + IN UINTN Offset + ); + +/** + MmcGetExtCsd24 + + @param[in] CardData + @param[in] Offset + + @retval UINT32 + +**/ +UINT32 +MmcGetExtCsd24 ( + IN CARD_DATA *CardData, + IN UINTN Offset + ); + +/** + MmcGetExtCsd32 + + @param[in] CardData + @param[in] Offset + + @retval UINT32 + +**/ +UINT32 +MmcGetExtCsd32 ( + IN CARD_DATA *CardData, + IN UINTN Offset + ); + +/** + MmcGetCurrentPartitionNum + + @param[in] CardData + + @retval UINTN + +**/ +UINTN +MmcGetCurrentPartitionNum ( + IN CARD_DATA *CardData + ); + +/** + SetEmmcWpOnEvent + + @param[in] Event + @param[in] Context + + @retval None + +**/ +VOID +EFIAPI +SetEmmcWpOnEvent( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + MmcSelectPartitionNum + + @param[in] CardData + @param[in] Partition + + @retval EFI_STATUS + +**/ +EFI_STATUS +MmcSelectPartitionNum ( + IN CARD_DATA *CardData, + IN UINT8 Partition + ); + +/** + MmcSelectPartition + + @param[in] Partition + + @retval EFI_STATUS + +**/ +EFI_STATUS +MmcSelectPartition ( + IN MMC_PARTITION_DATA *Partition + ); + +/** + MmcSetPartition + + @param[in] CardData + @param[in] Value + + @retval EFI_STATUS + +**/ +EFI_STATUS +MmcSetPartition ( + IN CARD_DATA *CardData, + IN UINT8 Value + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/BlockIoPei.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/BlockIoPei.h new file mode 100644 index 0000000000..74f0908989 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/BlockIoPei.h @@ -0,0 +1,275 @@ +/** @file + Provides the override services required to access a block I/O device during PEI recovery + boot mode. + + The Recovery Module PPI and the Device Recovery Module PPI are device neutral. + This PPI is device specific and addresses the most common form of recovery + media-block I/O devices such as legacy floppy, CD-ROM, or IDE devices. + + The Recovery Block I/O PPI is used to access block devices. Because the Recovery + Block I/O PPIs that are provided by the PEI ATAPI driver and PEI legacy floppy + driver are the same, here we define a set of general PPIs for both drivers to use. + + Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BLOCK_IO_PEI_H_ +#define _BLOCK_IO_PEI_H_ + +// +// Global ID for EFI_PEI_RECOVERY_BLOCK_IO_PPI +// +#define EFI_PEI_RECOVERY_BLOCK_IO_PPI_GUID \ + { \ + 0x695d8aa1, 0x42ee, 0x4c46, { 0x80, 0x5c, 0x6e, 0xa6, 0xbc, 0xe7, 0x99, 0xe3 } \ + } + +// +// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI. +// +typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI; + +// +// All blocks on the recovery device are addressed with a 64-bit Logical Block Address (LBA). +// +typedef UINT64 EFI_PEI_LBA; + +// +// EFI_PEI_BLOCK_DEVICE_TYPE +// +typedef enum { + LegacyFloppy = 0, ///< The recovery device is a floppy. + IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM + IdeLS120 = 2, ///< The recovery device is an IDE LS-120 + UsbMassStorage= 3, ///< The recovery device is a USB Mass Storage device + eMMCDevice = 4, ///< The recovery device is a eMMC device + UfsDevice = 5, ///< The recovery device is a UFS device + MaxDeviceType +} EFI_PEI_BLOCK_DEVICE_TYPE; + +typedef struct { + // + // The type of media device being referenced by DeviceIndex. + // + EFI_PEI_BLOCK_DEVICE_TYPE DeviceType; + // + // A flag that indicates if media is present. This flag is always set for + // nonremovable media devices. + // + BOOLEAN MediaPresent; + // + // The last logical block that the device supports. + // + UINTN LastBlock; + // + // The size of a logical block in bytes. + // + UINTN BlockSize; +} EFI_PEI_BLOCK_IO_MEDIA; + +/** + Gets the count of block I/O devices that one specific block driver detects. + + This function is used for getting the count of block I/O devices that one + specific block driver detects. To the PEI ATAPI driver, it returns the number + of all the detected ATAPI devices it detects during the enumeration process. + To the PEI legacy floppy driver, it returns the number of all the legacy + devices it finds during its enumeration process. If no device is detected, + then the function will return zero. + + @param[in] PeiServices General-purpose services that are available + to every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI + instance. + @param[out] NumberBlockDevices The number of block I/O devices discovered. + + @retval EFI_SUCCESS The operation performed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + OUT UINTN *NumberBlockDevices + ); + +/** + Gets a block device's media information. + + This function will provide the caller with the specified block device's media + information. If the media changes, calling this function will update the media + information accordingly. + + @param[in] PeiServices General-purpose services that are available to every + PEIM + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, the PPIs that + want to talk to a single device must specify the + device index that was assigned during the enumeration + process. This index is a number from one to + NumberBlockDevices. + @param[out] MediaInfo The media information of the specified block media. + The caller is responsible for the ownership of this + data structure. + + @par Note: + The MediaInfo structure describes an enumeration of possible block device + types. This enumeration exists because no device paths are actually passed + across interfaces that describe the type or class of hardware that is publishing + the block I/O interface. This enumeration will allow for policy decisions + in the Recovery PEIM, such as "Try to recover from legacy floppy first, + LS-120 second, CD-ROM third." If there are multiple partitions abstracted + by a given device type, they should be reported in ascending order; this + order also applies to nested partitions, such as legacy MBR, where the + outermost partitions would have precedence in the reporting order. The + same logic applies to systems such as IDE that have precedence relationships + like "Master/Slave" or "Primary/Secondary". The master device should be + reported first, the slave second. + + @retval EFI_SUCCESS Media information about the specified block device + was obtained successfully. + @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + IN UINTN DeviceIndex, + OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo + ); + +/** + Reads the requested number of blocks from the specified block device. + + The function reads the requested number of blocks from the device. All the + blocks are read, or an error is returned. If there is no media in the device, + the function returns EFI_NO_MEDIA. + + @param[in] PeiServices General-purpose services that are available to + every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, PPIs that + want to talk to a single device must specify the device + index that was assigned during the enumeration process. + This index is a number from one to NumberBlockDevices. + @param[in] StartLBA The starting logical block address (LBA) to read from + on the device + @param[in] BufferSize The size of the Buffer in bytes. This number must be + a multiple of the intrinsic block size of the device. + @param[out] Buffer A pointer to the destination buffer for the data. + The caller is responsible for the ownership of the + buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting + to perform the read operation. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not + valid, or the buffer is not properly aligned. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of + the intrinsic block size of the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_READ_BLOCKS)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + IN UINTN DeviceIndex, + IN EFI_PEI_LBA StartLBA, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + + /** + Write the requested number of blocks to the specified block device. + + The function writes the requested number of blocks to the device. All the + blocks are written, or an error is returned. If there is no media in the device, + the function returns EFI_NO_MEDIA. + + @param[in] PeiServices General-purpose services that are available to + every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, PPIs that + want to talk to a single device must specify the device + index that was assigned during the enumeration process. + This index is a number from one to NumberBlockDevices. + @param[in] StartLBA The starting logical block address (LBA) to write to + on the device + @param[in] BufferSize The size of the Buffer in bytes. This number must be + a multiple of the intrinsic block size of the device. + @param[in] Buffer A pointer to the destination buffer for the data. + The caller is responsible for the ownership of the + buffer. + + @retval EFI_SUCCESS The data was written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting + to perform the write operation. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not + valid, or the buffer is not properly aligned. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of + the intrinsic block size of the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_WRITE_BLOCKS)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + IN UINTN DeviceIndex, + IN EFI_PEI_LBA StartLBA, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +// +// EFI_PEI_RECOVERY_BLOCK_IO_PPI provides the services that are required +// to access a block I/O device during PEI recovery boot mode. +// +struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI { + // + // Gets the number of block I/O devices that the specific block driver manages. + // + EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices; + + // + // Gets the specified media information. + // + EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo; + + // + // Reads the requested number of blocks from the specified block device. + // + EFI_PEI_READ_BLOCKS ReadBlocks; + + // + // Writes the requested number of blocks to the specified block device. + // + EFI_PEI_WRITE_BLOCKS WriteBlocks; +}; + +extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/PeiBlockIo.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/PeiBlockIo.h new file mode 100644 index 0000000000..8e2cfd599b --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/PeiBlockIo.h @@ -0,0 +1,236 @@ +/** @file + Block IO protocol as defined in the UEFI 2.0 specification. + + The Block IO protocol is used to abstract block devices like hard drives, + DVD-ROMs and floppy drives + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PEI_BLOCK_IO_H__ +#define __PEI_BLOCK_IO_H__ + +#define PEI_BLOCK_IO_PPI_GUID \ + { \ + 0xbc5fa650, 0xedbb, 0x4d0d, { 0xb3, 0xa3, 0xd9, 0x89, 0x7, 0xf8, 0x47, 0xdf } \ + } + +typedef struct _PEI_BLOCK_IO_PPI PEI_BLOCK_IO_PPI; + + +/** + Reset the Block Device. + + @param[in] This Indicates a pointer to the calling context. + @param[in] ExtendedVerification Driver may perform diagnostics on reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning properly and could + not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_RESET)( + IN PEI_BLOCK_IO_PPI *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Read BufferSize bytes from Lba into Buffer. + + @param[in] PeiServices + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId Id of the media, changes every time the media is replaced. + @param[in] Lba The starting Logical Block Address to read from + @param[in] BufferSize Size of Buffer, must be a multiple of device block size. + @param[out] Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while performing the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_READ)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BLOCK_IO_PPI *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Write BufferSize bytes from Lba into Buffer. + + @param[in] PeiServices + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId The media ID that the write request is for. + @param[in] Lba The starting logical block address to be written. The caller is + responsible for writing to only legitimate locations. + @param[in] BufferSize Size of Buffer, must be a multiple of device block size. + @param[in] Buffer A pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data was written correctly to the device. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_WRITE)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BLOCK_IO_PPI *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush the Block Device. + + @param[in] This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data was written to the device + @retval EFI_DEVICE_ERROR The device reported an error while writting back the data + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_FLUSH)( + IN PEI_BLOCK_IO_PPI *This + ); + +/** + Block IO read only mode data and updated only via members of BlockIO + +**/ +typedef struct { + // + // The curent media Id. If the media changes, this value is changed. + // + UINT32 MediaId; + + // + // TRUE if the media is removable; otherwise, FALSE. + // + BOOLEAN RemovableMedia; + + // + // TRUE if there is a media currently present in the device; + // othersise, FALSE. THis field shows the media present status + // as of the most recent ReadBlocks() or WriteBlocks() call. + // + BOOLEAN MediaPresent; + + // + // TRUE if LBA 0 is the first block of a partition; otherwise + // FALSE. For media with only one partition this would be TRUE. + // + BOOLEAN LogicalPartition; + + // + // TRUE if the media is marked read-only otherwise, FALSE. + // This field shows the read-only status as of the most recent WriteBlocks () call. + // + BOOLEAN ReadOnly; + + // + // TRUE if the WriteBlock () function caches write data. + // + BOOLEAN WriteCaching; + + // + // The intrinsic block size of the device. If the media changes, then + // this field is updated. + // + UINT32 BlockSize; + + // + // Supplies the alignment requirement for any buffer to read or write block(s). + // + UINT32 IoAlign; + + // + // The last logical block address on the device. + // If the media changes, then this field is updated. + // + EFI_LBA LastBlock; + + // + // Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + // EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to + // a physical block boundary. + // + EFI_LBA LowestAlignedLba; + + // + // Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + // EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks + // per physical block. + // + UINT32 LogicalBlocksPerPhysicalBlock; + + // + // Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + // EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length + // granularity as a number of logical blocks. + // + UINT32 OptimalTransferLengthGranularity; +} PEI_BLOCK_IO_MEDIA; + +#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000 +#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001 +#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031 + +// +// Revision defined in EFI1.1. +// +#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION + +// +// This protocol provides control over block devices. +// +struct _PEI_BLOCK_IO_PPI { + // + // The revision to which the block IO interface adheres. All future + // revisions must be backwards compatible. If a future version is not + // back wards compatible, it is not the same GUID. + // + UINT64 Revision; + // + // Pointer to the EFI_BLOCK_IO_MEDIA data for this device. + // + PEI_BLOCK_IO_MEDIA *Media; + PEI_BLOCK_RESET Reset; + PEI_BLOCK_READ ReadBlocks; + PEI_BLOCK_WRITE WriteBlocks; + PEI_BLOCK_FLUSH FlushBlocks; +}; + +extern EFI_GUID gPeiBlockIoPpiGuid; +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPcieDeviceTable.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPcieDeviceTable.h new file mode 100644 index 0000000000..2525f61f8b --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPcieDeviceTable.h @@ -0,0 +1,54 @@ +/** @file + SC policy PPI produced by a platform driver specifying PCIe device overrides. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PCIE_DEVICE_TABLE_H_ +#define _SC_PCIE_DEVICE_TABLE_H_ + +// +// PCIe device table PPI GUID. +// +extern EFI_GUID gScPcieDeviceTablePpiGuid; + +typedef struct _SC_PCIE_DEVICE_OVERRIDE SC_PCIE_DEVICE_OVERRIDE; + +typedef enum { + ScPcieOverrideDisabled = 0, + ScPcieL1L2Override = 0x01, + ScPcieL1SubstatesOverride = 0x02, + ScPcieL1L2AndL1SubstatesOverride = 0x03, + ScPcieLtrOverride = 0x04 +} SC_PCIE_OVERRIDE_CONFIG; + +struct _SC_PCIE_DEVICE_OVERRIDE { + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideConfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG). + UINT16 L1SubstatesCapOffset; + UINT8 L1SubstatesCapMask; + UINT8 L1sCommonModeRestoreTime; + UINT8 L1sTpowerOnScale; + UINT8 L1sTpowerOnValue; + UINT16 SnoopLatency; + UINT16 NonSnoopLatency; + UINT32 Reserved; +}; + +#endif // SC_PCIE_DEVICE_TABLE_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicy.h new file mode 100644 index 0000000000..2a6dad16ce --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicy.h @@ -0,0 +1,37 @@ +/** @file + SC policy PPI produced by a platform driver specifying various + expected SC settings. This PPI is consumed by the SC PEI modules + and carried over to SC DXE modules. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_POLICY_PPI_H_ +#define _SC_POLICY_PPI_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// + +#include +#include + +extern EFI_GUID gScPolicyPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct SC_POLICY SC_POLICY_PPI; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicyPreMem.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicyPreMem.h new file mode 100644 index 0000000000..cb1a9cb0f1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Ppi/ScPolicyPreMem.h @@ -0,0 +1,35 @@ +/** @file + SC policy PPI produced by a platform driver specifying various + expected SC settings. This PPI is consumed by the SC PEI modules. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PREMEM_POLICY_PPI_H_ +#define _SC_PREMEM_POLICY_PPI_H_ +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// + +#include +#include + +extern EFI_GUID gScPreMemPolicyPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _SC_PREMEM_POLICY SC_PREMEM_POLICY_PPI; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Guid/ScPolicyHobGuid.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Guid/ScPolicyHobGuid.h new file mode 100644 index 0000000000..0d55eb3ee6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Guid/ScPolicyHobGuid.h @@ -0,0 +1,26 @@ +/** @file + This file contains definitions of SC policy hob guid. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_POLICY_HOB_GUID_H_ +#define _SC_POLICY_HOB_GUID_H_ + +#include + +typedef struct SC_POLICY SC_POLICY_HOB; + +extern EFI_GUID gScPolicyHobGuid; + +#endif // _SC_POLICY_HOB_GUID_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/DxeScHdaNhlt.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/DxeScHdaNhlt.h new file mode 100644 index 0000000000..2e8862d3c3 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/DxeScHdaNhlt.h @@ -0,0 +1,132 @@ +/** @file + Header file for DxeScHdaLib - NHLT structure definitions. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _DXE_SC_HDA_NHLT_H_ +#define _DXE_SC_HDA_NHLT_H_ + +#include + +// +// ACPI support protocol instance signature definition. +// +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T') + +// +// MSFT defined structures +// +#define SPEAKER_FRONT_LEFT 0x1 +#define SPEAKER_FRONT_RIGHT 0x2 +#define SPEAKER_FRONT_CENTER 0x4 +#define SPEAKER_BACK_LEFT 0x10 +#define SPEAKER_BACK_RIGHT 0x20 + +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER) +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT) +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT) + +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* Microsoft */ +#define KSDATAFORMAT_SUBTYPE_PCM \ + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}} + +#pragma pack (push, 1) + +typedef struct { + UINT16 wFormatTag; + UINT16 nChannels; + UINT32 nSamplesPerSec; + UINT32 nAvgBytesPerSec; + UINT16 nBlockAlign; + UINT16 wBitsPerSample; + UINT16 cbSize; +} WAVEFORMATEX; + +typedef struct { + WAVEFORMATEX Format; + union { + UINT16 wValidBitsPerSample; + UINT16 wSamplesPerBlock; + UINT16 wReserved; + } Samples; + UINT32 dwChannelMask; + GUID SubFormat; +} WAVEFORMATEXTENSIBLE; + +// +// List of supported link type. +// +enum NHLT_LINK_TYPE +{ + HdaNhltLinkHd = 0, + HdaNhltLinkDsp = 1, + HdaNhltLinkDmic = 2, + HdaNhltLinkSsp = 3, + HdaNhltLinkInvalid +}; + +// +// List of supported device type. +// +enum NHLT_DEVICE_TYPE +{ + HdaNhltDeviceBt = 0, + HdaNhltDeviceDmic = 1, + HdaNhltDeviceI2s = 4, + HdaNhltDeviceInvalid +}; + +typedef struct { + UINT32 CapabilitiesSize; + UINT8 Capabilities[1]; +} SPECIFIC_CONFIG; + +typedef struct { + WAVEFORMATEXTENSIBLE Format; + SPECIFIC_CONFIG FormatConfiguration; +} FORMAT_CONFIG; + +typedef struct { + UINT8 FormatsCount; + FORMAT_CONFIG FormatsConfiguration[1]; +} FORMATS_CONFIG; + +typedef struct { + UINT32 EndpointDescriptorLength; + UINT8 LinkType; + UINT8 InstanceId; + UINT16 HwVendorId; + UINT16 HwDeviceId; + UINT16 HwRevisionId; + UINT32 HwSubsystemId; + UINT8 DeviceType; + UINT8 Direction; + UINT8 VirtualBusId; + SPECIFIC_CONFIG EndpointConfig; + FORMATS_CONFIG FormatsConfig; +} ENDPOINT_DESCRIPTOR; + +// +// High Level Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'} + UINT8 EndpointCount; // Actual number of endpoints + ENDPOINT_DESCRIPTOR EndpointDescriptors[1]; + SPECIFIC_CONFIG OedConfiguration; +} NHLT_ACPI_TABLE; + +#pragma pack (pop) + +#endif // _DXE_SC_HDA_NHLT_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/PeiDxeSmmScPciExpressHelpersLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/PeiDxeSmmScPciExpressHelpersLib.h new file mode 100644 index 0000000000..fa673dee95 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/PeiDxeSmmScPciExpressHelpersLib.h @@ -0,0 +1,376 @@ +/** @file + Header file for PCH PCI Express helpers library. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_DXE_SMM_PCH_PCI_EXPRESS_HELPERS_LIB_H_ +#define _PEI_DXE_SMM_PCH_PCI_EXPRESS_HELPERS_LIB_H_ + +#include +#include + +// +// Function prototypes +// +/** + Find the Offset to a given Capabilities ID. + CAPID list: + 0x01 = PCI Power Management Interface + 0x04 = Slot Identification + 0x05 = MSI Capability + 0x10 = PCI Express Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID + +**/ +UINT8 +PcieFindCapId ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ); + +/** + Search and return the offset of desired Pci Express Capability ID. + CAPID list: + 0x0001 = Advanced Error Rreporting Capability + 0x0002 = Virtual Channel Capability + 0x0003 = Device Serial Number Capability + 0x0004 = Power Budgeting Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID + +**/ +UINT16 +PcieFindExtendedCapId ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ); + +/** + This function returns PID according to Root Port Number. + + @param[in] RpPort Root Port Number + + @retval SC_SBI_PID Returns PID for SBI Access + +**/ +SC_SBI_PID +GetRpSbiPid ( + IN UINTN RpPort + ); + +/** + This function returns the Config Hide bit according to to Root Port Number. + + @param[in] RpPort Root Port Number + + @retval UINT32 Port Config Hide bit + +**/ +UINT32 +GetRpConfigHideBit ( + IN UINTN RpPort + ); + +/** + This function reads Pci Config register via SBI Access. + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[out] *Data32 Value of Config register + + @retval EFI_SUCCESS SBI Read successful. + +**/ +EFI_STATUS +PchSbiRpPciRead32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + OUT UINT32 *Data32 + ); + +/** + This function And then Or Pci Config register via SBI Access. + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[in] Data32And Value of Config register to be And-ed + @param[in] Data32AOr Value of Config register to be Or-ed + + @retval EFI_SUCCESS SBI Read and Write successful. + +**/ +EFI_STATUS +PchSbiRpPciAndThenOr32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + IN UINT32 Data32And, + IN UINT32 Data32Or + ); + +/** + This function returns the maximum number of ClkReq signals available. + + @retval UINT8 Returns maximum number of ClkReq signals + +**/ +UINT8 +GetClkReqMax ( + VOID + ); + +/** + This returns ClkReq Number from Port Number. + + @param[in] PortIndex PCIe Port Number (Zero Base. Please use 23 for GBe) + + @retval ClkReq Number + +**/ +UINT8 +GetPortClkReqNumber ( + IN UINT8 PortIndex + ); + +/** + This function assigns a ClkReq signal to Pcie ports and returns updated ClkReq Count. + + @param[in] PcieConfig PCH Pcie Configuration + @param[in] PortIndex PCIe Port Number (Zero Base) + + @retval EFI_SUCCESS Successfully set ClkReq Number to Root Port + +**/ +EFI_STATUS +SetPortClkReqNumber ( + IN SC_PCIE_CONFIG *PcieConfig, + IN UINT8 PortIndex + ); + +/** + Set Common clock to Root port and Endpoint PCI device. + + @param[in] Bus1 Root port Pci Bus Number + @param[in] Device1 Root port Pci Device Number + @param[in] Function1 Root port Pci Function Number + @param[in] Bus2 Endpoint Pci Bus Number + @param[in] Device2 Endpoint Pci Device Number + + @retval EFI_UNSUPPORTED Unsupported operation. + @retval EFI_SUCCESS VC mapping correctly initialized + +**/ +EFI_STATUS +PcieSetCommonClock ( + IN UINT8 Bus1, + IN UINT8 Device1, + IN UINT8 Function1, + IN UINT8 Bus2, + IN UINT8 Device2 + ); + +/** + This function enables the CLKREQ# PM on all the end point functions + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] RootDevice Rootport Device Number + @param[in] RootFunction Rootport Function Number + + @retval None + +**/ +VOID +PcieSetClkreq ( + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice, + IN UINT8 RootDevice, + IN UINT8 RootFunction + ); + +/** + This function get or set the Max Payload Size on all the end point functions + + @param[in] EndPointBus The Bus Number of the Endpoint + @param[in] EndPointDevice The Device Number of the Endpoint + @param[in] MaxPayload The Max Payolad Size of the root port + @param[in] Operation True: Set the Max Payload Size on all the end point functions + False: Get the Max Payload Size on all the end point functions + + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +PcieMaxPayloadSize ( + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice, + IN OUT UINT16 *MaxPayload, + IN BOOLEAN Operation + ); + +/** + This function disable the forwarding of EOI messages unless it discovers + an IOAPIC behind this root port. + + @param[in] RootBus The Bus Number of the root port + @param[in] RootDevice The Device Number of the root port + @param[in] RootFunction The Function Number of the root port + @param[in] EndPointBus The Bus Number of the Endpoint + @param[in] EndPointDevice The Device Number of the Endpoint + + @retval EFI_UNSUPPORTED Unsupported operation. + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +PcieSetEoiFwdDisable ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice + ); + +/** + This function performs the Power Management settings for root port and downstream device + + @param[in] RootBus Pci Bus Number of the root port + @param[in] RootDevice Pci Device Number of the root port + @param[in] RootFunction Pci Function Number of the root port + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary + bus number) and its down stream switches + @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate + bus number) and its down stream switches + @param[in] RootPortConfig Pcie Power Optimizer Configuration + @param[in, out] L1SubstatesSupported L1 substates supported on the root port + @param[in] PolicyRevision Policy revision for codes compatibility + @param[in] FirstRPToSetPm Indicates if this is the first root port to be set + @param[in] L1SupportedInAllEnabledPorts Check if L1 is supported in all enabled ports + @param[in] ClkreqSupportedInAllEnabledPorts Check if clkreq is supported in all enabled ports + @param[out] LtrSupported Return to check if all endpoints support LTR + @param[in] AllowRpAspmProgramming Allow fine grain control on when the RP ASPM programming is to be done, + particularly used by the RST PCIe storage remapping feature + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found + +**/ +EFI_STATUS +PcieSetPm ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT8 TempBusNumberMin, + IN UINT8 TempBusNumberMax, + IN CONST SC_PCIE_ROOT_PORT_CONFIG *RootPortConfig, + IN OUT BOOLEAN *L1SubstatesSupported, + IN UINT8 PolicyRevision, + IN BOOLEAN FirstRPToSetPm, + IN BOOLEAN L1SupportedInAllEnabledPorts, + IN BOOLEAN ClkreqSupportedInAllEnabledPorts, + OUT BOOLEAN *LtrSupported, + IN BOOLEAN AllowRpAspmProgramming + ); + +/** + This function checks if the root port and downstream device support Clkreq per port, ASPM L1 and L1 substates. + + @param[in] RootBus Pci Bus Number of the root port + @param[in] RootDevice Pci Device Number of the root port + @param[in] RootFunction Pci Function Number of the root port + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary + bus number) and its down stream switches + @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate + bus number) and its down stream switches + @param[in] RootPortConfig Pcie Power Optimizer Configuration + @param[in, out] L1SubstatesSupported Flag to indicate if L1 Substates are supported + @param[in] PolicyRevision Revision of the policy + @param[in, out] AspmVal Aspm value for both rootport and end point devices + @param[in, out] ClkreqPerPortSupported Clkreq support for both rootport and endpoint devices + @param[out] LtrSupported Return to check if all endpoints support LTR + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found + +**/ +EFI_STATUS +PcieCheckPmConfig ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT32 NumOfDevAspmOverride, + IN SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT8 TempBusNumberMin, + IN UINT8 TempBusNumberMax, + IN CONST SC_PCIE_ROOT_PORT_CONFIG *RootPortConfig, + IN OUT BOOLEAN *L1SubstatesSupported, + IN UINT8 PolicyRevision, + IN OUT UINT16 *AspmVal, + IN OUT BOOLEAN *ClkreqPerPortSupported, + OUT BOOLEAN *LtrSupported + ); + +/** + Initializes the root port and its down stream devices + + @param[in] RootPortBus Pci Bus Number of the root port + @param[in] RootPortDevice Pci Device Number of the root port + @param[in] RootPortFunc Pci Function Number of the root port + @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary + bus number) and its down stream switches + @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate + bus number) and its down stream switches + @param[out] PortWithMaxPayload128 At least one Port with MaxPayload set to 128 bits + + @retval EFI_SUCCESS Successfully completed + @retval EFI_NOT_FOUND Can not find device. + +**/ +EFI_STATUS +PchPcieInitRootPortDownstreamDevices ( + IN UINT8 RootPortBus, + IN UINT8 RootPortDevice, + IN UINT8 RootPortFunc, + IN UINT8 TempBusNumberMin, + IN UINT8 TempBusNumberMax, + OUT BOOLEAN *PortWithMaxPayload128 + ); + +#endif // _PEI_DXE_SMM_PCH_PCI_EXPRESS_HELPERS_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScHdaLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScHdaLib.h new file mode 100644 index 0000000000..1ce2731658 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScHdaLib.h @@ -0,0 +1,67 @@ +/** @file + This library provides SC HD Audio functions. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_HDA_LIB_H_ +#define _SC_HDA_LIB_H_ + +#include +#include + +/** + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offload Engine Driver) Configuration Table). + + @param[in] NhltAcpiTable The NHLT table to print + +**/ +VOID +NhltAcpiTableDump( + IN NHLT_ACPI_TABLE *NhltTable + ); + +/** + Constructs EFI_ACPI_DESCRIPTION_HEADER structure for NHLT table. + + @param[in, out] NhltTable NHLT table for which header will be created + @param[in] NhltTableSize Size of NHLT table + + @retval None + +**/ +VOID +NhltAcpiHeaderConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN UINT32 NhltTableSize + ); + +/** + Constructs NHLT_ACPI_TABLE structure based on given Endpoints list. + + @param[in] EndpointTable List of endpoints for NHLT + @param[in, out] NhltTable NHLT table to be created + @param[in, out] NhltTableSize Size of created NHLT table + + @retval EFI_SUCCESS NHLT created successfully + @retval EFI_BAD_BUFFER_SIZE Not enough resources to allocate NHLT + +**/ +EFI_STATUS +NhltConstructor( + IN SC_HDA_NHLT_ENDPOINTS *EndpointTable, + IN OUT NHLT_ACPI_TABLE **NhltTable, + IN OUT UINT32 *NhltTableSize + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScInitCommonLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScInitCommonLib.h new file mode 100644 index 0000000000..5ffd9d946b --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScInitCommonLib.h @@ -0,0 +1,119 @@ +/** @file + Header file for SC Init Common Lib. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_INIT_COMMON_LIB_H_ +#define _SC_INIT_COMMON_LIB_H_ + +#include +#include + +/** + This function returns PID according to Root Port Number. + + @param[in] RpPort Root Port Number + + @retval SC_SBI_PID Returns PID for SBI Access + +**/ +SC_SBI_PID +GetRpSbiPid ( + IN UINTN RpPort + ); + +/** + Calculate root port device number based on physical port index. + + @param[in] RpIndex Root port index (0-based). + + @retval Root port device number. + +**/ +UINT32 +PchGetPcieRpDevice ( + IN UINT32 RpIndex + ); + +/** + This function reads Pci Config register via SBI Access. + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[out] Data32 Value of Config register + + @retval EFI_SUCCESS SBI Read successful + +**/ +EFI_STATUS +PchSbiRpPciRead32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + OUT UINT32 *Data32 + ); + +/** + This function And then Or Pci Config register via SBI Access. + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[in] Data32And Value of Config register to be And-ed + @param[in] Data32AOr Value of Config register to be Or-ed + + @retval EFI_SUCCESS SBI Read and Write successful + +**/ +EFI_STATUS +PchSbiRpPciAndThenOr32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + IN UINT32 Data32And, + IN UINT32 Data32Or + ); + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None + +**/ +VOID +PrintRegisters ( + IN UINTN PrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ); + +/** + PrintPchPciConfigSpace + + @param[in] None + + @retval None + +**/ +VOID +PrintPchPciConfigSpace ( + VOID + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScSmbusCommonLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScSmbusCommonLib.h new file mode 100644 index 0000000000..fac111b215 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/ScSmbusCommonLib.h @@ -0,0 +1,183 @@ +/** @file + SC Smbus Protocol. + + Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_SMBUS_COMMON_LIB_H +#define _SC_SMBUS_COMMON_LIB_H + +// +// Definitions +// +#define STALL_PERIOD 10 * STALL_ONE_MICRO_SECOND ///< 10 microseconds +#define STALL_TIME STALL_ONE_SECOND ///< 1 second +#define BUS_TRIES 3 ///< How many times to retry on Bus Errors +#define SMBUS_NUM_RESERVED 38 ///< Number of device addresses that are reserved by the SMBus spec. +#define SMBUS_ADDRESS_ARP 0xC2 >> 1 +#define SMBUS_DATA_PREPARE_TO_ARP 0x01 +#define SMBUS_DATA_RESET_DEVICE 0x02 +#define SMBUS_DATA_GET_UDID_GENERAL 0x03 +#define SMBUS_DATA_ASSIGN_ADDRESS 0x04 +#define SMBUS_GET_UDID_LENGTH 17 ///< 16 byte UDID + 1 byte address + +// +// Private data and functions +// + +typedef +UINT8 +(EFIAPI *SMBUS_IO_READ) ( + IN UINT8 Offset + ); + +typedef +VOID +(EFIAPI *SMBUS_IO_WRITE) ( + IN UINT8 Offset, + IN UINT8 Data + ); + +typedef +BOOLEAN +(EFIAPI *SMBUS_IO_DONE) ( + IN UINT8 *StsReg + ); + +#define PCH_SMBUS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('p', 's', 'm', 'b') + +/** + Get SMBUS IO Base address. + + @param[in] None + + @retval UINT32 The SMBUS IO Base Address + +**/ +UINT32 +SmbusGetIoBase ( + VOID + ); + +/** + This function provides a standard way to read PCH Smbus IO registers. + + @param[in] Offset Register offset from Smbus base IO address. + + @retval UINT8 Returns data read from IO. + +**/ +UINT8 +EFIAPI +SmbusIoRead ( + IN UINT8 Offset + ); + +/** + This function provides a standard way to write PCH Smbus IO registers. + + @param[in] Offset Register offset from Smbus base IO address. + @param[in] Data Data to write to register. + + @retval None + +**/ +VOID +EFIAPI +SmbusIoWrite ( + IN UINT8 Offset, + IN UINT8 Data + ); + +/** + This function provides a standard way to check if an SMBus transaction has + completed. + + @param[in] StsReg Not used for input. On return, contains the + value of the SMBus status register. + + @retval TRUE Transaction is complete + @retval FALSE Otherwise. + +**/ +BOOLEAN +EFIAPI +IoDone ( + IN UINT8 *StsReg + ); + +/** + Check if it's ok to use the bus. + + @param[in] None + + @retval EFI_SUCCESS SmBus is acquired and it's safe to send commands. + @retval EFI_TIMEOUT SmBus is busy, it's not safe to send commands. + +**/ +EFI_STATUS +AcquireBus ( + VOID + ); + +/** + This function provides a standard way to execute Smbus protocols + as defined in the SMBus Specification. The data can either be of + the Length byte, word, or a block of data. The resulting transaction will be + either the SMBus Slave Device accepts this transaction or this function + returns with an error + + @param[in] SlaveAddress Smbus Slave device the command is directed at + @param[in] Command Slave Device dependent + @param[in] Operation Which SMBus protocol will be used + @param[in] PecCheck Defines if Packet Error Code Checking is to be used + @param[in, out] Length How many bytes to read. Must be 0 <= Length <= 32 depending on Operation + It will contain the actual number of bytes read/written. + @param[in, out] Buffer Contain the data read/written. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED The operation is unsupported. + + @retval EFI_INVALID_PARAMETER Length or Buffer is NULL for any operation besides + quick read or quick write. + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period, or the controller is not + available for use. + @retval EFI_DEVICE_ERROR There was an Smbus error (NACK) during the operation. + This could indicate the slave device is not present + or is in a hung condition. + +**/ +EFI_STATUS +SmbusExec ( + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ); + +/** + This function initializes the Smbus Registers. + + @param[in] None + + @retval None + +**/ +VOID +InitializeSmbusRegisters ( + VOID + ); +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/UsbCommonLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/UsbCommonLib.h new file mode 100644 index 0000000000..092c14009c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Library/UsbCommonLib.h @@ -0,0 +1,161 @@ +/** @file + Header file for USB Common Lib. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _USB_COMMON_H_ +#define _USB_COMMON_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + UINT8 Device; + UINT8 Function; +} USB_CONTROLLER; + +#define INIT_COMMON_SCRIPT_IO_WRITE(TableName, Width, Address, Count, Buffer) +#define INIT_COMMON_SCRIPT_IO_READ_WRITE(TableName, Width, Address, Data, DataMask) +#define INIT_COMMON_SCRIPT_MEM_WRITE(TableName, Width, Address, Count, Buffer) +#define INIT_COMMON_SCRIPT_MEM_READ_WRITE(TableName, Width, Address, Data, DataMask) +#define INIT_COMMON_SCRIPT_PCI_CFG_WRITE(TableName, Width, Address, Count, Buffer) +#define INIT_COMMON_SCRIPT_PCI_CFG_READ_WRITE(TableName, Width, Address, Data, DataMask) +#define INIT_COMMON_SCRIPT_STALL(TableName, Duration) + + +/** + Configures SC USB controller. + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] BusNumber PCI Bus Number of the SC device + @param[in] FuncDisableReg Function Disable Register + @param[in] BootMode current boot mode + + @retval EFI_INVALID_PARAMETER The parameter of ScPolicy is invalid + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +CommonUsbInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINT8 BusNumber, + IN OUT UINT32 *FuncDisableReg, + IN EFI_BOOT_MODE BootMode + ); + +/** + Performs basic configuration of SC USB3 (xHCI) controller. + + @param[in] UsbConfig The SC Platform Policy for USB configuration + @param[in] XhciMmioBase Memory base address of xHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +CommonXhciHcInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase, + IN EFI_BOOT_MODE BootMode + ); + +/** + Setup XHCI Over-Current Mapping. + + @param[in] UsbConfig The SC Platform Policy for USB configuration + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciOverCurrentMapping ( + IN SC_USB_CONFIG *UsbConfig, + IN UINTN XhciPciMmBase + ); + +/** + Program and enable XHCI Memory Space. + + @param[in] UsbConfig The SC Platform Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciMemorySpaceOpen ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase + ); + +/** + Clear and disable XHCI Memory Space. + + @param[in] UsbConfig The SC Platform Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciMemorySpaceClose ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase + ); + +/** + Lock USB registers before boot. + + @param[in] ScPolicy The SC Platform Policy + + @retval None + +**/ +VOID +UsbInitBeforeBoot ( + IN SI_POLICY_HOB *SiPolicy, + IN SC_POLICY_HOB *ScPolicy + ); + +/** + Initialization USB Clock Gating registers. + + @retval None + +**/ +VOID +ConfigureUsbClockGating ( + VOID + ); + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/PcieIoTrap.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/PcieIoTrap.h new file mode 100644 index 0000000000..ee3614e880 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/PcieIoTrap.h @@ -0,0 +1,46 @@ +/** @file + This file defines the PCH PCIE IoTrap Protocol. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PCIE_IOTRAP_H_ +#define _SC_PCIE_IOTRAP_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gScPcieIoTrapProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _SC_PCIE_IOTRAP_PROTOCOL SC_PCIE_IOTRAP_PROTOCOL; + +// +// Pcie Trap valid types +// +typedef enum { + PciePmTrap, + PcieTrapTypeMaximum +} SC_PCIE_TRAP_TYPE; + +/** + This protocol is used to provide the IoTrap address to trigger PCH PCIE call back events + +**/ +struct _SC_PCIE_IOTRAP_PROTOCOL { + UINT16 PcieTrapAddress; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvs.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvs.h new file mode 100644 index 0000000000..ba1fa8592d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvs.h @@ -0,0 +1,37 @@ +/** @file + This file defines the SC NVS Protocol. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_NVS_H_ +#define _SC_NVS_H_ + +#include "ScNvsArea.h" + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gScNvsAreaProtocolGuid; + +/** + This protocol is used to sync PCH information from POST to runtime ASL. + This protocol exposes the pointer of PCH NVS Area only. Please refer to + ASL definition for PCH NVS AREA. + +**/ +typedef struct { + SC_NVS_AREA *Area; +} SC_NVS_AREA_PROTOCOL; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvsArea.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvsArea.h new file mode 100644 index 0000000000..d66c5978a6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/Protocol/ScNvsArea.h @@ -0,0 +1,211 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Define SC NVS Area operatino region. +// + +#ifndef _SC_NVS_AREA_H_ +#define _SC_NVS_AREA_H_ + +#pragma pack (push,1) +typedef struct { + UINT32 RcRevision; ///< Offset 0 RC Revision + UINT16 PchSeries; ///< Offset 4 PCH Series + UINT16 PchGeneration; ///< Offset 6 PCH Generation + UINT32 RpAddress[20]; ///< Offset 8 Root Port address 1 + ///< Offset 12 Root Port address 2 + ///< Offset 16 Root Port address 3 + ///< Offset 20 Root Port address 4 + ///< Offset 24 Root Port address 5 + ///< Offset 28 Root Port address 6 + ///< Offset 32 Root Port address 7 + ///< Offset 36 Root Port address 8 + ///< Offset 40 Root Port address 9 + ///< Offset 44 Root Port address 10 + ///< Offset 48 Root Port address 11 + ///< Offset 52 Root Port address 12 + ///< Offset 56 Root Port address 13 + ///< Offset 60 Root Port address 14 + ///< Offset 64 Root Port address 15 + ///< Offset 68 Root Port address 16 + ///< Offset 72 Root Port address 17 + ///< Offset 76 Root Port address 18 + ///< Offset 80 Root Port address 19 + ///< Offset 84 Root Port address 20 + UINT32 NHLA; ///< Offset 88 HD-Audio NHLT ACPI address + UINT32 NHLL; ///< Offset 92 HD-Audio NHLT ACPI length + UINT32 ADFM; ///< Offset 96 HD-Audio DSP Feature Mask + UINT32 SBRG; ///< Offset 100 SBREG_BAR + UINT32 GPEM; ///< Offset 104 GPP_X to GPE_DWX mapping + UINT16 PcieLtrMaxSnoopLatency[20]; ///< Offset 108 PCIE LTR max snoop Latency 1 + ///< Offset 110 PCIE LTR max snoop Latency 2 + ///< Offset 112 PCIE LTR max snoop Latency 3 + ///< Offset 114 PCIE LTR max snoop Latency 4 + ///< Offset 116 PCIE LTR max snoop Latency 5 + ///< Offset 118 PCIE LTR max snoop Latency 6 + ///< Offset 120 PCIE LTR max snoop Latency 7 + ///< Offset 122 PCIE LTR max snoop Latency 8 + ///< Offset 124 PCIE LTR max snoop Latency 9 + ///< Offset 126 PCIE LTR max snoop Latency 10 + ///< Offset 128 PCIE LTR max snoop Latency 11 + ///< Offset 130 PCIE LTR max snoop Latency 12 + ///< Offset 132 PCIE LTR max snoop Latency 13 + ///< Offset 134 PCIE LTR max snoop Latency 14 + ///< Offset 136 PCIE LTR max snoop Latency 15 + ///< Offset 138 PCIE LTR max snoop Latency 16 + ///< Offset 140 PCIE LTR max snoop Latency 17 + ///< Offset 142 PCIE LTR max snoop Latency 18 + ///< Offset 144 PCIE LTR max snoop Latency 19 + ///< Offset 146 PCIE LTR max snoop Latency 20 + UINT16 PcieLtrMaxNoSnoopLatency[20]; ///< Offset 148 PCIE LTR max no snoop Latency 1 + ///< Offset 150 PCIE LTR max no snoop Latency 2 + ///< Offset 152 PCIE LTR max no snoop Latency 3 + ///< Offset 154 PCIE LTR max no snoop Latency 4 + ///< Offset 156 PCIE LTR max no snoop Latency 5 + ///< Offset 158 PCIE LTR max no snoop Latency 6 + ///< Offset 160 PCIE LTR max no snoop Latency 7 + ///< Offset 162 PCIE LTR max no snoop Latency 8 + ///< Offset 164 PCIE LTR max no snoop Latency 9 + ///< Offset 166 PCIE LTR max no snoop Latency 10 + ///< Offset 168 PCIE LTR max no snoop Latency 11 + ///< Offset 170 PCIE LTR max no snoop Latency 12 + ///< Offset 172 PCIE LTR max no snoop Latency 13 + ///< Offset 174 PCIE LTR max no snoop Latency 14 + ///< Offset 176 PCIE LTR max no snoop Latency 15 + ///< Offset 178 PCIE LTR max no snoop Latency 16 + ///< Offset 180 PCIE LTR max no snoop Latency 17 + ///< Offset 182 PCIE LTR max no snoop Latency 18 + ///< Offset 184 PCIE LTR max no snoop Latency 19 + ///< Offset 186 PCIE LTR max no snoop Latency 20 + UINT32 SerialIoDebugUart0Bar0; ///< Offset 188 SerialIo Hidden UART0 BAR 0 + UINT32 SerialIoDebugUart1Bar0; ///< Offset 192 SerialIo Hidden UART1 BAR 0 + UINT32 ADPM; ///< Offset 196 HD-Audio DSP Post-Processing Module Mask + UINT8 XHPC; ///< Offset 200 Number of HighSpeed ports implemented in XHCI controller + UINT8 XRPC; ///< Offset 201 Number of USBR ports implemented in XHCI controller + UINT8 XSPC; ///< Offset 202 Number of SuperSpeed ports implemented in XHCI controller + UINT8 XSPA; ///< Offset 203 Address of 1st SuperSpeed port + UINT32 HPTB; ///< Offset 204 HPET base address + UINT8 HPTE; ///< Offset 208 HPET enable + // + // 110-bytes large SerialIo block + // + UINT8 SMD[11]; ///< Offset 209 SerialIo controller 0 (sdma) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 210 SerialIo controller 1 (i2c0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 211 SerialIo controller 2 (i2c1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 212 SerialIo controller 3 (spi0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 213 SerialIo controller 4 (spi1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 214 SerialIo controller 5 (ua00) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 215 SerialIo controller 6 (ua01) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 216 SerialIo controller 7 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 217 SerialIo controller 8 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 218 SerialIo controller 9 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + ///< Offset 219 SerialIo controller A (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + UINT8 SIR[11]; ///< Offset 220 SerialIo controller 0 (sdma) irq number + ///< Offset 221 SerialIo controller 1 (i2c0) irq number + ///< Offset 222 SerialIo controller 2 (i2c1) irq number + ///< Offset 223 SerialIo controller 3 (spi0) irq number + ///< Offset 224 SerialIo controller 4 (spi1) irq number + ///< Offset 225 SerialIo controller 5 (ua00) irq number + ///< Offset 226 SerialIo controller 6 (ua01) irq number + ///< Offset 227 SerialIo controller 7 (shdc) irq number + ///< Offset 228 SerialIo controller 8 (shdc) irq number + ///< Offset 229 SerialIo controller 9 (shdc) irq number + ///< Offset 230 SerialIo controller A (shdc) irq number + UINT32 SB0[11]; ///< Offset 231 SerialIo controller 0 (sdma) BAR0 + ///< Offset 235 SerialIo controller 1 (i2c0) BAR0 + ///< Offset 239 SerialIo controller 2 (i2c1) BAR0 + ///< Offset 243 SerialIo controller 3 (spi0) BAR0 + ///< Offset 247 SerialIo controller 4 (spi1) BAR0 + ///< Offset 251 SerialIo controller 5 (ua00) BAR0 + ///< Offset 255 SerialIo controller 6 (ua01) BAR0 + ///< Offset 259 SerialIo controller 7 (shdc) BAR0 + ///< Offset 263 SerialIo controller 8 (shdc) BAR0 + ///< Offset 267 SerialIo controller 9 (shdc) BAR0 + ///< Offset 271 SerialIo controller A (shdc) BAR0 + UINT32 SB1[11]; ///< Offset 275 SerialIo controller 0 (sdma) BAR1 + ///< Offset 279 SerialIo controller 1 (i2c0) BAR1 + ///< Offset 283 SerialIo controller 2 (i2c1) BAR1 + ///< Offset 287 SerialIo controller 3 (spi0) BAR1 + ///< Offset 291 SerialIo controller 4 (spi1) BAR1 + ///< Offset 295 SerialIo controller 5 (ua00) BAR1 + ///< Offset 299 SerialIo controller 6 (ua01) BAR1 + ///< Offset 303 SerialIo controller 7 (shdc) BAR1 + ///< Offset 307 SerialIo controller 8 (shdc) BAR1 + ///< Offset 311 SerialIo controller 9 (shdc) BAR1 + ///< Offset 315 SerialIo controller A (shdc) BAR1 + // + // end of SerialIo block + // + UINT8 GPEN; ///< Offset 319 GPIO enabled + UINT8 SGIR; ///< Offset 320 GPIO IRQ + UINT8 RstPcieStorageInterfaceType[3]; ///< Offset 321 RST PCIe Storage Cycle Router#1 Interface Type + ///< Offset 322 RST PCIe Storage Cycle Router#2 Interface Type + ///< Offset 323 RST PCIe Storage Cycle Router#3 Interface Type + UINT8 RstPcieStoragePmCapPtr[3]; ///< Offset 324 RST PCIe Storage Cycle Router#1 Power Management Capability Pointer + ///< Offset 325 RST PCIe Storage Cycle Router#2 Power Management Capability Pointer + ///< Offset 326 RST PCIe Storage Cycle Router#3 Power Management Capability Pointer + UINT8 RstPcieStoragePcieCapPtr[3]; ///< Offset 327 RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer + ///< Offset 328 RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer + ///< Offset 329 RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer + UINT16 RstPcieStorageL1ssCapPtr[3]; ///< Offset 330 RST PCIe Storage Cycle Router#1 L1SS Capability Pointer + ///< Offset 332 RST PCIe Storage Cycle Router#2 L1SS Capability Pointer + ///< Offset 334 RST PCIe Storage Cycle Router#3 L1SS Capability Pointer + UINT8 RstPcieStorageEpL1ssControl2[3]; ///< Offset 336 RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2 + ///< Offset 337 RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2 + ///< Offset 338 RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2 + UINT32 RstPcieStorageEpL1ssControl1[3]; ///< Offset 339 RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1 + ///< Offset 343 RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1 + ///< Offset 347 RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1 + UINT16 RstPcieStorageLtrCapPtr[3]; ///< Offset 351 RST PCIe Storage Cycle Router#1 LTR Capability Pointer + ///< Offset 353 RST PCIe Storage Cycle Router#2 LTR Capability Pointer + ///< Offset 355 RST PCIe Storage Cycle Router#3 LTR Capability Pointer + UINT32 RstPcieStorageEpLtrData[3]; ///< Offset 357 RST PCIe Storage Cycle Router#1 Endpoint LTR Data + ///< Offset 361 RST PCIe Storage Cycle Router#2 Endpoint LTR Data + ///< Offset 365 RST PCIe Storage Cycle Router#3 Endpoint LTR Data + UINT16 RstPcieStorageEpLctlData16[3]; ///< Offset 369 RST PCIe Storage Cycle Router#1 Endpoint LCTL Data + ///< Offset 371 RST PCIe Storage Cycle Router#2 Endpoint LCTL Data + ///< Offset 373 RST PCIe Storage Cycle Router#3 Endpoint LCTL Data + UINT16 RstPcieStorageEpDctlData16[3]; ///< Offset 375 RST PCIe Storage Cycle Router#1 Endpoint DCTL Data + ///< Offset 377 RST PCIe Storage Cycle Router#2 Endpoint DCTL Data + ///< Offset 379 RST PCIe Storage Cycle Router#3 Endpoint DCTL Data + UINT16 RstPcieStorageEpDctl2Data16[3]; ///< Offset 381 RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data + ///< Offset 383 RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data + ///< Offset 385 RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data + UINT16 RstPcieStorageRpDctl2Data16[3]; ///< Offset 387 RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data + ///< Offset 389 RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data + ///< Offset 391 RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data + UINT32 RstPcieStorageUniqueTableBar[3]; ///< Offset 393 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR + ///< Offset 397 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR + ///< Offset 401 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR + UINT32 RstPcieStorageUniqueTableBarValue[3]; ///< Offset 405 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value + ///< Offset 409 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value + ///< Offset 413 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value + UINT32 RstPcieStorageUniquePbaBar[3]; ///< Offset 417 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR + ///< Offset 421 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR + ///< Offset 425 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR + UINT32 RstPcieStorageUniquePbaBarValue[3]; ///< Offset 429 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value + ///< Offset 433 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value + ///< Offset 437 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value + UINT8 SDME; ///< Offset 441 SCS SDIO Controller Mode (0: disabled, 1: pci, 2: acpi) + UINT8 SDIR; ///< Offset 442 SCS SDIO Controller interrupt number + UINT32 SDB0; ///< Offset 443 SCS SDIO controller BAR0 + UINT32 SDB1; ///< Offset 447 SCS SDIO controller BAR1 + UINT8 ExitBootServicesFlag; ///< Offset 451 Flag indicating Exit Boot Service, to inform SMM + UINT32 SxMemBase; ///< Offset 452 Sx handler reserved MMIO base + UINT32 SxMemSize; ///< Offset 456 Sx handler reserved MMIO size +} SC_NVS_AREA; + +#pragma pack(pop) +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScHdaEndpoints.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScHdaEndpoints.h new file mode 100644 index 0000000000..ff990329fc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScHdaEndpoints.h @@ -0,0 +1,131 @@ +/** @file + Header file for ScHdaLib Endpoint descriptors. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_HDA_ENDPOINTS_H_ +#define _SC_HDA_ENDPOINTS_H_ + +#include + +typedef enum { + HdaDmicX2 = 0, + HdaDmicX4, + HdaBtRender, + HdaBtCapture, + HdaI2sRenderSKP, + HdaI2sCaptureSKP, + HdaI2sRenderHP, + HdaI2sCaptureHP, + HdaModem1Render, + HdaModem1Capture, + HdaModem2Render, + HdaModem2Capture, + HdaEndpointMax +} NHLT_ENDPOINT; + +typedef struct { + NHLT_ENDPOINT EndpointType; + BOOLEAN Enable; +} SC_HDA_NHLT_ENDPOINTS; + +#define SC_HDA_NHLT_TABLE_SIZE 0x2000 + +// +// Format bitmask +// +#define B_HDA_2CH_48KHZ_16BIT_FORMAT BIT0 +#define B_HDA_2CH_48KHZ_24BIT_FORMAT BIT1 +#define B_HDA_2CH_48KHZ_32BIT_FORMAT BIT2 +#define B_HDA_4CH_48KHZ_16BIT_FORMAT BIT3 +#define B_HDA_4CH_48KHZ_32BIT_FORMAT BIT4 +#define B_HDA_NARROWBAND_FORMAT BIT5 +#define B_HDA_WIDEBAND_FORMAT BIT6 +#define B_HDA_A2DP_FORMAT BIT7 +#define V_HDA_FORMAT_MAX 8 + +// +// Formats +// +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz16bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz24bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz32bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz16bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz32bitFormat; +extern CONST WAVEFORMATEXTENSIBLE NarrowbandFormat; +extern CONST WAVEFORMATEXTENSIBLE WidebandFormat; +extern CONST WAVEFORMATEXTENSIBLE A2dpFormat; + +// +// Format Config +// +extern CONST UINT32 DmicStereo16BitFormatConfig[]; +extern CONST UINT32 DmicStereo32BitFormatConfig[]; +extern CONST UINT32 DmicQuad16BitFormatConfig[]; +extern CONST UINT32 DmicQuad32BitFormatConfig[]; +extern CONST UINT32 DmicFormatConfigSize; +extern CONST UINT32 DmicCommonFormatConfig[]; +extern CONST UINT32 DmicCommonFormatConfigSize; + +extern CONST UINT32 I2sFormatConfigRender[]; +extern CONST UINT32 I2sFormatConfigRenderSize; +extern CONST UINT32 I2sFormatConfigRender_Bxtp[]; +extern CONST UINT32 I2sFormatConfigRenderSize_Bxtp; +extern CONST UINT32 I2sFormatConfigCapture[]; +extern CONST UINT32 I2sFormatConfigCaptureSize; +extern CONST UINT32 I2sFormatConfigCapture_Bxtp[]; +extern CONST UINT32 I2sFormatConfigCaptureSize_Bxtp; +extern CONST UINT32 BtFormatConfig[]; +extern CONST UINT32 BtFormatConfigSize; + +// +// Endpoints +// +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX2; +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX4; +extern ENDPOINT_DESCRIPTOR HdaEndpointBtRender; +extern ENDPOINT_DESCRIPTOR HdaEndpointBtCapture; +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sRenderSKP; +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sRenderHP; +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sCapture; +extern ENDPOINT_DESCRIPTOR HdaEndpointModem1Render; +extern ENDPOINT_DESCRIPTOR HdaEndpointModem1Capture; +extern ENDPOINT_DESCRIPTOR HdaEndpointModem2Render; +extern ENDPOINT_DESCRIPTOR HdaEndpointModem2Capture; + +// +// Endpoint Config +// +extern CONST UINT8 DmicX2Config[]; +extern CONST UINT32 DmicX2ConfigSize; +extern CONST UINT8 DmicX4Config[]; +extern CONST UINT32 DmicX4ConfigSize; +extern CONST UINT8 BtConfig[]; +extern CONST UINT32 BtConfigSize; +extern CONST UINT8 I2sConfig[]; +extern CONST UINT32 I2sConfigSize; +extern CONST UINT8 I2sConfigSKP[]; +extern CONST UINT32 I2sConfigSKPSize; +extern CONST UINT8 Modem1Config[]; +extern CONST UINT32 Modem1ConfigSize; +extern CONST UINT8 Modem2Config[]; +extern CONST UINT32 Modem2ConfigSize; + +// +// Oed Configuration +// +extern CONST UINT32 NhltConfiguration[]; +extern CONST UINT32 NhltConfigurationSize; + +#endif // _SC_HDA_ENDPOINTS_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScPmcFunctionDisableResetHob.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScPmcFunctionDisableResetHob.h new file mode 100644 index 0000000000..c8ca4f2a77 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Private/ScPmcFunctionDisableResetHob.h @@ -0,0 +1,37 @@ +/** @file + This file contains definitions of SC PMC function disable reset hob. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PMC_FUNCTION_DISABLE_RESET_HOB_H_ +#define _SC_PMC_FUNCTION_DISABLE_RESET_HOB_H_ + +#define SC_PMC_FUNCTION_DISABLE_NO_RESET 0 +#define SC_PMC_FUNCTION_DISABLE_COLD_RESET 1 +#define SC_PMC_FUNCTION_DISABLE_GLOBAL_RESET 2 + +// +// This structure contains the HOB for PMC function disable. +// +typedef struct { + /** + Using to do proper reset for PMC function disable. + 0: No Reset, 1: Cold reset, 2: Global reset + **/ + UINT8 ResetType; +} SC_PMC_FUNCTION_DISABLE_RESET_HOB; + +extern EFI_GUID gScPmcFunctionDisableResetHobGuid; + +#endif ///< _SC_PMC_FUNCTION_DISABLE_RESET_HOB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h new file mode 100644 index 0000000000..78a3972ce5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h @@ -0,0 +1,38 @@ +/** @file + Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EMMC_CARD_INFO_H_ +#define _EMMC_CARD_INFO_H_ + +#define EFI_EMMC_CARD_INFO_PROTOCOL_GUID \ + { \ + 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd } \ + } + +typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL; + + +/** + This is Protocol is used to get CARD_DATA pointer. + +**/ +struct _EFI_EMMC_CARD_INFO_PROTOCOL{ + CARD_DATA *CardData; +}; + +extern EFI_GUID gEfiEmmcCardInfoProtocolGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/HwWatchdogTimer.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/HwWatchdogTimer.h new file mode 100644 index 0000000000..296cd69ede --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/HwWatchdogTimer.h @@ -0,0 +1,234 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ +#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ + +#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \ + { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } + +#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \ + { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf } + +#include + +// +// General Purpose Constants +// +#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48. +#define B_INSTAFLUSH BIT4 + +// +// Other Watchdog timer values +// +#define WDT_COUNTDOWN_VALUE 0x14 +#define BDS_WDT_COUNTDOWN_VALUE 0x35 + +// +// Prototypes for the Watchdog Timer Driver Protocol +// +/** + This service begins the Watchdog Timer countdown. If the countdown completes prior to + Stop Timer or Restart Timer the system will reset. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_START_TIMER) ( + VOID + ); + +/** + This service resets the Watchdog Timer countdown and should only be called after the + Start Timer function. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_RESET_TIMER) ( + VOID + ); + +/** + This service restarts the Watchdog Timer countdown and should only be called after the + Start Timer function. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) ( + VOID + ); + +/** + This service disables the Watchdog Timer countdown. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_STOP_TIMER) ( + VOID + ); + +/** + This service disables the Watchdog Timer countdown. + + @param[out] WatchdogTimeout + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) ( + OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout + ); + +/** + This service forces a reboot of the system due to a reset of the POWERGOOD_PS, + POWERGOOD_CLK, and the BSEL Override + + @param[in] ForceTimeout + @param[in] ResetType + + @retval EFI_DEVICE_ERROR The command was unsuccessful and a reboot did not occur + This function should not return! + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) ( + IN BOOLEAN ForceTimeout, + IN UINT8 ResetType + ); + +/** + This service notifies the Watchdog Timer of the fact that a known reset is occuring. + + @param[in] AllowReset TRUE if a Reset is currently expected + FALSE if a Reset is not currently expected + + @retval EFI_DEVICE_ERROR The command was unsuccessful and a reboot did not occur + This function should not return! + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) ( + IN BOOLEAN AllowReset + ); + +/** + This service reads the current Watchdog Timer countdown reload value. + + @param[in] CountdownValue Pointer to UINT32 to return the value of the reload register. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 *CountdownValue + ); + +/** + This service reads the current Watchdog Timer countdown reload value. + + @param[out] CountdownValue Value to set the reload register. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 CountdownValue + ); + +/** + This service clears the state that indicates the Watchdog Timer fired. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) ( + ); + +/** + This service disables the Watchdog Timer countdown. It also closes the recurring restart event + if the event exists. + + @param[in] Stall TRUE = Stop the timer countdown, FALSE = Start the timer countdown + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) ( + IN BOOLEAN Stall + ); + +/** + This protocol allow a platform module to perform watch dog timer operations. + +**/ +typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL { + EFI_WATCHDOG_START_TIMER StartWatchdogTimer; + PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout; + EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer; + EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer; + EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout; + EFI_WATCHDOG_FORCE_REBOOT ForceReboot; + EFI_WATCHDOG_KNOWN_RESET AllowKnownReset; + EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod; + EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod; + PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState; + EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown; +} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL; + +extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid; +extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/MmcHostIo.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/MmcHostIo.h new file mode 100644 index 0000000000..18557e4b8f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/MmcHostIo.h @@ -0,0 +1,384 @@ +/** @file + Interface definition for EFI_MMC_HOST_IO_PROTOCOL. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MMC_HOST_IO_H +#define _MMC_HOST_IO_H + +#define EFI_MMC_HOST_IO_PROTOCOL_GUID \ + { 0x88b7c251, 0xf4e6, 0x4a1e, { 0x90, 0xbb, 0xda, 0x8b, 0x06, 0xb7, 0xdc, 0xda } } + +typedef struct _EFI_MMC_HOST_IO_PROTOCOL EFI_MMC_HOST_IO_PROTOCOL; + +// +// @todo Move to Pci22.h +// +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_IF_STANDARD_HOST_NO_DMA 0x00 +#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01 + +// +// @todo Retire +// +#define EFI_MMC_HOST_IO_PROTOCOL_REVISION_01 0x01 + +// +// @todo Do these belong in an Industry Standard include file? +// +// MMIO Registers definition for MMC/SDIO controller +// +#define MMIO_DMAADR 0x00 +#define MMIO_BLKSZ 0x04 +#define MMIO_BLKCNT 0x06 +#define MMIO_CMDARG 0x08 +#define MMIO_XFRMODE 0x0C +#define MMIO_SDCMD 0x0E +#define MMIO_RESP 0x10 +#define MMIO_BUFDATA 0x20 +#define MMIO_PSTATE 0x24 +#define MMIO_HOSTCTL 0x28 +#define MMIO_PWRCTL 0x29 +#define MMIO_BLKGAPCTL 0x2A +#define MMIO_WAKECTL 0x2B +#define MMIO_CLKCTL 0x2C +#define MMIO_TOCTL 0x2E +#define MMIO_SWRST 0x2F +#define MMIO_NINTSTS 0x30 +#define MMIO_ERINTSTS 0x32 +#define MMIO_NINTEN 0x34 +#define MMIO_ERINTEN 0x36 +#define MMIO_NINTSIGEN 0x38 +#define MMIO_ERINTSIGEN 0x3A +#define MMIO_AC12ERRSTS 0x3C +#define MMIO_HOST_CTL2 0x3E +#define MMIO_CAP 0x40 +#define MMIO_CAP2 0x44 +#define MMIO_MCCAP 0x48 +#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 +#define MMIO_FORCEEVENTERRINTSTAT 0x52 +#define MMIO_ADMAERRSTAT 0x54 +#define MMIO_ADMASYSADDR 0x58 +#define MMIO_PRESETVALUE0 0x60 +#define MMIO_PRESETVALUE1 0x64 +#define MMIO_PRESETVALUE2 0x68 +#define MMIO_PRESETVALUE3 0x6C +#define MMIO_BOOTTIMEOUTCTRL 0x70 +#define MMIO_DEBUGSEL 0x74 +#define MMIO_SHAREDBUS 0xE0 +#define MMIO_SPIINTSUP 0xF0 +#define MMIO_SLTINTSTS 0xFC +#define MMIO_CTRLRVER 0xFE + +typedef enum { + ResponseNo = 0, + ResponseR1, + ResponseR1b, + ResponseR2, + ResponseR3, + ResponseR4, + ResponseR5, + ResponseR5b, + ResponseR6, + ResponseR7 +} RESPONSE_TYPE; + +typedef enum { + NoData = 0, + InData, + OutData +} TRANSFER_TYPE; + +typedef enum { + Reset_Auto = 0, + Reset_DAT, + Reset_CMD, + Reset_DAT_CMD, + Reset_All, + Reset_HW +} RESET_TYPE; + +typedef enum { + SDMA = 0, + ADMA2, + PIO +} DMA_MOD; + +typedef struct { + UINT32 HighSpeedSupport: 1; ///< High speed supported + UINT32 V18Support: 1; ///< 1.8V supported + UINT32 V30Support: 1; ///< 3.0V supported + UINT32 V33Support: 1; ///< 3.3V supported + UINT32 SDR50Support: 1; + UINT32 SDR104Support: 1; + UINT32 DDR50Support: 1; + UINT32 HS400Support: 1; + UINT32 BusWidth4: 1; ///< 4 bit width + UINT32 BusWidth8: 1; ///< 8 bit width + UINT32 Reserved1: 6; + UINT32 SDMASupport: 1; + UINT32 ADMA2Support: 1; + UINT32 DmaMode: 2; + UINT32 ReTuneTimer: 4; + UINT32 ReTuneMode: 2; + UINT32 Reserved2: 6; + UINT32 BoundarySize; +} HOST_CAPABILITY; + +/** + The main function used to send the command to the card inserted into the MMC host + slot. + It will assemble the arguments to set the command register and wait for the command + and transfer completed until timeout. Then it will read the response register to fill + the ResponseData + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] CommandIndex The command index to set the command index field of command register + @param[in] Argument Command argument to set the argument field of command register + @param[in] DataType TRANSFER_TYPE, indicates no data, data in or data out + @param[in] Buffer Contains the data read from / write to the device + @param[in] BufferSize The size of the buffer + @param[in] ResponseType RESPONSE_TYPE + @param[in] TimeOut Time out value in 1 ms unit + @param[out] ResponseData Depending on the ResponseType, such as CSD or card status + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + @retval EFI_OUT_OF_RESOURCES + @retval EFI_TIMEOUT + @retval EFI_DEVICE_ERROR + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SEND_COMMAND) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData OPTIONAL + ); + +/** + Set max clock frequency of the host, the actual frequency + may not be the same as MaxFrequency. It depends on + the max frequency the host can support, divider, and host + speed mode. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] MaxFrequency Max frequency in HZ + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 MaxFrequency + ); + +/** + Set bus width of the host. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] BusWidth Bus width in 1, 4, 8 bits + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_BUS_WIDTH) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 BusWidth + ); + +/** + Set voltage which could supported by the host. + Support 0(Power off the host), 1.8V, 3.0V, 3.3V + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] Voltage Units in 0.1 V + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 Voltage + ); + +/** + Set Host High Speed. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] HighSpeed True for High Speed Mode set, false for normal mode + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 HighSpeed + ); + +/** + Set High Speed Mode. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] SetHostDdrMode True for DDR Mode set, false for normal mode + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 DdrMode + ); + +/** + Set Host SDR Mode. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] DdrMode True for SDR Mode set, false for normal mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER A parameter was incorrect. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 SdrMode + ); + +/** + Reset the host + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] ResetAll TRUE to reset all + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_RESET_MMC_HOST) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN RESET_TYPE ResetType + ); + +/** + Reset the host. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] Enable TRUE to enable, FALSE to disable + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + +/** + Find whether these is a card inserted into the slot. If so + init the host. If not, return EFI_NOT_FOUND. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This + ); + +/** + Set the Block length. + + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + @param[in] BlockLength card supports block length + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) ( + IN EFI_MMC_HOST_IO_PROTOCOL *This, + IN UINT32 BlockLength + ); + +/** + @param[in] This Pointer to EFI_MMC_HOST_IO_PROTOCOL + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_MMC_HOST_IO_PROTOCOL_SETUP_DEVICE)( + IN EFI_MMC_HOST_IO_PROTOCOL *This + ); + +/** + Interface structure for the EFI MMC Host I/O Protocol +**/ +struct _EFI_MMC_HOST_IO_PROTOCOL { + UINT32 Revision; + HOST_CAPABILITY HostCapability; + EFI_MMC_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand; + EFI_MMC_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency; + EFI_MMC_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth; + EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage; + EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode; + EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE SetHostSdrMode; + EFI_MMC_HOST_IO_PROTOCOL_RESET_MMC_HOST ResetMmcHost; + EFI_MMC_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd; + EFI_MMC_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost; + EFI_MMC_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength; + EFI_MMC_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice; + EFI_MMC_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode; +}; + +extern EFI_GUID gEfiMmcHostIoProtocolGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScExtendedReset.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScExtendedReset.h new file mode 100644 index 0000000000..d30036d62a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScExtendedReset.h @@ -0,0 +1,56 @@ +/** @file + SC Extended Reset Protocol. + + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_EXTENDED_RESET_H_ +#define _EFI_EXTENDED_RESET_H_ + +#define EFI_EXTENDED_RESET_PROTOCOL_GUID \ + { \ + 0xf0bbfca0, 0x684e, 0x48b3, 0xba, 0xe2, 0x6c, 0x84, 0xb8, 0x9e, 0x53, 0x39 \ + } +extern EFI_GUID gEfiExtendedResetProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_EXTENDED_RESET_PROTOCOL EFI_SC_EXTENDED_RESET_PROTOCOL; + +// +// Related Definitions +// +// +// SC Extended Reset Types +// +typedef struct { + UINT8 PowerCycle : 1; + UINT8 GlobalReset : 1; + UINT8 SusPwrDnAck : 1; + + UINT8 RsvdBits : 5; +} SC_EXTENDED_RESET_TYPES; + +typedef +EFI_STATUS +(EFIAPI *EFI_SC_EXTENDED_RESET) ( + IN EFI_SC_EXTENDED_RESET_PROTOCOL * This, + IN SC_EXTENDED_RESET_TYPES ScExtendedResetTypes + ); + +struct _EFI_EXTENDED_RESET_PROTOCOL { + EFI_SC_EXTENDED_RESET Reset; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScInfo.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScInfo.h new file mode 100644 index 0000000000..70de08754d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScInfo.h @@ -0,0 +1,42 @@ +/** @file + This file defines the Info Protocol. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_INFO_H_ +#define _SC_INFO_H_ + +#define EFI_INFO_PROTOCOL_GUID \ + { \ + 0xd31f0400, 0x7d16, 0x4316, 0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b \ + } +extern EFI_GUID gEfiInfoProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_INFO_PROTOCOL EFI_SC_INFO_PROTOCOL; + +#define INFO_PROTOCOL_REVISION_1 1 +#define INFO_PROTOCOL_REVISION_2 2 + +#define SC_RC_VERSION 0x01000000 + +struct _EFI_INFO_PROTOCOL { + UINT8 Revision; + UINT8 BusNumber; + UINT32 RCVersion; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScPcieSmiDispatch.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScPcieSmiDispatch.h new file mode 100644 index 0000000000..0bc1ee344d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScPcieSmiDispatch.h @@ -0,0 +1,125 @@ +/** @file + APIs of PCH PCIE SMI Dispatch Protocol. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PCIE_SMI_DISPATCH_PROTOCOL_H_ +#define _SC_PCIE_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gScPcieSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _SC_PCIE_SMI_DISPATCH_PROTOCOL SC_PCIE_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +typedef struct { + UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1) + UINT8 BusNum; ///< Root port pci bus number + UINT8 DevNum; ///< Root port pci device number + UINT8 FuncNum; ///< Root port pci function number +} SC_PCIE_SMI_RP_CONTEXT; + +/** + Callback function for an PCH PCIE RP SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + @param[in] RpContext Pointer of PCH PCIE Root Port context. + +**/ +typedef +VOID +(EFIAPI *SC_PCIE_SMI_RP_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle, + IN SC_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + Register a child SMI source dispatch function for PCH PCIERP SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] RpIndex Refer to PCH PCIE Root Port index. + 0: RP1, 1: RP2, n: RP(N+1) + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered. + +**/ +typedef +EFI_STATUS +(EFIAPI *SC_PCIE_SMI_RP_DISPATCH_REGISTER) ( + IN SC_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN SC_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent PCIE SMM driver. + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered. + +**/ +typedef +EFI_STATUS +(EFIAPI *SC_PCIE_SMI_DISPATCH_UNREGISTER) ( + IN SC_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +struct _SC_PCIE_SMI_DISPATCH_PROTOCOL { + /// + /// Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. + /// + SC_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; + /// + /// PcieRpXHotPlug + /// The event is triggered when PCIE root port Hot-Plug Presence Detect. + /// + SC_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; + /// + /// PcieRpXLinkActive + /// The event is triggered when Hot-Plug Link Active State Changed. + /// + SC_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; + /// + /// PcieRpXLinkEq + /// The event is triggered when Device Requests Software Link Equalization. + /// + SC_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScReset.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScReset.h new file mode 100644 index 0000000000..01b8654661 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScReset.h @@ -0,0 +1,104 @@ +/** @file + SC Reset Protocol. + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_RESET_H_ +#define _SC_RESET_H_ + +#define RESET_PROTOCOL_GUID \ + { \ + 0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \ + } +#define RESET_CALLBACK_PROTOCOL_GUID \ + { \ + 0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \ + } +extern EFI_GUID gScResetProtocolGuid; +extern EFI_GUID gScResetCallbackProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _SC_RESET_PROTOCOL SC_RESET_PROTOCOL; +typedef struct _SC_RESET_CALLBACK_PROTOCOL SC_RESET_CALLBACK_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// SC Reset Types +/// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc +} SC_RESET_TYPE; + +/// +/// Member functions +/// +/** + Execute SC Reset from the host controller. + + @param[in] This Pointer to the SC_RESET_PROTOCOL instance. + @param[in] ScResetType SC Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *SC_RESET) ( + IN SC_RESET_PROTOCOL * This, + IN SC_RESET_TYPE ScResetType + ); + +/** + Execute call back function for SC Reset. + + @param[in] ScResetType SC Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find SC Reset Callback protocol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from SC. + +**/ +typedef +EFI_STATUS +(EFIAPI *SC_RESET_CALLBACK) ( + IN SC_RESET_TYPE ScResetType + ); + +/// +/// Interface structure for the SC Reset Protocol +/// +struct _SC_RESET_PROTOCOL { + SC_RESET Reset; +}; + +/** + This protocol is used to execute South Cluster Reset from the host controller. +**/ +struct _SC_RESET_CALLBACK_PROTOCOL { + SC_RESET_CALLBACK ResetCallback; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScS3Support.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScS3Support.h new file mode 100644 index 0000000000..977b9eadc1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScS3Support.h @@ -0,0 +1,112 @@ +/** @file + This file defines the SC S3 support Protocol. + + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_S3_SUPPORT_PROTOCOL_H_ +#define _SC_S3_SUPPORT_PROTOCOL_H_ + +/// +/// Define the SC S3 Support protocol GUID +/// +#define EFI_SC_S3_SUPPORT_PROTOCOL_GUID \ + { \ + 0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \ + } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiScS3SupportProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SC_S3_SUPPORT_PROTOCOL EFI_SC_S3_SUPPORT_PROTOCOL; + +typedef enum { + ScS3ItemTypeSendCodecCommand, + ScS3ItemTypeInitPcieRootPortDownstream, + ScS3ItemTypePcieSetPm, + ScS3ItemTypeMax +} EFI_SC_S3_DISPATCH_ITEM_TYPE; + +/// +/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI +/// plug 4 to ParameterSize in PEIM if you really need it +/// +typedef struct { + UINT32 HdaBar; + UINT32 CodecCmdData; +} EFI_SC_S3_PARAMETER_SEND_CODEC_COMMAND; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; +} EFI_SC_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + UINT8 NumOfDevAspmOverride; + UINT32 DevAspmOverrideAddr; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; + UINT8 NumOfDevLtrOverride; + UINT32 DevLtrOverrideAddr; +} EFI_SC_S3_PARAMETER_PCIE_SET_PM; + +typedef struct { + EFI_SC_S3_DISPATCH_ITEM_TYPE Type; + VOID *Parameter; +} EFI_SC_S3_DISPATCH_ITEM; + +// +// Member functions +// +/** + Set an item to be dispatched at S3 resume time. At the same time, the entry point + of the SC S3 support image is returned to be used in subsequent boot script save + call. + + @param[in] This Pointer to the protocol instance. + @param[in] DispatchItem The item to be dispatched. + @param[out] S3DispatchEntryPoint The entry point of the SC S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SC_S3_SUPPORT_SET_S3_DISPATCH_ITEM) ( + IN EFI_SC_S3_SUPPORT_PROTOCOL * This, + IN EFI_SC_S3_DISPATCH_ITEM * DispatchItem, + OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint + ); + +/** + This is Protocol is used to set an item to be dispatched at S3 resume time. + At the same time, the entry point of the SC S3 support image is returned to + be used in subsequent boot script save call. +**/ +struct _EFI_SC_S3_SUPPORT_PROTOCOL { + EFI_SC_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem; ///< Set the item to be dispatched at S3 resume time. +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScSmmIoTrapControl.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScSmmIoTrapControl.h new file mode 100644 index 0000000000..71b8a99cf2 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/ScSmmIoTrapControl.h @@ -0,0 +1,62 @@ +/** @file + PCH SMM IO Trap Control Protocol. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_SMM_IO_TRAP_CONTROL_H_ +#define _SC_SMM_IO_TRAP_CONTROL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gScSmmIoTrapControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _SC_SMM_IO_TRAP_CONTROL_PROTOCOL SC_SMM_IO_TRAP_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume IoTrap callback function. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. + +**/ +typedef +EFI_STATUS +(EFIAPI *SC_SMM_IO_TRAP_CONTROL_FUNCTION) ( + IN SC_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + + +struct _SC_SMM_IO_TRAP_CONTROL_PROTOCOL { + SC_SMM_IO_TRAP_CONTROL_FUNCTION Pause; + SC_SMM_IO_TRAP_CONTROL_FUNCTION Resume; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h new file mode 100644 index 0000000000..7538b2882e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h @@ -0,0 +1,150 @@ +/** @file + SmmIchnDispatch Extended Protocol. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_ +#define _EFI_SMM_ICHN_DISPATCH_EX_H_ + +#include + +#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \ + { \ + 0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \ + } +extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// Ichn Dispatch Extended Types +/// +typedef enum { + IchnExPciExpress = NUM_ICHN_TYPES + 1, + IchnExMonitor, + IchnExSpi, + IchnExQRT, + IchnExGpioUnlock, + IchnExTmrOverflow, + IchnExPcie0Hotplug, + IchnExPcie1Hotplug, + IchnExPcie2Hotplug, + IchnExPcie3Hotplug, + IchnExPcie5Hotplug, + IchnExPcie6Hotplug, + IchnExPcie0LinkActive, + IchnExPcie1LinkActive, + IchnExPcie2LinkActive, + IchnExPcie3LinkActive, + IchnExPcie5LinkActive, + IchnExPcie6LinkActive, + IchnExTypeMAX // the maximum number of items in this enumeration +} EFI_SMM_ICHN_EX_SMI_TYPE; + +typedef struct { + EFI_SMM_ICHN_EX_SMI_TYPE Type; +} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT; + +/// +/// Member functions +/// +/** + @brief + Dispatch function for a ICH n Extended specific SMI handler. + + @param[in] DispatchHandle Handle of this dispatch function. + @param[in] DispatchContext Pointer to the dispatch function's context. + The DispatchContext fields are filled in + by the dispatching driver prior to + invoking this dispatch function. + + @retval None + +**/ +typedef +VOID +(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext + ); + +/** + Register a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] DispatchContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the ICHN SMI source for which the dispatch + function should be invoked. + @param[in] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this + child. + @retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value + is not within valid range. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext, + OUT EFI_HANDLE * DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval Others TBD + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + This protocol provides a parent dispatch service for ICHN Specific SMIs + This protocol extends EDK EFI_SMM_ICHN_DISPATCH_PROTOCOL. +**/ +struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL { + EFI_SMM_ICHN_EX_REGISTER Register; + EFI_SMM_ICHN_EX_UNREGISTER UnRegister; +}; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/TcoReset.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/TcoReset.h new file mode 100644 index 0000000000..23ab791a4c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Protocol/TcoReset.h @@ -0,0 +1,68 @@ +/** @file + Protocol to communicate with ICH TCO. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _TCO_RESET_H_ +#define _TCO_RESET_H_ + +#define EFI_TCO_RESET_PROTOCOL_GUID \ + {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3} + +typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL; + +/** + Enables the TCO timer to reset the system in case of a system hang. This is + used when writing the clock registers. + + @param[in] RcrbGcsSaveValue This is the value of the RCRB GCS register before it is + changed by this procedure. This will be used to restore + the settings of this register in PpiDisableTcoReset. + + @retval EFI_STATUS + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) ( + IN UINT32 *RcrbGcsSaveValue + ); + +/** + Disables the TCO timer. This is used after writing the clock registers. + + @param[out] RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that it can + restored. + + @retval EFI_STATUS + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) ( + OUT UINT32 RcrbGcsRestoreValue + ); + +/** + This protocol implement the interface that could enable/disable TCO timer + to reset the system in case of a system hang. +**/ +typedef struct _EFI_TCO_RESET_PROTOCOL { + EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset; + EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset; +} EFI_TCO_RESET_PROTOCOL; + +extern EFI_GUID gEfiTcoResetProtocolGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScAccess.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScAccess.h new file mode 100644 index 0000000000..66980271ec --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScAccess.h @@ -0,0 +1,264 @@ +/** @file + Macros that simplify accessing SC devices's PCI registers. + @note: Tthese macros assume the SC device is on BUS 0 + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_ACCESS_H_ +#define _SC_ACCESS_H_ + +#include +#include +#include "ScLimits.h" +#include "ScReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND + #define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND + #define STALL_ONE_SECOND 1000000 +#endif + +// +// The default PCI bus number +// +#define DEFAULT_PCI_BUS_NUMBER_SC 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_INTEL_VENDOR_ID 0x8086 ///< Default Intel Vendor ID +#define V_SC_DEFAULT_SID 0x7270 ///< Default Intel Subsystem ID +#define V_SC_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_SC_DEFAULT_SID << 16)) ///< Default INTEL Vendor ID and Subsystem ID +// +// Include device register definitions +// +#include "ScRegs/RegsLpss.h" +#include "ScRegs/RegsItss.h" +#include "ScRegs/RegsPcie.h" +#include "ScRegs/RegsPcu.h" +#include "ScRegs/RegsPmc.h" +#include "ScRegs/RegsIsh.h" +#include "ScRegs/RegsSata.h" +#include "ScRegs/RegsScc.h" +#include "ScRegs/RegsSpi.h" +#include "ScRegs/RegsUsb.h" +#include "ScRegs/RegsHda.h" +#include "ScRegs/RegsSmbus.h" +#include "ScRegs/RegsLpc.h" +#include "ScRegs/RegsPcr.h" +#include "ScRegs/RegsP2sb.h" +#include "ScRegs/RegsGpio.h" + +#define IS_EMMC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_SCC_EMMC_DEVICE_ID_0) || \ + (DeviceId == V_SCC_EMMC_DEVICE_ID_1) || \ + (DeviceId == V_SCC_EMMC_DEVICE_ID_2) || \ + (DeviceId == V_SCC_EMMC_DEVICE_ID_3) \ + ) + +#define IS_BXTP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_SATA_DEVICE_ID_BXTP_AHCI) \ + ) + +#define IS_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_DEVICE_ID_0) \ + ) + +// +// PCIE Device ID macros +// +#define IS_BXT_P_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_BXT_P_PCIE_DEVICE_ID_PORT6) \ + ) + +#define IS_BXT_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_BXT_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_BXT_PCIE_DEVICE_ID_PORT2) \ + ) + +#define IS_PCIE_DEVICE_ID(DeviceId) \ + ( \ + IS_BXT_P_PCIE_DEVICE_ID(DeviceId) || \ + IS_BXT_PCIE_DEVICE_ID(DeviceId) \ + ) + +// +// Memory Mapped PCI Access macros +// +// +// PCI Device MM Base +// +#ifndef MmPciAddress +#define MmPciAddress(Segment, Bus, Device, Function, Register) \ + ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + \ + (UINTN) (Bus << 20) + \ + (UINTN) (Device << 15) + \ + (UINTN) (Function << 12) + \ + (UINTN) (Register) \ + ) +#endif + +#ifdef SATA_SUPPORT + +// +// SATA device 0x13, Function 0 +// +#define SataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SATA, PCI_FUNCTION_NUMBER_SATA, Register)) + +#define SataPciCfg32Or(Register, OrData) \ + MmioOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + OrData \ + ) + +#define SataPciCfg32And(Register, AndData) \ + MmioAnd32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData \ + ) + +#define SataPciCfg32AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + +#define SataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SATA, PCI_FUNCTION_NUMBER_SATA, Register)) + +#define SataPciCfg16Or(Register, OrData) \ + MmioOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + OrData \ + ) + +#define SataPciCfg16And(Register, AndData) \ + MmioAnd16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData \ + ) + +#define SataPciCfg16AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + +#define SataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SATA, PCI_FUNCTION_NUMBER_SATA, Register)) + +#define SataPciCfg8Or(Register, OrData) \ + MmioOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + OrData \ + ) + +#define SataPciCfg8And(Register, AndData) \ + MmioAnd8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData \ + ) + +#define SataPciCfg8AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_SC, \ + PCI_DEVICE_NUMBER_SATA, \ + PCI_FUNCTION_NUMBER_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + +#endif + +// +// Device IDs that are PCH Server specific +// +#define IS_BXTP_SC_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_SC_LPC_DEVICE_ID_BXT_P_0) \ + ) +#endif + +/** + PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, SC_PCR_ADDRESS (Pid, Offset), Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, SC_PCR_ADDRESS (Pid, Offset), Buffer, Buffer, 1, 1); + +#define PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \ + S3BootScriptSaveMemReadWrite (Width, SC_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, SC_PCR_ADDRESS (Pid, Offset), DataOr, DataOr, 1, 1); + + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScLimits.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScLimits.h new file mode 100644 index 0000000000..21b94949b3 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScLimits.h @@ -0,0 +1,68 @@ +/** @file + Build time limits of SC resources. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_LIMITS_H_ +#define _SC_LIMITS_H_ + +// +// PCIe limits +// +#define SC_MAX_PCIE_ROOT_PORTS SC_BXTP_PCIE_MAX_ROOT_PORTS +#define SC_BXT_PCIE_MAX_ROOT_PORTS 2 +#define SC_BXTX_PCIE_MAX_ROOT_PORTS 4 +#define SC_BXTP_PCIE_MAX_ROOT_PORTS 6 + +#define SC_MAX_PCIE_CONTROLLERS SC_BXTP_PCIE_MAX_CONTROLLERS +#define SC_PCIE_CONTROLLER_PORTS 4 +#define SC_BXT_PCIE_MAX_CONTROLLERS 1 +#define SC_BXTX_PCIE_MAX_CONTROLLERS 1 +#define SC_BXTP_PCIE_MAX_CONTROLLERS 2 + +#define SC_PCIE_MAX_CLK_REQ 4 + +// +// PCIe clocks limits +// +#define SC_MAX_PCIE_CLOCKS 6 + +// +// SATA limits +// +#define SC_MAX_SATA_PORTS 2 +#define SC_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define HSIC_MAX_PORTS 2 +#define XHCI_MAX_USB3_PORTS 1 +#define XHCI_MAX_HSIC_PORTS 1 ///< BXT has only 1 HSIC port +#define XHCI_MAX_SSIC_PORTS 2 ///< BXT has 2 SSIC port + +#define SC_MAX_USB2_PORTS SC_BXTP_MAX_USB2_PORTS +#define SC_BXT_MAX_USB2_PORTS 3 +#define SC_BXTP_MAX_USB2_PORTS 8 + +#define SC_MAX_USB3_PORTS SC_BXTP_MAX_USB3_PORTS +#define SC_BXT_MAX_USB3_PORTS 2 +#define SC_BXTP_MAX_USB3_PORTS 6 + +// +// Flash Protection Range Register +// +#define SC_FLASH_PROTECTED_RANGES 5 + +#endif ///< _SC_LIMITS_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPolicyCommon.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPolicyCommon.h new file mode 100644 index 0000000000..94fe5c53e6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPolicyCommon.h @@ -0,0 +1,69 @@ +/** @file + SC configuration based on SC policy. + + Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_POLICY_COMMON_H_ +#define _SC_POLICY_COMMON_H_ + +#include +#include +#include "ConfigBlock/ScGeneralConfig.h" +#include "ConfigBlock/SataConfig.h" +#include "ConfigBlock/PcieRpConfig.h" +#include "ConfigBlock/HpetConfig.h" +#include "ConfigBlock/SmbusConfig.h" +#include "ConfigBlock/IoApicConfig.h" +#include "ConfigBlock/HdAudioConfig.h" +#include "ConfigBlock/GmmConfig.h" +#include "ConfigBlock/PmConfig.h" +#include "ConfigBlock/LockDownConfig.h" +#include "ConfigBlock/SerialIrqConfig.h" +#include "ConfigBlock/ScsConfig.h" +#include "ConfigBlock/LpssConfig.h" +#include "ConfigBlock/VtdConfig.h" +#include "ConfigBlock/IshConfig.h" +#include "ConfigBlock/UsbConfig.h" +#include "ConfigBlock/FlashProtectionConfig.h" +#include "ConfigBlock/DciConfig.h" +#include "ConfigBlock/P2sbConfig.h" +#include "ConfigBlock/ScInterruptAssign.h" + +#pragma pack (push,1) + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + +// +// Generic definitions for device enabling/disabling used by SC code. +// +#define DEVICE_ENABLE 1 +#define DEVICE_DISABLE 0 + +#define SC_POLICY_REVISION 2 + +struct SC_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +}; + +#pragma pack (pop) + +#endif // _SC_POLICY_COMMON_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPreMemPolicyCommon.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPreMemPolicyCommon.h new file mode 100644 index 0000000000..9e3b3d89db --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScPreMemPolicyCommon.h @@ -0,0 +1,34 @@ +/** @file + PCH configuration based on PCH policy. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PREMEM_POLICY_COMMON_H_ +#define _SC_PREMEM_POLICY_COMMON_H_ + +#include +#include "ScLimits.h" +#include "ConfigBlock/LpcConfig.h" +#include "ConfigBlock/PcieRpConfig.h" + +#pragma pack (push,1) +#define SC_PREMEM_POLICY_REVISION 1 + +typedef struct _SC_PREMEM_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +} SC_PREMEM_POLICY; + +#pragma pack (pop) + +#endif // _PCH_PREMEM_POLICY_COMMON_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsGpio.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsGpio.h new file mode 100644 index 0000000000..3056829d1d --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsGpio.h @@ -0,0 +1,61 @@ +/** @file + Register names for SC private chipset register + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_REGS_GPIO_H_ +#define _SC_REGS_GPIO_H_ + +// +// GPIO Common Private Configuration Registers +// +#define R_PCR_GPIO_PADCFGLOCK_0 0x60 +#define R_PCR_GPIO_PADCFGLOCKTX_0 0x64 +#define R_PCR_GPIO_PADCFGLOCK_1 0x68 +#define R_PCR_GPIO_PADCFGLOCKTX_1 0x6C +#define R_PCR_GPIO_PADCFGLOCK_2 0x70 +#define R_PCR_GPIO_PADCFGLOCKTX_2 0x74 + +#define R_PCR_GPIO_SMI_STS_0 0x140 +#define R_PCR_GPIO_SMI_STS_1 0x144 +#define R_PCR_GPIO_SMI_STS_2 0x148 +#define R_PCR_GPIO_SMI_EN_0 0x150 +#define R_PCR_GPIO_SMI_EN_1 0x154 +#define R_PCR_GPIO_SMI_EN_2 0x158 +#define S_GPIO_GP_SMI_EN 4 +#define S_GPIO_GP_SMI_STS 4 +#define V_GPIO_NUM_SUPPORTED_GPIS 248 + +#define B_GPIO_IOSSTATE (BIT17 | BIT16 | BIT15 | BIT14) ///< IO Standby State +#define N_GPIO_IOSSTATE 14 +#define B_GPIO_IOSTERM (BIT9 | BIT8) ///< IO Standby Termination +#define N_GPIO_IOSTERM 8 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsHda.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsHda.h new file mode 100644 index 0000000000..e93256c9a5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsHda.h @@ -0,0 +1,562 @@ +/** @file + Register names for SC High Definition Audio device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_HDA_H_ +#define _REGS_HDA_H_ + +/// +/// HD-Audio Controller Registers (D14:F0) +/// +#define PCI_DEVICE_NUMBER_HDA 14 +#define PCI_FUNCTION_NUMBER_HDA 0 + +#define R_HDA_DEVVENID 0x00 ///< Device / Vendor ID +#define B_HDA_DEVVENID_DEVICE_ID 0xFFFF0000 ///< Device ID +#define B_HDA_DEVVENID_VENDOR_ID 0x0000FFFF ///< Vendor ID +#define V_HDA_DEVVENID_VENDOR_ID V_INTEL_VENDOR_ID ///< Intel Vendor ID +#define V_HDA_DEVICE_ID_0 0x2284 +#define V_HDA_DEVICE_ID_1 0x2285 + +#define R_HDA_STSCMD 0x04 ///< Status Command +#define B_HDA_STSCMD_SSE BIT30 ///< SERR Status +#define B_HDA_STSCMD_RMA BIT29 ///< Received Master Abort +#define B_HDA_STSCMD_CAP_LST BIT20 ///< Capabilities List +#define B_HDA_STSCMD_INTR_STS BIT19 ///< Interrupt Status +#define B_HDA_STSCMD_INTR_DIS BIT10 ///< Interrupt Disable +#define B_HDA_STSCMD_SERR_EN BIT8 ///< SERR Enable +#define B_HDA_STSCMD_BME BIT2 ///< Bus Master Enable +#define B_HDA_STSCMD_MSE BIT1 ///< Memory Space Enable + +#define R_HDA_RID_CC 0x08 ///< Revision ID and Class Code +#define B_HDA_RID_CC_BCC 0xFF000000 ///< Base Class Code +#define B_HDA_RID_CC_SCC 0x00FF0000 ///< Sub Class Code +#define B_HDA_RID_CC_PI 0x0000FF00 ///< Programming Interface +#define B_HDA_RID_CC_RID 0x000000FF ///< Revision Identification + +#define R_HDA_CLS 0x0C ///< Cache Line Size +#define B_HDA_CLS 0xFF ///< Cache Line Size + +#define R_HDA_LT 0x0D ///< Latency Timer +#define B_HDA_LT 0xFF ///< Latency Timer + +#define R_HDA_HEADTYPE 0x0E ///< Header Type +#define B_HDA_HEADTYPE 0xFF ///< Header Type + +#define R_HDA_HDBARL 0x10 ///< HDA CTL Memory BAR Lower +#define B_HDA_HDBARL_LBA 0xFFFFC000 ///< Lower Base Address +#define B_HDA_HDBARL_PREF BIT3 ///< Prefetchable +#define B_HDA_HDBARL_ADDRNG (BIT2 | BIT1) ///< Address Range +#define B_HDA_HDBARL_SPTYP BIT0 ///< Space Type (Memory) +#define V_HDA_HDBARL_SIZE (1 << 14) +#define N_HDA_HDBARL_ALIGNMENT 14 + +#define R_HDA_HDBARU 0x14 ///< HDA CTL Memory BAR Upper +#define B_HDA_HDBARU_UBA 0xFFFFFFFF ///< Upper Base Address + +#define R_HDA_SPCBARL 0x18 ///< Shadowed PCI Config Lower Base Address +#define B_HDA_SPCBARL_LBA 0xFFFFF000 ///< Lower Base Address + +#define R_HDA_SVID 0x2C ///< Sub System Vendor ID +#define B_HDA_SVID 0xFFFF + +#define R_HDA_SSID 0x2E ///< Sub System ID +#define B_HDA_SSID 0xFFFF + +#define R_HDA_CAPPTR 0x34 ///< Capabilities Pointer +#define B_HDA_CAPPTR 0xFF ///< Capabilities Pointer + +#define R_HDA_INTLN 0x3C ///< Interrupt Line +#define B_HDA_INTLN 0xFF ///< Interrupt Line +#define V_HDA_INTLN 0x19 ///< IRQ + +#define R_HDA_INTPN 0x3D ///< Interrupt Pin +#define B_HDA_INTPN 0x0F ///< Interrupt Pin + +#define R_HDA_HDCTL 0x40 ///< Azalia Control +#define B_HDA_HDCTL_MODE BIT0 ///< Azalia or AC97 + +#define R_HDA_IOBC 0x42 ///< IO Buffer Control +#define B_HDA_IOBC_ASRC (BIT5 | BIT4) ///< Audio Buffer Slew Rate Control +#define B_HDA_IOBC_AVDDIS BIT2 ///< Automatic Voltage Detector Disable +#define B_HDA_IOBC_MVSEL BIT1 ///< Manual Voltage Select +#define B_HDA_IOBC_VMODE BIT0 ///< Voltage Mode + +#define R_HDA_TM1 0x43 ///< Test Mode 1 +#define B_HDA_TM1_FRESET BIT7 ///< Fast Reset +#define B_HDA_TM1_ACCD BIT6 ///< Audio Crypto Disable +#define B_HDA_TM1_BCSS BIT4 ///< Bclk Source Select +#define B_HDA_TM1_HAPD BIT3 ///< HD Audio PCI/PCIe # Device +#define B_HDA_TM1_MDCGEN BIT2 ///< Misc Dynamic Clock Gating Enable +#define B_HDA_TM1_IDCGEN BIT1 ///< IDMA Dynamic Clock Gating Enable +#define B_HDA_TM1_ODCGEN BIT0 ///< ODMA Dynamic Clock Gating Enable + + +#define R_HDA_PID 0x50 ///< Power Management Capability ID +#define B_HDA_PID_NEXT 0xFF00 ///< Next Capability +#define B_HDA_PID_CAP 0x00FF ///< Capability ID +#define N_HDA_PID_CAP 8 + + +#define R_HDA_MID 0x60 ///< MSI Capability ID +#define B_HDA_MID_NEXT 0xFF00 ///< Next Capability +#define B_HDA_MID_CAP 0x00FF ///< capability ID + +#define R_HDA_MMC 0x62 ///< MSI Message Control +#define B_HDA_MMC_64ADD BIT7 ///< 64-bit Address Support +#define B_HDA_MMC_MME (BIT6 | BIT5 | BIT4) ///< Multiple Message Enable +#define B_HDA_MMC_MMC (BIT3 | BIT2 | BIT1) ///< Multiple Message Capable +#define B_HDA_MMC_ME BIT0 ///< MSI Enable + +#define R_HDA_MMLA 0x64 ///< MSI Lower Address +#define B_HDA_MMLA 0xFFFFFFFC ///< MSI Lower Address + +#define R_HDA_MMUA 0x68 ///< MSI Upper Address +#define B_HDA_MMUA 0xFFFFFFFF ///< MSI Upper Address + +#define R_HDA_MMD 0x6C ///< MSI Data +#define B_HDA_MMD 0xFFFF ///< MSI Data + +#define R_HDA_PXID 0x70 ///< PCIe Capability ID +#define B_HDA_PXID_NEXT 0xFF00 ///< Next capability +#define B_HDA_PXID_CAP 0x00FF ///< Capability ID + +#define R_HDA_PXC 0x72 ///< PCI Express Capabilities +#define B_HDA_PXC_IMN 0x3E00 ///< Interrupt Message Number +#define B_HDA_PXC_SI BIT8 ///< Slot Implemented +#define B_HDA_PXC_DPT 0x00F0 ///< Device / Port Type +#define B_HDA_PXC_CV 0x000F ///< Capability Version + +#define R_HDA_DEVCAP 0x74 ///< Device Capabilities +#define B_HDA_DEVCAP_FLR BIT28 ///< Function Level Reset +#define B_HDA_DEVCAP_SPLS (BIT27 | BIT26) ///< Captured Slot Power Limit Scale +#define B_HDA_DEVCAP_SPLV 0x03FC0000 ///< Captured Slot Power Limit Value +#define B_HDA_DEVCAP_PWRIP BIT14 ///< Power Indicator Present +#define B_HDA_DEVCAP_ATTNIP BIT13 ///< Attention Indicator Present +#define B_HDA_DEVCAP_ATTNBP BIT12 ///< Attention Button Present +#define B_HDA_DEVCAP_EL1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency +#define B_HDA_DEVCAP_EL0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency +#define B_HDA_DEVCAP_ETFS BIT5 ///< Extended Tag Field Support +#define B_HDA_DEVCAP_PFS (BIT4 | BIT3) ///< Phantom Functions Supported +#define B_HDA_DEVCAP_MPSS (BIT2 | BIT1 | BIT0) ///< Max Payload Size Supported + +#define R_HDA_DEVC 0x78 ///< Device Control +#define B_HDA_DEVC_IF BIT15 ///< Initiate FLR +#define B_HDA_DEVC_MRRS (BIT14 | BIT13 | BIT12) ///< Max Read Request Size +#define B_HDA_DEVC_NSNPEN BIT11 ///< Enable No Snoop +#define B_HDA_DEVC_APE BIT10 ///< Auxiliary Power PM Enable +#define B_HDA_DEVC_PFE BIT9 ///< Phantom Function Enable +#define B_HDA_DEVC_ETFE BIT8 ///< Extended Tag Field Enable +#define B_HDA_DEVC_MPS (BIT7 | BIT6 | BIT5) ///< Max Payload Size +#define B_HDA_DEVC_ERO BIT4 ///< Enable Relaxed Ordering +#define B_HDA_DEVC_URRE BIT3 ///< Unsupported Request Reporting Enable +#define B_HDA_DEVC_FERE BIT2 ///< Fatal Error Reporting Enable +#define B_HDA_DEVC_NFERE BIT1 ///< Non-Fatal Error Reporting Enable +#define B_HDA_DEVC_CERE BIT0 ///< Correctable Error Reporting Enable + +#define R_HDA_DEVS 0x7A ///< Device Status +#define B_HDA_DEVS_TP BIT5 ///< Transactions Pending +#define B_HDA_DEVS_AUXPD BIT4 ///< AUX Power Detected +#define B_HDA_DEVS_URD BIT3 ///< Unsupported Request Detected +#define B_HDA_DEVS_FED BIT2 ///< Fatal Error Detected +#define B_HDA_DEVS_NFED BIT1 ///< Non-Fatal Error Detected +#define B_HDA_DEVS_CED BIT0 ///< Correctable Error Detected + +#define R_HDA_VSCID 0x80 ///< Vendor Specific Capabilities Identifiers + + +#define R_HDA_VCCAP 0x100 ///< Virtual Channel Cap Header +#define B_HDA_VCCAP_NCO 0xFFF00000 ///< Next capability Offset +#define B_HDA_VCCAP_CAPVER 0x000F0000 ///< Capability Version +#define B_HDA_VCCAP_PCIEEC 0x0000FFFF ///< PCI Express Extended Capability ID + +#define R_HDA_PVCCAP1 0x104 ///< Port VC Capability +#define B_HDA_PVCCAP1_PATES 0x00000C00 ///< Port Arbitration Table Entry Size +#define B_HDA_PVCCAP1_RC 0x00000300 ///< Reference Clock +#define B_HDA_PVCCAP1_LPEVCC 0x00000070 ///< Low Priority Extended VC Count +#define B_HDA_PVCCAP1_EVCC 0x00000007 ///< Extended VC Count + +#define R_HDA_PVCCAP2 0x108 ///< Port VC Capability 2 +#define B_HDA_PVCCAP2_VCATO 0xFF000000 ///< VC Arbitration Table Offset +#define B_HDA_PVCCAP2_VCAC 0x000000FF ///< VC Arbitration Capability + +#define R_HDA_PVCCTL 0x10C ///< VC Port Control +#define B_HDA_PVCCTL_VCAS 0x000E ///< VC Arbitration Select +#define B_HDA_PVCCTL_LVCAT 0x0001 ///< Load VC Arbitration Table + +#define R_HDA_PVCSTS 0x10E ///< Port VC Status +#define B_HDA_PVCSTS_VCATS BIT0 ///< VC Arbitration Table Status + +#define R_HDA_VC0CAP 0x110 ///< VC0 Resource Capability +#define S_HDA_VC0CAP 4 +#define B_HDA_VC0CAP_PATO 0xFF000000 ///< Port Arbitration Table Offset +#define B_HDA_VC0CAP_MTS 0x007F0000 ///< Maximum Time Slot +#define B_HDA_VC0CAP_RST BIT15 ///< Reject Snoop Transactions +#define B_HDA_VC0CAP_APS BIT14 ///< Advanced Packet Switching +#define B_HDA_VC0CAP_PAC 0x000000FF ///< Port Arbitration Capability + +#define R_HDA_VC0CTL 0x114 ///< VC0 Resource Control +#define S_HDA_VC0CTL 4 +#define B_HDA_VC0CTL_VC0EN BIT31 ///< VC0 Enable +#define B_HDA_VC0CTL_VC0ID 0x07000000 ///< VC0 ID +#define B_HDA_VC0CTL_PAS 0x000E0000 ///< Port Arbitration Select +#define B_HDA_VC0CTL_LPAT BIT16 ///< Load Port Arbitration Table +#define B_HDA_VC0CTL_TCVC0_MAP 0x000000FE ///< TC / VC0 Map + +#define R_HDA_VC0STS 0x11A ///< VC0 Resource Status +#define S_HDA_VC0STS 2 +#define B_HDA_VC0STS_VC0NP BIT1 ///< VC0 Negotiation Pending +#define B_HDA_VC0STS_PATS BIT0 ///< Port Arbitration Table Status + +#define R_HDA_VCICAP 0x11C ///< VCi Resource Capabilities +#define S_HDA_VCICAP 4 +#define B_HDA_VCICAP_PATO 0xFF000000 ///< Port Arbitration Table Offset +#define B_HDA_VCICAP_MTS 0x007F0000 ///< Maximum Time Slots +#define B_HDA_VCICAP_RST BIT15 ///< Reject Snoop Transactions +#define B_HDA_VCICAP_APS BIT14 ///< Advanced Packet Switching +#define B_HDA_VCICAP_PAC 0x000000FF ///< Port Arbitration Capability + +#define R_HDA_VCICTL 0x120 ///< VCi Control Register +#define S_HDA_VCICTL 4 +#define B_HDA_VCICTL_EN BIT31 ///< VCi Enable +#define B_HDA_VCICTL_ID (BIT26 | BIT25 | BIT24) ///< VCi ID +#define V_HDA_VCICTL_PAS 0x000E0000 ///< Port Arbitration Select +#define V_HDA_VCICTL_LPAT BIT16 ///< Load Port Arbitration Table +#define B_HDA_VCICTL_TCVCI_MAP 0x000000FE ///< TC / VCi Map + +#define R_HDA_VCISTS 0x126 ///< VCi Resource Status +#define S_HDA_VCISTS 1 +#define B_HDA_VCISTS_VCINP BIT1 ///< VCi Negotiation Pending +#define B_HDA_VCISTS_PATS BIT0 ///< Port Arbitration Table Status + +#define R_HDA_RCCAP 0x130 ///< Root Complex Link Declaration Capability Header +#define B_HDA_RCCAP_NCO 0xFFF00000 ///< Next Capability Offset +#define B_HDA_RCCAP_CV 0x000F0000 ///< Capability Version +#define B_HDA_RCCAP_PCIEECID 0x0000FFFF ///< PCI Express Extended Capability ID + +#define R_HDA_ESD 0x134 ///< Element Self Description +#define B_HDA_ESD_PN 0xFF000000 ///< Port Number +#define B_HDA_ESD_CID 0x00FF0000 ///< Number of Link Entries +#define B_HDA_ESD_ELTYP 0x0000000F ///< Element Type + +#define R_HDA_L1DESC 0x140 ///< Link 1 Description +#define S_HDA_L1DESC 4 +#define B_HDA_LIDESC_TPN 0xFF000000 ///< Target Port Number +#define B_HDA_LIDESC_TCID 0x00FF0000 ///< Target Component ID +#define B_HDA_LIDESC_LT BIT1 ///< Link Type +#define B_HDA_LIDESC_LV BIT0 ///< Link Valid + +#define R_HDA_L1ADDL 0x148 ///< Link 1 Lower Address +#define B_HDA_L1ADDL_LNK1LA 0xFFFFC000 ///< Link 1 Lower Address + +#define R_HDA_L1ADDU 0x14C ///< Link 1 Upper Address +#define B_HDA_L1ADDU 0xFFFFFFFF ///< Link 1 Upper Address + +/// +/// Intel High Definition Audio Memory Mapped Configuration Registers +/// +#define R_HDA_GCAP 0x00 ///< Global Capabilities +#define S_HDA_GCAP 2 +#define B_HDA_GCAP_NOSSUP 0xF000 ///< Number of Output Streams Supported +#define B_HDA_GCAP_NISSUP 0x0F00 ///< Number of Input Streams Supported +#define B_HDA_GCAP_NBSSUP 0x00F8 ///< Number of Bidirectional Streams Supported +#define B_HDA_GCAP_NSDOS (BIT2 | BIT1) ///< Number of Serial Data Out Signals +#define B_HDA_GCAP_64ADSUP BIT0 ///< 64bit Address Supported + +#define R_HDA_VMIN 0x02 ///< Minor Version +#define B_HDA_VMIN_MV 0xFF ///< Minor Version + +#define R_HDA_VMAJ 0x03 ///< Major Version +#define B_HDA_VMAJ_MV 0xFF ///< Major Version + +#define R_HDA_OUTPAY 0x04 ///< Output Payload Capability +#define B_HDA_OUTPAY_CAP 0xFFFF ///< Output Payload Capability + +#define R_HDA_INPAY 0x06 ///< Input Payload Capability +#define B_HDA_INPAY_CAP 0xFFFF ///< Input Payload Capability +#define V_HDA_INPAY_DEFAULT 0x1C + +#define R_HDA_GCTL 0x08 ///< Global Control +#define B_HDA_GCTL_AURE BIT8 ///< Accept Unsolicited Response Enable +#define B_HDA_GCTL_FC BIT1 ///< Flush Control +#define B_HDA_GCTL_CRST BIT0 ///< Controller Reset + +#define R_HDA_WAKEEN 0x0C ///< Wake Enable +#define B_HDA_WAKEEN_SDI_3 BIT3 ///< SDIN Wake Enable Flag 3 +#define B_HDA_WAKEEN_SDI_2 BIT2 ///< SDIN Wake Enable Flag 2 +#define B_HDA_WAKEEN_SDI_1 BIT1 ///< SDIN Wake Enable Flag 1 +#define B_HDA_WAKEEN_SDI_0 BIT0 ///< SDIN Wake Enable Flag 0 + +#define R_HDA_STATESTS 0x0E ///< Wake Status +#define B_HDA_STATESTS_SDIN3 BIT3 ///< SDIN State Change 3 +#define B_HDA_STATESTS_SDIN2 BIT2 ///< SDIN State Change 2 +#define B_HDA_STATESTS_SDIN1 BIT1 ///< SDIN State Change 1 +#define B_HDA_STATESTS_SDIN0 BIT0 ///< SDIN State Change 0 + +#define R_HDA_GSTS 0x10 ///< Global Status +#define B_HDA_GSTS_FS BIT1 ///< Flush Status + +#define R_HDA_OUTSTRMPAY 0x18 ///< Output Stream Payload Capability +#define S_HDA_OUTSTRMPAY 2 +#define B_HDA_OUTSTRMPAY_OUTSTRMPAY 0xFFFF ///< Output Stream Payload Capability + +#define R_HDA_INSTRMPAY 0x1A ///< Input Stream Payload Capability +#define B_HDA_INSTRMPAY_INSTRMPAY 0xFFFF ///< Input Stream Payload Capability + +#define R_HDA_INTCTL 0x20 ///< Interrupt Control +#define B_HDA_INTCTL_GIE BIT31 ///< Global Interrupt Enable +#define B_HDA_INTCTL_CIE BIT30 ///< Controller Interrupt Enable +#define B_HDA_INTCTL_SIE_OS4 BIT7 ///< Stream Interrupt Enable - Output Stream 4 +#define B_HDA_INTCTL_SIE_OS3 BIT6 ///< Stream Interrupt Enable - Output Stream 3 +#define B_HDA_INTCTL_SIE_OS2 BIT5 ///< Stream Interrupt Enable - Output Stream 2 +#define B_HDA_INTCTL_SIE_OS1 BIT4 ///< Stream Interrupt Enable - Output Stream 1 +#define B_HDA_INTCTL_SIE_IS4 BIT3 ///< Stream Interrupt Enable - Input Stream 4 +#define B_HDA_INTCTL_SIE_IS3 BIT2 ///< Stream Interrupt Enable - Input Stream 3 +#define B_HDA_INTCTL_SIE_IS2 BIT1 ///< Stream Interrupt Enable - Input Stream 2 +#define B_HDA_INTCTL_SIE_IS1 BIT0 ///< Stream Interrupt Enable - Input Stream 1 + +#define R_HDA_INTSTS 0x24 ///< Interrupt Status +#define B_HDA_INTSTS_GIS BIT31 ///< Global Interrupt Status +#define B_HDA_INTSTS_CIS BIT30 ///< Controller Interrupt Status +#define B_HDA_INTSTS_SIS_OS4 BIT7 ///< Stream Interrupt Status - Output Stream 4 +#define B_HDA_INTSTS_SIS_OS3 BIT6 ///< Stream Interrupt Status - Output Stream 3 +#define B_HDA_INTSTS_SIS_OS2 BIT5 ///< Stream Interrupt Status - Output Stream 2 +#define B_HDA_INTSTS_SIS_OS1 BIT4 ///< Stream Interrupt Status - Output Stream 1 +#define B_HDA_INTSTS_SIS_IS4 BIT3 ///< Stream Interrupt Enable - Input Stream 4 +#define B_HDA_INTSTS_SIS_IS3 BIT2 ///< Stream Interrupt Enable - Input Stream 3 +#define B_HDA_INTSTS_SIS_IS2 BIT1 ///< Stream Interrupt Enable - Input Stream 2 +#define B_HDA_INTSTS_SIS_IS1 BIT0 ///< Stream Interrupt Enable - Input Stream 1 + +#define R_HDA_WALCLK 0x30 ///< Wall Clock Counter +#define B_HDA_WALCLK_WCC 0xFFFFFFFF ///< Wall Clock Counter + +#define R_HDA_SSYNC 0x38 ///< Stream Synchronization +#define S_HDA_SSYNC 4 +#define B_HDA_SSYNC_OS4 BIT7 ///< Stream Synchronization - Output Stream 4 +#define B_HDA_SSYNC_OS3 BIT6 ///< Stream Synchronization - Output Stream 3 +#define B_HDA_SSYNC_OS2 BIT5 ///< Stream Synchronization - Output Stream 2 +#define B_HDA_SSYNC_OS1 BIT4 ///< Stream Synchronization - Output Stream 1 +#define B_HDA_SSYNC_IS4 BIT3 ///< Stream Synchronization - Input Stream 4 +#define B_HDA_SSYNC_IS3 BIT2 ///< Stream Synchronization - Input Stream 3 +#define B_HDA_SSYNC_IS2 BIT1 ///< Stream Synchronization - Input Stream 2 +#define B_HDA_SSYNC_IS1 BIT0 ///< Stream Synchronization - Input Stream 1 + +#define R_HDA_CORBLBASE 0x40 ///< CORB Lower Base Address +#define B_HDA_CORBLBASE_BA 0xFFFFFF80 ///< CORB Lower Base Address +#define B_HDA_CORBLBASE_UB 0x0000007F ///< CORB Lower Base Unimplemented Bits + +#define R_HDA_CORBUBASE 0x44 ///< CORB Upper Base Address +#define B_HDA_CORBUBASE_BA 0xFFFFFFFF ///< CORB Upper Base Address + +#define R_HDA_CORBWP 0x48 ///< CORB Write Pointer +#define B_HDA_CORBWP 0x000000FF ///< CORB Write Pointer + +#define R_HDA_CORBRP 0x4A ///< CORB Read Pointer +#define B_HDA_CORBRP_PRST BIT15 ///< CORB Read Pointer Reset +#define B_HDA_CORBRP_RP 0x00FF ///< CORB Read Pointer + +#define R_HDA_CORBCTL 0x4C ///< CORB Control +#define B_HDA_CORBCTL_DMA_EN BIT1 ///< Enable CORB DMA Engine +#define B_HDA_CORBCTL_MEMERRINTR_EN BIT0 ///< CORB Memory Error Interrupt Enable + +#define R_HDA_CORBST 0x4D ///< CORB Status +#define B_HDA_CORBST_CMEI BIT0 ///< CORB Memory Error Indication + +#define R_HDA_CORBSIZE 0x4E ///< CORB Size +#define B_HDA_CORBSIZE_CAP 0xF0 ///< CORB Size Capability +#define B_HDA_CORBSIZE_SIZE (BIT1 | BIT0) ///< CORB Size + +#define R_HDA_RIRBLBASE 0x50 ///< RIRB Lower Base Address +#define B_HDA_RIRBLBASE_BA 0xFFFFFF80 ///< RIRB Lower Base Address +#define B_HDA_RIRBLBASE_UB 0x0000007F ///< RIRB Lower Base Unimplemented Bits + +#define R_HDA_RIRBUBASE 0x54 ///< RIRB Upper Base Address +#define B_HDA_RIRBUBASE_BA 0xFFFFFFFF ///< RIRB Upper Base Address + +#define R_HDA_RIRBWP 0x58 ///< RIRB Write Pointer +#define B_HDA_RIRBWP_RST BIT15 ///< RIRB Write Pointer Reset +#define B_HDA_RIRBWP_WP 0x00FF ///< RIRB Write Pointer + +#define R_HDA_RINTCNT 0x5A ///< Response Interrupt Count +#define B_HDA_RINTCNT 0x00FF ///< Number of Response Interrupt Count + +#define R_HDA_RIRBCTL 0x5C ///< RIRB Control +#define B_HDA_RIRBCTL_ROIC BIT2 ///< Response Overrun Interrupt Control +#define B_HDA_RIRBCTL_DMA BIT1 ///< RIRB DMA Enable +#define B_HDA_RIRBCTL_RIC BIT0 ///< Response Interrupt Control + +#define R_HDA_RIRBSTS 0x5D ///< RIRB Status +#define B_HDA_RIRBSTS_ROIS BIT2 ///< Response Overrun Interrupt Status +#define B_HDA_RIRBSTS_RI BIT0 ///< Response Interrupt + +#define R_HDA_RIRBSIZE 0x5E ///< RIRB Size +#define B_HDA_RIRBSIZE_CAP 0xF0 ///< RIRB Size Capability +#define B_HDA_RIRBSIZE_SIZE 0x03 ///< RIRB Size + +#define R_HDA_DPLBASE 0x70 ///< DMA Position Lower Base Address +#define B_HDA_DPLBASE_LBA 0xFFFFFF80 ///< DMA Position Lower Base Address +#define B_HDA_DPLBASE_LBU 0x0000007E ///< DMA Position Lower Base Unimplemented Bits +#define B_HDA_DPLBASE_BUF_EN 0x00000001 ///< DMA Position Buffer Enable + +#define R_HDA_DPUBASE 0x74 ///< DMA Position Upper Base Address +#define B_HDA_DPUBASE_UBA 0xFFFFFFFF ///< DMA Position Upper Base Address + +#define R_HDA_ISD0CTL_STS 0x80 ///< Input Stream Descriptor 0 Control and Status +#define R_HDA_ISD1CTL_STS 0xA0 ///< Input Stream Descriptor 1 Control and Status +#define R_HDA_ISD2CTL_STS 0xC0 ///< Input Stream Descriptor 2 Control and Status +#define R_HDA_ISD3CTL_STS 0xE0 ///< Input Stream Descriptor 3 Control and Status +#define R_HDA_OSD0CTL_STS 0x100 ///< Output Stream Descriptor 0 Control and Status +#define R_HDA_OSD1CTL_STS 0x120 ///< Output Stream Descriptor 1 Control and Status +#define R_HDA_OSD2CTL_STS 0x140 ///< Output Stream Descriptor 2 Control and Status +#define R_HDA_OSD3CTL_STS 0x160 ///< Output Stream Descriptor 3 Control and Status +#define B_HDA_XSDXCTL_STS_FIFORDY BIT29 ///< FIFO Ready +#define B_HDA_XSDXCTL_STS_DE BIT28 ///< Descriptor Error +#define B_HDA_XSDXCTL_STS_FIFO_ERROR BIT27 ///< FIFO Error +#define B_HDA_XSDXCTL_STS_BUF_COMPINTR_STS BIT26 ///< Buffer Completion Interrupt Status +#define B_HDA_XSDXCTL_STS_SN (BIT23 | BIT22 | BIT21 | BIT20) ///< Stream Number +#define B_HDA_XSDXCTL_STS_BDC BIT19 ///< Bidirectional Direction Control +#define B_HDA_XSDXCTL_STS_TP BIT18 ///< Traffic Priority +#define B_HDA_XSDXCTL_STS_SC (BIT17 | BIT16) ///< Stripe Control +#define B_HDA_XSDXCTL_STS_DEIE BIT4 ///< Descriptor Error Interrupt Enable +#define B_HDA_XSDXCTL_STS_FIFO_ERRINT_EN BIT3 ///< FIFO Error Interrupt Enable +#define B_HDA_XSDXCTL_STS_INTR_ONCOMP_EN BIT2 ///< Interrupt On Completion Enable +#define B_HDA_XSDXCTL_STS_RUN BIT1 ///< Stream Run +#define B_HDA_XSDXCTL_STS_SRST BIT0 ///< Stream Reset + +#define R_HDA_SDLPIB_IN_0 0x84 ///< Input Stream Descriptor 0 Link Position in Buffer +#define R_HDA_SDLPIB_IN_1 0xA4 ///< Input Stream Descriptor 1 Link Position in Buffer +#define R_HDA_SDLPIB_IN_2 0xC4 ///< Input Stream Descriptor 2 Link Position in Buffer +#define R_HDA_SDLPIB_IN_3 0xE4 ///< Input Stream Descriptor 3 Link Position in Buffer +#define R_HDA_SDLPIB_OUT_0 0x104 ///< Output Stream Descriptor 0 Link Position in Buffer +#define R_HDA_SDLPIB_OUT_1 0x124 ///< Output Stream Descriptor 1 Link Position in Buffer +#define R_HDA_SDLPIB_OUT_2 0x144 ///< Output Stream Descriptor 2 Link Position in Buffer +#define R_HDA_SDLPIB_OUT_3 0x164 ///< Output Stream Descriptor 3 Link Position in Buffer +#define B_HDA_SDLPIB_BUFFER 0xFFFFFFFF ///< Link Position In Buffer + +#define R_HDA_SDCBL_IN_0 0x88 ///< Input Stream Descriptor 0 Cyclic Buffer Length +#define R_HDA_SDCBL_IN_1 0xA8 ///< Input Stream Descriptor 1 Cyclic Buffer Length +#define R_HDA_SDCBL_IN_2 0xC8 ///< Input Stream Descriptor 2 Cyclic Buffer Length +#define R_HDA_SDCBL_IN_3 0xE8 ///< Input Stream Descriptor 3 Cyclic Buffer Length +#define R_HDA_SDCBL_OUT_0 0x108 ///< Output Stream Descriptor 0 Cyclic Buffer Length +#define R_HDA_SDCBL_OUT_1 0x128 ///< Output Stream Descriptor 1 Cyclic Buffer Length +#define R_HDA_SDCBL_OUT_2 0x148 ///< Output Stream Descriptor 2 Cyclic Buffer Length +#define R_HDA_SDCBL_OUT_3 0x168 ///< Output Stream Descriptor 3 Cyclic Buffer Length +#define B_HDA_SDCBL_BUFLNG 0xFFFFFFFF ///< Cyclic Buffer Length + +#define R_HDA_SDLVI_IN_0 0x8C ///< Input Stream Descriptor 0 Last Valid Index +#define R_HDA_SDLVI_IN_1 0xAC ///< Input Stream Descriptor 1 Last Valid Index +#define R_HDA_SDLVI_IN_2 0xCC ///< Input Stream Descriptor 2 Last Valid Index +#define R_HDA_SDLVI_IN_3 0xEC ///< Input Stream Descriptor 3 Last Valid Index +#define R_HDA_SDLVI_OUT_0 0x10C ///< Output Stream Descriptor 0 Last Valid Index +#define R_HDA_SDLVI_OUT_1 0x12C ///< Output Stream Descriptor 1 Last Valid Index +#define R_HDA_SDLVI_OUT_2 0x14C ///< Output Stream Descriptor 2 Last Valid Index +#define R_HDA_SDLVI_OUT_3 0x16C ///< Output Stream Descriptor 3 Last Valid Index +#define B_HDA_SDLVI_LVI 0x00FF ///< Last Valid Index + +#define R_HDA_SDFIFOW_IN_0 0x8E ///< Input Stream Descriptor 0 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_IN_1 0xAE ///< Input Stream Descriptor 1 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_IN_2 0xCE ///< Input Stream Descriptor 2 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_IN_3 0xEE ///< Input Stream Descriptor 3 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_OUT_0 0x10E ///< Output Stream Descriptor 0 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_OUT_1 0x12E ///< Output Stream Descriptor 1 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_OUT_2 0x14E ///< Output Stream Descriptor 2 FIFO Eviction Watermark +#define R_HDA_SDFIFOW_OUT_3 0x16E ///< Output Stream Descriptor 3 FIFO Eviction Watermark +#define V_HDA_SDFIFOW_FIFOW_32B 0x0004 ///< 32 Bytes +#define V_HDA_SDFIFOW_FIFOW_64B 0x0005 ///< 64 Bytes + +#define R_HDA_SDFIFOS_IN_0 0x90 ///< Input Stream Descriptor 0 FIFO Size +#define R_HDA_SDFIFOS_IN_1 0xB0 ///< Input Stream Descriptor 1 FIFO Size +#define R_HDA_SDFIFOS_IN_2 0xD0 ///< Input Stream Descriptor 2 FIFO Size +#define R_HDA_SDFIFOS_IN_3 0xF0 ///< Input Stream Descriptor 3 FIFO Size +#define R_HDA_SDFIFOS_OUT_0 0x110 ///< Output Stream Descriptor 0 FIFO Size +#define R_HDA_SDFIFOS_OUT_1 0x130 ///< Output Stream Descriptor 1 FIFO Size +#define R_HDA_SDFIFOS_OUT_2 0x150 ///< Output Stream Descriptor 2 FIFO Size +#define R_HDA_SDFIFOS_OUT_3 0x170 ///< Output Stream Descriptor 3 FIFO Size + +#define R_HDA_SDFMT_IN_0 0x92 ///< Input Stream Descriptor 0 Format +#define R_HDA_SDFMT_IN_1 0xB2 ///< Input Stream Descriptor 1 Format +#define R_HDA_SDFMT_IN_2 0xD2 ///< Input Stream Descriptor 2 Format +#define R_HDA_SDFMT_IN_3 0xF2 ///< Input Stream Descriptor 3 Format +#define R_HDA_SDFMT_OUT_0 0x112 ///< Output Stream Descriptor 0 Format +#define R_HDA_SDFMT_OUT_1 0x132 ///< Output Stream Descriptor 1 Format +#define R_HDA_SDFMT_OUT_2 0x152 ///< Output Stream Descriptor 2 Format +#define R_HDA_SDFMT_OUT_3 0x172 ///< Output Stream Descriptor 3 Format +#define B_HDA_SDFMT_SBR BIT14 ///< Sample Base Rate +#define B_HDA_SDFMT_SBRM (BIT13 | BIT12 | BIT11) ///< Sample Base Rate Multiple +#define B_HDA_SDFMT_SBRD (BIT10 | BIT9 | BIT8) ///< Sample Base Rate Divisor +#define B_HDA_SDFMT_BITS (BIT6 | BIT5 | BIT4) ///< Bits Per Sample +#define B_HDA_SDFMT_CHAN (BIT3 | BIT2 | BIT1 | BIT0) ///< Number of Channels + +#define R_HDA_SDBDPL_IN_0 0x98 ///< Input Stream Descriptor 0 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_IN_1 0xB8 ///< Input Stream Descriptor 1 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_IN_2 0xD8 ///< Input Stream Descriptor 2 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_IN_3 0xF8 ///< Input Stream Descriptor 3 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_OUT_0 0x118 ///< Output Stream Descriptor 0 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_OUT_1 0x138 ///< Output Stream Descriptor 1 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_OUT_2 0x158 ///< Output Stream Descriptor 2 Buffer Descriptor List Pointer +#define R_HDA_SDBDPL_OUT_3 0x178 ///< Output Stream Descriptor 3 Buffer Descriptor List Pointer +#define B_HDA_SDBDPL_LBA 0xFFFFFF80 ///< Buffer Descriptor List Lower Base Address + +#define R_HDA_SDBDPU_IN_0 0x9C ///< Input Stream Descriptor 0 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_IN_1 0xBC ///< Input Stream Descriptor 1 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_IN_2 0xDC ///< Input Stream Descriptor 2 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_IN_3 0xFC ///< Input Stream Descriptor 3 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_OUT_0 0x11C ///< Output Stream Descriptor 0 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_OUT_1 0x13C ///< Output Stream Descriptor 1 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_OUT_2 0x15C ///< Output Stream Descriptor 2 Buffer Descriptor List Pointer +#define R_HDA_SDBDPU_OUT_3 0x17C ///< Output Stream Descriptor 3 Buffer Descriptor List Pointer +#define B_HDA_SDBDPU_LBA 0xFFFFFFFF ///< Buffer Descriptor List Upper Base Address + +/// +/// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +/// +#define R_HDA_PPCH 0x0800 ///< Processing Pipe Capability Structure (Memory Space, offset 0800h) +#define R_HDA_PPCTL (R_HDA_PPCH + 0x04) +#define B_HDA_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define V_HDA_HDALINK_INDEX 0 +#define V_HDA_IDISPLINK_INDEX 1 + +#define R_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h) +#define R_HDABA_LCTLX(x) (R_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_HDABA_LCTLX_CPA BIT23 +#define B_HDABA_LCTLX_SPA BIT16 +#define N_HDABA_LCTLX_SCF 0 +#define V_HDABA_LCTLX_SCF_6MHZ 0x0 +#define V_HDABA_LCTLX_SCF_12MHZ 0x1 +#define V_HDABA_LCTLX_SCF_24MHZ 0x2 +#define V_HDABA_LCTLX_SCF_48MHZ 0x3 +#define V_HDABA_LCTLX_SCF_96MHZ 0x4 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsIsh.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsIsh.h new file mode 100644 index 0000000000..279dcc2a93 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsIsh.h @@ -0,0 +1,105 @@ +/** @file + Register names for Low Power Audio device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_ISH_H_ +#define _REGS_ISH_H_ + +/// +/// ISH Config Registers (D21:F0) +/// +#define PCI_DEVICE_NUMBER_ISH 17 +#define PCI_FUNCTION_NUMBER_ISH 0 + +#define R_ISH_DEVVENID 0x00 ///< Device / Vendor ID +#define B_ISH_DEVVENID_DEVICE_ID 0xFFFF0000 ///< Device ID +#define B_ISH_DEVVENID_VENDOR_ID 0x0000FFFF ///< Vendor ID +#define V_ISH_DEVVENID_VENDOR_ID V_INTEL_VENDOR_ID ///< Intel Vendor ID +#define V_ISH_DEVICE_ID_0 0x1AA2 + +#define R_ISH_STSCMD 0x04 ///< Status Command +#define B_ISH_STSCMD_RMA BIT29 ///< Received Master Abort +#define B_ISH_STSCMD_RCA BIT28 ///< RCA +#define B_ISH_STSCMD_CAP_LST BIT20 ///< Capabilities List +#define B_ISH_STSCMD_INTR_STS BIT19 ///< Interrupt Status +#define B_ISH_STSCMD_INTR_DIS BIT10 ///< Interrupt Disable +#define B_ISH_STSCMD_SERR_EN BIT8 ///< SERR Enable +#define B_ISH_STSCMD_BME BIT2 ///< Bus Master Enable +#define B_ISH_STSCMD_MSE BIT1 ///< Memory Space Enable + +#define R_ISH_RID_CC 0x08 ///< Revision ID and Class Code +#define B_ISH_RID_CC_BCC 0xFF000000 ///< Base Class Code +#define B_ISH_RID_CC_SCC 0x00FF0000 ///< Sub Class Code +#define B_ISH_RID_CC_PI 0x0000FF00 ///< Programming Interface +#define B_ISH_RID_CC_RID 0x000000FF ///< Revision Identification + +#define R_ISH_BAR0 0x10 ///< BAR 0 +#define B_ISH_BAR0_BA 0xFFE00000 ///< Base Address +#define V_ISH_BAR0_SIZE 0x200000 +#define N_ISH_BAR0_ALIGNMENT 21 +#define B_ISH_BAR0_PREF BIT3 ///< Prefetchable +#define B_ISH_BAR0_ADDRNG (BIT2 | BIT1) ///< Address Range +#define B_ISH_BAR0_SPTYP BIT0 ///< Space Type (Memory) + +#define R_ISH_BAR1 0x18 ///< BAR 1 +#define B_ISH_BAR1_BA 0xFFFFF000 ///< Base Address +#define B_ISH_BAR1_PREF BIT3 ///< Prefetchable +#define B_ISH_BAR1_ADDRNG (BIT2 | BIT1) ///< Address Range +#define B_ISH_BAR1_SPTYP BIT0 ///< Space Type (Memory) +#define V_ISH_BAR1_SIZE (1 << 12) + +#define R_ISH_SSID 0x2C ///< Sub System ID +#define B_ISH_SSID_SID 0xFFFF0000 ///< Sub System ID +#define B_ISH_SSID_SVID 0x0000FFFF ///< Sub System Vendor ID + +#define R_ISH_ERBAR 0x30 ///< Expansion ROM BAR +#define B_ISH_ERBAR_BA 0xFFFFFFFF ///< Expansion ROM Base Address + +#define R_ISH_CAPPTR 0x34 ///< Capability Pointer +#define B_ISH_CAPPTR_CPPWR 0xFF ///< Capability Pointer Power + +#define R_ISH_INTR 0x3C ///< Interrupt +#define B_ISH_INTR_ML 0xFF000000 ///< Max Latency +#define B_ISH_INTR_MG 0x00FF0000 +#define B_ISH_INTR_IP 0x00000F00 ///< Interrupt Pin +#define B_ISH_INTR_IL 0x000000FF ///< Interrupt Line + +#define R_ISH_PCS 0x84 ///< PME Control Status +#define B_ISH_PCS_PMESTS BIT15 ///< PME Status +#define B_ISH_PCS_PMEEN BIT8 ///< PME Enable +#define B_ISH_PCS_NSS BIT3 ///< No Soft Reset +#define B_ISH_PCS_PS (BIT1 | BIT0) ///< Power State + +/// +/// ISH MMIO Registers, accessed by MMIO +/// + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsItss.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsItss.h new file mode 100644 index 0000000000..8d3d6265fb --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsItss.h @@ -0,0 +1,138 @@ +/** @file + Register names for Interrupt Timer Sub System (ITSS) module. + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_ITSS_H_ +#define _REGS_ITSS_H_ + +/// +/// Interrupt Timer Sub System (ITSS) Module Registers +/// +/// +/// LPSS Private Sideband Registers +/// +#define R_ITSS_PORT_ID 0xD0 ///< ITSS port ID + +#define R_ITSS_SB_PARC 0x3100 ///< PIRQA Routing Control +#define R_ITSS_SB_PBRC 0x3101 ///< PIRQB Routing Control +#define R_ITSS_SB_PCRC 0x3102 ///< PIRQC Routing Control +#define R_ITSS_SB_PDRC 0x3103 ///< PIRQD Routing Control +#define R_ITSS_SB_PERC 0x3104 ///< PIRQE Routing Control +#define R_ITSS_SB_PFRC 0x3105 ///< PIRQF Routing Control +#define R_ITSS_SB_PGRC 0x3106 ///< PIRQG Routing Control +#define R_ITSS_SB_PHRC 0x3107 ///< PIRQH Routing Control + +#define N_ITSS_SB_REN 7 +#define V_ITSS_SB_REN_ENABLE (0 < + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_REGS_LPC_H_ +#define _SC_REGS_LPC_H_ + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +// +// BXT-P LPC Device IDs +// +#define V_SC_LPC_DEVICE_ID_BXT_P_0 0x5AE8 ///< BXT-P SKU + +#define V_PCH_LPC_RID_0 0x00 +#define V_PCH_LPC_RID_1 0x01 +#define V_PCH_LPC_RID_9 0x09 +#define R_PCH_LPC_SERIRQ_CNT 0x64 +#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80 +#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40 +#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C +#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2 +#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03 +#define N_PCH_LPC_SERIRQ_CNT_SFPW 0 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_PCH_LPC_IOD 0x80 +#define B_PCH_LPC_IOD_FDD 0x1000 +#define N_PCH_LPC_IOD_FDD 12 +#define V_PCH_LPC_IOD_FDD_3F0 0 +#define V_PCH_LPC_IOD_FDD_370 1 +#define B_PCH_LPC_IOD_LPT 0x0300 +#define N_PCH_LPC_IOD_LPT 8 +#define V_PCH_LPC_IOD_LPT_378 0 +#define V_PCH_LPC_IOD_LPT_278 1 +#define V_PCH_LPC_IOD_LPT_3BC 2 +#define B_PCH_LPC_IOD_COMB 0x0070 +#define N_PCH_LPC_IOD_COMB 4 +#define V_PCH_LPC_IOD_COMB_3F8 0 +#define V_PCH_LPC_IOD_COMB_2F8 1 +#define V_PCH_LPC_IOD_COMB_220 2 +#define V_PCH_LPC_IOD_COMB_228 3 +#define V_PCH_LPC_IOD_COMB_238 4 +#define V_PCH_LPC_IOD_COMB_2E8 5 +#define V_PCH_LPC_IOD_COMB_338 6 +#define V_PCH_LPC_IOD_COMB_3E8 7 +#define B_PCH_LPC_IOD_COMA 0x0007 +#define N_PCH_LPC_IOD_COMA 0 +#define V_PCH_LPC_IOD_COMA_3F8 0 +#define V_PCH_LPC_IOD_COMA_2F8 1 +#define V_PCH_LPC_IOD_COMA_220 2 +#define V_PCH_LPC_IOD_COMA_228 3 +#define V_PCH_LPC_IOD_COMA_238 4 +#define V_PCH_LPC_IOD_COMA_2E8 5 +#define V_PCH_LPC_IOD_COMA_338 6 +#define V_PCH_LPC_IOD_COMA_3E8 7 +#define R_PCH_LPC_IOE 0x82 +#define B_PCH_LPC_IOE_ME2 BIT13 +#define B_PCH_LPC_IOE_SE BIT12 +#define B_PCH_LPC_IOE_ME1 BIT11 +#define B_PCH_LPC_IOE_KE BIT10 +#define B_PCH_LPC_IOE_HGE BIT9 +#define B_PCH_LPC_IOE_LGE BIT8 +#define B_PCH_LPC_IOE_FDE BIT3 +#define B_PCH_LPC_IOE_PPE BIT2 +#define B_PCH_LPC_IOE_CBE BIT1 +#define B_PCH_LPC_IOE_CAE BIT0 +#define R_PCH_LPC_GEN1_DEC 0x84 +#define R_PCH_LPC_GEN2_DEC 0x88 +#define R_PCH_LPC_GEN3_DEC 0x8C +#define R_PCH_LPC_GEN4_DEC 0x90 +#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000 +#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC +#define B_PCH_LPC_GENX_DEC_EN 0x00000001 +#define R_PCH_LPC_ULKMC 0x94 +#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15 +#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11 +#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10 +#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9 +#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8 +#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7 +#define B_PCH_LPC_ULKMC_PSTATE BIT6 +#define B_PCH_LPC_ULKMC_A20PASSEN BIT5 +#define B_PCH_LPC_ULKMC_USBSMIEN BIT4 +#define B_PCH_LPC_ULKMC_64WEN BIT3 +#define B_PCH_LPC_ULKMC_64REN BIT2 +#define B_PCH_LPC_ULKMC_60WEN BIT1 +#define B_PCH_LPC_ULKMC_60REN BIT0 +#define R_PCH_LPC_LGMR 0x98 +#define B_PCH_LPC_LGMR_MA 0xFFFF0000 +#define B_PCH_LPC_LGMR_LMRD_EN BIT0 + +#define R_PCH_LPC_FWH_BIOS_SEL 0xD0 +#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000 +#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000 +#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000 +#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000 +#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000 +#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00 +#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0 +#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F +#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4 +#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000 +#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00 +#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0 +#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F +#define R_PCH_LPC_BDE 0xD8 ///< BIOS decode enable +#define B_PCH_LPC_BDE_F8 0x8000 +#define B_PCH_LPC_BDE_F0 0x4000 +#define B_PCH_LPC_BDE_E8 0x2000 +#define B_PCH_LPC_BDE_E0 0x1000 +#define B_PCH_LPC_BDE_D8 0x0800 +#define B_PCH_LPC_BDE_D0 0x0400 +#define B_PCH_LPC_BDE_C8 0x0200 +#define B_PCH_LPC_BDE_C0 0x0100 +#define B_PCH_LPC_BDE_LEG_F 0x0080 +#define B_PCH_LPC_BDE_LEG_E 0x0040 +#define B_PCH_LPC_BDE_70 0x0008 +#define B_PCH_LPC_BDE_60 0x0004 +#define B_PCH_LPC_BDE_50 0x0002 +#define B_PCH_LPC_BDE_40 0x0001 +#define R_PCH_LPC_PCC 0xE0 +#define B_PCH_LPC_PCC_CLKRUN_EN 0x0001 +#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000 +#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400 +#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800 +#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002 +#define R_PCH_LPC_FVEC1 0x01 +#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000 +#define R_PCH_LPC_FVEC2 0x02 +#define B_PCH_LPC_FVEC2_IATT_CAP 0x00400000 +#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 +#define R_PCH_LPC_FVEC3 0x03 +#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 +#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 + +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +#define R_PCH_APM_STS 0xB3 + +#define R_PCH_LPC_BC 0xDC ///< Bios Control +#define S_PCH_LPC_BC 1 +#define B_PCH_LPC_BC_BILD BIT7 ///< BIOS Interface Lock-Down +#define B_PCH_LPC_BC_BBS BIT6 ///< Boot BIOS strap +#define N_PCH_LPC_BC_BBS 6 +#define V_PCH_LPC_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_PCH_LPC_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_PCH_LPC_BC_EISS BIT5 ///< Enable InSMM.STS +#define B_PCH_LPC_BC_TS BIT4 ///< Top Swap +#define B_PCH_LPC_BC_LE BIT1 ///< Lock Enable +#define N_PCH_LPC_BC_LE 1 +#define B_PCH_LPC_BC_WPD BIT0 ///< Write Protect Disable + +#define R_PCH_ESPI_PCBC 0xDC ///< Peripheral Channel BIOS Control +#define S_PCH_ESPI_PCBC 4 ///< Peripheral Channel BIOS Control register size +#define B_PCH_ESPI_PCBC_BWRE BIT11 ///< BIOS Write Report Enable +#define N_PCH_ESPI_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position +#define B_PCH_ESPI_PCBC_BWRS BIT10 ///< BIOS Write Report Status +#define N_PCH_ESPI_PCBC_BWRS 10 ///< BIOS Write Report Status bit position +#define B_PCH_ESPI_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status +#define N_PCH_ESPI_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position +#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap +#define B_PCH_ESPI_PCBC_LE BIT1 ///< Lock Enable + +// +// Processor interface registers +// +#define R_PCH_NMI_SC 0x61 +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_NMI_EN 0x70 +#define B_PCH_NMI_EN_NMI_EN BIT7 + +// +// Reset Generator I/O Port +// +#define R_PCH_RST_CNT 0xCF9 +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_PCH_RTC_INDEX 0x70 +#define R_PCH_RTC_TARGET 0x71 +#define R_PCH_RTC_EXT_INDEX 0x72 +#define R_PCH_RTC_EXT_TARGET 0x73 +#define R_PCH_RTC_REGA 0x0A +#define B_PCH_RTC_REGA_UIP 0x80 +#define R_PCH_RTC_REGB 0x0B +#define B_PCH_RTC_REGB_SET 0x80 +#define B_PCH_RTC_REGB_PIE 0x40 +#define B_PCH_RTC_REGB_AIE 0x20 +#define B_PCH_RTC_REGB_UIE 0x10 +#define B_PCH_RTC_REGB_DM 0x04 +#define B_PCH_RTC_REGB_HOURFORM 0x02 +#define R_PCH_RTC_REGC 0x0C +#define R_PCH_RTC_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_PCH_PCR_RTC_CONF 0x3400 ///< RTC Configuration register +#define S_PCH_PCR_RTC_CONF 4 +#define B_PCH_PCR_RTC_CONF_BILD BIT31 ///< BIOS Interface Lock-Down +#define B_PCH_PCR_RTC_CONF_HPM_HW_DIS BIT6 ///< RTC High Power Mode HW Disable +#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK BIT4 ///< Partial Range Lock in Upper 128 Bytes +#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK BIT3 ///< Partial Range Lock in Lower 128 Bytes +#define B_PCH_PCR_RTC_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable +#define R_PCH_PCR_RTC_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control +#define B_PCH_PCR_RTC_RTCDCG_RTCPGCBDCGEN BIT2 ///< pgcb_clk (12MHz) Dynamic Clock Gate Enable +#define B_PCH_PCR_RTC_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define B_PCH_PCR_RTC_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable + +// +// LPC PCR Registers +// +#define R_PCH_PCR_LPC_GCFD 0x3418 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h new file mode 100644 index 0000000000..51e4e95670 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h @@ -0,0 +1,191 @@ +/** @file + Register names for Low Power Sub System (LPSS) module. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_LPSS_H_ +#define _REGS_LPSS_H_ + +/// +/// Low Power Input Output (LPSS) Module Registers +/// +/// Define LPSS IO Devices Generic PCI Registers +/// +#define R_LPSS_IO_DEVVENDID 0x00 ///< Device ID & Vendor ID +#define B_LPSS_IO_DEVVENDID_DID 0xFFFF0000 ///< Device ID +#define B_LPSS_IO_DEVVENDID_VID 0x0000FFFF ///< Vendor ID + +#define R_LPSS_IO_STSCMD 0x04 ///< Status & Command +#define B_LPSS_IO_STSCMD_SSE BIT30 ///< Signaled System Error +#define B_LPSS_IO_STSCMD_RMA BIT29 ///< Received Master Abort +#define B_LPSS_IO_STSCMD_RTA BIT28 ///< Received Target Abort +#define B_LPSS_IO_STSCMD_STA BIT27 ///< Signaled Target Abort +#define B_LPSS_IO_STSCMD_CAPLIST BIT20 ///< Capability List +#define B_LPSS_IO_STSCMD_INTRSTS BIT19 ///< Interrupt Status +#define B_LPSS_IO_STSCMD_INTRDIS BIT10 ///< Interrupt Disable +#define B_LPSS_IO_STSCMD_SERREN BIT8 ///< SERR# Enable +#define B_LPSS_IO_STSCMD_BME BIT2 ///< Bus Master Enable +#define B_LPSS_IO_STSCMD_MSE BIT1 ///< Memory Space Enable + +#define R_LPSS_IO_REVCC 0x08 ///< Revision ID & Class Code +#define B_LPSS_IO_REVCC_CC 0xFFFFFF00 ///< Class Code +#define B_LPSS_IO_REVCC_RID 0x000000FF ///< Revision ID + +#define R_LPSS_IO_CLHB 0x0C +#define B_LPSS_IO_CLHB_MULFNDEV BIT23 ///< Multi Function Device +#define B_LPSS_IO_CLHB_HT 0x007F0000 ///< Header Type +#define B_LPSS_IO_CLHB_LT 0x0000FF00 ///< Latency Timer +#define B_LPSS_IO_CLHB_CLS 0x000000FF ///< Cache Line Size + +#define R_LPSS_IO_BAR 0x10 ///< BAR0 Low +#define R_LPSS_IO_BAR_HIGH 0x14 ///< BAR0 High +#define B_LPSS_IO_BAR_BA 0xFFFFF000 ///< Base Address +#define V_LPSS_IO_BAR_SIZE 0x1000 +#define N_LPSS_IO_BAR_ALIGNMENT 12 +#define B_LPSS_IO_BAR_SI 0x00000FF0 ///< Size Indicator +#define B_LPSS_IO_BAR_PF BIT3 ///< Prefetchable +#define B_LPSS_IO_BAR_TYPE (BIT2 | BIT1) ///< Type +#define B_LPSS_IO_BAR_MS BIT0 ///< Message Space + +#define R_LPSS_IO_BAR1 0x18 ///< BAR1 Low +#define R_LPSS_IO_BAR1_HIGH 0x1C ///< BAR1 High +#define B_LPSS_IO_BAR1_BA 0xFFFFF000 ///< Base Address +#define V_LPSS_IO_BAR1_SIZE 0x1000 +#define B_LPSS_IO_BAR1_SI 0x00000FF0 ///< Size Indicator +#define B_LPSS_IO_BAR1_PF BIT3 ///< Prefetchable +#define B_LPSS_IO_BAR1_TYPE (BIT2 | BIT1) ///< Type +#define B_LPSS_IO_BAR1_MS BIT0 ///< Message Space + +#define R_LPSS_IO_SSID 0x2C ///< Sub System ID +#define B_LPSS_IO_SSID_SID 0xFFFF0000 ///< Sub System ID +#define B_LPSS_IO_SSID_SVID 0x0000FFFF ///< Sub System Vendor ID + +#define R_LPSS_IO_ERBAR 0x30 ///< Expansion ROM BAR +#define B_LPSS_IO_ERBAR_BA 0xFFFFFFFF ///< Expansion ROM Base Address + +#define R_LPSS_IO_CAPPTR 0x34 ///< Capability Pointer +#define B_LPSS_IO_CAPPTR_CPPWR 0xFF ///< Capability Pointer Power + +#define R_LPSS_IO_INTR 0x3C ///< Interrupt +#define B_LPSS_IO_INTR_ML 0xFF000000 ///< Max Latency +#define B_LPSS_IO_INTR_MG 0x00FF0000 +#define B_LPSS_IO_INTR_IP 0x00000F00 ///< Interrupt Pin +#define B_LPSS_IO_INTR_IL 0x000000FF ///< Interrupt Line + +#define R_LPSS_IO_PCAPID 0x80 ///< Power Capability ID +#define B_LPSS_IO_PCAPID_PS 0xF8000000 ///< PME Support +#define B_LPSS_IO_PCAPID_VS 0x00070000 ///< Version +#define B_LPSS_IO_PCAPID_NC 0x0000FF00 ///< Next Capability +#define B_LPSS_IO_PCAPID_PC 0x000000FF ///< Power Capability + +#define R_LPSS_IO_PCS 0x84 ///< PME Control Status +#define B_LPSS_IO_PCS_PMESTS BIT15 ///< PME Status +#define B_LPSS_IO_PCS_PMEEN BIT8 ///< PME Enable +#define B_LPSS_IO_PCS_NSS BIT3 ///< No Soft Reset +#define B_LPSS_IO_PCS_PS (BIT1 | BIT0) ///< Power State + +#define R_LPSS_IO_MANID 0xF8 ///< Manufacturer ID +#define B_LPSS_IO_MANID_MANID 0xFFFFFFFF ///< Manufacturer ID + +#define R_LPSS_IO_D0I3MAXDEVPG 0x0A0 ///< D0i3 Max Power On Latency and Device PG config + +/// +/// LPSS IO Device Generic MMIO Register +/// MMIO Registers (BAR0 + Offset) +/// +#define R_LPSS_IO_MEM_PCP 0x200 ///< Private Clock Parameters +#define B_LPSS_IO_MEM_PCP_CLK_UPDATE BIT31 ///< Clock Divider Update +#define B_LPSS_IO_MEM_PCP_N_VAL 0x7FFF0000 ///< N value for the M over N divider +#define B_LPSS_IO_MEM_PCP_M_VAL 0x0000FFFE ///< M value for the M over N divider +#define B_LPSS_IO_MEM_PCP_CLK_EN BIT0 ///< Clock Enable +#define V_LPSS_IO_PPR_CLK_M_DIV 1152 ///< Max Baudrate = (100MHz * (1152 / 15625)) / 16 = 460800Hz +#define V_LPSS_IO_PPR_CLK_N_DIV 15625 + +#define R_LPSS_IO_MEM_RESETS 0x204 ///< Software Reset +#define B_LPSS_IO_MEM_HC_RESET_REL (BIT0|BIT1) ///< LPSS IO Host Controller Reset Release +#define B_LPSS_IO_MEM_iDMA_RESET_REL BIT2 ///< iDMA Reset Release + +#define R_LPSS_IO_ACTIVELTR 0x210 + #define B_LPSS_IO_ACTIVELTR_LATENCY BIT11 ///< When the LTR registers are under Platform/HW default control, the value need set to 0x800 + +#define R_LPSS_IO_IDLELTR 0x214 + #define B_LPSS_IO_IDLELTR_LATENCY BIT11 ///< When the LTR registers are under Platform/HW default control, the value need set to 0x800 + +#define R_LPSS_IO_REMAP_ADDRESS_LOW 0x240 ///< Low 32 bits of BAR address read by SW from BAR Low CFG Offset 0x10 +#define R_LPSS_IO_REMAP_ADDRESS_HI 0x244 ///< High 32 bits of BAR address read by SW from BAR High CFG Offset 0x14 + +#define R_LPSS_IO_DEV_IDLE_CTRL 0x24C ///< DevIdle Control per LPSS slice + + +/// +/// LPSS I2C Module +/// PCI Config Space Registers +/// +#define PCI_DEVICE_NUMBER_LPSS_I2C0 22 + #define PCI_FUNCTION_NUMBER_LPSS_I2C0 0 + #define PCI_FUNCTION_NUMBER_LPSS_I2C1 1 + #define PCI_FUNCTION_NUMBER_LPSS_I2C2 2 + #define PCI_FUNCTION_NUMBER_LPSS_I2C3 3 + +#define PCI_DEVICE_NUMBER_LPSS_I2C1 23 + #define PCI_FUNCTION_NUMBER_LPSS_I2C4 0 + #define PCI_FUNCTION_NUMBER_LPSS_I2C5 1 + #define PCI_FUNCTION_NUMBER_LPSS_I2C6 2 + #define PCI_FUNCTION_NUMBER_LPSS_I2C7 3 + +#define LPSS_I2C_TMP_BAR0_DELTA 0x10000 ///< Increasement for each I2C device BAR0 +#define LPSS_I2C_TMP_BAR1_OFFSET 0x8000 ///< Offset from I2C BAR0 to BAR1 + +#define R_LPSS_I2C_IC_ENABLE 0x6C + #define B_LPSS_I2C_IC_ENABLE_ENABLE BIT0 + +/// +/// LPSS HSUART Modules +/// PCI Config Space Registers +/// +#define PCI_DEVICE_NUMBER_LPSS_HSUART 24 +#define PCI_FUNCTION_NUMBER_LPSS_HSUART0 0 +#define PCI_FUNCTION_NUMBER_LPSS_HSUART1 1 +#define PCI_FUNCTION_NUMBER_LPSS_HSUART2 2 +#define PCI_FUNCTION_NUMBER_LPSS_HSUART3 3 + +/// +/// LPSS SPI Module +/// PCI Config Space Registers +/// +#define PCI_DEVICE_NUMBER_LPSS_SPI 25 +#define PCI_FUNCTION_NUMBER_LPSS_SPI0 0 +#define PCI_FUNCTION_NUMBER_LPSS_SPI1 1 +#define PCI_FUNCTION_NUMBER_LPSS_SPI2 2 + +#define R_LPSS_SPI_MEM_SSP_CONTROL0 0x000 + #define B_LPSS_SPI_MEM_SSP_CONTROL0_SSE BIT7 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsP2sb.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsP2sb.h new file mode 100644 index 0000000000..f6985e791a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsP2sb.h @@ -0,0 +1,139 @@ +/** @file + Register names for SC P2SB device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D13:F0) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 13 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 0 + +#define V_PCH_P2SB_VENDOR_ID V_INTEL_VENDOR_ID +#define R_PCH_P2SB_SBREG_BAR 0x10 +#define B_PCH_P2SB_SBREG_RBA 0xFF000000 +#define R_PCH_P2SB_SBREG_BARH 0x14 +#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF +#define R_PCH_P2SB_VBDF 0x50 +#define B_PCH_P2SB_VBDF_BUF 0xFF00 +#define B_PCH_P2SB_VBDF_DEV 0x00F8 +#define B_PCH_P2SB_VBDF_FUNC 0x0007 +#define R_PCH_P2SB_ESMBDF 0x52 +#define B_PCH_P2SB_ESMBDF_BUF 0xFF00 +#define B_PCH_P2SB_ESMBDF_DEV 0x00F8 +#define B_PCH_P2SB_ESMBDF_FUNC 0x0007 +#define R_PCH_P2SB_RCFG 0x54 +#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00 +#define B_PCH_P2SB_RCFG_RSE BIT0 +#define R_PCH_P2SB_HPTC 0x60 +#define B_PCH_P2SB_HPTC_AE BIT7 +#define B_PCH_P2SB_HPTC_AS 0x0003 +#define N_PCH_HPET_ADDR_ASEL 12 +#define V_PCH_HPET_BASE0 0xFED00000 +#define V_PCH_HPET_BASE1 0xFED01000 +#define V_PCH_HPET_BASE2 0xFED02000 +#define V_PCH_HPET_BASE3 0xFED03000 +#define R_PCH_P2SB_IOAC 0x64 +#define B_PCH_P2SB_IOAC_AE BIT8 +#define B_PCH_P2SB_IOAC_ASEL 0x00FF +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define R_PCH_IO_APIC_EOI 0xFEC00040 +#define R_PCH_P2SB_IBDF 0x6C +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_80 0x80 +#define R_PCH_P2SB_84 0x84 +#define R_PCH_P2SB_88 0x88 +#define R_PCH_P2SB_8C 0x8C +#define R_PCH_P2SB_90 0x90 +#define R_PCH_P2SB_94 0x94 +#define R_PCH_P2SB_98 0x98 +#define R_PCH_P2SB_9C 0x9C +#define R_PCH_P2SB_DISPBDF 0xA0 +#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000 +#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00 +#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8 +#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007 +#define R_PCH_P2SB_ICCOS 0xA4 +#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00 +#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF +#define R_PCH_P2SB_EPMASK0 0xB0 +#define R_PCH_P2SB_EPMASK1 0xB4 +#define R_PCH_P2SB_EPMASK2 0xB8 +#define R_PCH_P2SB_EPMASK3 0xBC +#define R_PCH_P2SB_EPMASK4 0xC0 +#define R_PCH_P2SB_EPMASK5 0xC4 +#define R_PCH_P2SB_EPMASK6 0xC8 +#define R_PCH_P2SB_EPMASK7 0xCC + +// +// Definition for SBI +// +#define R_PCH_P2SB_SBIADDR 0xD0 +#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000 +#define B_PCH_P2SB_SBIADDR_RS 0x000F0000 +#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF +#define R_PCH_P2SB_SBIDATA 0xD4 +#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF +#define R_PCH_P2SB_SBISTAT 0xD8 +#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00 +#define B_PCH_P2SB_SBISTAT_POSTED BIT7 +#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006 +#define N_PCH_P2SB_SBISTAT_RESPONSE 1 +#define B_PCH_P2SB_SBISTAT_INITRDY BIT0 +#define R_PCH_P2SB_SBIRID 0xDA +#define B_PCH_P2SB_SBIRID_FBE 0xF000 +#define B_PCH_P2SB_SBIRID_BAR 0x0700 +#define B_PCH_P2SB_SBIRID_FID 0x00FF +#define R_PCH_P2SB_SBIEXTADDR 0xDC +#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_PCH_P2SB_E0 0xE0 +#define R_PCH_P2SB_E4 0xE4 + +#ifdef PCH_PO_FLAG +#define R_PCH_P2SB_E8 0xE8 +#define R_PCH_P2SB_EA 0xEA +#endif // PCH_PO_FLAG + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcie.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcie.h new file mode 100644 index 0000000000..03ee1cc8fa --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcie.h @@ -0,0 +1,307 @@ +/** @file + Register names for SC PCI-E root port devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +#define PCIE_MAX_ROOT_PORTS 6 + + + +/// +/// PCI Express Root Ports (PCIe 0: D20:F0~F1, PCIe1: D19:F0~F3) +/// +#define PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_1 20 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_2 1 +#define PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_2 19 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_3 0 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_4 1 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_5 2 +#define PCI_FUNCTION_NUMBER_PCIE_ROOT_PORT_6 3 + + +#define V_PCH_PCIE_VENDOR_ID V_INTEL_VENDOR_ID + +#define V_BXT_P_PCIE_DEVICE_ID_PORT1 0x5AD6 ///< PCI Express Root Port #1, BXT-P SC +#define V_BXT_P_PCIE_DEVICE_ID_PORT2 0x5AD7 ///< PCI Express Root Port #2, BXT-P SC +#define V_BXT_P_PCIE_DEVICE_ID_PORT3 0x5AD8 ///< PCI Express Root Port #3, BXT-P SC +#define V_BXT_P_PCIE_DEVICE_ID_PORT4 0x5AD9 ///< PCI Express Root Port #4, BXT-P SC +#define V_BXT_P_PCIE_DEVICE_ID_PORT5 0x5ADA ///< PCI Express Root Port #5, BXT-P SC +#define V_BXT_P_PCIE_DEVICE_ID_PORT6 0x5ADB ///< PCI Express Root Port #6, BXT-P SC +#define V_BXT_PCIE_DEVICE_ID_PORT1 0x1AD6 ///< PCI Express Root Port #1, BXT B0 SC +#define V_BXT_PCIE_DEVICE_ID_PORT2 0x1AD7 ///< PCI Express Root Port #2, BXT B0 SC +#define R_PCH_PCIE_CLIST 0x40 +#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PCIE_XCAP_OFFSET) +#define R_PCH_PCIE_DCAP (R_PCH_PCIE_CLIST + R_PCIE_DCAP_OFFSET) +#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PCIE_DCTL_OFFSET) +#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PCIE_LCAP_OFFSET) +#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PCIE_LCTL_OFFSET) +#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET) +#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PCIE_SLCAP_OFFSET) +#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PCIE_SLCTL_OFFSET) +#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PCIE_SLSTS_OFFSET) +#define R_PCH_PCIE_RCTL (R_PCH_PCIE_CLIST + R_PCIE_RCTL_OFFSET) +#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PCIE_RSTS_OFFSET) +#define R_PCH_PCIE_DCAP2 (R_PCH_PCIE_CLIST + R_PCIE_DCAP2_OFFSET) +#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PCIE_DCTL2_OFFSET) +#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PCIE_LCTL2_OFFSET) + + +#define R_PCIE_LCTL_LSTS 0x50 ///< Link Control; Link Status +#define B_PCIE_LCTL_LSTS_LABS BIT31 ///< Link Autonomous Bandwidth Status +#define B_PCIE_LCTL_LSTS_LBMS BIT30 ///< Link Bandwidth Management Status +#define B_PCIE_LCTL_LSTS_DLLA BIT29 ///< Link Active +#define B_PCIE_LCTL_LSTS_SCC BIT28 ///< Slot Clock Configuration +#define B_PCIE_LCTL_LSTS_LT BIT27 ///< Link Training +#define B_PCIE_LCTL_LSTS_LTE BIT26 ///< Reserved, previously was Link Training Error +#define B_PCIE_LCTL_LSTS_NLW 0x03F00000 ///< Negotiated Link Width +#define V_PCIE_LCTL_LSTS_NLW_1 0x00100000 +#define V_PCIE_LCTL_LSTS_NLW_2 0x00200000 +#define V_PCIE_LCTL_LSTS_NLW_4 0x00400000 +#define B_PCIE_LCTL_LSTS_LS 0x000F0000 ///< Current Link Speed +#define B_PCIE_LCTL_LSTS_LABIE BIT11 ///< Link Autonomous Bandwidth Interrupt Enable +#define B_PCIE_LCTL_LSTS_LBMIE BIT10 ///< Link Bandwidth Management Interrupt Enable +#define B_PCIE_LCTL_LSTS_HAWD BIT9 ///< Hardware Autonomous Width Disable +#define B_PCIE_LCTL_LSTS_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_LSTS_CCC BIT6 ///< Common Clock Configuration +#define B_PCIE_LCTL_LSTS_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LSTS_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_LSTS_RCBC BIT3 ///< Read Completion Boundary +#define B_PCIE_LCTL_LSTS_ASPM (BIT1 | BIT0) ///< Active State Link PM Control +#define V_PCIE_LCTL_LSTS_ASPM_L0S 1 ///< L0s Entry Enabled +#define V_PCIE_LCTL_LSTS_ASPM_L1 2 ///< L1 Entry Enable +#define V_PCIE_LCTL_LSTS_ASPM_L0S_L1 3 ///< L0s and L1 Entry Enabled + + +#define R_PCIE_LCTL2_LSTS2 0x70 ///< Link Control 2; Link Status 2 +#define B_PCIE_LCTL2_LSTS2_CDL BIT16 ///< Current De-emphasis Level +#define B_PCIE_LCTL2_LSTS2_CD BIT12 ///< Compliance De-emphasis +#define B_PCIE_LCTL2_LSTS2_CSOS BIT11 ///< Compliance SOS +#define B_PCIE_LCTL2_LSTS2_EMC BIT10 ///< Enter Modified Compliance +#define B_PCIE_LCTL2_LSTS2_TM (BIT9 | BIT8 | BIT7) ///< Transmit Margin +#define B_PCIE_LCTL2_LSTS2_SD BIT6 ///< Selectable De-emphasis +#define B_PCIE_LCTL2_LSTS2_HASD BIT5 ///< Reserved. Hardware Autonomous Speed Disable +#define B_PCIE_LCTL2_LSTS2_EC BIT4 ///< Enter Compliance +#define B_PCIE_LCTL2_LSTS2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed + + +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 + +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define R_PCH_PCIE_SVID 0x94 +#define S_PCH_PCIE_SVID 4 + +#define R_PCIE_SVID 0x94 ///< Subsystem Vendor IDs +#define S_PCIE_SVID 4 +#define B_PCIE_SVID_SID 0xFFFF0000 ///< Subsystem Identifier +#define B_PCIE_SVID_SVID 0x0000FFFF ///< Subsystem Vendor Identifier + +#define R_PCH_PCIE_PMCAP 0xA0 +#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PCIE_PMCS_OFFST) + +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_MPC2_TLPF BIT9 +#define B_PCH_PCIE_MPC2_LSTP BIT6 +#define B_PCH_PCIE_MPC2_IEIME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S 1 << 2 +#define V_PCH_PCIE_MPC2_ASPMCO_L1 2 << 2 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 3 << 2 +#define B_PCH_PCIE_MPC2_EOIFD BIT1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDLCGEN BIT3 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header +#define V_PCH_PCIE_EX_AEC_CV 0x1 +#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_PCIE_EX_UEM_OFFSEST) + +#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended Capability Header +#define V_PCH_PCIE_EX_ACS_CV 0x1 +#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_EX_PTMECH 0x150 ///< PTM Extended Capability Header +#define V_PCH_PCIE_EX_PTM_CV 0x1 +#define R_PCH_PCIE_EX_PTMCAPR (R_PCH_PCIE_EX_PTMECH + R_PCIE_EX_PTMCAPR_OFFSET) + + +#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI Express Extended Capability Header +#define V_PCH_PCIE_EX_SPEECH_CV 0x1 +#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_EX_L01EC_UPL1RPH (BIT30 | BIT29 | BIT28) +#define V_PCH_PCIE_EX_L01EC_UPL1TP 0x01000000 +#define B_PCH_PCIE_EX_L01EC_DPL1RPH (BIT22 | BIT21 | BIT20) +#define V_PCH_PCIE_EX_L01EC_DPL1TP 0x00020000 +#define B_PCH_PCIE_EX_L01EC_UPL0RPH (BIT14 | BIT13 | BIT12) +#define V_PCH_PCIE_EX_L01EC_UPL0TP 0x00000000 +#define B_PCH_PCIE_EX_L01EC_DPL0RPH (BIT6 | BIT5 | BIT4) +#define V_PCH_PCIE_EX_L01EC_DPL0TP 0x00000001 + +#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET) +#define B_PCH_PCIE_EX_L23EC_UPL3RPH (BIT30 | BIT29 | BIT28) +#define V_PCH_PCIE_EX_L23EC_UPL3TP 0x02000000 +#define B_PCH_PCIE_EX_L23EC_DPL3RPH (BIT22 | BIT21 | BIT20) +#define V_PCH_PCIE_EX_L23EC_DPL3TP 0x00010000 +#define B_PCH_PCIE_EX_L23EC_UPL2RPH (BIT14 | BIT13 | BIT12) +#define V_PCH_PCIE_EX_L23EC_UPL2TP 0x00000300 +#define B_PCH_PCIE_EX_L23EC_DPL2RPH (BIT6 | BIT5 | BIT4) +#define V_PCH_PCIE_EX_L23EC_DPL2TP 0x00000003 + +#define R_PCH_PCIE_PCIERTP1 0x300 +#define R_PCH_PCIE_PCIERTP2 0x304 + +#define R_PCH_PCIE_PCIESTS1 0x328 +#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19) +#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7 + + +#define R_PCH_PCIE_PTMPSDC2 0x3A0 +#define R_PCH_PCIE_PTMPSDC3 0x3A4 +#define R_PCH_PCIE_PTMECFG 0x3B0 + +#define R_PCH_PCIE_PCE 0x428 +#define B_PCH_PCIE_PCE_HAE BIT5 +#define B_PCH_PCIE_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_EQCFG1 0x450 +#define S_PCH_PCIE_EQCFG1 4 +#define N_PCH_PCIE_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_RTPCL1 0x454 +#define B_PCH_PCIE_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_RTPCL2 0x458 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_RTPCL3 0x45C +#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_RTPCL4 0x460 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_HAEQ 0x468 +#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28) +#define V_PCH_PCIE_HAEQ_HAPCCPI_2PCPI 2 +#define N_PCH_PCIE_HAEQ_HAPCCPI_2PCPI 28 + + +#define R_PCH_PCIE_LTCO1 0x470 +#define B_PCH_PCIE_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F + +#define R_PCH_PCIE_LTCO2 0x474 +#define B_PCH_PCIE_LTCO1_L3TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L2TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO1_L3TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO1_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO1_L2TPRECO 0x3F + +#define R_PCH_PCIE_G3L0SCTL 0x478 +#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_EQCFG2 0x47C +#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20) +#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCIE_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_EQCFG2_REWMET 0xFF + +// +// PCI Express Extended End Point Capability Registers +// +#define R_PCH_PCIE_LTRECH_OFFSET 0x00 +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcr.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcr.h new file mode 100644 index 0000000000..ba9f0f333c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcr.h @@ -0,0 +1,54 @@ +/** @file + Register names for SC private chipset register. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_REGS_PCR_H_ +#define _SC_REGS_PCR_H_ + +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ + +#define SC_PCR_ADDRESS(Pid, Offset) (SC_PCR_BASE_ADDRESS | ((UINT8) (Pid) << 16) | (UINT16) (Offset)) + +typedef enum { + PID0 = 0xD1, + PID1 = 0xD0, + PID2 = 0xC6, + PID3 = 0xB0, + PID4 = 0xB3, + PID5 = 0xB4, + PID6 = 0xB6, + PID7 = 0xA9, +} SC_SBI_PID; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcu.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcu.h new file mode 100644 index 0000000000..35920e9e5a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPcu.h @@ -0,0 +1,1043 @@ +/** @file + Register names for PCU device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_PCU_H_ +#define _REGS_PCU_H_ + + +#include + +/// +/// PCU Registers (D13:F0) +/// +#define PCI_DEVICE_NUMBER_P2SB 13 +#define PCI_FUNCTION_NUMBER_P2SB 0 + +#define B_P2SB_BAR_BA 0xFFFFF000 ///< Base Address + +#define R_P2SB_BASE 0x10 +#define B_P2SB_BASE_PREF BIT3 ///< Prefetchable +#define B_P2SB_BASE_ADDRNG BIT2 ///< Address Range +#define B_P2SB_BASE_EN BIT1 ///< Enable Bit +#define B_P2SB_BASE_MEMI BIT0 ///< Memory Space Indication +#define R_PCH_P2SB_VBDF 0x50 ///< VLW BDF register +#define R_P2SB_IOAC 0x64 ///< IOxAPIC Configuration +#define B_P2SB_IOAC_AE BIT8 ///< Address Enable +#define R_P2SB_HPET 0x60 ///< HPET Configuration +#define B_P2SB_HPET_AE BIT7 ///< Address Enable +#define R_PCH_P2SB_IBDF 0x6C ///< IOAPIC BDF register +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 ///< HPET BDF register +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_DBDF 0xA0 ///< Display BDF register (RAVDMs upstream/downstream ID) +#define B_PCH_P2SB_DBDF_BUF 0xFF00 +#define B_PCH_P2SB_DBDF_DEV 0x00F8 +#define B_PCH_P2SB_DBDF_FUNC 0x0007 +#define R_P2SB_RCFG 0x54 ///< P2SB RCFG +#define B_P2SB_RCFG_RSE BIT0 ///< RTC Shadow Enable +#define R_P2SB_P2SBC 0xE0 ///< P2SB Control +#define B_P2SB_P2SBC_HIDE BIT8 ///< Hide Device +#define B_P2SB_P2SBC_PGCBCGE BIT16 ///< PGCB Clock Gating Enable +#define R_P2SB_PCE 0xE4 ///< Power Control Enable +#define B_P2SB_PCE_PMCRE BIT0 ///< PMC Request Enable +#define B_P2SB_PCE_SE BIT3 ///< Sleep Enable +#define B_P2SB_PCE_HAE BIT5 ///< Hardware Autonomous Enable +#define R_P2SB_PDOMAIN 0xE8 ///< Primary Clock Domain Controls +#define B_P2SB_PDOMAIN_CGD BIT0 ///< Primary Clock Gating Disable +#define B_P2SB_PDOMAIN_CRD BIT1 ///< Primary Clock Request Disabled +#define R_P2SB_SDOMAIN 0xEA ///< Sideband Clock Domain Controls +#define B_P2SB_SDOMAIN_CGD BIT0 ///< Sideband Clock Gating Disable +#define B_P2SB_SDOMAIN_CRD BIT1 ///< Sideband Clock Request Disabled + +#define R_P2SB_STSCMD 0x04 ///< Status & Command Register +#define B_P2SB_STSCMD_BME BIT2 ///< Bus Master Enable +#define B_P2SB_STSCMD_MSE BIT1 ///< Memory Space Enable + +#define P2SB_MMIO_ADDR(base, port, reg) (base | (port&0xFF)<<16 | (reg&0xFFFC)) + +/// +/// PCU Registers (D31:F0) +/// +#define PCI_DEVICE_NUMBER_LPC 31 +#define PCI_FUNCTION_NUMBER_LPC 0 + +typedef enum { + ScA0 = 0, + ScA1 = 1, + ScSteppingMax +} SC_STEPPING; + +#define R_LPC_REG_ID 0x00 ///< Identifiers Register +#define B_LPC_DEVICE_ID 0xFFFF0000 ///< Device Identification +#define B_LPC_VENDOR_ID 0x0000FFFF ///< Vendor Identification +#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID ///< Vendor ID for Intel +/// +/// General PCU Device ID +/// +#define V_LPC_DEVICE_ID_0 0x229C +#define V_LPC_DEVICE_ID_1 0x229D +#define V_LPC_DEVICE_ID_2 0x229E +#define V_LPC_DEVICE_ID_3 0x229F + +#define R_LPC_COMMAND 0x04 ///< Command +#define B_LPC_COMMAND_ID BIT10 ///< Interrupt Disable +#define B_LPC_COMMAND_FBE BIT9 ///< Fast Back to Back Enable +#define B_LPC_COMMAND_SERR_EN BIT8 ///< SERR# Enable +#define B_LPC_COMMAND_WCC BIT7 ///< Wait Cycle Control +#define B_LPC_COMMAND_PER BIT6 ///< Parity Error Response Enable +#define B_LPC_COMMAND_VPS BIT5 ///< VGA Palette Snoop +#define B_LPC_COMMAND_MWIE BIT4 ///< Memory Write and Invalidate Enable +#define B_LPC_COMMAND_SCE BIT3 ///< Special Cycle Enable +#define B_LPC_COMMAND_BME BIT2 ///< Bus Master Enable +#define B_LPC_COMMAND_MSE BIT1 ///< Memory Space Enable +#define B_LPC_COMMAND_IOSE BIT0 ///< I/O Space Enable + +#define R_LPC_DEV_STS 0x06 ///< Status +#define B_LPC_DEV_STS_DPE BIT15 ///< Detected Parity Error +#define B_LPC_DEV_STS_SSE BIT14 ///< Signaled System Error +#define B_LPC_DEV_STS_RMA BIT13 ///< Received Master Abort +#define B_LPC_DEV_STS_RTA BIT12 ///< Received Target Abort +#define B_LPC_DEV_STS_STA BIT11 ///< Signaled Target Abort +#define B_LPC_DEV_STS_DEVT_STS (BIT10 | BIT9) ///< DEVSEL# Timing Status +#define B_LPC_DEV_STS_MDPED BIT8 ///< Data Parity Error +#define B_LPC_DEV_STS_FB2B BIT7 ///< Fast Back to Back Capable +#define B_LPC_DEV_STS_66MHZ_CAP BIT5 ///< 66 MHz capable +#define B_LPC_DEV_STS_CAP_LIST BIT4 ///< Capabilities List +#define B_LPC_DEV_STS_INT_STS BIT3 ///< Interrupt Status + +#define R_LPC_RID_CC 0x08 ///< Revision ID & Class Code +#define B_LPC_RID_CC_BCC 0xFF000000 ///< Base Class Code +#define B_LPC_RID_CC_SCC 0x00FF0000 ///< Sub-Class Code +#define B_LPC_RID_CC_PI 0x0000FF00 ///< Programming Interface +#define B_LPC_RID_CC_RID 0x000000FF ///< Revision ID +#define V_LPC_RID_0 0x01 ///< A0 Stepping (17 x 17) +#define V_LPC_RID_1 0x02 ///< A0 Stepping (25 x 27) +#define V_LPC_RID_2 0x03 ///< A1 Stepping (17 x 17) +#define V_LPC_RID_3 0x04 ///< A1 Stepping (25 x 27) + +#define R_LPC_MLT 0x0D ///< Master Latency Timer +#define B_LPC_MLT_MLC 0xF8 ///< Master Latency Count + +#define R_LPC_HEADTYP 0x0E ///< Header Type +#define B_LPC_HEADTYP_MFD BIT7 ///< Multi-function Device +#define B_LPC_HEADTYP_HT 0x7F ///< Header Type + +#define R_LPC_SS 0x2C ///< Subsystem ID & Vendor ID +#define B_LPC_SS_SSID 0xFFFF0000 ///< Subsystem ID +#define B_LPC_SS_SSVID 0x0000FFFF ///< Subsystem Vendor ID + +#define R_LPC_CAP_LIST 0x34 ///< Capability List +#define B_LPC_CAP_LIST_CP 0xFF ///< Capability Pointer + + +#define R_LPC_UART_CTRL 0x80 ///< UART Control +#define B_LPC_UART_CTRL_COM1_EN BIT0 ///< COM1 Enable + +#define R_LPC_FWH_BIOS_DEC 0xD8 ///< BIOS Decode Enable +#define B_LPC_FWH_BIOS_DEC_EF8 BIT15 ///< F8-FF Enable +#define B_LPC_FWH_BIOS_DEC_EF0 BIT14 ///< F0-F8 Enable +#define B_LPC_FWH_BIOS_DEC_EE8 BIT13 ///< E8-EF Enable +#define B_LPC_FWH_BIOS_DEC_EE0 BIT12 ///< E0-E8 Enable +#define B_LPC_FWH_BIOS_DEC_ED8 BIT11 ///< D8-DF Enable +#define B_LPC_FWH_BIOS_DEC_ED0 BIT10 ///< D0-D8 Enable +#define B_LPC_FWH_BIOS_DEC_EC8 BIT9 ///< C8-CF Enable +#define B_LPC_FWH_BIOS_DEC_EC0 BIT8 ///< C0-C8 Enable +#define B_LPC_FWH_BIOS_DEC_LFE BIT7 ///< Legacy F Segment Enable +#define B_LPC_FWH_BIOS_DEC_LEE BIT6 ///< Legacy E Segment Enable +#define B_LPC_FWH_BIOS_DEC_E70 BIT3 ///< 70-7F Enable +#define B_LPC_FWH_BIOS_DEC_E60 BIT2 ///< 60-6F Enable +#define B_LPC_FWH_BIOS_DEC_E50 BIT1 ///< 50-5F Enable +#define B_LPC_FWH_BIOS_DEC_E40 BIT0 ///< 40-4F Enable + +#define R_LPC_FDCAP 0xE0 ///< Feature Detection Capability ID +#define B_LPC_FDCAP_NEXT 0xFF00 ///< Next Capability +#define B_LPC_FDCAP_CAPID 0x00FF ///< Capability ID + +#define R_LPC_FDLEN 0xE2 ///< Feature Detection Capability Length +#define B_LPC_FDLEN_CAPLEN 0xFF ///< Capability Length + +#define R_LPC_FDVER 0xE3 ///< Feature Detection Capability Version +#define B_LPC_FDVER_VSCID 0xF0 ///< Vendor Specific Capability ID +#define B_LPC_FDVER_CAPVER 0x0F ///< Capability Version + +#define R_LPC_FVECTIDX 0xE4 ///< Feature Vector Index + +#define R_LPC_FVECTD 0xE8 ///< Feature Vector Data + +#define R_LPC_ULT_OBS 0xF4 ///< ULT Observability +#define B_LPC_ULT_OBS_WNUM 0x3FF000 ///< Reserved Wafer Number +#define B_LPC_ULT_OBS_XLOC 0xFC0 ///< Reserved X Loc +#define B_LPC_ULT_OBS_YLOC 0x3F ///< Reserved Y Loc + +#define R_LPC_MAN_ID 0xF8 ///< Manufacturer ID +#define B_LPC_MAN_ID_DPID 0xF000000 ///< Dot Portion of Process ID +#define B_LPC_MAN_ID_MSID 0xFF0000 ///< Manufacturing Stepping Identifier +#define B_LPC_MAN_ID_MID 0xFF00 ///< Manufacturing Identifier +#define B_LPC_MAN_ID_PPID 0xFF ///< Process Portion of Process ID + +#define R_LPC_CGC 0xFC ///< Clock Gating Control +#define B_LPC_CGC_SBLCG BIT9 ///< IOSF-SB Local Clock Gating Disable +#define B_LPC_CGC_SBTCG BIT8 ///< IOSF-SB Trunk Clock Gating (Request) Disable +#define B_LPC_CGC_PRILCG BIT1 ///< IOSF-PRI Local Clock Gating Disable +#define B_LPC_CGC_PRITCG BIT0 ///< IOSF-PRI Trunk Clock Gating (Request) Disable + +/// +/// iLB Memory Space Registers (IBASE) +/// +#define R_ILB_MC 0x04 ///< Miscellaneous Control +#define B_ILB_MC_DRTC BIT3 ///< Disable RTC +#define B_ILB_MC_D8259 BIT2 ///< Disable 8259 +#define B_ILB_MC_D8254 BIT1 ///< Disable 8254 +#define B_ILB_MC_AME BIT0 ///< Alternate Access Mode Enable + +/// +/// Bit values are the same for R_ILB_PIRQA_ROUT to R_ILB_PIRQH_ROUT +/// +#define B_ILB_PIRQX_ROUT_IRQEN BIT7 ///< Interrupt Routing Enable +#define B_ILB_PIRQX_ROUT 0x0F ///< IRQ Routing +#define V_ILB_PIRQX_ROUT_IRQ_3 0x03 ///< Route to IRQ3 +#define V_ILB_PIRQX_ROUT_IRQ_4 0x04 ///< Route to IRQ4 +#define V_ILB_PIRQX_ROUT_IRQ_5 0x05 ///< Route to IRQ5 +#define V_ILB_PIRQX_ROUT_IRQ_6 0x06 ///< Route to IRQ6 +#define V_ILB_PIRQX_ROUT_IRQ_7 0x07 ///< Route to IRQ7 +#define V_ILB_PIRQX_ROUT_IRQ_9 0x09 ///< Route to IRQ9 +#define V_ILB_PIRQX_ROUT_IRQ_10 0x0A ///< Route to IRQ10 +#define V_ILB_PIRQX_ROUT_IRQ_11 0x0B ///< Route to IRQ11 +#define V_ILB_PIRQX_ROUT_IRQ_12 0x0C ///< Route to IRQ12 +#define V_ILB_PIRQX_ROUT_IRQ_14 0x0E ///< Route to IRQ14 +#define V_ILB_PIRQX_ROUT_IRQ_15 0x0F ///< Route to IRQ15 + +#define R_ILB_SERIRQ_CNT 0x10 ///< Serial IRQ Control +#define B_ILB_SERIRQ_CNT_SIRQMD BIT7 ///< Mode + +#define R_ILB_ULKMC 0x14 ///< USB Legacy Keyboard / Mouse Control +#define B_ILB_ULKMC_TRAPBY64W BIT11 ///< SMI Caused by Port 64 Write +#define B_ILB_ULKMC_TRAPBY64R BIT10 ///< SMI Caused by Port 64 Read +#define B_ILB_ULKMC_TRAPBY60W BIT9 ///< SMI Caused by Port 60 Write +#define B_ILB_ULKMC_TRAPBY60R BIT8 ///< SMI Caused by Port 60 Read +#define B_ILB_ULKMC_64WEN BIT3 ///< SMI on Port 64 Writes Enable +#define B_ILB_ULKMC_64REN BIT2 ///< SMI on Port 64 Reads Enable +#define B_ILB_ULKMC_60WEN BIT1 ///< SMI on Port 60 Writes Enable +#define B_ILB_ULKMC_60REN BIT0 ///< SMI on Port 60 Reads Enable + +#define R_ILB_FWH_BIOS_SEL 0x18 ///< FWH ID Select +#define B_ILB_FWH_BIOS_SEL_F8 0xF0000000 ///< F8-FF ID Select +#define B_ILB_FWH_BIOS_SEL_F0 0x0F000000 ///< F0-F7 ID Select +#define B_ILB_FWH_BIOS_SEL_E8 0x00F00000 ///< E8-EF ID Select +#define B_ILB_FWH_BIOS_SEL_E0 0x000F0000 ///< E0-E7 ID Select +#define B_ILB_FWH_BIOS_SEL_D8 0x0000F000 ///< D8-DF ID Select +#define B_ILB_FWH_BIOS_SEL_D0 0x00000F00 ///< D0-D7 ID Select +#define B_ILB_FWH_BIOS_SEL_C8 0x000000F0 ///< C8-CF ID Select +#define B_ILB_FWH_BIOS_SEL_C0 0x0000000F ///< C0-C7 ID Select + +#define R_ILB_BIOS_CNTL 0x1C ///< BIOS Control +#define S_ILB_BIOS_CNTL 4 +#define B_ILB_BIOS_CNTL_PFE BIT8 ///< Prefetch Enable +#define B_ILB_BIOS_CNTL_LE BIT1 ///< Lock Enable +#define N_ILB_BIOS_CNTL_LE 1 +#define B_ILB_BIOS_CNTL_WP BIT0 ///< Write Protect + +#define R_ILB_D0IR 0x20 ///< Device 0 Interrupt Route +#define R_ILB_D1IR 0x22 ///< Device 1 Interrupt Route +#define R_ILB_D2IR 0x24 ///< Device 2 Interrupt Route +#define R_ILB_D3IR 0x26 ///< Device 3 Interrupt Route +#define R_ILB_D4IR 0x28 ///< Device 4 Interrupt Route +#define R_ILB_D5IR 0x2A ///< Device 5 Interrupt Route +#define R_ILB_D6IR 0x2C ///< Device 6 Interrupt Route +#define R_ILB_D7IR 0x2E ///< Device 7 Interrupt Route +#define R_ILB_D8IR 0x30 ///< Device 8 Interrupt Route +#define R_ILB_D9IR 0x32 ///< Device 9 Interrupt Route +#define R_ILB_D10IR 0x34 ///< Device 10 Interrupt Route +#define R_ILB_D11IR 0x36 ///< Device 11 Interrupt Route +#define R_ILB_D12IR 0x38 ///< Device 12 Interrupt Route +#define R_ILB_D13IR 0x3A ///< Device 13 Interrupt Route +#define R_ILB_D14IR 0x3C ///< Device 14 Interrupt Route +#define R_ILB_D15IR 0x3E ///< Device 15 Interrupt Route +#define R_ILB_D16IR 0x40 ///< Device 16 Interrupt Route +#define R_ILB_D17IR 0x42 ///< Device 17 Interrupt Route +#define R_ILB_D18IR 0x44 ///< Device 18 Interrupt Route +#define R_ILB_D19IR 0x46 ///< Device 19 Interrupt Route +#define R_ILB_D20IR 0x48 ///< Device 20 Interrupt Route +#define R_ILB_D21IR 0x4A ///< Device 21 Interrupt Route +#define R_ILB_D22IR 0x4C ///< Device 22 Interrupt Route +#define R_ILB_D23IR 0x4E ///< Device 23 Interrupt Route +#define R_ILB_D24IR 0x50 ///< Device 24 Interrupt Route +#define R_ILB_D25IR 0x52 ///< Device 25 Interrupt Route +#define R_ILB_D26IR 0x54 ///< Device 26 Interrupt Route +#define R_ILB_D27IR 0x56 ///< Device 27 Interrupt Route +#define R_ILB_D28IR 0x58 ///< Device 28 Interrupt Route +#define R_ILB_D29IR 0x5A ///< Device 29 Interrupt Route +#define R_ILB_D30IR 0x5C ///< Device 30 Interrupt Route +#define R_ILB_D31IR 0x5E ///< Device 31 Interrupt Route + +#define B_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) ///< INTD Mask +#define V_ILB_DXXIR_IDR_PIRQA 0 ///< INTD Mapping to IRQ A +#define V_ILB_DXXIR_IDR_PIRQB BIT12 ///< INTD Mapping to IRQ B +#define V_ILB_DXXIR_IDR_PIRQC BIT13 ///< INTD Mapping to IRQ C +#define V_ILB_DXXIR_IDR_PIRQD (BIT13 | BIT12) ///< INTD Mapping to IRQ D +#define V_DXXIR_IDR_PIRQE BIT14 ///< INTD Mapping to IRQ E +#define V_ILB_DXXIR_IDR_PIRQF (BIT14 | BIT12) ///< INTD Mapping to IRQ F +#define V_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) ///< INTD Mapping to IRQ G +#define V_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) ///< INTD Mapping to IRQ H + +#define B_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) ///< INTC Mask +#define V_ILB_DXXIR_ICR_PIRQA 0 ///< INTC Mapping to IRQ A +#define V_ILB_DXXIR_ICR_PIRQB BIT8 ///< INTC Mapping to IRQ B +#define V_ILB_DXXIR_ICR_PIRQC BIT9 ///< INTC Mapping to IRQ C +#define V_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) ///< INTC Mapping to IRQ D +#define V_ILB_DXXIR_ICR_PIRQE BIT10 ///< INTC Mapping to IRQ E +#define V_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) ///< INTC Mapping to IRQ F +#define V_ILB_DXXIR_ICR_PIRQG (BIT10 | BIT9) ///< INTC Mapping to IRQ G +#define V_ILB_DXXIR_ICR_PIRQH (BIT10 | BIT9 | BIT8) ///< INTC Mapping to IRQ H + +#define B_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) ///< INTB Mask +#define V_ILB_DXXIR_IBR_PIRQA 0 ///< INTB Mapping to IRQ A +#define V_ILB_DXXIR_IBR_PIRQB BIT4 ///< INTB Mapping to IRQ B +#define V_ILB_DXXIR_IBR_PIRQC BIT5 ///< INTB Mapping to IRQ C +#define V_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) ///< INTB Mapping to IRQ D +#define V_ILB_DXXIR_IBR_PIRQE BIT6 ///< INTB Mapping to IRQ E +#define V_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) ///< INTB Mapping to IRQ F +#define V_ILB_DXXIR_IBR_PIRQG (BIT6 | BIT5) ///< INTB Mapping to IRQ G +#define V_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) ///< INTB Mapping to IRQ H + +#define B_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) ///< INTA Mask +#define V_ILB_DXXIR_IAR_PIRQA 0 ///< INTA Mapping to IRQ A +#define V_ILB_DXXIR_IAR_PIRQB BIT0 ///< INTA Mapping to IRQ B +#define V_ILB_DXXIR_IAR_PIRQC BIT1 ///< INTA Mapping to IRQ C +#define V_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) ///< INTA Mapping to IRQ D +#define V_ILB_DXXIR_IAR_PIRQE BIT2 ///< INTA Mapping to IRQ E +#define V_ILB_DXXIR_IAR_PIRQF (BIT2 | BIT0) ///< INTA Mapping to IRQ F +#define V_ILB_DXXIR_IAR_PIRQG (BIT2 | BIT1) ///< INTA Mapping to IRQ G +#define V_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) ///< INTA Mapping to IRQ H + +#define R_ILB_OIC 0x60 ///< Other Interrupt Controller +#define B_ILB_OIC_SIRQEN BIT12 ///< Serial IRQ Enable +#define B_ILB_OIC_AEN BIT8 ///< APIC Enable + +#define R_ILB_RTC_CONF 0x64 ///< RTC Control +#define B_ILB_RTC_CONF_UCMOS_LOCK BIT1 ///< Upper 128 Byte Lock +#define B_ILB_RTC_CONF_LCMOS_LOCK BIT0 ///< Lower 128 Byte Lock + +#define R_ILB_RTM 0x68 ///< RTC Test Mode +#define B_ILB_RTM_RTM1 (BIT2 | BIT1 | BIT0) + +#define R_ILB_BCS 0x6C ///< BIOS Control Status +#define B_ILB_BCS_SMIWPEN BIT1 ///< SMI WPD Enable +#define B_ILB_BCS_SMIWPST BIT0 ///< SMI WPD Status + +#define R_ILB_LE 0x70 ///< LE +#define B_ILB_LE_IRQ12C BIT1 ///< IRQ12 Cause +#define B_ILB_LE_IRQ1C BIT0 ///< IRQ1 Cause + +#define R_ILB_RTCC 0x74 ///< RTC HIP Configuration +#define B_ILB_RTCC_RTCB4 BIT6 ///< RTC Bias Resistor 4, Adds 480 Kohm +#define B_ILB_RTCC_RTCB3 BIT5 ///< RTC Bias Resistor 3, Adds 240 Kohm +#define B_ILB_RTCC_RTCB2 BIT4 ///< RTC Bias Resistor 2, Adds 120 Kohm +#define B_ILB_RTCC_RTCB1 BIT3 ///< RTC Bias Resistor 1, Adds 60 Kohm +#define B_ILB_RTCC_RTCB0 BIT2 ///< RTC Bias Resistor 0, Adds 30 Kohm +#define B_ILB_RTCC_DSWEN BIT1 ///< Deep Sleep Well Enable +#define B_ILB_RTCC_FEN BIT0 ///< Enable the Fast Oscillator Bypass Mode + +#define R_ILB_DEF0 0x78 ///< Defeature Register 0 +#define B_ILB_DEF0_SHRTSYNC BIT22 ///< Short Sync Abort Defeature +#define B_ILB_DEF0_SDD BIT21 ///< Sub Decode Disable + +#define R_ILB_DEF1 0x7C ///< Defeature Register 1 +#define B_ILB_DEF1_TPMPF BIT10 ///< usb2leg_chknbit_TPM_PF +#define B_ILB_DEF1_HPETDEF BIT8 ///< usb2leg_chknbit_hpet +#define B_ILB_DEF1_ECWS BIT6 ///< 8254 Early CW Select +#define B_ILB_DEF1_FOF BIT5 ///< 8254 Freeze on first on 1st rd wr11 +#define B_ILB_DEF1_FOAR BIT4 ///< 8254 Freeze_On_AnyRead +#define B_ILB_DEF1_LMOO BIT3 ///< 8259 L2L0_Match_On_OCW2 +#define B_ILB_DEF1_DFP BIT2 ///< 8259 Disable_Freeze_Priority +#define B_ILB_DEF1_EETI BIT1 ///< 8259 Extend_EdgeTrig_IRQ +#define B_ILB_DEF1_DSAEOI BIT0 ///< 8259 Disable_Slave_AEOI + +#define R_ILB_GNMI 0x80 ///< NMI Register +#define S_ILB_GNMI 4 +#define B_ILB_GNMI_NMI2SMIEN BIT6 ///< NMI to SMI Enable +#define N_ILB_GNMI_NMI2SMIEN 6 +#define B_ILB_GNMI_NMI2SMIST BIT5 ///< NMI to SMI Status +#define N_ILB_GNMI_NMI2SMIST 5 +#define B_ILB_GNMI_NMIN BIT4 ///< NMI NOW +#define B_ILB_GNMI_NMINS BIT3 ///< NMI NOW Status +#define B_ILB_GNMI_GNMIED BIT2 ///< GPIO NMI Edge Detection +#define B_ILB_GNMI_GNMIE BIT1 ///< GPIO NMI Enable +#define B_ILB_GNMI_GNMIS BIT0 ///< GPIO NMI Status + +#define R_ILB_LPCC 0x84 ///< LPC Control +#define B_ILB_LPCC_LPCCLK_SLC BIT8 ///< iLPCCLK Mux Select +#define B_ILB_LPCC_LPCCLK_FORCE_OFF BIT3 +#define B_ILB_LPCC_CLKRUN_EN BIT2 ///< LPC CLKRUN Protocol Enable +#define B_ILB_LPCC_LPCCLK1EN BIT1 ///< Clock 1 Enable +#define B_ILB_LPCC_LPCCLK0EN BIT0 ///< Clock 0 Enable + +#define R_ILB_IRQE 0x88 ///< IRQ Enable Control +#define B_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 ///< UART IRQ4 Enable + +#define R_ILB_CGC 0x8C ///< Clock Gating Control +#define B_ILB_CGC_CGD BIT9 ///< SB Clock Gating Def +#define B_ILB_CGC_CGE BIT8 ///< SB Clock Gating Enable +#define B_ILB_CGC_IDC 0xFF ///< SB IDLE Count + +#define R_ILB_MSI_DIS 0x94 ///< IOAPIC MSI Disable +#define B_ILB_MSI_DIS BIT0 ///< IOAPIC MSI Disable + +#define R_ILB_GIRR 0x98 ///< IOAPIC RIRR Status +#define B_ILB_GIRR_IOAPIC_RIRR_STS BIT0 ///< IOAPIC.RTE(i).RIRR Status + +/// +/// ACPI and Legacy I/O Registers (ABASE) +/// +#define R_ACPI_PM1_STS 0x00 ///< Power Management 1 Status +#define S_ACPI_PM1_STS 2 +#define B_ACPI_PM1_STS_WAK BIT15 ///< Wake Status +#define B_ACPI_PM1_STS_WAK_PCIE0 BIT14 ///< PCI Express 0 Wake Status +#define B_ACPI_PM1_STS_USB_CLKLESS BIT13 ///< USB Clockless Status +#define B_ACPI_PM1_STS_PRBTNOR BIT11 ///< Power Button Override Status +#define B_ACPI_PM1_STS_RTC BIT10 ///< RTC Status +#define B_ACPI_PM1_STS_PWRBTN BIT8 ///< Power Button Status +#define B_ACPI_PM1_STS_GBL BIT5 ///< Global Status +#define B_ACPI_PM1_STS_WAK_PCIE3 BIT4 ///< PCI Express 3 Wake Status +#define B_ACPI_PM1_STS_WAK_PCIE2 BIT3 ///< PCI Express 2 Wake Status +#define B_ACPI_PM1_STS_WAK_PCIE1 BIT2 ///< PCI Express 1 Wake Status +#define B_ACPI_PM1_STS_TMROF BIT0 ///< Timer Overflow Status +#define N_ACPI_PM1_STS_WAK 15 +#define N_ACPI_PM1_STS_PRBTNOR 11 +#define N_ACPI_PM1_STS_RTC 10 +#define N_ACPI_PM1_STS_PWRBTN 8 +#define N_ACPI_PM1_STS_GBL 5 +#define N_ACPI_PM1_STS_TMROF 0 + +#define R_ACPI_PM1_EN 0x02 ///< Power Management 1 Enables +#define S_ACPI_PM1_EN 2 +#define B_ACPI_PM1_WAK_DIS_PCIE0 BIT14 ///< PCI Express 0 Disable +#define B_ACPI_PM1_EN_USB_CLKLESS BIT13 ///< USB Clockless Enable Bit +#define B_ACPI_PM1_EN_RTC BIT10 ///< RTC Alarm Enable Bit +#define B_ACPI_PM1_EN_PWRBTN BIT8 ///< Power Button Enable Bit +#define B_ACPI_PM1_EN_GBL BIT5 ///< Global Enable Bit +#define B_ACPI_PM1_WAK_DIS_PCIE3 BIT4 ///< PCI Express 3 Disable +#define B_ACPI_PM1_WAK_DIS_PCIE2 BIT3 ///< PCI Express 2 Disable +#define B_ACPI_PM1_WAK_DIS_PCIE1 BIT2 ///< PCI Express 1 Disable +#define B_ACPI_PM1_EN_TMROF BIT0 ///< Timer Overflow Interrupt Enable Bit +#define N_ACPI_PM1_EN_RTC 10 +#define N_ACPI_PM1_EN_PWRBTN 8 +#define N_ACPI_PM1_EN_GBL 5 +#define N_ACPI_PM1_EN_TMROF 0 + +#define R_ACPI_PM1_CNT 0x04 ///< Power Management 1 Control +#define S_ACPI_PM1_CNT 4 +#define B_ACPI_PM1_CNT_SLP_EN BIT13 ///< Sleep enable +#define B_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type +#define V_ACPI_PM1_CNT_S0 0x00000000 ///< ON (S0) +#define V_ACPI_PM1_CNT_S1 0x00000400 ///< Puts CPU in S1 state (S1) +#define V_ACPI_PM1_CNT_S3 0x00001400 ///< Suspend-to-RAM (S3) +#define V_ACPI_PM1_CNT_S4 0x00001800 ///< Suspend-to-Disk (S4) +#define V_ACPI_PM1_CNT_S5 0x00001C00 ///< Soft Off (S5) +#define B_ACPI_PM1_CNT_GBL_RLS BIT2 +#define B_ACPI_PM1_CNT_BM_RLD BIT1 ///< Treated as Scratchpad Bit +#define B_ACPI_PM1_CNT_SCI_EN BIT0 ///< SCI Enable + +#define R_ACPI_PM1_TMR 0x08 ///< Power Management 1 Timer +#define B_ACPI_PM1_TMR_VAL 0xFFFFFF ///< The timer value mask +#define V_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow +#define V_ACPI_PM1_TMR_FREQUENCY 3579545 ///< Timer Frequency +#define V_ACPI_PM1_TMR_NUM_BITS 24 ///< Programmed to 24 not 32 +#define V_ACPI_PM1_TMR_MAX_BITS 32 + +#define R_ACPI_GPE0a_STS 0x20 ///< General Purpose Event 0a Status +#define S_ACPI_GPE0a_STS 4 +#define B_ACPI_GPE0a_STS_CORE_GPIO 0xFF000000 ///< CORE GPIO Status +#define B_ACPI_GPE0a_STS_SUS_GPIO 0x00FF0000 ///< SUS GPIO Status +#define B_ACPI_GPE0a_STS_PME_B0 BIT13 ///< Power Management Event Bus 0 Status +#define B_ACPI_GPE0a_STS_BATLOW BIT10 ///< Battery Low Status +#define B_ACPI_GPE0a_STS_PCI_EXP BIT9 ///< PCI Express Status +#define B_ACPI_GPE0a_STS_GUNIT_SCI BIT5 ///< GUNIT SCI Status +#define B_ACPI_GPE0a_STS_PUNIT_SCI BIT4 ///< PUNIT SCI Status +#define B_ACPI_GPE0a_STS_SWGPE BIT2 ///< Software GPE Status +#define B_ACPI_GPE0a_STS_HOT_PLUG BIT1 ///< Hot Plug Status +#define N_ACPI_GPE0a_STS_PME_B0 13 +#define N_ACPI_GPE0a_STS_BATLOW 10 +#define N_ACPI_GPE0a_STS_PCI_EXP 9 +#define N_ACPI_GPE0a_STS_GUNIT_SCI 5 +#define N_ACPI_GPE0a_STS_PUNIT_SCI 4 +#define N_ACPI_GPE0a_STS_SWGPE 2 +#define N_ACPI_GPE0a_STS_HOT_PLUG 1 + +#if (ENBDT_PF_ENABLE == 1) +#define R_ACPI_GPE0a_EN 0x30 ///< General Purpose Event 0a Enables +#else +#define R_ACPI_GPE0a_EN 0x28 ///< General Purpose Event 0a Enables +#endif + +#define S_ACPI_GPE0a_EN 4 +#define B_ACPI_GPE0a_EN_CORE_GPIO 0xFF000000 ///< CORE GPIO Enable +#define B_ACPI_GPE0a_EN_SUS_GPIO 0x00FF0000 ///< SUS GPIO Enable + +#define B_ACPI_GPE0a_EN_SATA_PME_EN BIT17 ///< SATA PME Enable +#define B_ACPI_GPE0a_EN_SMB_WAK_EN BIT16 ///< GPIO SMBUS WAKE Enable +#define B_ACPI_GPE0a_EN_GPIO_TIER1_SCI_EN BIT15 ///< GPIO Tier1 SCI Enable +#define B_ACPI_GPE0a_EN_AVS_PME_EN BIT14 ///< AVS PME Enable +#define B_ACPI_GPE0a_EN_XHCI_PME_EN BIT13 ///< USB xHCI PME Wire Enable +#define B_ACPI_GPE0a_EN_XDCI_PME_EN BIT12 ///< USB xDCI PME Wire Enable +#define B_ACPI_GPE0a_EN_CSE_PME_EN BIT11 ///< CSE PME Message Enable +#define B_ACPI_GPE0a_EN_BATLOW_EN BIT10 ///< Low Battery Enable +#define B_ACPI_GPE0a_EN_PCIE_GPE_EN BIT9 ///< PCIE GPE Enable +#define B_ACPI_GPE0a_EN_PCIE_WAKE3_EN BIT8 ///< PCI Express Wake3 Enable +#define B_ACPI_GPE0a_EN_PCIE_WAKE2_EN BIT7 ///< PCI Express Wake2 Enable +#define B_ACPI_GPE0a_EN_PCIE_WAKE1_EN BIT6 ///< PCI Express Wake1 Enable +#define B_ACPI_GPE0a_EN_PUNIT_SCI_EN BIT4 ///< PUnit SCI Enable +#define B_ACPI_GPE0a_EN_PCIE_WAKE0_EN BIT3 ///< PCI Express Wake0 Enable +#define B_ACPI_GPE0a_EN_SWGPE_EN BIT2 ///< Software GPE Enable +#define B_ACPI_GPE0a_EN_PCIE_SCI_EN BIT0 ///< PCIE SCI Message Enable + +#define N_ACPI_GPE0a_EN_BATLOW 10 +#define N_ACPI_GPE0a_EN_PCIE_PME 9 +#define N_ACPI_GPE0a_EN_SWGPE 2 +#define N_ACPI_GPE0a_EN_HOT_PLUG 1 + +#if (ENBDT_PF_ENABLE == 1) + #define R_SMI_EN 0x40 ///< SMI Control and Enable +#else + #define R_SMI_EN 0x30 ///< SMI Control and Enable +#endif + +#define S_SMI_EN 4 +#define B_SMI_EN_SPI_SSMI BIT25 ///< SPI Sync SMI Enable +#define B_SMI_EN_LEGACY_USB3 BIT17 ///< Legacy USB 3 Enable +#define B_SMI_EN_PERIODIC BIT14 ///< Periodic Enable +#define B_SMI_EN_TCO BIT13 ///< TCO Enable +#define B_SMI_EN_GPIO_UNLOCK BIT11 ///< GPIO Unlock SMI EN +#define B_SMI_EN_GPIO BIT10 ///< GPIO Enable +#define B_SMI_EN_BIOS_RLS BIT7 ///< BIOS RLS +#define B_SMI_EN_SWSMI_TMR BIT6 ///< Software SMI Timer Enable +#define B_SMI_EN_APMC BIT5 ///< APMC Enable +#define B_SMI_EN_ON_SLP_EN BIT4 ///< SMI On Sleep Enable +#define B_SMI_EN_BIOS BIT2 ///< BIOS Enable +#define B_SMI_EN_EOS BIT1 ///< End of SMI +#define B_SMI_EN_GBL_SMI BIT0 ///< Global SMI Enable +#define N_SMI_EN_SPI_SSMI 25 +#define N_SMI_EN_LEGACY_USB3 17 +#define N_SMI_EN_PERIODIC 14 +#define N_SMI_EN_TCO 13 +#define N_SMI_EN_GPIO_UNLOCK 11 +#define N_SMI_EN_GPIO 10 +#define N_SMI_EN_BIOS_RLS 7 +#define N_SMI_EN_SWSMI_TMR 6 +#define N_SMI_EN_APMC 5 +#define N_SMI_EN_ON_SLP_EN 4 +#define N_SMI_EN_LEGACY_USB 3 +#define N_SMI_EN_BIOS 2 +#define N_SMI_EN_EOS 1 +#define N_SMI_EN_GBL_SMI 0 + +#if (ENBDT_PF_ENABLE == 1) +#define R_SMI_STS 0x44 ///< SMI Status Register +#else +#define R_SMI_STS 0x34 ///< SMI Status Register +#endif +#define S_SMI_STS 4 +#define B_SMI_STS_SPI BIT26 ///< SPI SMI Status +#define B_SMI_STS_SPI_SSMI BIT25 ///< SPI Sync SMI Status +#define B_SMI_STS_PCI_EXP BIT20 ///< PCI Express SMI Status +#define B_SMI_STS_LEGACY_USB3 BIT17 ///< Legacy USB 3 Status +#define B_SMI_STS_SERIRQ BIT15 ///< SERIRQ SMI Status +#define B_SMI_STS_PERIODIC BIT14 ///< Periodic Status +#define B_SMI_STS_TCO BIT13 ///< TCO Status +#define B_SMI_STS_GPIO_UNLOCK BIT11 ///< GPIO Unlock SMI EN +#define B_SMI_STS_GPIO BIT10 ///< GPIO Enable +#define B_SMI_STS_GPE0 BIT9 ///< GPE0 Status +#define B_SMI_STS_PM1_STS_REG BIT8 ///< PM1 Status Register +#define B_SMI_STS_SWSMI_TMR BIT6 ///< Software SMI Timer Status +#define B_SMI_STS_APM BIT5 ///< APM Status +#define B_SMI_STS_ON_SLP_EN BIT4 ///< SMI On Sleep Enable Status +#define B_SMI_STS_BIOS BIT2 ///< BIOS Status +#define N_SMI_STS_SPI 26 +#define N_SMI_STS_SPI_SSMI 25 +#define N_SMI_STS_PCI_EXP 20 +#define N_SMI_STS_LEGACY_USB3 17 +#define N_SMI_STS_SERIRQ 15 +#define N_SMI_STS_PERIODIC 14 +#define N_SMI_STS_TCO 13 +#define N_SMI_STS_GPIO_UNLOCK 11 +#define N_SMI_STS_GPIO 10 +#define N_SMI_STS_GPE0 9 +#define N_SMI_STS_PM1_STS_REG 8 +#define N_SMI_STS_SWSMI_TMR 6 +#define N_SMI_STS_APM 5 +#define N_SMI_STS_ON_SLP_EN 4 +#define N_SMI_STS_LEGACY_USB 3 +#define N_SMI_STS_BIOS 2 + +#define R_ALT_GP_SMI_EN 0x38 ///< Alternate GPI SMI Enable +#define S_ALT_GP_SMI_EN 2 +#define B_ALT_GP_SMI_EN_CORE_GPIO 0xFF00 ///< SUS GPIO SMI Enable +#define B_ALT_GP_SMI_EN_SUS_GPIO 0x00FF ///< CORE GPIO SMI Enable + +#define R_ALT_GP_SMI_STS 0x3A ///< Alternate GPI SMI Status +#define S_ALT_GP_SMI_STS 2 +#define B_ALT_GP_SMI_STS_CORE_GPIO 0xFF00 ///< SUS GPIO SMI Status +#define B_ALT_GP_SMI_STS_SUS_GPIO 0x00FF ///< CORE GPIO SMI Status + +#define R_UPRWC 0x3C ///< USB Per-Port Registers Write Control +#define S_UPRWC 2 +#define B_UPRWC_WR_EN_SMI_STS BIT8 ///< Write Enable Status +#define B_UPRWC_WR_EN BIT1 ///< USB Per-Port Registers Write Enable +#define B_UPRWC_WR_EN_SMI_EN BIT0 ///< Write Enable SMI Enable + + +#if (ENBDT_PF_ENABLE == 1) +#define R_ACPI_GPE_CNTL 0x50 ///< General Purpose Event Control +#else +#define R_ACPI_GPE_CNTL 0x40 ///< General Purpose Event Control +#endif +#define B_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 ///< Software GPE Control +#define B_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3 +#define B_ACPI_GPE_CNTL_PCIE2_SCI_EN BIT2 +#define B_ACPI_GPE_CNTL_PCIE1_SCI_EN BIT1 +#define B_ACPI_GPE_CNTL_PCIE0_SCI_EN BIT0 + +#define R_ACPI_PM2_CNT 0x50 ///< PM2a Control Block +#define B_ACPI_PM2_CNT_ARB_DIS BIT0 ///< Scratchpad Bit + +#define R_TCO_RLD 0x60 ///< TCO Reload +#define B_TCO_RLD_VAL 0x3FF ///< TCO Timer Count Value + +#define R_TCO_STS 0x64 ///< TCO Timer Status +#define S_TCO_STS 4 +#define B_TCO_STS_SECOND_TO BIT17 ///< Second Timeout Status +#define B_TCO_STS_TIMEOUT BIT3 ///< Timeout +#define N_TCO_STS_TIMEOUT 3 + +#define R_TCO_CNT 0x68 ///< TCO Control +#define S_TCO_CNT 2 +#define B_TCO_CNT_OS_POLICY (BIT21 | BIT20) ///< OS Policy +#define B_TCO_CNT_LOCK BIT12 ///< TCO Enable Lock +#define B_TCO_CNT_TMR_HLT BIT11 ///< TCO Timer Halt + +#define R_TCO_TMR 0x70 ///< TCO Timer +#define B_TCO_TMR_TCO_TRLD 0x3FF0000 + +#define R_DIRECT_IRQ_EN 0x7C ///< Direct IRQ Enables +#define B_DIRECT_IRQ_EN_PMIC_EN BIT9 +#define B_DIRECT_IRQ_EN_XHCI_EN BIT8 +#define B_DIRECT_IRQ_EN_XDCI_EN BIT7 +#define B_DIRECT_IRQ_EN_SDIO_D1_EN BIT6 +#define B_DIRECT_IRQ_EN_SDCARD_CD_EN BIT5 +#define B_DIRECT_IRQ_EN_SDCARD_D1_EN BIT4 +#define B_DIRECT_IRQ_EN_UART3_EN BIT3 +#define B_DIRECT_IRQ_EN_UART2_EN BIT2 +#define B_DIRECT_IRQ_EN_UART1_EN BIT1 +#define B_DIRECT_IRQ_EN_UART0_EN BIT0 + +/// +/// PMC Memory Space Registers (PBASE) +/// +#define V_PMC_GCR_OFFSET 0x1000 + +#define R_PMC_PRSTS 0x00 ///< Power and Reset Status +#define B_PMC_PRSTS_PRODID 0xFF000000 ///< Power Management Controller Product ID +#define B_PMC_PRSTS_REVID 0x00FF0000 ///< Power Management Controller Revision ID +#define B_PMC_PRSTS_PM_WD_TMR BIT15 ///< PMC Watchdog Timer Status +#define B_PMC_PRSTS_SEC_GBLRST_STS BIT7 ///< SEC Global Reset Status +#define B_PMC_PRSTS_SEC_WD_TMR_STS BIT6 ///< SEC Watchdog Timer Status + +#define R_PMC_PM_CFG 0x08 ///< Power Management Configuration +#define B_PMC_PM_CFG_SPS BIT5 ///< Shutdown Policy Select +#define B_PMC_PM_CFG_NO_REBOOT BIT4 ///< No Reboot Strap +#define B_PMC_PM_CFG_SX_ENT_TO_EN BIT3 ///< S1 / 3 / 4 / 5 Entry Timeout Enable + +#define R_PMC_CFG2 0x0C ///< Power Management Configuration 2 +#define B_PMC_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP) +#define N_PMC_CFG2_PBOP 29 ///< Power Button Override Period (PBOP) +#define B_PMC_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS) +#define B_PMC_CFG2_PB_PWRBTN_DB_MODE BIT10 ///< Power Button Debounce Mode + +#define R_PMC_GEN_PMCON_1 0x20 ///< General PM Configuration 1 +#define B_PMC_GEN_PMCON_COLD_BOOT_STS BIT27 ///< Cold boot Status +#define B_PMC_GEN_PMCON_COLD_RST_STS BIT26 ///< Cold Reset Status +#define B_PMC_GEN_PMCON_WARM_RST_STS BIT25 ///< Warm Reset Status +#define B_PMC_GEN_PMCON_GLOBAL_RST_STS BIT24 ///< Global Reset Status +#define B_PMC_GEN_PMCON_DRAM_INIT BIT23 ///< DRAM Initialization Scratchpad Bit +#define B_PMC_GEN_PMCON_MEM_SR BIT21 ///< Memory Placed in Self-Refresh +#define B_PMC_GEN_PMCON_SRS BIT20 ///< System Reset Status +#define B_PMC_GEN_PMCON_CTS BIT19 ///< CPU Thermal Trip Status +#define B_PMC_GEN_PMCON_MIN_SLP_S4 BIT18 ///< Minimum SLP_S4# Assertion Width Violation Status +#define B_PMC_GEN_PMCON_PWROK_FLR BIT16 ///< PWROK Failure +#define B_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 ///< PME B0 S5 Disable +#define B_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 ///< SUS Well Power Failure +#define B_PMC_GEN_PMCON_GEN_RST_STS BIT9 ///< General Reset Status +#define B_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) ///< SWSMI Rate Select +#define V_PMC_GEN_PMCON_SWSMI_RTSL_64MS 0xC0 ///< 64ms +/- 4ms +#define V_PMC_GEN_PMCON_SWSMI_RTSL_32MS 0x80 ///< 32ms +/- 4ms +#define V_PMC_GEN_PMCON_SWSMI_RTSL_16MS 0x40 ///< 16ms +/- 4ms +#define V_PMC_GEN_PMCON_SWSMI_RTSL_1_5MS 0x00 ///< 1.5ms +/- 0.6ms +#define B_PMC_GEN_PMCON_RTC_PWR_STS BIT2 ///< RTC Power Status +#define B_PMC_GEN_PMCON_AFTERG3_EN BIT0 ///< After G3 State Enable + +#define R_PMC_GEN_PMCON_2 0x24 ///< General PM Configuration 2 +#define B_PMC_GEN_PMCON_BIOS_PCI_EXP_EN BIT10 ///< BIOS PCI Express Enable +#define B_PMC_GEN_PMCON_PWRBTN_LVL BIT9 ///< Power Button Level +#define B_PMC_GEN_PMCON_SMI_LOCK BIT4 ///< SMI Lock +#define B_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) ///< Period SMI Select +#define V_PMC_GEN_PMCON_PER_SMI_64S 0x0000 ///< 64 seconds +#define V_PMC_GEN_PMCON_PER_SMI_32S 0x0001 ///< 32 seconds +#define V_PMC_GEN_PMCON_PER_SMI_16S 0x0002 ///< 16 seconds +#define V_PMC_GEN_PMCON_PER_SMI_8S 0x0003 ///< 8 seconds + +#define R_PMC_CRID 0x30 ///< Configured Revision ID +#define B_PMC_CRID_RID_SEL (BIT1 | BIT0) ///< Revision ID Select + +#define R_PMC_FUNC_DIS 0x34 ///< Function Disable Register (FUNC_DIS_31_0) +/// +/// applicable to Audio and ISH only for BXT0 +/// +#define B_PMC_FUNC_DIS_GMM BIT31 ///<31 GMM (GMM) Set by BIOS to inform PMC GMM is disabled. +#define B_PMC_FUNC_DIS_SPI BIT30 ///<30 SPI (SPI) Set by BIOS to inform PMC SPI is disabled. + ///<29 SSRAM (SSRAM) Set by BIOS to inform PMC SSRAM is disabled. +#define B_PMC_FUNC_DIS_AVS BIT28 ///<28 cAVS (cAVS) Set by BIOS to inform PMC cAVS is disabled. + ///<27 CSE_HECI1 (CSE_HECI1) Set by BIOS to inform PMC CSE_HECI1 is disabled. + ///<26 CSE_HECI2 (CSE_HECI2) Set by BIOS to inform PMC CSE_HECI2 is disabled. + ///<25 CSE_HECI3 (CSE_HECI3) Set by BIOS to inform PMC CSE_HECI3 is disabled. +#define B_PMC_FUNC_DIS_ISH BIT24 ///<24 ISH (ISH) Set by BIOS to inform PMC ISH is disabled. +#define B_PMC_FUNC_DIS_PCIE0_P0 BIT23 ///<23 Set by BIOS to inform PMC PCIE0 P0 is disabled. +#define B_PMC_FUNC_DIS_PCIE0_P1 BIT22 ///<22 Set by BIOS to inform PMC PCIE0 P1 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C0 BIT21 ///<21 LPSS_I2C0 (LPSS_I2C0) Set by BIOS to inform PMC LPSS_I2C0 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C1 BIT20 ///<20 LPSS_I2C1 (LPSS_I2C1) Set by BIOS to inform PMC LPSS_I2C1 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C2 BIT19 ///<19 LPSS_I2C2 (LPSS_I2C2) Set by BIOS to inform PMC LPSS_I2C2 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C3 BIT18 ///<18 LPSS_I2C3 (LPSS_I2C3) Set by BIOS to inform PMC LPSS_I2C3 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C4 BIT17 ///<17 LPSS_I2C4 (LPSS_I2C4) Set by BIOS to inform PMC LPSS_I2C4 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C5 BIT16 ///<16 LPSS_I2C5 (LPSS_I2C5) Set by BIOS to inform PMC LPSS_I2C5 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C6 BIT15 ///<15 LPSS_I2C6 (LPSS_I2C6) Set by BIOS to inform PMC LPSS_I2C6 is disabled. +#define B_PMC_FUNC_DIS_LPSS_I2C7 BIT14 ///<14 LPSS_I2C7 (LPSS_I2C7) Set by BIOS to inform PMC LPSS_I2C7 is disabled. +#define B_PMC_FUNC_DIS_LPSS_UART0 BIT13 ///<13 LPSS_UART0 (LPSS_UART0) Set by BIOS to inform PMC LPSS_UART0 is disabled. +#define B_PMC_FUNC_DIS_LPSS_UART1 BIT12 ///<12 LPSS_UART1 (LPSS_UART1) Set by BIOS to inform PMC LPSS_UART1 is disabled. +#define B_PMC_FUNC_DIS_LPSS_UART2 BIT11 ///<11 LPSS_UART2 (LPSS_UART2) Set by BIOS to inform PMC LPSS_UART2 is disabled. +#define B_PMC_FUNC_DIS_LPSS_UART3 BIT10 ///<10 LPSS_UART3 (LPSS_UART3) Set by BIOS to inform PMC LPSS_UART3 is disabled. +#define B_PMC_FUNC_DIS_LPSS_SPI0 BIT9 ///< 9 LPSS_SPI0 (LPSS_SPI0) Set by BIOS to inform PMC LPSS_SPI0 is disabled. +#define B_PMC_FUNC_DIS_LPSS_SPI1 BIT8 ///< 8 LPSS_SPI1 (LPSS_SPI1) Set by BIOS to inform PMC LPSS_SPI1 is disabled. +#define B_PMC_FUNC_DIS_LPSS_SPI2 BIT7 ///< 7 LPSS_SPI2 (LPSS_SPI2) Set by BIOS to inform PMC LPSS_SPI2 is disabled. +#define B_PMC_FUNC_DIS_LPSS_PWM BIT6 ///< 6 PWM (PWM) Set by BIOS to inform PMC PWM is disabled. +#define B_PMC_FUNC_DIS_SCC_SDCARD BIT5 ///< 5 SCC_SDCARD (SCC_SDCARD) Set by BIOS to inform PMC SCC_SDCARD is disabled. +#define B_PMC_FUNC_DIS_SCC_SDIO BIT4 ///< 4 SCC_SDIO (SCC_SDIO) Set by BIOS to inform PMC SCC_SDIO is disabled. +#define B_PMC_FUNC_DIS_SCC_EMMC BIT3 ///< 3 SCC_eMMC (SCC_eMMC) Set by BIOS to inform PMC SCC_eMMC is disabled. +#define B_PMC_FUNC_DIS_SCC_UFS BIT2 ///< 2 UFS (UFS) Set by BIOS to inform PMC UFS is disabled. +#define B_PMC_FUNC_DIS_USB_XHCI BIT1 ///< 1 xHCI (xHCI) Set by BIOS to inform PMC xHCI is disabled. +#define B_PMC_FUNC_DIS_USB_XDCI BIT0 ///< 0 xDCI (xDCI) Set by BIOS to inform PMC xDCI is disabled. +#define R_PMC_FUNC_DIS_1 0x38 ///< Function Disable Register 1 (FUNC_DIS_63_32) +#define B_PMC_FUNC_DIS_1_SATA BIT9 ///< Set by BIOS to inform PMC SATA is Disable +#define B_PMC_FUNC_DIS_1_PCIE1_P3 BIT6 ///< Set by BIOS to inform PMC PCIE1 P3 is disabled. +#define B_PMC_FUNC_DIS_1_PCIE1_P2 BIT5 ///< Set by BIOS to inform PMC PCIE1 P2 is disabled. +#define B_PMC_FUNC_DIS_1_PCIE1_P1 BIT4 ///< Set by BIOS to inform PMC PCIE1 P1 is disabled. +#define B_PMC_FUNC_DIS_1_PCIE1_P0 BIT3 ///< Set by BIOS to inform PMC PCIE1 P0 is disabled. +#define B_PMC_FUNC_DIS_1_USF2 BIT2 ///< Set by BIOS to inform PMC USF 3rd lane Disable + +#define R_PMC_PMIR 0x48 ///< Extended Test Mode Register (ETR) +#define B_PMC_PMIR_CF9LOCK BIT31 ///< CF9h Lockdown +#define B_PMC_PMIR_CF9GR BIT20 ///< CF9h Global Reset +#define B_PMC_PMIR_MAX_S0IX (BIT17 | BIT16) ///< Max S0ix State SoC Can Go + +#define R_PMC_GPIO_GPE_CFG 0x50 ///GPIO GPE Config register + +#define R_PMC_IRQ_SEL_0 0x64 ///< IRQ Select 0 +#define N_PMC_IRQ_SEL_0_DIR_IRQ_UART3 24 +#define N_PMC_IRQ_SEL_0_DIR_IRQ_UART2 16 +#define N_PMC_IRQ_SEL_0_DIR_IRQ_UART1 8 +#define N_PMC_IRQ_SEL_0_DIR_IRQ_UART0 0 + + +#define R_PMC_IRQ_SEL_1 0x68 ///< IRQ Select 1 +#define N_PMC_IRQ_SEL_1_DIR_IRQ_XHCI 24 +#define N_PMC_IRQ_SEL_1_DIR_IRQ_XDCI 16 +#define N_PMC_IRQ_SEL_1_DIR_IRQ_SDCARD_CD 8 +#define N_PMC_IRQ_SEL_1_DIR_IRQ_SDCARD_D1 0 + +#define R_PMC_IRQ_SEL_2 0x6C ///< IRQ Select 2 +#define N_PMC_IRQ_SEL_2_AX_SCIS 29 +#define N_PMC_IRQ_SEL_2_SCIS 24 +#define N_PMC_IRQ_SEL_2_AX_DIR_IRQ_SEL_PMIC 21 +#define N_PMC_IRQ_SEL_2_DIR_IRQ_SEL_PMIC 16 + +#define V_PMC_IRQ_SEL_2_AX_SCI_IRQ_9 0 ///< IRQ9 (A Stepping) +#define V_PMC_IRQ_SEL_2_SCI_IRQ_9 9 ///< IRQ9 +#define V_PMC_IRQ_SEL_2_SCI_IRQ_10 BIT0 ///< IRQ10 +#define V_PMC_IRQ_SEL_2_SCI_IRQ_11 BIT1 ///< IRQ11 +#define V_PMC_IRQ_SEL_2_SCI_IRQ_DIS (BIT1 | BIT0) ///< Routing Disabled +#define V_PMC_IRQ_SEL_2_SCI_IRQ_20 BIT2 ///< IRQ20 (Only if APIC enabled) +#define V_PMC_IRQ_SEL_2_SCI_IRQ_21 (BIT2 | BIT0) ///< IRQ21 (Only if APIC enabled) +#define V_PMC_IRQ_SEL_2_SCI_IRQ_22 (BIT2 | BIT1) ///< IRQ22 (Only if APIC enabled) +#define V_PMC_IRQ_SEL_2_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) ///< IRQ23 (Only if APIC enabled) + +#define R_PMC_FUNC_ACPI_ENUM_0 0x70 +#define R_PMC_FUNC_ACPI_ENUM_1 0x74 + +#define R_PMC_OBFF_DSPLAY_HPD_CTL 0x94 ///< Display Hot Plug Control + +#define R_PMC_OBFF_CTRL_STS 0xC8 ///< OBFF Control and Status + +#define R_PMC_LOCK 0xCC ///< Lock Register +#define B_PMC_LOCK_OBFF BIT12 ///< OBFF Lock +#define B_PMC_LOCK_PWRBTN BIT11 ///< Power Button Lock +#define B_PMC_LOCK_IRQ_SEL BIT8 ///< IRQ Select Lock +#define B_PMC_LOCK_CRID BIT7 ///< CRID Lock +#define B_PMC_LOCK_SX_WAKE BIT6 ///< Sx Wake Lock +#define B_PMC_LOCK_PER_SMI BIT5 ///< Periodic SMI Lock +#define B_PMC_LOCK_FUNC_DIS BIT3 ///< Func Dis Lock +#define B_PMC_LOCK_S0IX BIT2 ///< S0ix Lock + +/// +/// IO Memory Space Registers (IOBASE) +/// +#define R_CFIO_PAD_CONF0 0x00 ///< CFIO PAD_CONF0 +#define R_CFIO_PAD_CONF1 0x04 ///< CFIO PAD_CONF1 +#define R_CFIO_PAD_VAL 0x08 ///< CFIO PAD_VAL +#define R_CFIO_PAD_DFT 0x0C ///< CFIO PAD_CFT + +/// +/// MPHY Memory Space Registers (MPBASE) +/// +#define R_MPHY_USBIR_Port_0 0x80000 ///< USB Initialization Register Port 0 +#define R_MPHY_USBIR_Port_1 0x80004 ///< USB Initialization Register Port 1 +#define R_MPHY_USBIR_Port_2 0x80008 ///< USB Initialization Register Port 2 +#define R_MPHY_USBIR_Port_3 0x8000C ///< USB Initialization Register Port 3 +#define R_MPHY_USBIR_Port_4 0x80010 ///< USB Initialization Register Port 4 +#define R_MPHY_USBIR_Port_5 0x80014 ///< USB Initialization Register Port 5 +#define R_MPHY_USBIR_Port_6 0x80018 ///< USB Initialization Register Port 6 +#define R_MPHY_USBIR_Port_7 0x8001C ///< USB Initialization Register Port 7 +#define R_MPHY_USBIR_Port_8 0x80020 ///< USB Initialization Register Port 8 +#define R_MPHY_USBIR_Port_9 0x80024 ///< USB Initialization Register Port 9 +#define R_MPHY_USBIR_Port_10 0x80028 ///< USB Initialization Register Port 10 +#define R_MPHY_USBIR_Port_11 0x8002C ///< USB Initialization Register Port 11 +#define R_MPHY_USBIR_Port_12 0x80030 ///< USB Initialization Register Port 12 +#define R_MPHY_USBIR_Port_13 0x80034 ///< USB Initialization Register Port 13 +#define B_MPHY_USB_PI_FIELD_1_MASK 0x0FFF ///< USB Port Initialization Field 1 + +#define R_MPHY_USBIRA 0x80064 ///< USB Initialization Register A +#define R_MPHY_USBIRB 0x80070 ///< USB Initialization Register B +#define R_MPHY_USBIRC 0x8007C ///< USB Initialization Register C + + +/// +/// Fixed IO Space +/// +/// +/// Processor Interface Registers +/// +#define R_NMI_SC 0x61 ///< NMI Status and Control +#define B_NMI_SC_SERR_NMI_STS BIT7 ///< SERR# NMI Status +#define B_NMI_SC_IOCHK_NMI_STS BIT6 ///< IOCHK NMI Status +#define B_NMI_SC_TMR2_OUT_STS BIT5 ///< Timer Counter 2 Status +#define B_NMI_SC_REF_TOGGLE BIT4 ///< Refresh Cycle toggle Status +#define B_NMI_SC_IOCHK_NMI_EN BIT3 ///< IOCHK NMI Enable +#define B_NMI_SC_PCI_SERR_EN BIT2 ///< SERR# NMI Enable +#define B_NMI_SC_SPKR_DAT_EN BIT1 ///< Speaker Data Enable +#define B_NMI_SC_TIM_CNT2_EN BIT0 ///< Timer Counter 2 Enable + +#define R_NMI_EN 0x70 ///< NMI Enable and Real Time Clock Index, Co-function with R_RTC_INDEX +#define B_NMI_EN_NMI_EN BIT7 ///< NMI Enable, must preserve this bit first before writing to IO port 0x70 + +/// +/// RTC Registers +/// +#define R_RTC_INDEX 0x70 ///< NMI Enable and Real Time Clock Index, Co-function with R_NMI_EN +#define R_RTC_TARGET 0x71 ///< Real-Time Clock Target Register +#define R_RTC_EXT_INDEX 0x72 ///< Extended RAM Index Register +#define R_RTC_EXT_TARGET 0x73 ///< Extended RAM Target Register +#define R_RTC_INDEX2 0x74 ///< Real-Time Clock Index Register +#define R_RTC_TARGET2 0x75 ///< Real-Time Clock Target Register +#define R_RTC_EXT_INDEX2 0x76 ///< Extended RAM Index Register +#define R_RTC_EXT_TARGET2 0x77 ///< Extended RAM Target Register + +#define R_RTC_SECONDS 0x00 ///< Seconds, Range 0..59 +#define R_RTC_SECONDSALARM 0x01 ///< Seconds Alarm, Range 0..59 +#define R_RTC_MINUTES 0x02 ///< Minutes, Range 0..59 +#define R_RTC_MINUTESALARM 0x03 ///< Minutes Alarm, Range 0..59 +#define R_RTC_HOURS 0x04 ///< Hours, Range 1..12 or 0..23 Bit 7 is AM/PM +#define R_RTC_HOURSALARM 0x05 ///< Hours Alarm, Range 1..12 or 0..23 Bit 7 is AM/PM +#define R_RTC_DAYOFWEEK 0x06 ///< Day of Week, Range 1..7 +#define R_RTC_DAYOFMONTH 0x07 ///< Day of Month, Range 1..31 +#define R_RTC_MONTH 0x08 ///< Month, Range 1..12 +#define R_RTC_YEAR 0x09 ///< Year, Range 0..99 + +#define R_RTC_REGISTERA 0x0A ///< RTC Register A +#define B_RTC_REGISTERA_UIP BIT7 ///< Update In Progress +#define B_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) ///< Division Chain Select +#define V_RTC_REGISTERA_DV_NORM_OP 0x20 ///< Normal Operation +#define V_RTC_REGISTERA_DV_BYP_5 0x30 ///< Bypass 5 Stages (Test mode only) +#define V_RTC_REGISTERA_DV_BYP_10 0x40 ///< Bypass 10 Stages (Test mode only) +#define V_RTC_REGISTERA_DV_BYP_15 0x50 ///< Bypass 15 Stages (Test mode only) +#define V_RTC_REGISTERA_DV_DIV_RST1 0x60 ///< Divider Reset +#define V_RTC_REGISTERA_DV_DIV_RST2 0x70 ///< Divider Reset +#define B_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) ///< Rate Select +#define V_RTC_REGISTERA_RS_INT_NV_TGL 0x00 ///< Interrupt Never Toggles +#define V_RTC_REGISTERA_RS_3P906MS1 0x01 ///< 3.90625 ms +#define V_RTC_REGISTERA_RS_7P812MS1 0x02 ///< 7.8125 ms +#define V_RTC_REGISTERA_RS_122P0US 0x03 ///< 122.070 us +#define V_RTC_REGISTERA_RS_244P1US 0x04 ///< 244.141 us +#define V_RTC_REGISTERA_RS_488P2US 0x05 ///< 488.281 us +#define V_RTC_REGISTERA_RS_976P5US 0x06 ///< 976.5625 us +#define V_RTC_REGISTERA_RS_1P953MS 0x07 ///< 1.953125 ms +#define V_RTC_REGISTERA_RS_3P906MS 0x08 ///< 3.90625 ms +#define V_RTC_REGISTERA_RS_7P812MS 0x09 ///< 7.8125 ms +#define V_RTC_REGISTERA_RS_15P62MS 0x0A ///< 15.625 ms +#define V_RTC_REGISTERA_RS_31P25MS 0x0B ///< 31.25 ms +#define V_RTC_REGISTERA_RS_62P5MS 0x0C ///< 62.5 ms +#define V_RTC_REGISTERA_RS_125MS 0x0D ///< 125 ms +#define V_RTC_REGISTERA_RS_250MS 0x0E ///< 250 ms +#define V_RTC_REGISTERA_RS_500MS 0x0F ///< 500 ms + +#define R_RTC_REGISTERB 0x0B ///< RTC Register B +#define B_RTC_REGISTERB_SET BIT7 ///< Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs +#define B_RTC_REGISTERB_PIE BIT6 ///< Periodic Interrupt Enable +#define B_RTC_REGISTERB_AIE BIT5 ///< Alarm Interrupt Enable +#define B_RTC_REGISTERB_UIE BIT4 ///< Update-ended Interrupt Enable +#define B_RTC_REGISTERB_SQWE BIT3 ///< Square Wave Enable (Not implemented) +#define B_RTC_REGISTERB_DM BIT2 ///< Data Mode 1: Binary; 0:BCD +#define B_RTC_REGISTERB_HF BIT1 ///< Hour Format 1: 24 mode; 0: 12 mode. +#define B_RTC_REGISTERB_DSE BIT0 ///< Daylight Savings Enable (Not Implemented) + +#define R_RTC_REGISTERC 0x0C ///< RTC Register C +#define B_RTC_REGISTERC_IRQF BIT7 ///< Interrupt Request Flag +#define B_RTC_REGISTERC_PF BIT6 ///< Periodic Interrupt Flag +#define B_RTC_REGISTERC_AF BIT5 ///< Alarm Flag +#define B_RTC_REGISTERC_UF BIT4 ///< Update-ended Flag +#define B_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0) + +#define R_RTC_REGISTERD 0x0D ///< RTC Register D +#define B_RTC_REGISTERD_VRT BIT7 ///< Valid RAM and Time Bit +#define B_RTC_REGISTERD_RESERVED BIT6 +#define B_RTC_REGISTERD_DA 0x3F ///< Date Alarm + +#define B_RTC_CENTURY 0x32 ///< Century Data + +/// +/// APM Registers +/// +#define R_APM_CNT 0xB2 ///< Advanced Power Management Control Port +#define R_APM_STS 0xB3 ///< Advanced Power Management Status Port + +/// +/// INIT Register +/// +#define R_PORT92 0x92 +#define B_PORT92_ALT_A20_GATE BIT1 ///< Alternate A20 Gate +#define B_PORT92_INIT_NOW BIT0 ///< Init Now + +/// +/// PCU UART +/// +#define R_COM1_BASE 0x3F8 ///< COM1 IO BASE + +/// +/// Reset Control Register +/// +#define R_RST_CNT 0xCF9 ///< Reset Control +#define B_RST_CNT_FULL_RST BIT3 +#define B_RST_CNT_RST_CPU BIT2 +#define B_RST_CNT_SYS_RST BIT1 +#define V_RST_CNT_FULLRESET 0x0E +#define V_RST_CNT_HARDRESET 0x06 +#define V_RST_CNT_SOFTRESET 0x04 ///< Not supported by CHV +#define V_RST_CNT_HARDSTARTSTATE 0x02 +#define V_RST_CNT_SOFTSTARTSTATE 0x00 + +/// +/// Fixed Memory Region +/// + +/// +/// IO APIC Registers +/// +#define R_IO_APIC_INDEX IO_APIC_INDEX_REGISTER ///< IOAPIC Index Register, 8bit +#define R_IO_APIC_WINDOW IO_APIC_DATA_REGISTER ///< IOAPIC Window Register, 32bit +#define R_IO_APIC_EOI IO_APIC_EOI ///< IOAPIC EOI Register, 8bit + +#define R_IO_APIC_ID 0x00 ///< Identification +#define B_IO_APIC_ID_AID (BIT27 | BIT26 | BIT25 | BIT24) ///< APIC Identification + +#define R_IO_APIC_VS 0x01 ///< Version +#define B_IO_APIC_VS_MRE 0xFF0000 ///< Maximum Redirection Entries +#define B_IO_APIC_VS_PRQ BIT15 ///< Pin Assertion Register Supported +#define B_IO_APIC_VS_VS 0xFF ///< Version + +/// +/// HPET Registers +/// +#define R_HPET HPET_BASE_ADDRESS ///< HPET Base Address + +#define R_HPET_GCID 0x00 ///< HPET General Capabilities and ID, 64bit +#define B_HPET_GCID_CTP 0xFFFFFFFF00000000 ///< Counter Tick Period +#define B_HPET_GCID_VID 0xFFFF0000 ///< Vendor ID +#define B_HPET_GCID_LRC BIT15 ///< Legacy Rout Capable +#define B_HPET_GCID_CS BIT13 ///< Counter Size +#define B_HPET_GCID_NT 0x1F00 ///< Number of Timers +#define B_HPET_GCID_RID 0xFF ///< Revision ID +#define N_HPET_ADDR_ASEL 12 + +#define R_HPET_GCFG 0x10 ///< HPET General Configuration +#define B_HPET_GCFG_LRE BIT1 ///< Legacy Rout Enable +#define B_HPET_GCFG_EN BIT0 ///< Overall Enable + +#define R_HPET_GIS 0x20 ///< HPET General Interrupt Status +#define B_HPET_GIS_T2 BIT2 ///< Timer 2 Status +#define B_HPET_GIS_T1 BIT1 ///< Timer 1 Status +#define B_HPET_GIS_T0 BIT0 ///< Timer 0 Status + +#define R_HPET_MCV 0xF0 ///< HPET Main Counter Value, 64bit + +#define R_HPET_T0C 0x100 ///< HPET Timer 0 Config and Capabilities +#define R_HPET_T0CV_L 0x108 ///< HPET Timer 0 Lower Comparator Value +#define R_HPET_T0CV_H 0x10C ///< HPET Timer 0 Upper Comparator Value + +#define R_HPET_T1C 0x120 ///< HPET Timer 1 Config and Capabilities +#define R_HPET_T1CV 0x128 ///< HPET Timer 1 Comparator Value + +#define R_HPET_T2C 0x140 ///< HPET Timer 2 Config and Capabilities +#define R_HPET_T2CV 0x148 ///< HPET Timer 2 Comparator Value + +#define B_HPET_TXC_IRC 0xFFFFFFFF00000000 ///< Interrupt Rout Capability +#define B_HPET_TXC_FID BIT15 ///< FSB Interrupt Delivery +#define B_HPET_TXC_FE BIT14 ///< FSB Enable +#define B_HPET_TXC_IR 0x3E00 ///< Interrupt Rout +#define B_HPET_TXC_T32M BIT8 ///< Timer 32-bit Mode +#define B_HPET_TXC_TVS BIT6 ///< Timer Value Set +#define B_HPET_TXC_TS BIT5 ///< Timer Size +#define B_HPET_TXC_PIC BIT4 ///< Periodic Interrupt Capable +#define B_HPET_TXC_TYP BIT3 ///< Timer Type +#define B_HPET_TXC_IE BIT2 ///< Interrupt Enable +#define B_HPET_TXC_IT BIT1 ///< Timer Interrupt Type + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPmc.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPmc.h new file mode 100644 index 0000000000..16a1c6a1f3 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsPmc.h @@ -0,0 +1,64 @@ +/** @file + Register names for PMC device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_PCH_" in register names + - Registers / bits that are different between SC generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_CHV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_PCH_" without inserted. + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_PMC_H_ +#define _REGS_PMC_H_ + +/// +/// PMC Registers +/// +#define PMC_BASE_ADDRESS PcdGet32 (PcdPmcGcrBaseAddress) +#define GCR_BASE_ADDRESS PcdGet32 (PcdPmcGcrBaseAddress) + +#define PCI_DEVICE_NUMBER_PMC 13 +#define PCI_FUNCTION_NUMBER_PMC_SSRAM 3 + +/// +/// PMC LPC1 Controller Registers (D13:F1) +/// +#define PCI_DEVICE_NUMBER_PMC_IPC1 PCI_DEVICE_NUMBER_PMC +#define PCI_FUNCTION_NUMBER_PMC_IPC1 1 +#define R_PMC_IPC1_BASE 0x10 ///< BAR0 +#define R_PMC_ACPI_BASE 0x20 ///< BAR2 +#define PMC_GCR_GEN_PMCON1 0x20 + +/// +/// PMC PWM Modules +/// PCI Config Space Registers +/// +#define PCI_DEVICE_NUMBER_PMC_PWM 26 +#define PCI_FUNCTION_NUMBER_PMC_PWM 0 + +#define B_PMC_IOSF2OCP_PCICFGCTRL3_BAR1_DISABLE3 BIT7 + + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSata.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSata.h new file mode 100644 index 0000000000..4fd0538323 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSata.h @@ -0,0 +1,542 @@ +/** @file + Register names for SATA controllers. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_SATA_H_ +#define _REGS_SATA_H_ + +/// +/// SATA Controller Registers (D19:F0) +/// +#define PCI_BUS_NUMBER_SATA 0 +#define PCI_DEVICE_NUMBER_SATA 18 +#define PCI_FUNCTION_NUMBER_SATA 0 + +#define R_SATA_ID 0x00 ///< Identifiers +#define B_SATA_ID_DID 0xFFFF0000 ///< Device ID +#define B_SATA_ID_VID 0x0000FFFF ///< Vendor ID +#define V_SATA_VENDOR_ID V_INTEL_VENDOR_ID +#define V_SATA_DEVICE_ID_BXTP_AHCI 0x5AE3 ///< Broxton AHCI Mode (Ports 0 and 1) + +#define R_SATA_COMMAND 0x04 ///< Command +#define B_SATA_COMMAND_INT_DIS BIT10 ///< Interrupt Disable +#define B_SATA_COMMAND_FBE BIT9 ///< Fast Back-to-back Enable +#define B_SATA_COMMAND_SERR_EN BIT8 ///< SERR# Enable +#define B_SATA_COMMAND_WCC BIT7 ///< Wait Cycle Enable +#define B_SATA_COMMAND_PER BIT6 ///< Parity Error Response Enable +#define B_SATA_COMMAND_VPS BIT5 ///< VGA Palette Snooping Enable +#define B_SATA_COMMAND_PMWE BIT4 ///< Memory Write and Invalidate Enable +#define B_SATA_COMMAND_SCE BIT3 ///< Special Cycle Enable +#define B_SATA_COMMAND_BME BIT2 ///< Bus Master Enable +#define B_SATA_COMMAND_MSE BIT1 ///< Memory Space Enable +#define B_SATA_COMMAND_IOSE BIT0 ///< I/O Space Enable +#define R_SATA_CC 0x0A ///< Class Code +#define B_SATA_CC_BCC 0xFF00 ///< Base Class Code +#define B_SATA_CC_SCC 0x00FF ///< Sub Class Code +#define V_SATA_CC_SCC_IDE 0x01 +#define V_SATA_CC_SCC_AHCI 0x06 +#define V_SATA_CC_SCC_RAID 0x04 +#define R_SATA_AHCI_BAR 0x24 +#define B_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_SATA_AHCI_BAR_LENGTH 0x800 +#define N_SATA_AHCI_BAR_ALIGNMENT 11 +#define V_SATA_AHCI_BAR_LENGTH_64K 0x10000 +#define N_SATA_AHCI_BAR_ALIGNMENT_64K 16 +#define B_SATA_AHCI_BAR_PF BIT3 +#define B_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_SATA_AHCI_BAR_RTE BIT0 +#define R_SATA_PID 0x70 +#define B_SATA_PID_NEXT 0xFF00 +#define V_SATA_PID_NEXT_0 0xB000 +#define V_SATA_PID_NEXT_1 0xA800 +#define B_SATA_PID_CID 0x00FF +#define R_SATA_SS 0x2C ///< Sub System Identifiers +#define B_SATA_SS_SSID 0xFFFF0000 ///< Subsystem ID +#define B_SATA_SS_SSVID 0x0000FFFF ///< Subsystem Vendor ID +#define R_SATA_PC 0x72 +#define S_SATA_PC 2 +#define B_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) +#define V_SATA_PC_PME_0 0x0000 +#define V_SATA_PC_PME_1 0x4000 +#define B_SATA_PC_D2_SUP BIT10 +#define B_SATA_PC_D1_SUP BIT9 +#define B_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_SATA_PC_DSI BIT5 +#define B_SATA_PC_PME_CLK BIT3 +#define B_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_SATA_PMCS 0x74 +#define B_SATA_PMCS_PMES BIT15 +#define B_SATA_PMCS_PMEE BIT8 +#define B_SATA_PMCS_NSFRST BIT3 +#define V_SATA_PMCS_NSFRST_1 0x01 +#define V_SATA_PMCS_NSFRST_0 0x00 +#define B_SATA_PMCS_PS (BIT1 | BIT0) +#define V_SATA_PMCS_PS_3 0x03 +#define V_SATA_PMCS_PS_0 0x00 +#define R_SATA_MID 0x80 +#define B_SATA_MID_NEXT 0xFF00 +#define B_SATA_MID_CID 0x00FF +#define R_SATA_MC 0x82 +#define B_SATA_MC_C64 BIT7 +#define B_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_SATA_MC_MME_4 0x04 +#define V_SATA_MC_MME_2 0x02 +#define V_SATA_MC_MME_1 0x01 +#define V_SATA_MC_MME_0 0x00 +#define B_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_SATA_MC_MMC_4 0x04 +#define V_SATA_MC_MMC_0 0x00 +#define B_SATA_MC_MSIE BIT0 +#define V_SATA_MC_MSIE_1 0x01 +#define V_SATA_MC_MSIE_0 0x00 +#define R_SATA_MD 0x88 +#define B_SATA_MD_MSIMD 0xFFFF + +#define R_SATA_MAP 0x90 +#define B_SATA_MAP_SPD (BIT18 | BIT17 | BIT16) +#define N_SATA_MAP_SPD 16 +#define B_SATA_MAP_SPD2 BIT18 +#define B_SATA_MAP_SPD1 BIT17 +#define B_SATA_MAP_SPD0 BIT16 +#define B_SATA_MAP_PCD 0xFF +#define B_SATA_MAP_PORT7_PCD BIT7 +#define B_SATA_MAP_PORT6_PCD BIT6 +#define B_SATA_MAP_PORT5_PCD BIT5 +#define B_SATA_MAP_PORT4_PCD BIT4 +#define B_SATA_MAP_PORT3_PCD BIT3 +#define B_SATA_MAP_PORT2_PCD BIT2 +#define B_SATA_MAP_PORT1_PCD BIT1 +#define B_SATA_MAP_PORT0_PCD BIT0 + +#define R_SATA_SATAGC 0x9C +#define B_SATA_SATAGC_SMS_MASK BIT16 +#define N_SATA_SATAGC_SMS_MASK 16 +#define V_SATA_SATAGC_SMS_AHCI 0x0 +#define V_SATA_SATAGC_SMS_RAID 0x1 +#define B_SATA_SATAGC_AIE BIT7 +#define B_SATA_SATAGC_AIES BIT6 +#define B_SATA_SATAGC_MSS (BIT4 | BIT3) +#define V_SATA_SATAGC_MSS_8K 0x2 +#define N_SATA_SATAGC_MSS 3 +#define B_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) +#define V_SATA_SATAGC_ASSEL_64K 0x3 + +#define R_SATA_SIRI 0xA0 +#define R_SATA_STRD 0xA4 + +#define R_SATA_SIR_70 0x70 +#define R_SATA_SIR_80 0x80 +#define R_SATA_SIR_88 0x88 +#define R_SATA_SIR_90 0x90 +#define R_SATA_SIR_9C 0x9C +#define R_SATA_SIR_A0 0xA0 +#define R_SATA_SIR_A4 0xA4 +#define R_SATA_SIR_A8 0xA8 +#define R_SATA_SIR_D0 0xD0 +#define R_SATA_SIR_D4 0xD4 +#define B_SATA_STRD_DTA 0xFFFFFFFF +#define R_SATA_CR0 0xA8 +#define B_SATA_CR0_MAJREV 0x00F00000 +#define B_SATA_CR0_MINREV 0x000F0000 +#define B_SATA_CR0_NEXT 0x0000FF00 +#define B_SATA_CR0_CAP 0x000000FF +#define R_SATA_CR1 0xAC +#define B_SATA_CR1_BAROFST 0xFFF0 +#define B_SATA_CR1_BARLOC 0x000F +#define R_SATA_FLR_CID 0xB0 +#define B_SATA_FLR_CID_NEXT 0xFF00 +#define B_SATA_FLR_CID 0x00FF +#define V_SATA_FLR_CID_1 0x0009 +#define V_SATA_FLR_CID_0 0x0013 +#define R_SATA_FLR_CLV 0xB2 +#define B_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_SATA_FLRC 0xB4 +#define B_SATA_FLRC_TXP BIT8 +#define B_SATA_FLRC_INITFLR BIT0 +#define R_SATA_SP 0xC0 +#define B_SATA_SP 0xFFFFFFFF +#define R_SATA_MXID 0xD0 +#define N_SATA_MXID_NEXT 8 + +#define R_SATA_BFCS 0xE0 +#define B_SATA_BFCS_P7BFI BIT17 +#define B_SATA_BFCS_P6BFI BIT16 +#define B_SATA_BFCS_P5BFI BIT15 +#define B_SATA_BFCS_P4BFI BIT14 +#define B_SATA_BFCS_P3BFI BIT13 +#define B_SATA_BFCS_P2BFI BIT12 +#define B_SATA_BFCS_P2BFS BIT11 +#define B_SATA_BFCS_P2BFF BIT10 +#define B_SATA_BFCS_P1BFI BIT9 +#define B_SATA_BFCS_P0BFI BIT8 +#define B_SATA_BFCS_BIST_FIS_T BIT7 +#define B_SATA_BFCS_BIST_FIS_A BIT6 +#define B_SATA_BFCS_BIST_FIS_S BIT5 +#define B_SATA_BFCS_BIST_FIS_L BIT4 +#define B_SATA_BFCS_BIST_FIS_F BIT3 +#define B_SATA_BFCS_BIST_FIS_P BIT2 +#define R_SATA_BFTD1 0xE4 +#define B_SATA_BFTD1 0xFFFFFFFF +#define R_SATA_BFTD2 0xE8 +#define B_SATA_BFTD2 0xFFFFFFFF + +#define R_SATA_VS_CAP 0xA4 +#define B_SATA_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable +#define B_SATA_VS_CAP_MSL 0x1FFE ///< Memory Space Limit +#define N_SATA_VS_CAP_MSL 1 +#define V_SATA_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value +#define B_SATA_VS_CAP_NRMO 0xFFF0000 ///< NVM Remapped Memory Offset +#define N_SATA_VS_CAP_NRMO 16 +#define V_SATA_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value + +/// +/// Memory AHCI BAR Area Related Registers +/// +#define R_SATA_AHCI_CAP 0x0 ///< HBA Capabilities +#define B_SATA_AHCI_CAP_S64A BIT31 ///< Supports 64-bit Addressing +#define B_SATA_AHCI_CAP_SCQA BIT30 ///< Support Native Command Queuing Acceleration +#define B_SATA_AHCI_CAP_SSNTF BIT29 ///< Supports SNotification Register +#define B_SATA_AHCI_CAP_SIS BIT28 ///< Supports Mechanical Presence (Formerly Interlock Switch) +#define B_SATA_AHCI_CAP_SSS BIT27 ///< Supports Staggered Spin-up +#define B_SATA_AHCI_CAP_SALP BIT26 ///< Supports Aggressive Link Power Management +#define B_SATA_AHCI_CAP_SAL BIT25 ///< Supports Activity LED +#define B_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override +#define B_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) ///< Interface Speed Support +#define N_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support +#define V_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define V_SATA_AHCI_CAP_ISS_3_0_G 0x02 ///< Gen 2 (3.0 Gbps) +#define V_SATA_AHCI_CAP_ISS_1_5_G 0x01 ///< Gen 1 (1.5 Gbps) +#define B_SATA_AHCI_CAP_SNZO BIT19 ///< Supports Non-Zero DMA Offsets +#define B_SATA_AHCI_CAP_SAM BIT18 ///< Supports AHCI mode only +#define B_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier + +#define B_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block +#define B_SATA_AHCI_CAP_SSC BIT14 ///< Slumber Slate Capable +#define B_SATA_AHCI_CAP_PSC BIT13 ///< Partial State Capable +#define B_SATA_AHCI_CAP_NCS 0x1F00 ///< Indicating Support for 32 slots +#define B_SATA_AHCI_CAP_CCCS BIT7 ///< Command Completion Coalescing Supported +#define B_SATA_AHCI_CAP_EMS BIT6 ///< Enclosure Management Supported +#define B_SATA_AHCI_CAP_SXS BIT5 ///< Supports External SATA +#define B_SATA_AHCI_CAP_NPS 0x001F + +#define R_SATA_AHCI_GHC 0x04 ///< Global HBA Control +#define B_SATA_AHCI_GHC_AE BIT31 ///< AHCI Enable +#define B_SATA_AHCI_GHC_PITO 0xFF00 +#define B_SATA_AHCI_GHC_MRSM BIT2 ///< MSI Revert to Single Message +#define B_SATA_AHCI_GHC_IE BIT1 ///< Interrupt Enable +#define B_SATA_AHCI_GHC_HR BIT0 ///< HBA Reset + +#define R_SATA_AHCI_IS 0x08 ///< Interrupt Status Register +#define B_SATA_AHCI_IS_PORT5 BIT5 ///< Interrupt Pending Status Port 5 +#define B_SATA_AHCI_IS_PORT4 BIT4 ///< Interrupt Pending Status Port 4 +#define B_SATA_AHCI_IS_PORT3 BIT3 ///< Interrupt Pending Status Port 3 +#define B_SATA_AHCI_IS_PORT2 BIT2 ///< Interrupt Pending Status Port 2 +#define B_SATA_AHCI_IS_PORT1 BIT1 ///< Interrupt Pending Status Port 1 +#define B_SATA_AHCI_IS_PORT0 BIT0 ///< Interrupt Pending Status Port 0 + +#define R_SATA_AHCI_PI 0x0C ///< Ports Implemented +#define B_SATA_PORT_MASK 0x03 +#define B_SATA_PORT5_IMPLEMENTED BIT5 ///< Port 5 Implemented +#define B_SATA_PORT4_IMPLEMENTED BIT4 ///< Port 4 Implemented +#define B_SATA_PORT3_IMPLEMENTED BIT3 ///< Port 3 Implemented +#define B_SATA_PORT2_IMPLEMENTED BIT2 ///< Port 2 Implemented +#define B_SATA_PORT1_IMPLEMENTED BIT1 ///< Port 1 Implemented +#define B_SATA_PORT0_IMPLEMENTED BIT0 ///< Port 0 Implemented + +#define R_SATA_AHCI_VS 0x10 ///< AHCI Version +#define B_SATA_AHCI_VS_MJR 0xFFFF0000 ///< Major Version Number +#define B_SATA_AHCI_VS_MNR 0x0000FFFF ///< Minor Version Number + +#define R_SATA_AHCI_EM_LOC 0x1C ///< Enclosure Management Location +#define B_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 ///< Offset +#define B_SATA_AHCI_EM_LOC_SZ 0x0000FFFF ///< Buffer Size + +#define R_SATA_AHCI_EM_CTRL 0x20 ///< Enclosure Management Control +#define B_SATA_AHCI_EM_CTRL_ATTR_PM BIT27 ///< Port Multiplier Support +#define B_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 ///< Activity LED Hardware Driven +#define B_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 ///< Transmit Only +#define B_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 ///< Single Message Buffer +#define B_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 ///< SGPIO Enclosure Management Messages +#define B_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 ///< SES-2 Enclosure Management Messages +#define B_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 ///< SAF-TE Enclosure Management Messages +#define B_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 ///< LED Message Types +#define B_SATA_AHCI_EM_CTRL_RST BIT9 ///< Reset +#define B_SATA_AHCI_EM_CTRL_CTL_TM BIT8 ///< Transmit Message +#define B_SATA_AHCI_EM_CTRL_STS_MR BIT0 ///< Message Received + +#define R_SATA_AHCI_CAP2 0x24 ///< HBA Capabilities Extended +#define B_SATA_AHCI_CAP2_DESO BIT5 +#define B_SATA_AHCI_CAP2_SADM BIT4 +#define B_SATA_AHCI_CAP2_SDS BIT3 +#define B_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions +#define B_SATA_AHCI_CAP2_BOH BIT0 ///< BIOS / OS Handoff (Not Supported) + +#define R_SATA_AHCI_VSP 0xA0 ///< Vendor Specific +#define B_SATA_AHCI_VSP_SFMS BIT6 ///< Software Feature Mask Supported +#define B_SATA_AHCI_VSP_PFS BIT5 ///< Premium Features Supported +#define B_SATA_AHCI_VSP_PT BIT4 ///< Platform Type +#define B_SATA_AHCI_VSP_SRPIR BIT3 ///< Supports RAID Platform ID Reporting + +#define R_SATA_AHCI_VSCAP 0xA4 ///< Vendor Specific Capabilities Register +#define B_SATA_AHCI_VSCAP_PNRRO 0xFFFF0000 ///< PCIe NAND Remapped Register Offset +#define B_SATA_AHCI_VSCAP_MSL 0x00000FFE +#define B_SATA_AHCI_VSCAP_PNABRE BIT0 ///< PCIe NAND AHCI BAR Remapped Enable + +#define R_SATA_AHCI_RPID 0xC0 ///< RAID Platform ID +#define B_SATA_AHCI_RPID_OFST 0xFFFF0000 ///< Offset +#define B_SATA_AHCI_RPID_RPID 0x0000FFFF ///< RAID Platform ID + +#define R_SATA_AHCI_PFB 0xC4 ///< Premium Feature Block +#define B_SATA_AHCI_PFB_SEA BIT1 ///< Supports Email Alert +#define B_SATA_AHCI_PFB_SOI BIT0 ///< Supports OEM IOCTL + +#define R_SATA_AHCI_SFM 0xC8 ///< SW Feature Mask +#define B_SATA_AHCI_SFM_OUND (BIT11 | BIT10) ///< OROM UI Normal Delay +#define B_SATA_AHCI_SFM_SRT BIT9 ///< Smart Response Technology +#define B_SATA_AHCI_SFM_IROES BIT8 ///< IRRT Only on ESATA +#define B_SATA_AHCI_SFM_LEDL BIT7 ///< LED Locate +#define B_SATA_AHCI_SFM_HDDLK BIT6 ///< HDD Unlock +#define B_SATA_AHCI_SFM_OROMUNB BIT5 ///< OROM UI and Banner +#define B_SATA_AHCI_SFM_IRRT BIT4 ///< IRRT +#define B_SATA_AHCI_SFM_R5E BIT3 ///< R5 Enable +#define B_SATA_AHCI_SFM_R10E BIT2 ///< R10 Enable +#define B_SATA_AHCI_SFM_R1E BIT1 ///< R1 Enable +#define B_SATA_AHCI_SFM_R0E BIT0 ///< R0 Enable +#define B_SATA_AHCI_SFM_LOWBYTES 0x1FF + +#define R_SATA_AHCI_P0CLB 0x100 ///< Port 0 Command List Base Address +#define R_SATA_AHCI_P1CLB 0x180 ///< Port 1 Command List Base Address +#define B_SATA_AHCI_PXCLB 0xFFFFFC00 ///< Command List Base Address + +#define R_SATA_AHCI_P0CLBU 0x104 ///< Port 0 Command List Base Address Upper 32-bits +#define R_SATA_AHCI_P1CLBU 0x184 ///< Port 1 Command List Base Address Upper 32-bits +#define B_SATA_AHCI_PXCLBU 0xFFFFFFFF ///< Command List Base Address Upper + +#define R_SATA_AHCI_P0FB 0x108 ///< Port 0 FIS Base Address +#define R_SATA_AHCI_P1FB 0x188 ///< Port 1 FIS Base Address +#define B_SATA_AHCI_PXFB 0xFFFFFF00 ///< FIS Base Address + +#define R_SATA_AHCI_P0FBU 0x10C ///< Port 0 FIS Base Address Upper 32-bits +#define R_SATA_AHCI_P1FBU 0x18C ///< Port 1 FIS Base Address Upper 32-bits +#define B_SATA_AHCI_PXFBU 0xFFFFFFFF ///< FIS Base Address Upper + +#define R_SATA_AHCI_P0IS 0x110 ///< Port 0 Interrupt Status +#define R_SATA_AHCI_P1IS 0x190 ///< Port 1 Interrupt Status +#define B_SATA_AHCI_PXIS_CPDS BIT31 ///< Cold Presence Detect Status +#define B_SATA_AHCI_PXIS_TFES BIT30 ///< Task File Error Status +#define B_SATA_AHCI_PXIS_HBFS BIT29 ///< Host Bus Fatal Error Status +#define B_SATA_AHCI_PXIS_HBDS BIT28 ///< Host Bus Data Error Status +#define B_SATA_AHCI_PXIS_IFS BIT27 ///< Interface Fatal Error Status +#define B_SATA_AHCI_PXIS_INFS BIT26 ///< Interface Non-Fatal Error Status +#define B_SATA_AHCI_PXIS_OFS BIT24 ///< Overflow Status +#define B_SATA_AHCI_PXIS_IPMS BIT23 ///< Incorrect Port Multiplier Status +#define B_SATA_AHCI_PXIS_PRCS BIT22 ///< PhyRdy Change Status +#define B_SATA_AHCI_PXIS_DMPS BIT7 ///< Device Mechanical Presence Status (Formerly Interlock Switch) +#define B_SATA_AHCI_PXIS_PCS BIT6 ///< Port Connect Change Status +#define B_SATA_AHCI_PXIS_DPS BIT5 ///< Descriptor Processed +#define B_SATA_AHCI_PXIS_UFS BIT4 ///< Unknown FIS Interrupt +#define B_SATA_AHCI_PXIS_SDBS BIT3 ///< Set Device Bits Interrupt +#define B_SATA_AHCI_PXIS_DSS BIT2 ///< DMA Setup FIS Interrupt +#define B_SATA_AHCI_PXIS_PSS BIT1 ///< PIO Setup FIS Interrupt +#define B_SATA_AHCI_PXIS_DHRS BIT0 ///< Device to Host Register FIS Interrupt + +#define R_SATA_AHCI_P0IE 0x114 ///< Port 0 Interrupt Enable +#define R_SATA_AHCI_P1IE 0x194 ///< Port 1 Interrupt Enable +#define B_SATA_AHCI_PXIE_CPDE BIT31 ///< Cold Presence Detect Enable +#define B_SATA_AHCI_PXIE_TFEE BIT30 ///< Task File Error Enable +#define B_SATA_AHCI_PXIE_HBFE BIT29 ///< Host Bus Fatal Error Enable +#define B_SATA_AHCI_PXIE_HBDE BIT28 ///< Host Bus Data Error Enable +#define B_SATA_AHCI_PXIE_IFE BIT27 ///< Interface Fatal Error Enable +#define B_SATA_AHCI_PXIE_INFE BIT26 ///< Interface Non-Fatal Error Enable +#define B_SATA_AHCI_PXIE_OFE BIT24 ///< Overflow Enable +#define B_SATA_AHCI_PXIE_IPME BIT23 ///< Incorrect Port Multiplier Enable +#define B_SATA_AHCI_PXIE_PRCE BIT22 ///< PhyRdy Change Interrupt Enable +#define B_SATA_AHCI_PXIE_DIE BIT7 ///< Device Mechanical Enable (Formerly Interlock Switch) +#define B_SATA_AHCI_PXIE_PCE BIT6 ///< Port Change Interrupt Enable +#define B_SATA_AHCI_PXIE_DPE BIT5 ///< Descriptor Processed Interrupt Enable +#define B_SATA_AHCI_PXIE_UFIE BIT4 ///< Unknown FIS Interrupt Enable +#define B_SATA_AHCI_PXIE_SDBE BIT3 ///< Set Device Bits FIS Interrupt Enable +#define B_SATA_AHCI_PXIE_DSE BIT2 ///< DMA Setup FIS Interrupt Enable +#define B_SATA_AHCI_PXIE_PSE BIT1 ///< PIO Setup FIS Interrupt Enable +#define B_SATA_AHCI_PXIE_DHRE BIT0 ///< Device to Host Register FIS Interrupt Enable + +#define R_SATA_AHCI_P0CMD 0x118 ///< Port 0 Command +#define R_SATA_AHCI_P1CMD 0x198 ///< Port 1 Command +#define B_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) ///< Interface Communication Control +#define B_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT21 | BIT22 | BIT19 | BIT18) +#define B_SATA_AHCI_PxCMD_ASP BIT27 ///< Aggressive Slumber Partial +#define B_SATA_AHCI_PxCMD_ALPE BIT26 ///< Aggressive Link Power Management Enable +#define B_SATA_AHCI_PxCMD_DLAE BIT25 ///< Drive LED on ATAPI Enable +#define B_SATA_AHCI_PxCMD_ATAPI BIT24 ///< Device is ATAPI +#define B_SATA_AHCI_PxCMD_APSTE BIT23 ///< Automatic Partial to Slumber Transitions Enable + +#define B_SATA_AHCI_PxCMD_ESP BIT21 ///< External SATA Port +#define B_SATA_AHCI_PxCMD_CPD BIT20 ///< Cold Presence Detection +#define B_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Presence Switch Attached to Port +#define B_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hot Plug Capable Port + +#define B_SATA_AHCI_PxCMD_CR BIT15 ///< Command List Running +#define B_SATA_AHCI_PxCMD_FR BIT14 ///< FIS Receive Running +#define B_SATA_AHCI_PxCMD_MPSS BIT13 ///< Mechanical Presence Switch State (Formerly Interlock Switch) +#define B_SATA_AHCI_PxCMD_CCS 0x00001F00 ///< Current Command Slot +#define B_SATA_AHCI_PxCMD_FRE BIT4 ///< FIS Receive Enable +#define B_SATA_AHCI_PxCMD_CLO BIT3 ///< Command List Overide +#define B_SATA_AHCI_PxCMD_POD BIT2 ///< Power On Device +#define B_SATA_AHCI_PxCMD_SUD BIT1 ///< Spin-Up Device +#define B_SATA_AHCI_PxCMD_ST BIT0 ///< Start + +#define R_SATA_AHCI_P0TFD 0x120 ///< Port 0 Task File Data +#define R_SATA_AHCI_P1TFD 0x1A0 ///< Port 1 Task File Data +#define B_SATA_AHCI_PXTFD_ERR 0x0000FF00 ///< Error +#define B_SATA_AHCI_PXTFD_STS 0x000000FF ///< Status +#define B_SATA_AHCI_PXTFD_STS_BSY BIT7 ///< Status Busy +#define B_SATA_AHCI_PXTFD_STS_DRQ BIT3 ///< Status DRQ +#define B_SATA_AHCI_PXTFD_STS_ERR BIT0 ///< Status Error + +#define R_SATA_AHCI_P0SIG 0x124 ///< Port 0 Signature +#define R_SATA_AHCI_P1SIG 0x1A4 ///< Port 1 Signature +#define B_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_SATA_AHCI_PXSIG_SCR 0x000000FF + +#define R_SATA_AHCI_P0SSTS 0x128 ///< Port 0 Serial ATA Status +#define R_SATA_AHCI_P1SSTS 0x1A8 ///< Port 1 Serial ATA Status +#define B_SATA_AHCI_PXSSTS_IPM 0x00000F00 ///< Interface Power Management +#define B_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_SATA_AHCI_PXSSTS_SPD 0x000000F0 ///< Current Interface Speed +#define B_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_SATA_AHCI_PXSSTS_DET 0x0000000F ///< Device Detection +#define B_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_SATA_AHCI_PXSSTS_DET_4 0x00000004 + +#define R_SATA_AHCI_P0SCTL 0x12C ///< Port 0 Serial ATA Control +#define R_SATA_AHCI_P1SCTL 0x1AC ///< Port 1 Serial ATA Control +#define B_SATA_AHCI_PXSCTL_IPM 0x00000F00 ///< Interface Power Management Transitions Allowed +#define V_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_SATA_AHCI_PXSCTL_SPD 0x000000F0 ///< Speed Allowed +#define V_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_SATA_AHCI_PXSCTL_DET 0x0000000F ///< Device Detection Initialization +#define V_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_SATA_AHCI_PXSCTL_DET_4 0x00000004 + +#define R_SATA_AHCI_P0SERR 0x130 ///< Port 0 Serial ATA Error +#define R_SATA_AHCI_P1SERR 0x1B0 ///< Port 1 Serial ATA Error +#define B_SATA_AHCI_PXSERR_DIAG 0xFFFF0000 ///< Diagnostics +#define B_SATA_AHCI_PXSERR_ERR 0x0000FFFF ///< Error +#define B_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_SATA_AHCI_PXSERR_RCE BIT1 +#define B_SATA_AHCI_PXSERR_RDIE BIT0 + +#define R_SATA_AHCI_P0SACT 0x134 ///< Port 0 Serial ATA Active +#define R_SATA_AHCI_P1SACT 0x1B4 ///< Port 1 Serial ATA Active +#define B_SATA_AHCI_PXSACT_DS 0xFFFFFFFF + +#define R_SATA_AHCI_P0CI 0x138 ///< Port 0 Commands Issued +#define R_SATA_AHCI_P1CI 0x1B8 ///< Port 1 Commands Issued +#define B_SATA_AHCI_PXCI 0xFFFFFFFF + +#define R_SATA_AHCI_P0DEVSLP 0x144 ///< Port [0-5] Device Sleep +#define R_SATA_AHCI_P1DEVSLP 0x1C4 ///< Port [0-5] Device Sleep + +#define B_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 + +#define R_SATA_AHCI_EM_MF 0x580 ///< Enclosure Management Message Format +#define B_SATA_AHCI_EM_MF_MTYPE 0x0F000000 ///< Message Type +#define B_SATA_AHCI_EM_MF_DSIZE 0x00FF0000 ///< Data Size +#define B_SATA_AHCI_EM_MF_MSIZE 0x0000FF00 ///< Message Size + +#define R_SATA_AHCI_EM_LED 0x584 ///< Enclosure Management LED +#define B_SATA_AHCI_EM_LED_VAL 0xFFFF0000 +#define B_SATA_AHCI_EM_LED_PM 0x0000FF00 +#define B_SATA_AHCI_EM_LED_HBA 0x000000FF + +/// +/// Macros of capabilities for SATA controller which are used by SATA controller driver +/// +/// +/// +/// Define the individual capabilities of each SATA controller +/// +#define SATA_MAX_CONTROLLERS 1 ///< Max SATA controllers number supported +#define SATA_MAX_DEVICES 2 ///< Max SATA devices number of single SATA channel +#define IDE_MAX_CHANNELS 2 ///< Max IDE channels number of single SATA controller +#define IDE_MAX_DEVICES 2 ///< Max IDE devices number of single SATA channel +#define AHCI_MAX_PORTS 2 ///< Max number of SATA ports +#define IDE_MAX_PORTS 2 ///< Max number of IDE ports + +/// +/// GPIOS_14 SATA0GP is the SATA port 0 reset pin. +/// +#define GPIO_SATA_PORT0_RESET 14 +/// +/// GPIOS_15 SATA1GP is the SATA port 1 reset pin. +/// +#define GPIO_SATA_PORT1_RESET 15 + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsScc.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsScc.h new file mode 100644 index 0000000000..55ea81535a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsScc.h @@ -0,0 +1,233 @@ +/** @file + Register names for SCC module. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_SCC_H_ +#define _REGS_SCC_H_ + +/// +/// SCC Modules Registers +/// +/// +/// SCC SDIO Modules +/// PCI Config Space Registers +/// +#define PCI_DEVICE_NUMBER_SCC_SDCARD 27 +#define PCI_DEVICE_NUMBER_SCC_EMMC 28 +#define PCI_DEVICE_NUMBER_SCC_UFS 29 +#define PCI_DEVICE_NUMBER_SCC_SDIO 30 +#define PCI_FUNCTION_NUMBER_SCC_FUNC0 0 + +#define R_SCC_DEVVENDID 0x00 ///< Device ID & Vendor ID +#define B_SCC_DEVVENDID_DID 0xFFFF0000 ///< Device ID +#define B_SCC_DEVVENDID_VID 0x0000FFFF ///< Vendor ID + +#define V_SCC_EMMC_DEVICE_ID_0 0x0F50 ///< RVP +#define V_SCC_EMMC_DEVICE_ID_1 0x0ACC ///< BXT-A +#define V_SCC_EMMC_DEVICE_ID_2 0x5ACC ///< BXTP +#define V_SCC_EMMC_DEVICE_ID_3 0x1ACC ///< BXT-B + +#define R_SCC_STSCMD 0x04 ///< Status & Command +#define B_SCC_STSCMD_RMA BIT29 ///< RMA +#define B_SCC_STSCMD_RCA BIT28 ///< RCA +#define B_SCC_STSCMD_CAPLIST BIT20 ///< Capability List +#define B_SCC_STSCMD_INTRSTS BIT19 ///< Interrupt Status +#define B_SCC_STSCMD_INTRDIS BIT10 ///< Interrupt Disable +#define B_SCC_STSCMD_SERREN BIT8 ///< SERR# Enable +#define B_SCC_STSCMD_BME BIT2 ///< Bus Master Enable +#define B_SCC_STSCMD_MSE BIT1 ///< Memory Space Enable + +#define R_SCC_REVCC 0x08 ///< Revision ID & Class Code +#define B_SCC_REVCC_CC 0xFFFFFF00 ///< Class Code +#define B_SCC_REVCC_RID 0x000000FF ///< Revision ID + +#define R_SCC_CLHB 0x0C +#define B_SCC_CLHB_MULFNDEV BIT23 ///< Multi Function Device +#define B_SCC_CLHB_HT 0x007F0000 ///< Header Type +#define B_SCC_CLHB_LT 0x0000FF00 ///< Latency Timer +#define B_SCC_CLHB_CLS 0x000000FF ///< Cache Line Size + +#define R_SCC_BAR 0x10 ///< BAR +#define B_SCC_BAR_BA 0xFFFFF000 ///< Base Address +#define V_SCC_BAR_SIZE 0x1000 +#define N_SCC_BAR_ALIGNMENT 12 +#define B_SCC_BAR_SI 0x00000FF0 ///< Size Indicator +#define B_SCC_BAR_PF BIT3 ///< Prefetchable +#define B_SCC_BAR_TYPE (BIT2 | BIT1) ///< Type +#define B_SCC_BAR_MS BIT0 ///< Message Space + +#define R_SCC_BAR_HIGH 0x14 ///< BAR High +#define B_SCC_BAR_HIGH_BA 0xFFFFFFFF ///< Base Address + +#define R_SCC_BAR1 0x18 ///< BAR 1 +#define B_SCC_BAR1_BA 0xFFFFF000 ///< Base Address +#define V_SCC_BAR1_SIZE 0x1000 +#define B_SCC_BAR1_SI 0x00000FF0 ///< Size Indicator +#define B_SCC_BAR1_PF BIT3 ///< Prefetchable +#define B_SCC_BAR1_TYPE (BIT2 | BIT1) ///< Type +#define B_SCC_BAR1_MS BIT0 ///< Message Space + +#define R_SCC_BAR1_HIGH 0x1C ///< BAR 1 High +#define B_SCC_BAR1_HIGH_BA 0xFFFFFFFF ///< Base Address + +#define R_SCC_SSID 0x2C ///< Sub System ID +#define B_SCC_SSID_SID 0xFFFF0000 ///< Sub System ID +#define B_SCC_SSID_SVID 0x0000FFFF ///< Sub System Vendor ID + +#define R_SCC_ERBAR 0x30 ///< Expansion ROM BAR +#define B_SCC_ERBAR_BA 0xFFFFFFFF ///< Expansion ROM Base Address + +#define R_SCC_CAPPTR 0x34 ///< Capability Pointer +#define B_SCC_CAPPTR_CPPWR 0xFF ///< Capability Pointer Power + +#define R_SCC_INTR 0x3C ///< Interrupt +#define B_SCC_INTR_ML 0xFF000000 ///< Max Latency +#define B_SCC_INTR_MG 0x00FF0000 +#define B_SCC_INTR_IP 0x00000F00 ///< Interrupt Pin +#define B_SCC_INTR_IL 0x000000FF ///< Interrupt Line + +#define R_SCC_PCAPID 0x80 ///< Power Capability ID +#define B_SCC_PCAPID_PS 0xF8000000 ///< PME Support +#define B_SCC_PCAPID_VS 0x00070000 ///< Version +#define B_SCC_PCAPID_NC 0x0000FF00 ///< Next Capability +#define B_SCC_PCAPID_PC 0x000000FF ///< Power Capability + +#define R_SCC_PCS 0x84 ///< PME Control Status +#define B_SCC_PCS_PMESTS BIT15 ///< PME Status +#define B_SCC_PCS_PMEEN BIT8 ///< PME Enable +#define B_SCC_PCS_NSS BIT3 ///< No Soft Reset +#define B_SCC_PCS_PS (BIT1 | BIT0) ///< Power State + +#define R_SCC_MANID 0xF8 ///< Manufacturer ID +#define B_SCC_MANID_MANID 0xFFFFFFFF ///< Manufacturer ID + +#define R_SCC_D0I3MAXDEVPG 0x0A0 ///< D0i3 Max Power On Latency and Device PG config + +/// +/// SCC Devices MMIO Space Register +/// +#define R_SCC_MEM_DMAADR 0x00 +#define R_SCC_MEM_BLKSZ 0x04 +#define R_SCC_MEM_BLKCNT 0x06 +#define R_SCC_MEM_CMDARG 0x08 +#define R_SCC_MEM_XFRMODE 0x0C +#define B_SCC_MEM_XFRMODE_DMA_EN BIT0 +#define B_SCC_MEM_XFRMODE_BLKCNT_EN BIT1 +#define B_SCC_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3) +#define V_SCC_MEM_XFRMODE_AUTOCMD12_EN 1 +#define B_SCC_MEM_XFRMODE_DATA_TRANS_DIR BIT4 ///< 1: Read (Card to Host), 0: Write (Host to Card) +#define B_SCC_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 ///< 1: Multiple Block, 0: Single Block +#define R_SCC_MEM_SDCMD 0x0E +#define B_SCC_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1) +#define V_SCC_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0 +#define V_SCC_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1 +#define V_SCC_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2 +#define V_SCC_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3 +#define B_SCC_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3 +#define B_SCC_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4 +#define B_SCC_MEM_SDCMD_DATA_PRESENT_SEL BIT5 +#define R_SCC_MEM_RESP 0x10 +#define R_SCC_MEM_BUFDATAPORT 0x20 +#define R_SCC_MEM_PSTATE 0x24 +#define B_SCC_MEM_PSTATE_DAT0 BIT20 +#define R_SCC_MEM_PWRCTL 0x29 +#define R_SCC_MEM_CLKCTL 0x2C +#define R_SCC_MEM_TIMEOUT_CTL 0x2E ///< Timeout Control +#define B_SCC_MEM_TIMEOUT_CTL_DTCV 0x0F ///< Data Timeout Counter Value +#define R_SCC_MEM_SWRST 0x2F +#define B_SCC_MEM_SWRST_CMDLINE BIT1 +#define B_SCC_MEM_SWRST_DATALINE BIT2 +#define R_SCC_MEM_NINTSTS 0x30 +#define B_SCC_MEM_NINTSTS_MASK 0xFFFF +#define B_SCC_MEM_NINTSTS_CLEAR_MASK 0x60FF +#define B_SCC_MEM_NINTSTS_CMD_COMPLETE BIT0 +#define B_SCC_MEM_NINTSTS_TRANSFER_COMPLETE BIT1 +#define B_SCC_MEM_NINTSTS_DMA_INTERRUPT BIT3 +#define B_SCC_MEM_NINTSTS_BUF_READ_READY_INTR BIT5 +#define R_SCC_MEM_ERINTSTS 0x32 +#define B_SCC_MEM_ERINTSTS_MASK 0x13FF +#define B_SCC_MEM_ERINTSTS_CLEAR_MASK 0x13FF +#define R_SCC_MEM_NINTEN 0x34 +#define B_SCC_MEM_NINTEN_MASK 0x7FFF +#define R_SCC_MEM_ERINTEN 0x36 +#define B_SCC_MEM_ERINTEN_MASK 0x13FF +#define R_SCC_MEM_NINTSIGNEN 0x38 +#define B_SCC_MEM_NINTSIGNEN_MASK 0x7FFF +#define R_SCC_MEM_ERINTSIGNEN 0x3A +#define B_SCC_MEM_ERINTSIGNEN_MASK 0x13FF +#define R_SCC_MEM_HOST_CTL2 0x3E +#define B_SCC_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2) +#define V_SCC_MEM_HOST_CTL2_MODE_HS400 5 +#define V_SCC_MEM_HOST_CTL2_MODE_SDR104 3 +#define R_SCC_MEM_CESHC2 0x3C ///< Auto CMD12 Error Status Register & Host Control 2 +#define B_SCC_MEM_CESHC2_ASYNC_INT BIT30 ///< Asynchronous Interrupt Enable +#define R_SCC_MEM_CAP1 0x40 +#define R_SCC_MEM_CAP2 0x44 +#define B_SCC_MEM_CAP2_HS400_SUPPORT BIT31 +#define B_SCC_MEM_CAP2_SDR104_SUPPORT BIT1 + +#define R_SCC_MEM_SW_LTR_VALUE 0x804 ///< Software LTR Register +#define R_SCC_MEM_AUTO_LTR_VALUE 0x808 ///< Auto LTR Value +#define R_SCC_MEM_CAP_BYPASS_CNTL 0x810 ///< Capabilities Bypass Control +#define V_SCC_MEM_CAP_BYPASS_CNTL_EN 0x5A +#define R_SCC_MEM_CAP_BYPASS_REG1 0x814 ///< Capabilities Bypass Register 1 +#define V_SCC_MEM_CAP_BYPASS_REG1_DEFAULTS 0x3040EB1E +#define B_SCC_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_COUNT (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22) +#define N_SCC_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_COUNT 22 +#define V_SCC_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_COUNT 1 +#define B_SCC_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20 | BIT19 | BIT18 | BIT17) +#define N_SCC_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17 +#define V_SCC_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8 +#define B_SCC_MEM_CAP_BYPASS_REG1_HIGH_SPEED_MODE BIT3 +#define B_SCC_MEM_CAP_BYPASS_REG1_3P3V_SUPPORT BIT6 +#define B_SCC_MEM_CAP_BYPASS_REG1_ASYNC_INTERRUPT BIT10 +#define B_SCC_MEM_CAP_BYPASS_REG1_SDR50 BIT13 +#define B_SCC_MEM_CAP_BYPASS_REG1_SDR104 BIT14 +#define B_SCC_MEM_CAP_BYPASS_REG1_DDR50 BIT15 +#define B_SCC_MEM_CAP_BYPASS_REG1_HS400 BIT29 + +#define R_SCC_MEM_CAP_BYPASS_REG2 0x818 ///< Capabilities Bypass Register 2 +#define V_SCC_MEM_CAP_BYPASS_REG2_DEFAULTS 0x040040C8 +#define B_SCC_MEM_CAP_BYPASS_REG2_8BIT_SUPPORT BIT14 +#define R_SCC_MEM_IDLE_CTRL 0x81C ///< DevIdle Control per SCC slice +#define R_SCC_MEM_TX_CMD_DLL_CNTL 0x820 ///< Tx CMD Path Ctrl +#define R_SCC_MEM_TX_DATA_DLL_CNTL1 0x824 ///< Tx Data Path Ctrl 1 +#define R_SCC_MEM_TX_DATA_DLL_CNTL2 0x828 ///< Tx Data Path Ctrl 2 +#define R_SCC_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C ///< Rx CMD&Data Path Ctrl 1 +#define R_SCC_MEM_RX_STROBE_DLL_CNTL 0x830 ///< Rx Strobe Ctrl Path +#define R_SCC_MEM_RX_CMD_DATA_DLL_CNTL2 0x834 ///< Rx CMD&Data Path Ctrl 2 +#define N_SCC_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16 +#define V_SCC_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2 +#define R_SCC_MEM_MASTER_DLL_SW_CNTL 0x838 ///< Master DLL Software Ctrl + +#define R_SCC_MEM_CUR_XFSM 0x858 ///< Internal Clock Unit XFSM + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSmbus.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSmbus.h new file mode 100644 index 0000000000..baa0ec4ea6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSmbus.h @@ -0,0 +1,225 @@ +/** @file + Register names for Smbus Device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_SMBUS_H_ +#define _REGS_SMBUS_H_ + +/// +/// SMBus Controller Registers (D31:F3) +/// +#define PCI_DEVICE_NUMBER_SMBUS 31 +#define PCI_FUNCTION_NUMBER_SMBUS 1 + +#define R_SMBUS_VENDOR_ID 0x00 ///< Vendor ID +#define V_SMBUS_VENDOR_ID V_INTEL_VENDOR_ID ///< Intel Vendor ID + +#define R_SMBUS_DEVICE_ID 0x02 ///< Device ID +#define V_SMBUS_DEVICE_ID 0x5AD4 + +#define R_SMBUS_PCICMD 0x04 ///< CMD register enables/disables, Memory/IO space access and interrupt +#define B_SMBUS_PCICMD_INTR_DIS BIT10 ///< Interrupt Disable +#define B_SMBUS_PCICMD_FBE BIT9 ///< FBE - reserved as '0' +#define B_SMBUS_PCICMD_SERR_EN BIT8 ///< SERR Enable - reserved as '0' +#define B_SMBUS_PCICMD_WCC BIT7 ///< Wait Cycle Control - reserved as '0' +#define B_SMBUS_PCICMD_PER BIT6 ///< Parity Error - reserved as '0' +#define B_SMBUS_PCICMD_VPS BIT5 ///< VGA Palette Snoop - reserved as '0' +#define B_SMBUS_PCICMD_PMWE BIT4 ///< Postable Memory Write Enable - reserved as '0' +#define B_SMBUS_PCICMD_SCE BIT3 ///< Special Cycle Enable - reserved as '0' +#define B_SMBUS_PCICMD_BME BIT2 ///< Bus Master Enable - reserved as '0' +#define B_SMBUS_PCICMD_MSE BIT1 ///< Memory Space Enable +#define B_SMBUS_PCICMD_IOSE BIT0 ///< I/O Space Enable + +#define R_SMBUS_PCISTS 0x06 ///< Configuration status register +#define B_SMBUS_PCISTS_DPE BIT15 ///< Detect Parity Error - reserved as '0' +#define B_SMBUS_PCISTS_SSE BIT14 ///< Signaled System Error - reserved as '0' +#define B_SMBUS_PCISTS_RMA BIT13 ///< Received Master Abort - reserved as '0' +#define B_SMBUS_PCISTS_RTA BIT12 ///< Received Target Abort - reserved as '0' +#define B_SMBUS_PCISTS_STA BIT11 ///< Signaled Target Abort - reserved as '0' +#define B_SMBUS_PCISTS_DEVT (BIT10 | BIT9) ///< Devsel Timing Status +#define B_SMBUS_PCISTS_DPED BIT8 ///< Data Parity Error Detected - reserved as '0' +#define B_SMBUS_PCISTS_FB2BC BIT7 ///< Fast Back To Back Capable - reserved as '1' +#define B_SMBUS_PCISTS_UDF BIT6 ///< User Defined Features - reserved as '0' +#define B_SMBUS_PCISTS_66MHZ_CAP BIT5 ///< 66 MHz Capable - reserved as '0' +#define B_SMBUS_PCISTS_CAP_LIST BIT4 ///< Capabilities List Indicator - reserved as '0' +#define B_SMBUS_PCISTS_INTS BIT3 ///< Interrupt Status + +#define R_SMBUS_RID 0x08 ///< Revision ID +#define B_SMBUS_RID 0xFF ///< Revision ID + +#define R_SMBUS_PRGIF 0x09 ///< Programming Interface +#define B_SMBUS_PRGIF 0xFF ///< Programming Interface + +#define R_SMBUS_SCC 0x0A ///< Sub Class Code +#define V_SMBUS_SCC 0x05 ///< A value of 05h indicates that this device is a SM Bus serial controller + +#define R_SMBUS_BCC 0x0B ///< Base Class Code +#define V_SMBUS_BCC 0x0C ///< A value of 0Ch indicates that this device is a serial controller + +#define R_SMBUS_BAR0 0x10 ///< The memory bar low +#define B_SMBUS_BAR0_BAR 0xFFFFFFE0 ///< Base Address +#define B_SMBUS_BAR0_PREF BIT3 ///< Hardwired to 0. Indicated that SMBMBAR is not prefetchable +#define B_SMBUS_BAR0_ADDRNG (BIT2 | BIT1) +#define B_SMBUS_BAR0_MSI BIT0 ///< Memory Space Indicator + +#define R_SMBUS_BAR1 0x14 ///< The memory bar high +#define B_SMBUS_BAR1_BAR 0xFFFFFFFF ///< Base Address + +#define R_SMBUS_BASE 0x20 ///< The I/O memory bar +#define B_SMBUS_BASE_BAR 0x0000FFE0 ///< Base Address +#define B_SMBUS_BASE_IOSI BIT0 ///< IO Space Indicator + +#define R_SMBUS_SVID 0x2C ///< Subsystem Vendor ID +#define B_SMBUS_SVID 0xFFFF ///< Subsystem Vendor ID + +#define R_SMBUS_SID 0x2E ///< Subsystem ID +#define B_SMBUS_SID 0xFFFF ///< Subsystem ID + +#define R_SMBUS_INT_LN 0x3C ///< Interrupt Line +#define B_SMBUS_INT_LN 0xFF ///< Interrupt Line + +#define R_SMBUS_INT_PN 0x3D ///< Interrupt Pin +#define B_SMBUS_INT_PN 0xFF ///< Interrupt Pin + +#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W +#define B_PCH_SMBUS_START BIT6 // Start +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block + +#define R_SMBUS_HOSTC 0x40 ///< Host Configuration Register +#define B_SMBUS_HOSTC_SPD_WD BIT4 ///< SPD Write Disable +#define B_SMBUS_HOSTC_SSRESET BIT3 ///< Soft SMBus Reset +#define B_SMBUS_HOSTC_I2C_EN BIT2 ///< I2C Enable Bit +#define B_SMBUS_HOSTC_SMI_EN BIT1 ///< SMI Enable Bit +#define B_SMBUS_HOSTC_HST_EN BIT0 ///< Host Controller Enable Bit + +#define R_SMBUS_TCOBASE 0x50 ///< TCO Base Address +#define B_SMBUS_TCOBASE_BAR 0x0000FFE0 + +#define R_SMBUS_TCOCTL 0x54 ///< TCO Control +#define B_SMBUS_TCOCTL_TCO_BASE_EN BIT8 ///< TCO Base Enable +#define R_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 ///< TCO Base Lock + +#define R_SMBUS_MANID 0xF8 ///< Manufacturer's ID Register +#define B_SMBUS_MANID_DOTID 0x0F000000 ///< DOT ID +#define B_SMBUS_MANID_SID 0x00FF0000 ///< Stepping ID +#define B_SMBUS_MANID_MID 0x0000FF00 ///< Manufacturer ID +#define B_SMBUS_MANID_PPID 0x000000FF ///< Process ID + +/// +/// SMBus I/O Registers +/// +#define R_SMBUS_HSTS 0x00 ///< Host Status Register R/W +#define B_SMBUS_HSTS_ALL 0xFF +#define B_SMBUS_BYTE_DONE_STS BIT7 ///< Byte Done Status +#define B_SMBUS_IUS BIT6 ///< In Use Status +#define B_SMBUS_SMBALERT_STS BIT5 ///< SMBUS Alert +#define B_SMBUS_FAIL BIT4 ///< Failed +#define B_SMBUS_BERR BIT3 ///< Bus Error +#define B_SMBUS_DERR BIT2 ///< Device Error +#define B_SMBUS_ERRORS (B_SMBUS_FAIL | B_SMBUS_BERR | B_SMBUS_DERR) +#define B_SMBUS_INTR BIT1 ///< Interrupt +#define B_SMBUS_HBSY BIT0 ///< Host Busy + +#define R_SMBUS_HCTL 0x02 ///< Host Control Register R/W +#define B_SMBUS_PEC_EN BIT7 ///< Packet Error Checking Enable +#define B_SMBUS_START BIT6 ///< Start +#define B_SMBUS_LAST_BYTE BIT5 ///< Last Byte +#define B_SMBUS_SMB_CMD 0x1C ///< SMB Command +#define V_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C ///< Block Process +#define V_SMBUS_SMB_CMD_IIC_READ 0x18 ///< I2C Read +#define V_SMBUS_SMB_CMD_BLOCK 0x14 ///< Block +#define V_SMBUS_SMB_CMD_PROCESS_CALL 0x10 ///< Process Call +#define V_SMBUS_SMB_CMD_WORD_DATA 0x0C ///< Word Data +#define V_SMBUS_SMB_CMD_BYTE_DATA 0x08 ///< Byte Data +#define V_SMBUS_SMB_CMD_BYTE 0x04 ///< Byte +#define V_SMBUS_SMB_CMD_QUICK 0x00 ///< Quick +#define B_SMBUS_KILL BIT1 ///< Kill +#define B_SMBUS_INTREN BIT0 ///< Interrupt Enable + +#define R_SMBUS_HCMD 0x03 ///< Host Command Register R/W +#define B_SMBUS_HCMD 0xFF ///< Command to be transmitted + +#define R_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W +#define B_SMBUS_ADDRESS 0xFE ///< 7-bit address of the targeted slave +#define B_SMBUS_RW_SEL BIT0 ///< Direction of the host transfer, 1 = read, 0 = write +#define B_SMBUS_RW_SEL_READ 0x01 ///< Read +#define B_SMBUS_RW_SEL_WRITE 0x00 ///< Write + +#define R_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_SMBUS_HBD 0x07 ///< Host Block Data Register R/W +#define R_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W + +#define R_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W +#define B_SMBUS_SLAVE_ADDR 0x7F ///< TCO slave address (Not used, reserved) + +#define R_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W + +#define R_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC +#define B_SMBUS_CRCE BIT0 ///< CRC Error + +#define R_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W +#define B_SMBUS_E32B BIT1 ///< Enable 32-byte Buffer +#define B_SMBUS_AAC BIT0 ///< Automatically Append CRC + +#define R_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W +#define B_SMBUS_SMLINK_CLK_CTL BIT2 ///< Not supported +#define B_SMBUS_SMLINK1_CUR_STS BIT1 ///< Not supported +#define B_SMBUS_SMLINK0_CUR_STS BIT0 ///< Not supported + +#define R_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W +#define B_SMBUS_SMBCLK_CTL BIT2 ///< SMBCLK Control +#define B_SMBUS_SMBDATA_CUR_STS BIT1 ///< SMBDATA Current Status +#define B_SMBUS_SMBCLK_CUR_STS BIT0 ///< SMBCLK Current Status + +#define R_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC +#define B_SMBUS_HOST_NOTIFY_STS BIT0 ///< Host Notify Status + +#define R_SMBUS_SCMD 0x11 ///< Slave Command Register R/W +#define B_SMBUS_SMBALERT_DIS BIT2 ///< Not supported +#define B_SMBUS_HOST_NOTIFY_WKEN BIT1 ///< Host Notify Wake Enable +#define B_SMBUS_HOST_NOTIFY_INTREN BIT0 ///< Host Notify Interrupt Enable + +#define R_SMBUS_NDA 0x14 ///< Notify Device Address Register RO +#define B_SMBUS_DEVICE_ADDRESS 0xFE ///< Device Address + +#define R_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO +#define R_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h new file mode 100644 index 0000000000..27cc50be1c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h @@ -0,0 +1,439 @@ +/** @file + Register names for SPI device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, SC registers are denoted by "_SC_" in register names + - Registers / bits that are different between SC generations are denoted by + "_SC__" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_SPI_H_ +#define _REGS_SPI_H_ + +/// +/// SPI Controller Registers (D13:F2) +/// +#define PCI_DEVICE_NUMBER_SPI 13 +#define PCI_FUNCTION_NUMBER_SPI 2 + +#define R_SPI_ID 0x00 ///< Identifiers +#define R_SPI_COMMAND 0x04 ///< Command +#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register +#define B_SPI_BASE_BAR 0xFFFFF000 ///< MEMBAR +#define B_SPI_BAR0_MASK 0x0FFF +#define B_SPI_BASE_PREF BIT3 ///< Prefetchable +#define B_SPI_BASE_MEMI BIT0 ///< Memory Space Indicator +#define R_SPI_BDE 0xD8 ///< BIOS Decode Enable +#define R_SPI_BCR 0xDC ///< BIOS Control Register +#define S_SPI_BCR 4 +#define B_SPI_BC_OSFH BIT9 ///< OS Function Hide +#define B_SPI_BC_BILD BIT7 +#define B_SPI_BC_BBS BIT6 ///< Boot BIOS strap +#define N_SPI_BC_BBS 6 +#define V_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_SPI_BCR_SMM_BWP BIT5 ///< Enable InSMM.STS +#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC) +#define V_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 ///< Prefetch Enable, Cache Enable +#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable +#define V_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 ///< Prefetch Disable, Cache Enable +#define N_SPI_BCR_SYNC_SS 8 +#define B_SPI_BCR_SYNC_SS BIT8 +#define B_SPI_BCR_BILD BIT7 +#define B_SPI_BCR_EISS BIT5 ///< Enable InSMM.STS +#define B_SPI_BCR_BLE BIT1 ///< Lock Enable (LE) +#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD) +#define N_SPI_BCR_BLE 1 +#define N_SPI_BCR_BIOSWE 0 + +/// +/// SPI Host Interface Registers +/// +#define R_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register (32bits) +#define B_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit +#define B_SPI_BFPR_PRB 0x7FFF ///< BIOS Flash Primary Region Base +#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_SPI_HSFS_FSMIE BIT31 ///< Flash SPI SMI# Enable +#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. +#define N_SPI_HSFS_FDBC 24 +#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle. +#define N_SPI_HSFS_CYCLE 17 +#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read +#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write +#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase +#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase +#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP +#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID +#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status +#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status +#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go. +#define B_SPI_HSFS_FLOCKDN BIT15 ///< Flash Configuration Lock-Down +#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid +#define B_SPI_HSFS_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status +#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress +#define B_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) ///< Block/Sector Erase Size +#define V_SPI_HSFS_BERASE_256B 0//0x00 ///< Block/Sector = 256 Bytes +#define V_SPI_HSFS_BERASE_4K 1//0x01 ///< Block/Sector = 4K Bytes +#define V_SPI_HSFS_BERASE_8K 2//0x10 ///< Block/Sector = 8K Bytes +#define V_SPI_HSFS_BERASE_64K 3//0x11 ///< Block/Sector = 64K Bytes +#define B_SPI_HSFS_AEL BIT2 ///< Access Error Log +#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error +#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done + +#define R_SPI_HSFC 0x06 ///< Hardware Sequencing Flash Control Register (16bits) +#define B_SPI_HSFC_FSMIE BIT15 ///< Flash SPI SMI# Enable +#define B_SPI_HSFC_FDBC_MASK 0x3F00 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. +#define B_SPI_HSFC_FCYCLE_MASK 0x001E ///< Flash Cycle. +#define V_SPI_HSFC_FCYCLE_READ 0 ///< Flash Cycle Read +#define V_SPI_HSFC_FCYCLE_WRITE 2 ///< Flash Cycle Write +#define V_SPI_HSFC_FCYCLE_ERASE 3 ///< Flash Cycle 4k Block Erase +#define V_SPI_HSFC_FCYCLE_SERASE 4 ///< Flash Cycle 64k Sector Erase +#define B_SPI_HSFC_FCYCLE_FGO BIT0 ///< Flash Cycle Go. + +#define R_SPI_FADDR 0x08 ///< SPI Flash Address +#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit) + +#define R_SPI_DLOCK 0x0C ///< Discrete Lock Bits +#define B_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN + +#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits) +#define R_SPI_FDATA01 0x14 ///< SPI Data 01 +#define R_SPI_FDATA02 0x18 ///< SPI Data 02 +#define R_SPI_FDATA03 0x1C ///< SPI Data 03 +#define R_SPI_FDATA04 0x20 ///< SPI Data 04 +#define R_SPI_FDATA05 0x24 ///< SPI Data 05 +#define R_SPI_FDATA06 0x28 ///< SPI Data 06 +#define R_SPI_FDATA07 0x2C ///< SPI Data 07 +#define R_SPI_FDATA08 0x30 ///< SPI Data 08 +#define R_SPI_FDATA09 0x34 ///< SPI Data 09 +#define R_SPI_FDATA10 0x38 ///< SPI Data 10 +#define R_SPI_FDATA11 0x3C ///< SPI Data 11 +#define R_SPI_FDATA12 0x40 ///< SPI Data 12 +#define R_SPI_FDATA13 0x44 ///< SPI Data 13 +#define R_SPI_FDATA14 0x48 ///< SPI Data 14 +#define R_SPI_FDATA15 0x4C ///< SPI Data 15 + +#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register +#define B_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< Master Write Access Grant MASK +#define B_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< Master Read Access Grant Grant MASK +#define B_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK +#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for Region4 PlatformData +#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for Region3 GbE +#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC +#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS +#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor +#define B_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK +#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData +#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE +#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC +#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS +#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor + +#define V_SPI_FLREG_DISABLED 0x00007FFF ////< Region Base all 1's and Limits all 0's indicates the region is disabled. + +#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits) +#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2] + +#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits) +#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2] + +#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits) +#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifies address bits [26:12] +#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifies address bits [26:2] + +#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE)(32bits) +#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifies address bits [26:12] +#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifies address bits [26:2] + +#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits) +#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12] +#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2] + +#define R_SPI_FREG5_DEVICE_EXPANSION_1 0x68 ///< Flash Region 5 (Device Expansion) (32bits) +#define B_SPI_FREG5_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG5_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG6_SECONDARY_BIOS 0x6C ///< Flash Region 6 (Secondary BIOS) (32bits) +#define B_SPI_FREG6_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG6_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG7_UCODE_PATCH 0x70 ///< Flash Region 7 (uCode Patch) (32bits) +#define B_SPI_FREG7_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG7_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG8_EC 0x74 ///< Flash Region 8 (Embedded Controller) (32bits) +#define B_SPI_FREG8_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG8_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG9_DEVICE_EXPANSION_2 0x78 ///< Flash Region 9 (Device Expansion 2) (32bits) +#define B_SPI_FREG9_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG9_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG10_IE_ENGINE 0x7c ///< Flash Region 10 (IE Innovation Engine) (32bits) +#define B_SPI_FREG10_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG10_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define R_SPI_FREG11_10_GBE_A 0x80 ///< Flash Region 11 (10 GBE A) (32bits) +#define B_SPI_FREG11_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_SPI_FREG11_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] + +#define S_SPI_FREGX 4 ///< Size of Flash Region register +#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh +#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position +#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position +#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12] +#define N_SPI_FREGX_BASE 0 ///< Region base bit position +#define N_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position + +#define R_SPI_PR0 0x84 ///< Protected Region 0 Register +#define B_SPI_PR0_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PR0_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] +#define B_SPI_PR0_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PR0_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] + +#define R_SPI_PR1 0x88 ///< Protected Region 1 Register +#define B_SPI_PR1_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PR1_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_SPI_PR1_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PR1_PRB_MASK 0x00007FFF ///< Protected Range Base Mask + +#define R_SPI_PR2 0x8C ///< Protected Region 2 Register +#define B_SPI_PR2_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PR2_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_SPI_PR2_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PR2_PRB_MASK 0x00007FFF ///< Protected Range Base Mask + +#define R_SPI_PR3 0x90 ///< Protected Region 3 Register +#define B_SPI_PR3_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PR3_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_SPI_PR3_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PR3_PRB_MASK 0x00007FFF ///< Protected Range Base Mask + +#define R_SPI_PR4 0x94 ///< Protected Region 4 Register +#define B_SPI_PR4_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PR4_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_SPI_PR4_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PR4_PRB_MASK 0x00007FFF ///< Protected Range Base Mask + +#define S_SPI_PRX 4 ///< Protected Region X Register size +#define B_SPI_PRX_WPE BIT31 ///< Write Protection Enable +#define B_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] +#define N_SPI_PRX_PRL 16 ///< Protected Range Limit bit position +#define B_SPI_PRX_RPE BIT15 ///< Read Protection Enable +#define B_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] +#define N_SPI_PRX_PRB 0 ///< Protected Range Base bit position + +#define R_SPI_GPR0 0x98 ///< Global Protected Range 0 Register +#define B_SPI_GPR0_WPE BIT31 ///< Write Protection Enable +#define B_SPI_GPR0_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_SPI_GPR0_RPE BIT15 ///< Read Protection Enable +#define B_SPI_GPR0_PRB_MASK 0x00007FFF ///< Protected Range Base Mask + +#define R_SPI_SSFCS 0xA0 ///< Software Sequencing Flash Control Status Register +#define B_SPI_SSFCS_SCF_MASK (BIT26 | BIT25 | BIT24) ///< SPI Cycle Frequency +#define V_SPI_SSFCS_SCF_48MHZ 2 ///< SPI Cycle Frequency = 48MHz +#define V_SPI_SSFCS_SCF_30MHZ 4 ///< SPI Cycle Frequency = 30MHz +#define V_SPI_SSFCS_SCF_17MHZ 6 ///< SPI Cycle Frequency = 17MHz + +#define B_SPI_SSFCS_SME BIT23 ///< SPI SMI# Enable +#define B_SPI_SSFCS_DC BIT22 ///< SPI Data Cycle +#define B_SPI_SSFCS_DBC_MASK 0x3F0000 ///< SPI Data Byte Count (value here + 1 = count) +#define B_SPI_SSFCS_COP 0x7000 ///< Cycle Opcode Pointer +#define B_SPI_SSFCS_SPOP BIT11 ///< Sequence Prefix Opcode Pointer +#define B_SPI_SSFCS_ACS BIT10 ///< Atomic Cycle Sequence +#define B_SPI_SSFCS_SCGO BIT9 ///< SPI Cycle Go +#define B_SPI_SSFCS_FRS BIT7 ///< Fast Read Supported +#define B_SPI_SSFCS_DOFRS BIT6 ///< Dual Output Fast Read Supported +#define B_SPI_SSFCS_AEL BIT4 ///< Access Error Log +#define B_SPI_SSFCS_FCERR BIT3 ///< Flash Cycle Error +#define B_SPI_SSFCS_CDS BIT2 ///< Cycle Done Status +#define B_SPI_SSFCS_SCIP BIT0 ///< SPI Cycle in Progress + +#define R_SPI_PREOP 0xA4 ///< Prefix Opcode Configuration Register (16 bits) +#define B_SPI_PREOP1_MASK 0xFF00 ///< Prefix Opcode 1 Mask +#define B_SPI_PREOP0_MASK 0x00FF ///< Prefix Opcode 0 Mask + +#define R_SPI_OPTYPE 0xA6 ///< Opcode Type Configuration +#define B_SPI_OPTYPE7_MASK (BIT15 | BIT14) ///< Opcode Type 7 Mask +#define B_SPI_OPTYPE6_MASK (BIT13 | BIT12) ///< Opcode Type 6 Mask +#define B_SPI_OPTYPE5_MASK (BIT11 | BIT10) ///< Opcode Type 5 Mask +#define B_SPI_OPTYPE4_MASK (BIT9 | BIT8) ///< Opcode Type 4 Mask +#define B_SPI_OPTYPE3_MASK (BIT7 | BIT6) ///< Opcode Type 3 Mask +#define B_SPI_OPTYPE2_MASK (BIT5 | BIT4) ///< Opcode Type 2 Mask +#define B_SPI_OPTYPE1_MASK (BIT3 | BIT2) ///< Opcode Type 1 Mask +#define B_SPI_OPTYPE0_MASK (BIT1 | BIT0) ///< Opcode Type 0 Mask +#define V_SPI_OPTYPE_RDNOADDR 0x00 ///< Read cycle type without address +#define V_SPI_OPTYPE_WRNOADDR 0x01 ///< Write cycle type without address +#define V_SPI_OPTYPE_RDADDR 0x02 ///< Address required; Read cycle type +#define V_SPI_OPTYPE_WRADDR 0x03 ///< Address required; Write cycle type + +#define R_SPI_OPMENU0 0xA8 ///< Opcode Menu Configuration 0 (32bits) +#define R_SPI_OPMENU1 0xAC ///< Opcode Menu Configuration 1 (32bits) + +#define R_SPI_SFRAP 0xB0 ///< Secondary Flash Region Access Permissions (32 bits) + +#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits) +#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select +#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map +#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component +#define V_SPI_FDOC_FDSS_REGN 0x2000 ///< Region +#define V_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master +#define V_SPI_FDOC_FDSS_STRP 0x4000 ///< Soft Straps +#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index + +#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits) + +#define R_SPI_AFC 0xC0 ///< Additional Flash Control Register +#define B_SPI_AFC_RRWSP 0xFE ///< Reserved RW Scratch Pad bit [7:1] +#define B_SPI_AFC_SPFP BIT0 ///< Stop Prefetch on Flush Pending + +#define R_SPI_LVSCC 0xC4 ///_" in register/bit names. + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SC generation will be just named + as "_SC_" without inserted. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _REGS_USB_H_ +#define _REGS_USB_H_ + +/// +/// USB3 (XHCI) related definitions +/// +#define PCI_DEVICE_NUMBER_XHCI 21 +#define PCI_FUNCTION_NUMBER_XHCI 0 + +/// +/// XHCI PCI Config Space registers +/// +#define R_XHCI_VENDOR_ID 0x00 ///< Vendor ID +#define B_XHCI_VENDOR_ID 0xFFFF + +#define R_XHCI_DEVICE_ID 0x02 ///< Device ID +#define B_XHCI_DEVICE_ID 0xFFFF + +#define R_XHCI_COMMAND_REGISTER 0x04 ///< Command +#define B_XHCI_COMMAND_ID BIT10 ///< Interrupt Disable +#define B_XHCI_COMMAND_FBE BIT9 ///< Fast Back to Back Enable +#define B_XHCI_COMMAND_SERR BIT8 ///< SERR# Enable +#define B_XHCI_COMMAND_WCC BIT7 ///< Wait Cycle Control +#define B_XHCI_COMMAND_PER BIT6 ///< Parity Error Response +#define B_XHCI_COMMAND_VPS BIT5 ///< VGA Palette Snoop +#define B_XHCI_COMMAND_MWI BIT4 ///< Memory Write Invalidate +#define B_XHCI_COMMAND_SCE BIT3 ///< Special Cycle Enable +#define B_XHCI_COMMAND_BME BIT2 ///< Bus Master Enable +#define B_XHCI_COMMAND_MSE BIT1 ///< Memory Space Enable + +#define R_XHCI_MEM_BASE 0x10 ///< Memory Base Address +#define B_XHCI_MEM_BASE_BA 0xFFFFFFFFFFFF0000 ///< Base Address +#define V_XHCI_MEM_LENGTH 0x10000 ///< 64 KB of Memory Length +#define N_XHCI_MEM_ALIGN 16 ///< Memory Space Alignment +#define B_XHCI_MEM_BASE_PREF BIT3 ///< Prefetchable +#define B_XHCI_MEM_BASE_TYPE (BIT2 | BIT1) ///< Type +#define B_XHCI_MEM_BASE_RTE BIT0 ///< Resource Type Indicator + +#define R_XHCI_SVID 0x2C +#define B_XHCI_SVID 0xFFFF + +#define R_XHCI_SID 0x2E +#define B_XHCI_SID 0xFFFF + +#define R_XHCI_INT_LN 0x3C ///< Interrupt Line +#define B_XHCI_INT_LN 0xFF ///< Interrupt Line Mask + +#define R_XHCI_INT_PN 0x3D ///< Interrupt Pin +#define B_XHCI_INT_PN 0xFF ///< Interrupt Line Mask +#define V_XHCI_INT_PN BIT0 ///< Interrupt Pin Value (INTA) + +#define R_XHCI_XHCC1 0x40 +#define B_XHCI_XHCC1_ACCTRL BIT31 +#define B_XHCI_XHCC1_RMTASERR BIT24 +#define B_XHCI_XHCC1_URD BIT23 +#define B_XHCI_XHCC1_URRE BIT22 +#define B_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_XHCI_XHCC1_IIL1E_DIS 0 +#define V_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_XHCI_XHCC1_XHCIL1E BIT18 ///< XHC Initiated L1 Enable +#define B_XHCI_XHCC1_D3IL1E BIT17 ///< D3 Initiated L1 Enable +#define B_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) ///< Periodic Complete Pre Wake Time +#define B_XHCI_XHCC1_SWAXHCI BIT11 ///< SW Assisted xHC Idle +#define B_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) ///< L23 to Host Reset Acknowledge Wait Count +#define V_XHCI_XHCC1_L23HRAWC_DIS 0 +#define V_XHCI_XHCC1_L23HRAWC_128 (BIT8) +#define V_XHCI_XHCC1_L23HRAWC_256 (BIT9) +#define V_XHCI_XHCC1_L23HRAWC_512 (BIT9 | BIT8) +#define V_XHCI_XHCC1_L23HRAWC_1024 (BIT10) +#define V_XHCI_XHCC1_L23HRAWC_2048 (BIT10 | BIT8) +#define V_XHCI_XHCC1_L23HRAWC_4096 (BIT10 | BIT9) +#define V_XHCI_XHCC1_L23HRAWC_131072 (BIT10 | BIT9 | BIT8) +#define B_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) ///< Upstream Type Arbiter Grant Count Posted +#define B_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) ///< Upstream Type Arbiter Grant Count Non Posted +#define B_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) ///< Upstream Type Arbiter Grant Count Completion +#define B_XHCI_XHCC1_UDAGC (BIT1 | BIT0) ///< Upstream Type Arbiter Grant Count + +#define R_XHCI_XHCC2 0x44 ///< XHC System Bus Configuration 2 +#define B_XHCI_XHCC2_OCCFDONE BIT31 ///< OC Configuration Done +#define B_XHCI_XHCC2_DREQBCC BIT25 ///< DMA Request Boundary Crossing Control +#define B_XHCI_XHCC2_IDMARRSC (BIT24 | BIT23 | BIT22) ///< IDMA Read Request Size Control +#define B_XHCI_XHCC2_XHCUPRDROE BIT21 ///< XHC Upstream Read Relaxed Ordering Enable +#define B_XHCI_XHCC2_IOSFSRAD BIT20 ///< IOSF Sideband Register Access Disable +#define B_XHCI_XHCC2_UNPPA 0xFC000 ///< Upstream Non-Posted Pre-Allocation +#define B_XHCI_XHCC2_SWAXHCIP (BIT13 | BIT12) ///< SW Assisted xHC Idle Policy +#define B_XHCI_XHCC2_RAWDD BIT11 ///< MMIO Read After MMIO Write Delay Disable +#define B_XHCI_XHCC2_WAWDE BIT10 ///< MMIO Write After MMIO Write Delay Enable +#define B_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) ///< SW Assisted Cx Inhibit +#define B_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) ///< SW Assisted DMI L1 Inhibit +#define B_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) ///< L1 Force P2 clock Gating Wait Count +#define V_XHCI_XHCC2_L1FP2CGWC_DIS 0 +#define V_XHCI_XHCC2_L1FP2CGWC_128 (BIT3) +#define V_XHCI_XHCC2_L1FP2CGWC_256 (BIT4) +#define V_XHCI_XHCC2_L1FP2CGWC_512 (BIT4 | BIT3) +#define V_XHCI_XHCC2_L1FP2CGWC_1024 (BIT5) +#define V_XHCI_XHCC2_L1FP2CGWC_2048 (BIT5 | BIT3) +#define V_XHCI_XHCC2_L1FP2CGWC_4096 (BIT5 | BIT4) +#define V_XHCI_XHCC2_L1FP2CGWC_131072 (BIT5 | BIT4 | BIT3) +#define B_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) ///< Read Request Size Control +#define V_XHCI_XHCC2_RDREQSZCTRL_128 0 +#define V_XHCI_XHCC2_RDREQSZCTRL_256 (BIT0) +#define V_XHCI_XHCC2_RDREQSZCTRL_512 (BIT1) +#define V_XHCI_XHCC2_RDREQSZCTRL_64 (BIT2 | BIT1 | BIT0) + +#define R_XHCI_XHCLKGTEN 0x50 ///< Clock Gating +#define B_XHCI_XHCLKGTEN_NUEFBCGPS BIT28 ///< Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown +#define B_XHCI_XHCLKGTEN_SRAMPGTEN BIT27 ///< SRAM Power Gate Enable +#define B_XHCI_XHCLKGTEN_SSLSE BIT26 ///< SS Link PLL Shutdown Enable +#define B_XHCI_XHCLKGTEN_USB2PLLSE BIT25 ///< USB2 PLL Shutdown Enable +#define B_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 ///< IOSF Sideband Trunk Clock Gating Enable +#define B_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) ///< HS Backbone PXP Trunk Clock Gate Enable +#define B_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) ///< SS Backbone PXP Trunk Clock Gate Enable +#define B_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 ///< XHC Ignore_EU3S +#define B_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 ///< XHC Frame Timer Clock Shutdown Enable +#define B_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 ///< XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP +#define B_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 ///< XHC HS Backbone PXP Trunk Clock Gate U2 non RWE +#define B_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) ///< XHC USB2 PLL Shutdown Lx Enable +#define B_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) ///< HS Backbone PXP PLL Shutdown Ux Enable +#define B_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) ///< SS backbone PXP PLL Shutdown Ux Enable +#define B_XHCI_XHCLKGTEN_XHCBLCGE BIT4 ///< XHC Backbone Local Clock Gating Enable +#define B_XHCI_XHCLKGTEN_HSLTCGE BIT3 ///< HS Link Trunk Clock Gating Enable +#define B_XHCI_XHCLKGTEN_SSLTCGE BIT2 ///< SS Link Trunk Clock Gating Enable +#define B_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 ///< IOSF Backbone Trunk Clock Gating Enable +#define B_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 ///< IOSF Gasket Backbone Local Clock Gating Enable + +#define R_XHCI_USB_RELNUM 0x60 +#define B_XHCI_USB_RELNUM 0xFF + +#define R_XHCI_FL_ADJ 0x61 +#define B_XHCI_FL_ADJ 0x3F + +#define R_XHCI_PWR_CAPID 0x70 +#define B_XHCI_PWR_CAPID 0xFF + +#define R_XHCI_NXT_PTR1 0x71 +#define B_XHCI_NXT_PTR1 0xFF + +#define R_XHCI_PWR_CAP 0x72 +#define B_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_XHCI_PWR_CAP_DSI BIT5 +#define B_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) + +#define R_XHCI_PWR_CNTL_STS 0x74 +#define B_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) + +#define R_XHCI_MSI_CAPID 0x80 +#define B_XHCI_MSI_CAPID 0xFF + +#define R_XHCI_NXT_PTR2 0x81 +#define B_XHCI_NXT_PTR2 0xFF + +#define R_XHCI_MSI_MCTL 0x82 +#define B_XHCI_MSI_MCTL_MSIENABLE BIT0 + +#define V_XHCI_MSI_NEXT 0x90 ///< Pointer to DevIdle capability structure + +#define R_XHCI_PCE 0xA2 ///< Power control enable +#define B_XHCI_PCE_HAE BIT5/// + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PRESERVED_RESOURCES_H_ +#define _SC_PRESERVED_RESOURCES_H_ +#define SC_PRESERVED_BASE_ADDRESS 0xD0000000 ///< SC preserved MMIO base address +#define SC_PRESERVED_MMIO_SIZE 0x01000000 ///< 16MB +#define SC_PCR_BASE_ADDRESS 0xD0000000 ///< SBREG MMIO base address +#define SC_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define SC_SPI_BASE_ADDRESS 0xFED01000 ///< SPI BAR0 MMIO base address +#define SC_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define SC_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO base address +#define SC_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB +#define SC_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address +#define SC_TRACE_HUB_SW_MMIO_SIZE 0x00040000 ///< 2MB + +#endif // _SC_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdCard.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdCard.h new file mode 100644 index 0000000000..af76c8e166 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdCard.h @@ -0,0 +1,138 @@ +/** @file + Header file for Industry SD Card 2.0 spec. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SD_CARD_H +#define _SD_CARD_H + +#include "MMC.h" + +#pragma pack(1) + +#define CHECK_PATTERN 0xAA ///< Physical Layer Simplified Specification Version 3.01 recommended 0xAA + +#define ACMD6 6 +#define ACMD13 13 +#define ACMD23 23 +#define ACMD41 41 +#define ACMD42 42 +#define ACMD51 51 + +#define SWITCH_FUNC CMD6 +#define SEND_IF_COND CMD8 + +#define SET_BUS_WIDTH ACMD6 +#define SD_STATUS ACMD13 +#define SET_WR_BLK_ERASE_COUNT ACMD23 +#define SD_SEND_OP_COND ACMD41 +#define SET_CLR_CARD_DETECT ACMD42 +#define SEND_SCR ACMD51 + +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 + +#define FREQUENCY_SD_PP (25 * 1000 * 1000) +#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000) + +#define SD_SPEC_10 0 +#define SD_SPEC_11 1 +#define SD_SPEC_20 2 + +#define VOLTAGE_27_36 0x1 + +typedef struct { + UINT8 NotUsed: 1; ///< 1 [0:0] + UINT8 CRC: 7; ///< CRC [7:1] + UINT8 ECC: 2; ///< ECC code [9:8] + UINT8 FILE_FORMAT: 2; ///< File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; ///< Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; ///< Permanent write protection [13:13] + UINT8 COPY: 1; ///< Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; ///< File format group [15:15] + UINT16 Reserved0: 5; ///< 0 [20:16] + UINT16 WRITE_BL_PARTIAL: 1; ///< Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; ///< Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; ///< Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; ///< Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; ///< Write protect group enable [31:31] + UINT16 WP_GRP_SIZE: 7; ///< Write protect group size [38:32] + UINT16 SECTOR_SIZE: 7; ///< Erase sector size [45:39] + UINT16 ERASE_BLK_EN: 1; ///< Erase single block enable [46:46] + UINT16 Reserved1: 1; ///< 0 [47:47] + UINT32 C_SIZE: 22; ///< Device size [69:48] + UINT32 Reserved2: 6; ///< 0 [75:70] + UINT32 DSR_IMP: 1; ///< DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; ///< Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; ///< Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; ///< Partial blocks for read allowed [79:79] + UINT16 READ_BL_LEN: 4; ///< Max. read data block length [83:80] + UINT16 CCC: 12; ///< Card command classes [95:84] + UINT8 TRAN_SPEED ; ///< Max. bus clock frequency [103:96] + UINT8 NSAC ; ///< Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; ///< Data read access-time 1 [119:112] + UINT8 Reserved3: 6; ///< 0 [125:120] + UINT8 CSD_STRUCTURE: 2; ///< CSD structure [127:126] +} CSD_SDV2; + +typedef struct { + UINT32 Reserved0; + UINT32 Reserved1: 16; + UINT32 SD_BUS_WIDTH: 4; + UINT32 SD_SECURITY: 3; + UINT32 DATA_STAT_AFTER_ERASE: 1; + UINT32 SD_SPEC: 4; + UINT32 SCR_STRUCT: 4; +} SCR; + +typedef struct { + UINT8 Reserved0[50]; + UINT8 ERASE_OFFSET: 2; + UINT8 ERASE_TIMEOUT: 6; + UINT16 ERASE_SIZE; + UINT8 Reserved1: 4; + UINT8 AU_SIZE: 4; + UINT8 PERFORMANCE_MOVE; + UINT8 SPEED_CLASS; + UINT32 SIZE_OF_PROTECTED_AREA; + UINT32 SD_CARD_TYPE: 16; + UINT32 Reserved2: 13; + UINT32 SECURED_MODE: 1; + UINT32 DAT_BUS_WIDTH: 2; +} SD_STATUS_REG; + +typedef struct { + UINT8 Reserved0[34]; + UINT16 Group1BusyStatus; + UINT16 Group2BusyStatus; + UINT16 Group3BusyStatus; + UINT16 Group4BusyStatus; + UINT16 Group5BusyStatus; + UINT16 Group6BusyStatus; + UINT8 DataStructureVersion; + UINT8 Group21Status; + UINT8 Group43Status; + UINT8 Group65Status; + UINT16 Group1Function; + UINT16 Group2Function; + UINT16 Group3Function; + UINT16 Group4Function; + UINT16 Group5Function; + UINT16 Group6Function; + UINT16 MaxCurrent; +} SWITCH_STATUS; + +#pragma pack() + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdHostIo.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdHostIo.h new file mode 100644 index 0000000000..f2aa674562 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/SdHostIo.h @@ -0,0 +1,317 @@ +/** @file + Interface definition for EFI_SD_HOST_IO_PROTOCOL. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SD_HOST_IO_H +#define _SD_HOST_IO_H + +#include "SdCard.h" +#include "CEATA.h" + +#define EFI_SD_HOST_IO_PROTOCOL_GUID \ + { \ + 0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51} \ + } + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL; + +typedef enum { + ResponseNo = 0, + ResponseR1, + ResponseR1b, + ResponseR2, + ResponseR3, + ResponseR4, + ResponseR5, + ResponseR5b, + ResponseR6, + ResponseR7 +} RESPONSE_TYPE; + +typedef enum { + NoData = 0, + InData, + OutData +} TRANSFER_TYPE; + +typedef enum { + Reset_Auto = 0, + Reset_DAT, + Reset_CMD, + Reset_DAT_CMD, + Reset_All +} RESET_TYPE; + +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_IF_STANDARD_HOST_NO_DMA 0x00 +#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01 + +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + +// +//MMIO Registers definition for MMC/SDIO controller +// +#define MMIO_DMAADR 0x00 +#define MMIO_BLKSZ 0x04 +#define MMIO_BLKCNT 0x06 +#define MMIO_CMDARG 0x08 +#define MMIO_XFRMODE 0x0C +#define MMIO_SDCMD 0x0E +#define MMIO_RESP 0x10 +#define MMIO_BUFDATA 0x20 +#define MMIO_PSTATE 0x24 +#define MMIO_HOSTCTL 0x28 +#define MMIO_PWRCTL 0x29 +#define MMIO_BLKGAPCTL 0x2A +#define MMIO_WAKECTL 0x2B +#define MMIO_CLKCTL 0x2C +#define V_MMIO_CLKCTL_MAX_8BIT_FREQ_SEL 0x80 +#define V_MMIO_CLKCTL_MAX_10BIT_FREQ_SEL 0x3FF +#define B_MMIO_CLKCTL_UPR_SDCLK_FREQ_SEL_MASK 0xC0 +#define MMIO_TOCTL 0x2E +#define MMIO_SWRST 0x2F +#define MMIO_NINTSTS 0x30 +#define MMIO_ERINTSTS 0x32 +#define MMIO_NINTEN 0x34 +#define MMIO_ERINTEN 0x36 +#define MMIO_NINTSIGEN 0x38 +#define MMIO_ERINTSIGEN 0x3A +#define MMIO_AC12ERRSTS 0x3C +#define MMIO_HOSTCTL2 0x3E +#define MMIO_CAP 0x40 +#define MMIO_MCCAP 0x48 +#define MMIO_SLTINTSTS 0xFC +#define MMIO_CTRLRVER 0xFE +#define MMIO_SRST 0x1FC + +/** + The main function used to send the command to the card inserted into the SD host slot. + It will assemble the arguments to set the command register and wait for the command + and transfer completed until timeout. Then it will read the response register to fill + the ResponseData. + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param CommandIndex The command index to set the command index field of command register. + @param Argument Command argument to set the argument field of command register. + @param DataType TRANSFER_TYPE, indicates no data, data in or data out. + @param Buffer Contains the data read from / write to the device. + @param BufferSize The size of the buffer. + @param ResponseType RESPONSE_TYPE. + @param TimeOut Time out value in 1 ms unit. + @param ResponseData Depending on the ResponseType, such as CSD or card status. + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + @retval EFI_OUT_OF_RESOURCES + @retval EFI_TIMEOUT + @retval EFI_DEVICE_ERROR + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData OPTIONAL + ); + +/** + Set max clock frequency of the host, the actual frequency may not be the same as MaxFrequency. + It depends on the max frequency the host can support, divider, and host speed mode. + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param MaxFrequency Max frequency in HZ. + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 MaxFrequency + ); + +/** + Set bus width of the host controller + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param BusWidth Bus width in 1, 4, 8 bits. + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BusWidth + ); + +/** + Set voltage which could supported by the host controller. + Support 0(Power off the host), 1.8V, 3.0V, 3.3V + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param Voltage Units in 0.1 V. + + @retval EFI_SUCCESS + @retval EFI_INVALID_PARAMETER + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 Voltage + ); + +/** + Reset the host controller. + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param ResetAll TRUE to reset all. + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN RESET_TYPE ResetType + ); + +/** + Enable auto stop on the host controller. + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param Enable TRUE to enable, FALSE to disable. + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + +/** + Find whether these is a card inserted into the slot. If so init the host. + If not, return EFI_NOT_FOUND. + + @param[in] This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This + ); + +/** + Set the Block length on the host controller. + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param BlockLength card supportes block length. + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BlockLength + ); + +/** + Enable/Disable High Speed transfer mode + + @param This A pointer to the EFI_SD_HOST_IO_PROTOCOL instance. + @param Enable TRUE to Enable, FALSE to Disable + + @return EFI_SUCCESS +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_HIGH_SPEED_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DUAL_DATARATE_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + + +#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x02 + +typedef struct { + UINT32 HighSpeedSupport: 1; ///< High speed supported + UINT32 V18Support: 1; ///< 1.8V supported + UINT32 V30Support: 1; ///< 3.0V supported + UINT32 V33Support: 1; ///< 3.3V supported + UINT32 Reserved0: 4; + UINT32 HostVersion: 8; + UINT32 BusWidth4: 1; ///< 4 bit width + UINT32 BusWidth8: 1; ///< 8 bit width + UINT32 Reserved1: 14; + UINT32 BoundarySize; +} HOST_CAPABILITY; + +// +// Interface structure for the SD HOST I/O Protocol +// +struct _EFI_SD_HOST_IO_PROTOCOL { + UINT32 Revision; + HOST_CAPABILITY HostCapability; + EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand; + EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency; + EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage; + EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost; + EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd; + EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost; + EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength; + EFI_SD_HOST_IO_PROTOCOL_HIGH_SPEED_MODE SetHighSpeedMode; + EFI_SD_HOST_IO_PROTOCOL_DUAL_DATARATE_MODE SetDDRMode; +}; + +extern EFI_GUID gEfiSdHostIoProtocolGuid; + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.c new file mode 100644 index 0000000000..fda7b86fdd --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.c @@ -0,0 +1,2284 @@ +/** @file + PCI Library using PC Express access. + + Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include "DxeRuntimePciLibPciExpress.h" + +#define ASSERT_INVALID_PCI_ADDRESS(A) ASSERT (((A) &~0xfffffff) == 0) + +STATIC UINTN mPciExpressBaseAddress; + +typedef struct _REGISTERED_ADDRESS_MAP { + UINTN PciAddress; + UINTN Length; + UINTN RuntimeAddress; +} REGISTERED_ADDRESS_MAP; + +#define PCI_LIB_ADDRESS_MAP_MAX_ITEM 64 + +STATIC REGISTERED_ADDRESS_MAP mPciLibAddressMap[PCI_LIB_ADDRESS_MAP_MAX_ITEM]; + +STATIC UINTN mPciLibAddressMapIndex = 0; + +STATIC EFI_EVENT mVirtualAddressChangeEvent; + +#ifndef __GNUC__ + +// +// Code not used +// +/** + Get the base address of PCI Express memory space. + + @retval VOID* Return the pointer which points to base address of PCI Express. + +**/ +static +VOID * +EFIAPI +GetPciExpressBaseAddress ( + VOID + ) +{ + return (VOID *) (mPciExpressBaseAddress); +} +#endif + + +/** + Generate Pci Express address. + If Address > 0x0FFFFFFF or can't get the match Pci address, then ASSERT(). + + @param[in] Address Pci address. + + @retval UINTN Pci Express address. + +**/ +static +UINTN +EFIAPI +PreparePciExpressAddress ( + IN UINTN Address + ) +{ + UINTN Index; + + ASSERT_INVALID_PCI_ADDRESS (Address); + + if (EfiAtRuntime () == FALSE) { + return mPciExpressBaseAddress + Address; + } + + for (Index = 0; Index < PCI_LIB_ADDRESS_MAP_MAX_ITEM; Index++) { + if ((Address >= mPciLibAddressMap[Index].PciAddress) && + (Address < mPciLibAddressMap[Index].PciAddress + mPciLibAddressMap[Index].Length) + ) { + return mPciLibAddressMap[Index].RuntimeAddress + (Address - mPciLibAddressMap[Index].PciAddress); + } + } + + ASSERT (FALSE); + CpuDeadLoop (); + return 0; +} + + +/** + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT8 return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressRead8 ( + IN UINTN Address + ) +{ + return MmioRead8 (PreparePciExpressAddress (Address)); +} + + +/** + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Value The value to write + + @retval UINT8 The value to write to the MMIO register. + +**/ +UINT8 +EFIAPI +PciExpressWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + return MmioWrite8 (PreparePciExpressAddress (Address), Value); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + return MmioOr8 (PreparePciExpressAddress (Address), OrData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + return MmioAnd8 (PreparePciExpressAddress (Address), AndData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return MmioAndThenOr8 ( + PreparePciExpressAddress (Address), + AndData, + OrData + ); +} + + +/** + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + + @retval UINT8 The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return MmioBitFieldRead8 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit + ); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] Value New value of the bit field. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return MmioBitFieldWrite8 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return MmioBitFieldOr8 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return MmioBitFieldAnd8 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return MmioBitFieldAndThenOr8 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + + +/** + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT16 The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressRead16 ( + IN UINTN Address + ) +{ + return MmioRead16 (PreparePciExpressAddress (Address)); +} + + +/** + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Value The value to write. + + @retval UINT16 The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + return MmioWrite16 (PreparePciExpressAddress (Address), Value); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + return MmioOr16 (PreparePciExpressAddress (Address), OrData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + return MmioAnd16 (PreparePciExpressAddress (Address), AndData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return MmioAndThenOr16 ( + PreparePciExpressAddress (Address), + AndData, + OrData + ); +} + + +/** + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + + @retval UINT16 The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return MmioBitFieldRead16 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit + ); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] Value New value of the bit field. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return MmioBitFieldWrite16 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return MmioBitFieldOr16 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return MmioBitFieldAnd16 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return MmioBitFieldAndThenOr16 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + + +/** + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT32 The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressRead32 ( + IN UINTN Address + ) +{ + return MmioRead32 (PreparePciExpressAddress (Address)); +} + + +/** + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Value The value to write. + + @retval UINT32 The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + return MmioWrite32 (PreparePciExpressAddress (Address), Value); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + return MmioOr32 (PreparePciExpressAddress (Address), OrData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + return MmioAnd32 (PreparePciExpressAddress (Address), AndData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return MmioAndThenOr32 ( + PreparePciExpressAddress (Address), + AndData, + OrData + ); +} + + +/** + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + + @retval UNT32 The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return MmioBitFieldRead32 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit + ); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] Value New value of the bit field. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return MmioBitFieldWrite32 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return MmioBitFieldOr32 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return MmioBitFieldAnd32 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return MmioBitFieldAndThenOr32 ( + PreparePciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + + +/** + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, Function and Register. + @param[in] Size Size in bytes of the transfer. + @param[out] Buffer Pointer to a buffer receiving the data read. + + @retval UINTN Size in bytes of the transfer. + +**/ +UINTN +EFIAPI +PciExpressReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return Size; + } + + if (Buffer == NULL) { + ASSERT (Buffer != NULL); + return EFI_OUT_OF_RESOURCES; + } + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & 1) != 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *) Buffer = PciExpressRead8 (StartAddress); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8 *) Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { + // + // Read a word if StartAddress is word aligned + // + *(volatile UINT16 *) Buffer = PciExpressRead16 (StartAddress); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16 *) Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Read as many double words as possible + // + *(volatile UINT32 *) Buffer = PciExpressRead32 (StartAddress); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32 *) Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + *(volatile UINT16 *) Buffer = PciExpressRead16 (StartAddress); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16 *) Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *) Buffer = PciExpressRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, Function and Register. + @param[in] Size Size in bytes of the transfer. + @param[in] Buffer Pointer to a buffer containing the data to write. + + @retval UINTN Size in bytes of the transfer. + +**/ +UINTN +EFIAPI +PciExpressWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return 0; + } + + if (Buffer == NULL) { + ASSERT (Buffer != NULL); + return EFI_OUT_OF_RESOURCES; + } + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & 1) != 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciExpressWrite8 (StartAddress, *(UINT8 *) Buffer); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8 *) Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { + // + // Write a word if StartAddress is word aligned + // + PciExpressWrite16 (StartAddress, *(UINT16 *) Buffer); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16 *) Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciExpressWrite32 (StartAddress, *(UINT32 *) Buffer); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32 *) Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciExpressWrite16 (StartAddress, *(UINT16 *) Buffer); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16 *) Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciExpressWrite8 (StartAddress, *(UINT8 *) Buffer); + } + + return ReturnValue; +} + + +/** + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT8 The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciRead8 ( + IN UINTN Address + ) +{ + return PciExpressRead8 (Address); +} + + +/** + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Data The value to write. + + @retval UINT8 The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciWrite8 ( + IN UINTN Address, + IN UINT8 Data + ) +{ + return PciExpressWrite8 (Address, Data); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + return PciExpressOr8 (Address, OrData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + return PciExpressAnd8 (Address, AndData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciExpressAndThenOr8 (Address, AndData, OrData); +} + + +/** + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + + @retval UINT8 The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return PciExpressBitFieldRead8 (Address, StartBit, EndBit); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] Value New value of the bit field. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData); +} + + +/** + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..7. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT8 The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData); +} + + +/** + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT16 The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciRead16 ( + IN UINTN Address + ) +{ + return PciExpressRead16 (Address); +} + + +/** + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Data The value to write. + + @retval UINT16 The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciWrite16 ( + IN UINTN Address, + IN UINT16 Data + ) +{ + return PciExpressWrite16 (Address, Data); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + return PciExpressOr16 (Address, OrData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + return PciExpressAnd16 (Address, AndData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciExpressAndThenOr16 (Address, AndData, OrData); +} + + +/** + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + + @retval UINT16 The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return PciExpressBitFieldRead16 (Address, StartBit, EndBit); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] Value New value of the bit field. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData); +} + + +/** + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..15. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT16 The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData); +} + + +/** + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + + @retval UINT32 The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciRead32 ( + IN UINTN Address + ) +{ + return PciExpressRead32 (Address); +} + + +/** + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] Data The value to write. + + @retval UINT32 The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciWrite32 ( + IN UINTN Address, + IN UINT32 Data + ) +{ + return PciExpressWrite32 (Address, Data); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + return PciExpressOr32 (Address, OrData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + return PciExpressAnd32 (Address, AndData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise inclusive OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address Address that encodes the PCI Bus, Device, Function and Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciExpressAndThenOr32 (Address, AndData, OrData); +} + + +/** + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to read. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + + @retval UINT32 The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return PciExpressBitFieldRead32 (Address, StartBit, EndBit); +} + + +/** + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] Value New value of the bit field. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise inclusive OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] OrData The value to OR with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData); +} + + +/** + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise inclusive OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address PCI configuration register to write. + @param[in] StartBit The original of the least significant bit in the bit field. Range 0..31. + @param[in] EndBit The original of the most significant bit in the bit field. Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @retval UINT32 The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData); +} + + +/** + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, Function and Register. + @param[in] Size Size in bytes of the transfer. + + @param[out] Buffer Pointer to a buffer receiving the data read. + + @retval UINTN Size in bytes of the transfer. + +**/ +UINTN +EFIAPI +PciReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + return PciExpressReadBuffer (StartAddress, Size, Buffer); +} + + +/** + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, Function and Register. + @param[in] Size Size in bytes of the transfer. + @param[in] Buffer Pointer to a buffer containing the data to write. + + @retval UINTN The value written back to the PCI configuration register. + +**/ +UINTN +EFIAPI +PciWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + return PciExpressWriteBuffer (StartAddress, Size, Buffer); +} + +/** + Register memory space + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If SmPciLibAddressMapIndex) > PCI_LIB_ADDRESS_MAP_MAX_ITEM, then ASSERT(). + + @param[in] Address Starting address of the memory space + @param[in] Length Length of the memory space + + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +PciLibRegisterMemory ( + IN UINTN Address, + IN UINTN Length + ) +{ + UINTN Index; + + ASSERT_INVALID_PCI_ADDRESS (Address); + ASSERT (mPciLibAddressMapIndex < PCI_LIB_ADDRESS_MAP_MAX_ITEM); + + // + // If already registered + // + for (Index = 0; Index < mPciLibAddressMapIndex; Index++) { + if (mPciLibAddressMap[Index].PciAddress == Address) { + return EFI_SUCCESS; + } + } + + mPciLibAddressMap[mPciLibAddressMapIndex].PciAddress = Address; + mPciLibAddressMap[mPciLibAddressMapIndex].Length = Length; + mPciLibAddressMap[mPciLibAddressMapIndex].RuntimeAddress = mPciExpressBaseAddress + Address; + mPciLibAddressMapIndex++; + + return EFI_SUCCESS; +} + + +/** + Virtual address notify. + The event handler changes PCIE base address to an virtual address. + Starting address of registered memory scope is converted as well. + + @param[in] Event The event that be siganlled when virtual address changed + @param[in] Context The pointer of the ESAL procedure instance + +**/ +VOID +EFIAPI +VirtualAddressNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + + for (Index = 0; Index < PCI_LIB_ADDRESS_MAP_MAX_ITEM; Index++) { + if (mPciLibAddressMap[Index].PciAddress != 0) { + EfiConvertPointer (0x0, (VOID **) &(mPciLibAddressMap[Index].RuntimeAddress)); + } + } + + EfiConvertPointer (0x0, (VOID **) &mPciExpressBaseAddress); +} + + +/** + Constructor for Pci library. Register VirtualAddressNotifyEvent() notify function + It will ASSERT() if that operation fails + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +PciLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress); + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + VirtualAddressNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mVirtualAddressChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + ZeroMem (mPciLibAddressMap, sizeof (mPciLibAddressMap)); + + return EFI_SUCCESS; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.h new file mode 100644 index 0000000000..c55e89ce95 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.h @@ -0,0 +1,30 @@ +/** @file + Header file for SC Pci Express helps library implementation. + + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_DXE_RUNTIME_PCI_EXPRESS_LIBRARY_H_ +#define _SC_DXE_RUNTIME_PCI_EXPRESS_LIBRARY_H_ + +#include "ScAccess.h" +#include "Library/PciLib.h" +#include "Library/IoLib.h" +#include "Library/DebugLib.h" +#include "Library/PcdLib.h" + +#include +#include +#include + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf new file mode 100644 index 0000000000..4aab494cb6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeRuntimePciLibPciExpress/DxeRuntimePciLibPciExpress.inf @@ -0,0 +1,47 @@ +## @file +# ScDxeRuntimePciLibPciExpress Driver. +# +# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ScDxeRuntimePciLibPciExpress + FILE_GUID = D048C113-CAE2-4107-AD0C-F78693EB6EBA + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = ScDxeRuntimePciLibPciExpress|DXE_RUNTIME_DRIVER + CONSTRUCTOR = PciLibConstructor + +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + DxeRuntimePciLibPciExpress.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + BaseLib + IoLib + DebugLib + UefiBootServicesTableLib + DxeServicesTableLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[Guids] + gEfiEventVirtualAddressChangeGuid ## PRODUCES ## Event diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c new file mode 100644 index 0000000000..a21816ec38 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.c @@ -0,0 +1,683 @@ +/** @file + This code provides a initialization of Intel VT-d (Virtualization Technology for Directed I/O). + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +/** + For device that specified by Device Num and Function Num, + mDevEnMap is used to check device presence. + 0x80 means use Device ID to determine presence + + The structure is used to check if device scope is valid when update DMAR table +**/ +UINT16 mDevEnMap[][2] = {{0x0200, 0x80}, {0x1500, 0x80}, {0x1501, 0x80}}; + +/** + Get the corresponding device Enable/Disable bit according DevNum and FunNum + + @param[in] DevNum Device Number + @param[in] FunNum Function Number + + @retval Bit If the device is found, return Disable/Enable bit in FD/DevEn register + @retval 0xFF When device not found + +**/ +UINT16 +GetFunDisableBit ( + IN UINT8 DevNum, + IN UINT8 FunNum + ) +{ + UINTN Index; + + for (Index = 0; Index < sizeof (mDevEnMap) / 4; Index++) { + if (mDevEnMap[Index][0] == ((DevNum << 0x08) | FunNum)) { + return mDevEnMap[Index][1]; + } + } + + return 0xFF; +} + + +/** + Update the DRHD structure + + @param[in, out] DrhdEnginePtr A pointer to DRHD structure + +**/ +VOID +UpdateDrhd ( + IN OUT VOID *DrhdEnginePtr + ) +{ + UINT16 Length; + UINT16 DisableBit; + UINTN DeviceScopeNum; + BOOLEAN NeedRemove; + EFI_ACPI_DRHD_ENGINE1_STRUCT *DrhdEngine; + + // + // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE1_STRUCT Pointer + // + DrhdEngine = (EFI_ACPI_DRHD_ENGINE1_STRUCT *) DrhdEnginePtr; + Length = DrhdEngine->Length; + DeviceScopeNum = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + + DisableBit = GetFunDisableBit ( + DrhdEngine->DeviceScope[0].PciPath[0], + DrhdEngine->DeviceScope[0].PciPath[1] + ); + + NeedRemove = FALSE; + + if ((DisableBit == 0xFF) || + (DrhdEngine->RegisterBaseAddress == 0) || + ((DisableBit == 0x80) && + (MmioRead32 (MmPciBase (0, DrhdEngine->DeviceScope[0].PciPath[0], DrhdEngine->DeviceScope[0].PciPath[1]) + 0x00) == 0xFFFFFFFF))) { + NeedRemove = TRUE; + } + + if (NeedRemove) { + Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } + + // + // If no device scope is left, we set the structure length as 0x00 + // + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) { + DrhdEngine->Length = Length; + } else { + DrhdEngine->Length = 0; + } + + return; +} + + +/** + Get IOAPIC ID from LPC. + + @retval UINT8 IO APIC ID + +**/ +UINT8 +GetIoApicId ( + VOID + ) +{ + UINT32 IoApicId; + UINTN P2sbMmbase; + + P2sbMmbase = MmPciAddress( + 0, + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_P2SB, + PCI_FUNCTION_NUMBER_P2SB, + 0 + ); + + + MmioOr16 (P2sbMmbase + R_P2SB_IOAC, (UINT16) (B_P2SB_IOAC_AE)); + // + // Reads back for posted write to take effect and make sure it is set properly. + // + if ((MmioRead16 (P2sbMmbase + R_P2SB_IOAC) & (UINT16) B_P2SB_IOAC_AE) == (UINT16) 0x00) { + DEBUG ((EFI_D_INFO, " IoApicId B_P2SB_IOAC_AE:0 Skip \n")); + return 0; + } + + // + // Get current IO APIC ID + // + MmioWrite8 ((UINTN) IO_APIC_INDEX_REGISTER, R_IO_APIC_ID); + IoApicId = MmioRead32 ((UINTN) IO_APIC_DATA_REGISTER) >> 24; + + return (UINT8) IoApicId; +} + + +/** + Update the second DRHD structure + + @param[in, out] DrhdEnginePtr A pointer to DRHD structure + +**/ +VOID +UpdateDrhd2 ( + IN OUT VOID *DrhdEnginePtr + ) +{ + UINT16 Length; + UINTN DeviceScopeNum; + UINTN ValidDeviceScopeNum; + UINT16 Data16; + UINT16 Index; + UINT8 Bus; + UINT8 Path[2] = { 0, 0 }; + BOOLEAN NeedRemove; + EFI_ACPI_DRHD_ENGINE2_STRUCT *DrhdEngine; + UINTN P2sbMmbase; + + P2sbMmbase = MmPciAddress( + 0, + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_P2SB, + PCI_FUNCTION_NUMBER_P2SB, + 0 + ); + + // + // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE2_STRUCT Pointer + // + DrhdEngine = (EFI_ACPI_DRHD_ENGINE2_STRUCT *) DrhdEnginePtr; + + Length = DrhdEngine->Length; + DeviceScopeNum = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + Data16 = 0; + Bus = 0; + ValidDeviceScopeNum = 0; + + for (Index = 0; Index < DeviceScopeNum; Index++) { + NeedRemove = FALSE; + // + // For HPET and APIC, update device scope if Interrupt remapping is supported. remove device scope + // if interrupt remapping is not supported. + // - Index = 0 - IOAPIC + // - Index = 1 - HPET + // + if ((MmioRead32 (PcdGet32 (PcdVtdGfxBaseAddress) + VTD_ECAP_REG) & IR) + && (MmioRead32 (DEF_VTD_BASE_ADDRESS + VTD_ECAP_REG) & IR) + && ((GetBxtSeries() == BxtP && BxtStepping() > BxtPA0) || GetBxtSeries() == Bxt1)) { + if (Index == 0) { + // + // Update source id for IoApic's device scope entry + // + Data16 = MmioRead16 (P2sbMmbase + R_PCH_P2SB_IBDF); + Bus = (UINT8) (Data16 >> 8); + + if (Bus != 0x00) { + Path[0] = (UINT8) ((Data16 & 0xff) >> 3); + Path[1] = (UINT8) (Data16 & 0x7); + } else { + Bus = 0xF0; + Path[0] = 0x1F; + Path[1] = 0x0; + } + + DrhdEngine->DeviceScope[Index].StartBusNumber = Bus; + DrhdEngine->DeviceScope[Index].PciPath[0] = Path[0]; + DrhdEngine->DeviceScope[Index].PciPath[1] = Path[1]; + + // + // Update APIC ID + // + DrhdEngine->DeviceScope[Index].EnumId = GetIoApicId(); + DEBUG ((EFI_D_INFO, " VTd check IoApicId : 0x%x\n", GetIoApicId())); + } + + if (Index == 1) { + // + // Update source id for HPET's device scope entry + // + Data16 = MmioRead16 (P2sbMmbase + R_PCH_P2SB_HBDF); + Bus = (UINT8) (Data16 >> 8); + Path[0] = (UINT8) ((Data16 & 0xFF) >> 3); + Path[1] = (UINT8) (Data16 & 0x7); + + DrhdEngine->DeviceScope[Index].StartBusNumber = Bus; + DrhdEngine->DeviceScope[Index].PciPath[0] = Path[0]; + DrhdEngine->DeviceScope[Index].PciPath[1] = Path[1]; + } + } else { + if ((Index == 0) || (Index == 1)) { + NeedRemove = TRUE; + } + } + + CopyMem ( + &DrhdEngine->DeviceScope[ValidDeviceScopeNum], + &DrhdEngine->DeviceScope[Index], + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) + ); + + if (NeedRemove) { + Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } else { + ValidDeviceScopeNum++; + } + } + + // + // If no device scope is left, we set the structure length as 0x00 + // + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) { + DrhdEngine->Length = Length; + } else { + DrhdEngine->Length = 0; + } +} + + +/** + Update the RMRR structure + + @param[in, out] RmrrPtr A pointer to RMRR structure + +**/ +VOID +UpdateRmrr ( + IN OUT VOID *RmrrPtr + ) +{ + UINT16 Length; + UINT16 DisableBit; + UINTN DeviceScopeNum; + UINTN ValidDeviceScopeNum; + UINTN Index; + BOOLEAN NeedRemove; + EFI_ACPI_RMRR_USB_STRUC *Rmrr; + + // + // To make sure all device scope can be checked, + // we convert the RmrrPtr to EFI_ACPI_RMRR_USB_STRUC pointer + // + Rmrr = (EFI_ACPI_RMRR_USB_STRUC *) RmrrPtr; + Length = Rmrr->Length; + ValidDeviceScopeNum = 0; + DeviceScopeNum = (Rmrr->Length - EFI_ACPI_RMRR_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + + for (Index = 0; Index < DeviceScopeNum; Index++) { + DisableBit = GetFunDisableBit ( + Rmrr->DeviceScope[Index].PciPath[0], + Rmrr->DeviceScope[Index].PciPath[1] + ); + NeedRemove = FALSE; + + if ((DisableBit == 0xFF) || + ((DisableBit == 0x80) && + (MmioRead32 (MmPciBase (0, Rmrr->DeviceScope[Index].PciPath[0], Rmrr->DeviceScope[Index].PciPath[1]) + 0x00) == 0xFFFFFFFF))) { + NeedRemove = TRUE; + } + + CopyMem ( + &Rmrr->DeviceScope[ValidDeviceScopeNum], + &Rmrr->DeviceScope[Index], + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) + ); + + if (NeedRemove) { + Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } else { + ValidDeviceScopeNum++; + } + } + + // + // If No deviceScope is left, set length as 0x00 + // + if (Length > EFI_ACPI_RMRR_HEADER_LENGTH) { + Rmrr->Length = Length; + } else { + Rmrr->Length = 0; + } +} + + +/** + Update the DMAR table + + @param[in, out] TableHeader The table to be set + @param[in, out] Version Version to publish + +**/ +VOID +DmarTableUpdate ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_ACPI_DMAR_TABLE *DmarTable; + EFI_ACPI_DMAR_TABLE TempDmarTable; + UINTN Offset; + UINTN StructureLen; + UINTN McD0BaseAddress; + UINTN MchBar; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + SC_POLICY_HOB *ScPolicy; + EFI_PEI_HOB_POINTERS HobPtr; + SC_VTD_CONFIG *VtdConfig; + EFI_STATUS Status; + + // + // Get SC VT-d config block + // + HobPtr.Guid = GetFirstGuidHob (&gScPolicyHobGuid); + ASSERT (HobPtr.Guid != NULL); + ScPolicy = (SC_POLICY_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid); + Status = GetConfigBlock ((VOID *) ScPolicy, &gVtdConfigGuid, (VOID *) &VtdConfig); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "ScPolicy VtdEnable = %x\n", VtdConfig->VtdEnable)); + + IgdMemSize = 0; + GttMemSize = 0; + DmarTable = (EFI_ACPI_DMAR_TABLE *) TableHeader; + + DEBUG ((DEBUG_INFO, "DmarTableUpdate() - start\n")); + + // + // Set INTR_REMAP bit (BIT 0) if interrupt remapping is supported + // + if ((MmioRead32 (PcdGet32 (PcdVtdGfxBaseAddress) + VTD_ECAP_REG) & IR) + && (MmioRead32 (DEF_VTD_BASE_ADDRESS + VTD_ECAP_REG) & IR) + && ((GetBxtSeries() == BxtP && BxtStepping() > BxtPA0) || GetBxtSeries() == Bxt1)) { + DmarTable->Flags |= BIT0; + } + + if (VtdConfig->x2ApicEnabled == 1) { + DmarTable->Flags |= BIT1; + } else { + DmarTable->Flags &= 0xFD; + } + + // + // Calculate IGD mem size + // + McD0BaseAddress = MmPciBase (SA_MC_BUS, 0, 0); + MchBar = MmioRead32 (McD0BaseAddress + R_SA_MCHBAR) & ~BIT0; + IgdMode = (MmioRead16 (McD0BaseAddress + R_SA_GGC) & B_SA_GGC_GMS_MASK) >> N_SA_GGC_GMS_OFFSET; + + if (IgdMode < V_SA_GGC_GMS_2016MB) { + IgdMemSize = IgdMode * 32 * (1024) * (1024); + } else { + IgdMemSize = 0; + } + + // + // Calculate GTT mem size + // + GttMemSize = 0; + GttMode = (MmioRead16 (McD0BaseAddress + R_SA_GGC) & B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; + + if (GttMode <= V_SA_GGC_GGMS_8MB) { + GttMemSize = (1 << GttMode) * (1024) * (1024); + } + + DmarTable->RmrrIgd.RmrBaseAddress = (MmioRead32 (McD0BaseAddress + R_SA_TOLUD) & ~(0x01)) - IgdMemSize - GttMemSize; + DmarTable->RmrrIgd.RmrLimitAddress = DmarTable->RmrrIgd.RmrBaseAddress + IgdMemSize + GttMemSize - 1; + + DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable->RmrrIgd.RmrBaseAddress)); + DEBUG ((DEBUG_INFO, "RMRR Limit address IGD %016lX\n", DmarTable->RmrrIgd.RmrLimitAddress)); + + DmarTable->RmrrUsb.RmrBaseAddress = VtdConfig->RmrrUsbBaseAddr; + DmarTable->RmrrUsb.RmrLimitAddress = VtdConfig->RmrrUsbLimit; + + // + // Convert to 4KB alignment. + // + DmarTable->RmrrUsb.RmrBaseAddress &= (EFI_PHYSICAL_ADDRESS) ~0xFFF; + DmarTable->RmrrUsb.RmrLimitAddress &= (EFI_PHYSICAL_ADDRESS) ~0xFFF; + DmarTable->RmrrUsb.RmrLimitAddress += 0x1000 - 1; + + DEBUG ((DEBUG_INFO, "RMRR Base address USB %016lX\n", DmarTable->RmrrUsb.RmrBaseAddress)); + DEBUG ((DEBUG_INFO, "RMRR Limit address USB %016lX\n", DmarTable->RmrrUsb.RmrLimitAddress)); + + + // + // Update DRHD structures of DmarTable + // + DmarTable->DrhdEngine1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~3); + DmarTable->DrhdEngine2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~3); + + DEBUG ((DEBUG_INFO, "VTD base address1 %x\n", DmarTable->DrhdEngine1.RegisterBaseAddress)); + DEBUG ((DEBUG_INFO, "VTD base address2 %x\n", DmarTable->DrhdEngine2.RegisterBaseAddress)); + + // + // Copy DmarTable to TempDmarTable to be processed + // + CopyMem (&TempDmarTable, DmarTable, sizeof (EFI_ACPI_DMAR_TABLE)); + + // + // Update DRHD structures of temp DMAR table + // + UpdateDrhd (&TempDmarTable.DrhdEngine1); + UpdateDrhd2 (&TempDmarTable.DrhdEngine2); + + // + // Update RMRR structures of temp DMAR table + // + UpdateRmrr ((VOID *) &TempDmarTable.RmrrUsb); + UpdateRmrr ((VOID *) &TempDmarTable.RmrrIgd); + + // + // Remove unused device scope or entire DRHD structures + // + Offset = (UINTN) (&TempDmarTable.DrhdEngine1); + if (TempDmarTable.DrhdEngine1.Length != 0) { + Offset += TempDmarTable.DrhdEngine1.Length; + } + + if (TempDmarTable.DrhdEngine2.Length != 0) { + StructureLen = TempDmarTable.DrhdEngine2.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.DrhdEngine2, TempDmarTable.DrhdEngine2.Length); + Offset += StructureLen; + } + + // + // Remove unused device scope or entire RMRR structures + // + if (TempDmarTable.RmrrUsb.Length != 0) { + StructureLen = TempDmarTable.RmrrUsb.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrUsb, TempDmarTable.RmrrUsb.Length); + Offset += StructureLen; + } + + if (TempDmarTable.RmrrIgd.Length != 0) { + StructureLen = TempDmarTable.RmrrIgd.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrIgd, TempDmarTable.RmrrIgd.Length); + Offset += StructureLen; + } + + Offset = Offset - (UINTN) &TempDmarTable; + + // + // Re-calculate DMAR table check sum + // + TempDmarTable.Header.Checksum = (UINT8) (TempDmarTable.Header.Checksum + TempDmarTable.Header.Length - Offset); + + // + // Set DMAR table length + // + TempDmarTable.Header.Length = (UINT32) Offset; + + // + // Replace DMAR table with rebuilt table TempDmarTable + // + CopyMem ((VOID *) DmarTable, (VOID *) &TempDmarTable, TempDmarTable.Header.Length); + + DEBUG ((DEBUG_INFO, "DmarTableUpdate() - end\n")); +} + + +/** + ReadyToBoot callback routine to update DMAR + +**/ +VOID +UpdateDmarOnReadyToBoot ( + BOOLEAN VtEnable + ) +{ + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport; + EFI_ACPI_TABLE_VERSION Version; + EFI_STATUS Status; + UINT8 Index; + UINTN Handle; + + AcpiSupport = NULL; + Index = 0; + + // + // Locate ACPI support protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiSupportProtocolGuid, NULL, (VOID **) &AcpiSupport); + ASSERT_EFI_ERROR (Status); + + // + // Find the DMAR ACPI table + // + do { + Status = AcpiSupport->GetAcpiTable(AcpiSupport, Index, (VOID **) &Table, &Version, &Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR(Status); + Index++; + } while (Table->Signature != EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE); + + DEBUG ((DEBUG_INFO, "DMAR ACPI Table: Address = 0x%x, Version = %u, Handle = %u\n", Table, Version, Handle)); + + if (VtEnable) { + // + // Update the DMAR table structure + // + DEBUG ((DEBUG_INFO, "DMAR ACPI table to be Installed \n")); + DmarTableUpdate (Table, &Version); + } else { + // + // Uninstall DMAR table + // + DEBUG ((DEBUG_INFO, "DMAR ACPI table to be Uninstalled \n")); + Table = NULL; + } + + // + // Update the DMAR ACPI table + // + Status = AcpiSupport->SetAcpiTable ( + AcpiSupport, + Table, + TRUE, + Version, + &Handle + ); + + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "DMAR ACPI table was successfully updated\n")); + } else { + DEBUG ((DEBUG_ERROR, "Error updating the DMAR ACPI table\n")); + } +} + + +/** + Update RMRR Base and Limit Address for USB. + +**/ +VOID +UpdateRmrrUsbAddress ( + IN SC_VTD_CONFIG *VtdConfig + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Address; + UINTN Size; + + if (VtdConfig->RmrrUsbBaseAddr != 0) { + // + // The buffer did assign. + // + return; + } + + Size = EFI_SIZE_TO_PAGES(VTD_RMRR_USB_LENGTH); + Address = 0xFFFFFFFF; + + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + Size, + &Address + ); + ASSERT_EFI_ERROR (Status); + + + VtdConfig->RmrrUsbBaseAddr = Address; + VtdConfig->RmrrUsbLimit = Address + VTD_RMRR_USB_LENGTH - 1; + + return; +} + + +/** + Locate the VT-d ACPI tables data file and update it based on current configuration and capabilities. + + @retval EFI_SUCCESS VT-d initialization complete + @retval EFI_UNSUPPORTED VT-d is disabled by policy or not supported + +**/ +EFI_STATUS +VtdInit ( + VOID + ) +{ + UINTN McD0BaseAddress; + SC_POLICY_HOB *ScPolicy; + EFI_PEI_HOB_POINTERS HobPtr; + SC_VTD_CONFIG *VtdConfig; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "VtdInit () - Start\n")); + McD0BaseAddress = MmPciBase (SA_MC_BUS, 0, 0); + + // + // Get SC VT-d config block + // + HobPtr.Guid = GetFirstGuidHob (&gScPolicyHobGuid); + ASSERT (HobPtr.Guid != NULL); + ScPolicy = (SC_POLICY_HOB*) GET_GUID_HOB_DATA (HobPtr.Guid); + Status = GetConfigBlock ((VOID *) ScPolicy, &gVtdConfigGuid, (VOID *) &VtdConfig); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "ScPolicy VtdEnable = %x\n", VtdConfig->VtdEnable)); + + if ((VtdConfig->VtdEnable == 0) || (MmioRead32 (McD0BaseAddress + R_SA_MC_CAPID0_A) & BIT23)) { + DEBUG ((DEBUG_INFO, "VT-d Disabled or not supported on this platform, skip DMAR Table update\n")); + return EFI_UNSUPPORTED; + } + + if (((AsmReadMsr64 (EFI_MSR_XAPIC_BASE)) & (BIT11 + BIT10)) == BIT11 + BIT10) { + VtdConfig->x2ApicEnabled = 1; + } else { + VtdConfig->x2ApicEnabled = 0; + } + + // + // Update RMRR USB address + // + UpdateRmrrUsbAddress (VtdConfig); + + DEBUG ((DEBUG_INFO, "VtdInit () - End\n")); + + return EFI_SUCCESS; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf new file mode 100644 index 0000000000..4f22249ac7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/DxeVtdLib/DxeVtdLib.inf @@ -0,0 +1,62 @@ +## @file +# Library for Intel VT-d. +# +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeVtdLib + FILE_GUID = A5525CF4-88CD-4c7b-8C9F-4E3343CED768 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DxeVtdLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + DxeVtdLib.c + +[Guids] + gVtdConfigGuid + gScPolicyHobGuid + +[Protocols] + gEfiAcpiSupportProtocolGuid ## CONSUMES + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonSiPkg/BroxtonSiPrivate.dec + +[LibraryClasses] + DebugLib + IoLib + BaseLib + PcdLib + UefiLib + HobLib + ScPlatformLib + MmPciLib + BaseMemoryLib + UefiBootServicesTableLib + MemoryAllocationLib + SteppingLib + ConfigBlockLib + +[Pcd] + gEfiBxtTokenSpaceGuid.PcdVtdGfxBaseAddress ## ALWAYS_CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## SOMETIMES_CONSUMES diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c new file mode 100644 index 0000000000..36dcf53d1c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c @@ -0,0 +1,293 @@ +/** @file + PCH Serial IO Lib implementation. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + UINT32 Bar0; + UINT32 Bar1; +} SERIAL_IO_CONTROLLER_DESCRIPTOR; + +typedef struct { + UINT8 DevNum; + UINT8 FuncNum; +} SERIAL_IO_BDF_NUMBERS; + +typedef struct { + UINT16 PciDevIdLp; + CHAR8 AcpiHid[SERIALIO_HID_LENGTH]; +} SERIAL_IO_ID; + +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_BDF_NUMBERS mSerialIoBdf [4] = +{ + {PCI_DEVICE_NUMBER_LPSS_HSUART, PCI_FUNCTION_NUMBER_LPSS_HSUART0}, + {PCI_DEVICE_NUMBER_LPSS_HSUART, PCI_FUNCTION_NUMBER_LPSS_HSUART1}, + {PCI_DEVICE_NUMBER_LPSS_HSUART, PCI_FUNCTION_NUMBER_LPSS_HSUART2}, + {PCI_DEVICE_NUMBER_LPSS_HSUART, PCI_FUNCTION_NUMBER_LPSS_HSUART3}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoAcpiAddress [4] = +{ + + {LPSS_I2C0_TMP_BAR0 + 0x80000,LPSS_I2C0_TMP_BAR0 + 0x81000}, + {LPSS_I2C0_TMP_BAR0 + 0x90000,LPSS_I2C0_TMP_BAR0 + 0x91000}, + {LPSS_I2C0_TMP_BAR0 + 0x100000,LPSS_I2C0_TMP_BAR0 + 0x101000}, + {LPSS_I2C0_TMP_BAR0 + 0x110000,LPSS_I2C0_TMP_BAR0 + 0x111000}, +}; + +typedef struct { + UINT16 PciCfgCtrAddr; + UINT16 Psf3BaseAddress; +} SERIAL_IO_CONTROLLER_PSF3_OFFSETS; + +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_PSF3_OFFSETS mPchLpSerialIoPsf3Offsets [4] = +{ + { 0x220, 0x1100}, + { 0x224, 0x1000}, + { 0x228, 0x0F00}, + { 0x22C, 0x0E00}, +}; + + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + + @retval UINT8 SerialIo device number + +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ) +{ + return mSerialIoBdf[SerialIoNumber].DevNum; +} + + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + + @retval UINT8 SerialIo funciton number + +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ) +{ + return mSerialIoBdf[SerialIoNumber].FuncNum; +} + + +/** + Finds BAR value of SerialIo devices. + + SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work. + If the SerialIo device is in PCI mode, a request for BAR1 will return its PCI CFG space instead + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + @param[in] BarNumber 0=BAR0, 1=BAR1 + + @retval UINTN SerialIo Bar value + +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ) +{ + UINT32 Bar; + UINTN PcieBase; + UINT32 VenId; + + PcieBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_SC, GetSerialIoDeviceNumber (SerialIoDevice), GetSerialIoFunctionNumber (SerialIoDevice)); + + VenId = MmioRead32 (PcieBase + PCI_VENDOR_ID_OFFSET) & 0xFFFF; + + if (VenId == V_INTEL_VENDOR_ID) { + if (BarNumber == 1) { + return PcieBase; + } + Bar = (MmioRead32 (PcieBase + PCI_BASE_ADDRESSREG_OFFSET + 8*BarNumber) & 0xFFFFF000); + return Bar; + } + + return 0xFFFFFFFF; +} + + +/** + Configures Serial IO Controller. + + @param[in] Controller 0=I2C0, ..., 11=UART2 + @param[in] DeviceMode Different type of serial io mode defined in PCH_SERIAL_IO_MODE + @param[in] SerialIoSafeRegister D0i3 Max Power On Latency and Device PG config + +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode +#ifdef PCH_PO_FLAG + , IN UINT32 SerialIoSafeRegister +#endif + ) +{ + UINTN PciCfgBase; + UINTN Bar; + UINT32 Data32; + SERIAL_IO_CONTROLLER_PSF3_OFFSETS *SerialIoPsf3Offsets; + + PciCfgBase = MmPciBase (0, GetSerialIoDeviceNumber (Controller), GetSerialIoFunctionNumber (Controller)); + + // + // Do not modify a device that has already been initialized + // + if (MmioRead16(PciCfgBase + PCI_VENDOR_ID_OFFSET) != V_INTEL_VENDOR_ID) { + return; + } + +#ifdef PCH_PO_FLAG + if (!SerialIoSafeRegister) { +#endif + // + // Step 1. Set Bit 16,17,18. + // + MmioOr32 (PciCfgBase + R_LPSS_IO_D0I3MAXDEVPG, BIT18 | BIT17 | BIT16); +#ifdef PCH_PO_FLAG + } +#endif + + SerialIoPsf3Offsets = mPchLpSerialIoPsf3Offsets; + + Bar = MmioRead32(PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000; + + switch (DeviceMode) { + case PchSerialIoDisabled: + MmioOr32 (PciCfgBase + R_LPSS_IO_PCS, BIT1 | BIT0); + PchPcrAndThenOr32 (0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddress+0x001C, 0xFFFFFFFF, BIT8); + break; + + case PchSerialIoAcpi: + case PchSerialIoAcpiHidden: + case PchSerialIoLegacyUart: + // + // Assign BAR0 + // Assign BAR1 + // + if (Bar == 0) { + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR, mSerialIoAcpiAddress[Controller].Bar0); + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR_HIGH, 0x0); + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR1, mSerialIoAcpiAddress[Controller].Bar1); + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR1_HIGH, 0x0); + Bar = MmioRead32 (PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000; + } + + MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar); + + // + // Set Memory space Enable + // + MmioOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); + + // + // Get controller out of reset + // + MmioWrite32 (Bar + R_LPSS_IO_MEM_RESETS, 0); + MmioWrite32 (Bar + R_LPSS_IO_MEM_RESETS, B_LPSS_IO_MEM_HC_RESET_REL | B_LPSS_IO_MEM_iDMA_RESET_REL); + break; + + case PchSerialIoPci: + if (Bar == 0) { + + PchPcrAndThenOr32 (0x90, SerialIoPsf3Offsets[Controller].PciCfgCtrAddr, 0xFFFFFFFF, BIT7); + PchPcrAndThenOr32 (0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddress + 0x001C, 0xFFFFFFFF, BIT18); + + do { + PchPcrRead32(0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddress + 0x001C, &Data32); + } while (Data32 & BIT18 != BIT18); + + // + // Assign BAR0 and Set Memory space Enable + // + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR, mSerialIoAcpiAddress[Controller].Bar0); + MmioWrite32 (PciCfgBase + R_LPSS_IO_BAR_HIGH, 0x0); + MmioOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); + + // + // Read Newly Assigned BAR + // + Bar = MmioRead32(PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000; + } + + // + // Update Address Remap Register with Current BAR + // + MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar); + + /// + /// Get controller out of reset + /// + MmioWrite32 (Bar + R_LPSS_IO_MEM_RESETS, 0); + + MmioOr32 (Bar + R_LPSS_IO_MEM_RESETS, B_LPSS_IO_MEM_HC_RESET_REL | B_LPSS_IO_MEM_iDMA_RESET_REL); + break; + + default: + return; + } + + // + // Program clock dividers for UARTs in legacy mode + // Enable Byte addressing for UARTs in legacy mode + // + if (Controller >= PchSerialIoIndexUart0 && Controller <= PchSerialIoIndexUart3) { + Data32 = B_LPSS_IO_MEM_PCP_CLK_UPDATE | (V_LPSS_IO_PPR_CLK_N_DIV << 16) | (V_LPSS_IO_PPR_CLK_M_DIV << 1) | B_LPSS_IO_MEM_PCP_CLK_EN; + MmioWrite32 (Bar + R_LPSS_IO_MEM_PCP, Data32); + + if (DeviceMode == PchSerialIoLegacyUart) { + // + // Set UART Byte Address Control - Control bit for 16550 8-Bit Addressing Mode. + // + PchPcrAndThenOr32(0x90, 0x618, 0xFFFFFFFF, (BIT0 << (Controller - PchSerialIoIndexUart0))); + + // + // An MMIO Read Must Immediately Be Issued to UART2 BAR0 + 0xF8 for 8-bit Legacy Mode to Activate + // + MmioRead32(Bar + R_LPSS_IO_MANID); + } + } +} + + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf new file mode 100644 index 0000000000..2e8b9b5bf0 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf @@ -0,0 +1,41 @@ +## @file +# Library for Pch Serial Io. +# +# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiDxeSmmPchSerialIoLib + FILE_GUID = 613A22A2-5736-40f8-909B-DF10EA389C72 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PchSerialIoLib + +[Sources] + PeiDxeSmmPchSerialIoLib.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + ScPlatformLib + +[BuildOptions] + *_*_IA32_ASM_FLAGS = /w /Od /GL- + *_*_IA32_CC_FLAGS = /w /Od /GL- + *_*_X64_CC_FLAGS = /w /Od /GL- diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c new file mode 100644 index 0000000000..ed34140562 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c @@ -0,0 +1,348 @@ +/** @file + PCH Serial IO UART Lib implementation. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_BAUD_RATE 460800 // Maximum Baud per SoC spec + +#define R_PCH_SERIAL_IO_8BIT_UART_RXBUF 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_TXBUF 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH 0x01 +#define R_PCH_SERIAL_IO_8BIT_UART_FCR 0x02 +#define R_PCH_SERIAL_IO_8BIT_UART_IIR 0x02 +#define R_PCH_SERIAL_IO_8BIT_UART_LCR 0x03 +#define R_PCH_SERIAL_IO_8BIT_UART_MCR 0x04 +#define R_PCH_SERIAL_IO_8BIT_UART_LSR 0x05 +#define R_PCH_SERIAL_IO_8BIT_UART_USR 0x1F + +#define R_PCH_SERIAL_IO_NATIVE_UART_RXBUF 0x00 +#define R_PCH_SERIAL_IO_NATIVE_UART_TXBUF 0x00 +#define R_PCH_SERIAL_IO_NATIVE_UART_BAUD_LOW 0x00 +#define R_PCH_SERIAL_IO_NATIVE_UART_BAUD_HIGH 0x04 +#define R_PCH_SERIAL_IO_NATIVE_UART_FCR 0x08 +#define R_PCH_SERIAL_IO_NATIVE_UART_IIR 0x08 +#define R_PCH_SERIAL_IO_NATIVE_UART_LCR 0x0C +#define R_PCH_SERIAL_IO_NATIVE_UART_MCR 0x10 +#define R_PCH_SERIAL_IO_NATIVE_UART_LSR 0x14 +#define R_PCH_SERIAL_IO_NATIVE_UART_USR 0x7C + +#define B_PCH_SERIAL_IO_UART_IIR_FIFOSE BIT7|BIT6 +#define B_PCH_SERIAL_IO_UART_LSR_TXRDY BIT5 +#define B_PCH_SERIAL_IO_UART_LSR_RXDA BIT0 +#define B_PCH_SERIAL_IO_UART_LCR_DLAB BIT7 +#define B_PCH_SERIAL_IO_UART_FCR_FCR BIT0 +#define B_PCH_SERIAL_IO_UART_MCR_RTS BIT1 +#define B_PCH_SERIAL_IO_UART_MCR_AFCE BIT5 +#define B_PCH_SERIAL_IO_UART_USR_TFNF BIT1 + +/** + Initialize selected SerialIo UART. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] FifoEnable When TRUE, enables 64-byte FIFOs. + @param[in] BaudRate Baud rate. + @param[in] LineControl Data length, parity, stop bits. + @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data. + +**/ +VOID +SerialIo16550Init ( + IN UINTN Base, + IN BOOLEAN FifoEnable, + IN UINT32 BaudRate, + IN UINT8 LineControl, + IN BOOLEAN HardwareFlowControl, + IN UINT8 ShiftOffset + ) +{ + UINTN Divisor; + + Divisor = MAX_BAUD_RATE / BaudRate; + // + // Configure baud rate + // + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_LCR >> ShiftOffset), B_PCH_SERIAL_IO_UART_LCR_DLAB); + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_BAUD_HIGH >> ShiftOffset), (UINT8) (Divisor >> 8)); + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_BAUD_LOW >> ShiftOffset), (UINT8) (Divisor & 0xff)); + // + // Configure Line control and switch back to bank 0 + // + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_LCR >> ShiftOffset), LineControl & 0x1F); + // + // Enable and reset FIFOs + // + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_FCR >> ShiftOffset), FifoEnable ? B_PCH_SERIAL_IO_UART_FCR_FCR : 0); + // + // Put Modem Control Register(MCR) into its reset state of 0x00. + // + MmioWrite8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_MCR >> ShiftOffset), B_PCH_SERIAL_IO_UART_MCR_RTS | (HardwareFlowControl ? B_PCH_SERIAL_IO_UART_MCR_AFCE : 0) ); + + return; +} + + +/** + Initialize selected SerialIo UART. + This init function MUST be used prior any SerialIo UART functions to init serial io controller + if platform is going use serialio UART as debug output. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] FifoEnable When TRUE, enables 64-byte FIFOs. + @param[in] BaudRate Baud rate. + @param[in] LineControl Data length, parity, stop bits. + @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, + and sets RTS when receiving data. + @retval BOOLEAN Initilization succeeded. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartInit ( + IN UINT8 UartNumber, + IN BOOLEAN FifoEnable, + IN UINT32 BaudRate, + IN UINT8 LineControl, + IN BOOLEAN HardwareFlowControl + ) +{ + UINT32 UartMode = 0; + UINTN Bar = 0; + UINT8 ShiftOffset = 0; + + if (UartNumber > 3) { + return FALSE; // In case of invalid UART device + } + +#ifdef PCH_PO_FLAG + ConfigureSerialIoController (UartNumber + PchSerialIoIndexUart0, PchSerialIoPci, 0); +#else + ConfigureSerialIoController (UartNumber + PchSerialIoIndexUart0, PchSerialIoPci); +#endif + + // + // Find UART Mode (Checking for 16550 Mode) + // + PchPcrRead32 (0x90, 0x618, &UartMode); + + if (UartMode == BIT2) { + ShiftOffset = 2; + } + + Bar = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + + if (Bar == 0xFFFFFFFF) { + return FALSE; + } + + SerialIo16550Init (Bar, FifoEnable, BaudRate, LineControl, HardwareFlowControl, ShiftOffset); + return TRUE; +} + + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval UINTN Actual number of bytes writed to serial device. +**/ +UINTN +EFIAPI +PchSerialIoUartOut ( + IN UINT8 UartNumber, + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN BytesLeft; + volatile UINTN Base; + UINT32 UartMode = 0; + UINT8 ShiftOffset = 0; + UINT32 TxAttemptCount = 0; + + if (UartNumber > 3) { + return 0; // In case of invalid UART device + } + + Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + + // + // Sanity checks to avoid infinite loop when trying to print through uninitialized UART + // + // If BAR is unavailable, write 0 bytes to the device + // + if (Base == 0xFFFFFFFF || + (Base & 0xFFFFFF00) == 0x0 || + MmioRead8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_USR >> ShiftOffset)) == 0xFF || + Buffer == NULL) { + return 0; + } + + PchPcrRead32(0x90, 0x618, &UartMode); + + if (UartMode == BIT2) + { + ShiftOffset = 2; + } + + BytesLeft = NumberOfBytes; + + while (BytesLeft != 0 && TxAttemptCount < 200) { + // + // Write data while there's room in TXFIFO. If HW Flow Control was enabled, it happens automatically on hardware level. + // + while ((MmioRead8(Base + (R_PCH_SERIAL_IO_NATIVE_UART_IIR >> ShiftOffset)) & 0xF) == 0x10); + + if (MmioRead8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_USR >> ShiftOffset)) & B_PCH_SERIAL_IO_UART_USR_TFNF) { + MmioWrite8 (Base + R_PCH_SERIAL_IO_NATIVE_UART_TXBUF, *Buffer); + + TxAttemptCount = 0; + Buffer++; + BytesLeft--; + } + TxAttemptCount++; + } + + return NumberOfBytes; +} + + +/** + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[out] Buffer Point of data buffer which need to be writed. + @param[in] NumberOfBytes Number of output bytes which are cached in Buffer. + @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, + function returns as soon as no new characters are available. + + @retval UINTN Actual number of bytes read to the serial device. + +**/ +UINTN +EFIAPI +PchSerialIoUartIn ( + IN UINT8 UartNumber, + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes, + IN BOOLEAN WaitUntilBufferFull + ) +{ + UINTN BytesReceived; + UINTN Base; + UINT32 UartMode = 0; + UINT8 ShiftOffset = 0; + + if (UartNumber > 3) { + return 0; // In case of invalid UART device + } + + Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + + // + // If BAR is unavailable, receive 0 bytes + // + if (Base == 0xFFFFFFFF) { + return 0; + } + + PchPcrRead32 (0x90, 0x618, &UartMode); + if (UartMode == 4) { + ShiftOffset = 2; + } + + if (NULL == Buffer) { + return 0; + } + + BytesReceived = 0; + + while (BytesReceived != NumberOfBytes) { + // + // check if there's data in RX buffer + // + if (MmioRead8 (Base + (R_PCH_SERIAL_IO_NATIVE_UART_LSR >> ShiftOffset)) & B_PCH_SERIAL_IO_UART_LSR_RXDA) { + // + // Receive data + // + *Buffer = MmioRead8 (Base + R_PCH_SERIAL_IO_NATIVE_UART_RXBUF); + Buffer++; + BytesReceived++; + } else { + if (!WaitUntilBufferFull && ((MmioRead8(Base + (R_PCH_SERIAL_IO_NATIVE_UART_LSR >> ShiftOffset)) & BIT0) == 0)) { + // + // If there's no data and function shouldn't wait, exit early + // + return BytesReceived; + } + } + } + + return BytesReceived; +} + + +/** + Polls a serial device to see if there is any data waiting to be read. + + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartPoll ( + IN UINT8 UartNumber + ) +{ + UINTN Base; + + if (UartNumber > 3) { + return FALSE; // In case of invalid UART device + } + + Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + // + // Read the serial port status + // + if ((MmioRead8 (Base + R_PCH_SERIAL_IO_NATIVE_UART_LSR) & B_PCH_SERIAL_IO_UART_LSR_RXDA) != 0) { + return TRUE; + } + return FALSE; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf new file mode 100644 index 0000000000..18ae567999 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf @@ -0,0 +1,40 @@ +## @file +# Library for Pch Serial Io Uart. +# +# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = PeiDxeSmmPchSerialIoUartLib + FILE_GUID = 55463A54-FD0D-4e8e-8D57-D54FAAEFDC2F + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PchSerialIoUartLib + +[Sources] + PeiDxeSmmPchSerialIoUartLib.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + BaseLib + IoLib + DebugLib + MmPciLib + PchSerialIoLib + TimerLib + +[Pcd] + gBxtRefCodePkgTokenSpaceGuid.PcdSerialIoUartNumber diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.c new file mode 100644 index 0000000000..bfdb6d0a1f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.c @@ -0,0 +1,862 @@ +/** @file + This file is PeiScPolicy library. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiScPolicyLibrary.h" +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] = { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED PRIVATE_PCICFGCTRL mDirectIrqTable[] = { + { 0x90, 0x200, 27, V_PCICFG_CTRL_INTA }, + { 0x90, 0x204, 28, V_PCICFG_CTRL_INTB }, + { 0x90, 0x208, 29, V_PCICFG_CTRL_INTC }, + { 0x90, 0x20C, 30, V_PCICFG_CTRL_INTD }, + { 0x90, 0x210, 31, V_PCICFG_CTRL_INTA }, + { 0x90, 0x214, 32, V_PCICFG_CTRL_INTB }, + { 0x90, 0x218, 33, V_PCICFG_CTRL_INTC }, + { 0x90, 0x21C, 34, V_PCICFG_CTRL_INTD }, + { 0x90, 0x220, 4, V_PCICFG_CTRL_INTA }, + { 0x90, 0x224, 5, V_PCICFG_CTRL_INTB }, + { 0x90, 0x228, 6, V_PCICFG_CTRL_INTC }, + { 0x90, 0x22C, 7, V_PCICFG_CTRL_INTD }, + { 0x90, 0x230, 35, V_PCICFG_CTRL_INTA }, + { 0x90, 0x234, 36, V_PCICFG_CTRL_INTB }, + { 0x90, 0x238, 37, V_PCICFG_CTRL_INTC }, + { 0xD6, 0x208, 3, V_PCICFG_CTRL_INTA }, + { 0xD6, 0x200, 39, V_PCICFG_CTRL_INTA }, + { 0xD6, 0x20C, 38, V_PCICFG_CTRL_INTA }, + { 0xD6, 0x204, 42, V_PCICFG_CTRL_INTA }, + { 0x98, 0x200, 26, V_PCICFG_CTRL_INTA }, + { 0xA4, 0x200, 13, V_PCICFG_CTRL_INTB }, +}; + +/** + mDevIntConfig[] table contains data on INTx and IRQ for each device. + + + PCI Express Root Ports mapping should be programmed only with values as in below table (D19/20) + otherwise _PRT methods in ACPI for RootPorts would require additional patching as + PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Mapping + + Configured IRQ values are not used if an OS chooses to be in PIC instead of APIC mode +**/ +GLOBAL_REMOVE_IF_UNREFERENCED SC_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = { + {19, 0, ScIntA, 16}, // PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh + {19, 1, ScIntB, 17}, // PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh + {19, 2, ScIntC, 18}, // PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh + {19, 3, ScIntD, 19}, // PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh + {20, 0, ScIntA, 16}, // PCI Express Port 1 (APL Only), INT is default, programmed in PciCfgSpace + FCh + {20, 1, ScIntB, 17}, // PCI Express Port 2 (APL Only), INT is default, programmed in PciCfgSpace + FCh +}; + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadScGeneralConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_GENERAL_CONFIG *ScGeneralConfig; + + ScGeneralConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "ScGeneralConfig->Header.Guid = %g\n", &ScGeneralConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "ScGeneralConfig->Header.Size = 0x%x\n", ScGeneralConfig->Header.Size)); + + ScGeneralConfig->SubSystemVendorId = V_INTEL_VENDOR_ID; + ScGeneralConfig->SubSystemId = V_SC_DEFAULT_SID; + + ScGeneralConfig->AcpiBase = (UINT16) PcdGet16 (PcdScAcpiIoPortBaseAddress); + ScGeneralConfig->PmcBase = (UINT32) PcdGet32 (PcdPmcGcrBaseAddress); + ScGeneralConfig->P2sbBase = (UINT32) PcdGet32 (PcdP2SBBaseAddress); +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadSataConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_SATA_CONFIG *SataConfig; + UINT8 PortIndex; + + SataConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SataConfig->Header.Guid = %g\n", &SataConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "SataConfig->Header.Size = 0x%x\n", SataConfig->Header.Size)); + + SataConfig->Enable = TRUE; + SataConfig->SalpSupport = TRUE; + SataConfig->SataMode = ScSataModeAhci; + SataConfig->SpeedLimit = ScSataSpeedDefault; + + for (PortIndex = 0; PortIndex < SC_MAX_SATA_PORTS; PortIndex++) { + SataConfig->PortSettings[PortIndex].Enable = TRUE; + SataConfig->PortSettings[PortIndex].DmVal = 15; + SataConfig->PortSettings[PortIndex].DitoVal = 625; + } +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadPcieConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_PCIE_CONFIG *PcieConfig; + UINT8 PortIndex; + + PcieConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PcieConfig->Header.Guid = %g\n", &PcieConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "PcieConfig->Header.Size = 0x%x\n", PcieConfig->Header.Size)); + + for (PortIndex = 0; PortIndex < GetScMaxPciePortNum (); PortIndex++) { + PcieConfig->RootPort[PortIndex].Aspm = ScPcieAspmAutoConfig; + PcieConfig->RootPort[PortIndex].Enable = TRUE; + PcieConfig->RootPort[PortIndex].SlotImplemented = TRUE; + PcieConfig->RootPort[PortIndex].PmSci = TRUE; + PcieConfig->RootPort[PortIndex].AcsEnabled = TRUE; + PcieConfig->RootPort[PortIndex].PhysicalSlotNumber = PortIndex; + PcieConfig->RootPort[PortIndex].L1Substates = ScPcieL1SubstatesL1_1_2; + PcieConfig->RootPort[PortIndex].SelectableDeemphasis = TRUE; + // + // PCIe LTR Configuration. + // + PcieConfig->RootPort[PortIndex].LtrEnable = TRUE; + PcieConfig->RootPort[PortIndex].LtrMaxSnoopLatency = 0x1003; + PcieConfig->RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + PcieConfig->RootPort[PortIndex].SnoopLatencyOverrideMode = 2; + PcieConfig->RootPort[PortIndex].SnoopLatencyOverrideMultiplier = 2; + PcieConfig->RootPort[PortIndex].SnoopLatencyOverrideValue = 60; + PcieConfig->RootPort[PortIndex].NonSnoopLatencyOverrideMode = 2; + PcieConfig->RootPort[PortIndex].NonSnoopLatencyOverrideMultiplier = 2; + PcieConfig->RootPort[PortIndex].NonSnoopLatencyOverrideValue = 60; + } + PcieConfig->AspmSwSmiNumber = SW_SMI_PCIE_ASPM_OVERRIDE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadUsbConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_USB_CONFIG *UsbConfig; + UINT32 PortIndex; + + UsbConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "UsbConfig->Header.Guid = %g\n", &UsbConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "UsbConfig->Header.Size = 0x%x\n", UsbConfig->Header.Size)); + + UsbConfig->Usb30Settings.Mode = XHCI_MODE_ON; + for (PortIndex = 0; PortIndex < GetScXhciMaxUsb2PortNum (); PortIndex++) { + UsbConfig->PortUsb20[PortIndex].Enable = TRUE; + } + for (PortIndex = 0; PortIndex < GetScXhciMaxUsb3PortNum (); PortIndex++) { + UsbConfig->PortUsb30[PortIndex].Enable = TRUE; + } + UsbConfig->XdciConfig.Enable = ScPciMode; + UsbConfig->SsicConfig.SsicPort[0].Enable = FALSE; + UsbConfig->SsicConfig.SsicPort[1].Enable = FALSE; + UsbConfig->SsicConfig.SsicPort[0].Rate = XhciSsicRateA; + UsbConfig->SsicConfig.SsicPort[1].Rate = XhciSsicRateA; + UsbConfig->SsicConfig.DlanePwrGating = TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadHpetConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_HPET_CONFIG *HpetConfig; + + HpetConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HpetConfig->Header.Guid = %g\n", &HpetConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "HpetConfig->Header.Size = 0x%x\n", HpetConfig->Header.Size)); + + HpetConfig->Enable = TRUE; + HpetConfig->Base = SC_HPET_BASE_ADDRESS; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadSmbusConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_SMBUS_CONFIG *SmbusConfig; + + SmbusConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SmbusConfig->Header.Guid = %g\n", &SmbusConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "SmbusConfig->Header.Size = 0x%x\n", SmbusConfig->Header.Size)); + + SmbusConfig->Enable = TRUE; + SmbusConfig->SmbusIoBase = PcdGet16(PcdSmbusBaseAddress); + ASSERT (sizeof (mSmbusRsvdAddresses) <= SC_MAX_SMBUS_RESERVED_ADDRESS); + SmbusConfig->NumRsvdSmbusAddresses = sizeof (mSmbusRsvdAddresses); + CopyMem ( + SmbusConfig->RsvdSmbusAddressTable, + mSmbusRsvdAddresses, + sizeof (mSmbusRsvdAddresses) + ); +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadIoApicConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_IOAPIC_CONFIG *IoApicConfig; + + IoApicConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "IoApicConfig->Header.Guid = %g\n", &IoApicConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "IoApicConfig->Header.Size = 0x%x\n", IoApicConfig->Header.Size)); +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadHdaConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_HDAUDIO_CONFIG *HdaConfig; + + HdaConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HdaConfig->Header.Guid = %g\n", &HdaConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "HdaConfig->Header.Size = 0x%x\n", HdaConfig->Header.Size)); + + HdaConfig->Enable = TRUE; + HdaConfig->DspEnable = TRUE; + HdaConfig->Mmt = ScHdaVc0; + HdaConfig->Hmt = ScHdaVc0; + HdaConfig->BiosCfgLockDown = TRUE; + HdaConfig->PwrGate = TRUE; + HdaConfig->ClkGate = TRUE; + HdaConfig->Pme = TRUE; + HdaConfig->IoBufferOwnership = ScHdaIoBufOwnerI2sPort; + HdaConfig->VcType = ScHdaVc0; + HdaConfig->HdAudioLinkFrequency = ScHdaLinkFreq24MHz; + HdaConfig->IDispLinkFrequency = ScHdaLinkFreq96MHz; + HdaConfig->IDispLinkTmode = ScHdaIDispMode2T; + HdaConfig->ResetWaitTimer = 300; + HdaConfig->RsvdBits3 = 0; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadGmmConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_GMM_CONFIG *GmmConfig; + + GmmConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "GmmConfig->Header.Guid = %g\n", &GmmConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "GmmConfig->Header.Size = 0x%x\n", GmmConfig->Header.Size)); + + GmmConfig->ClkGatingPgcbClkTrunk = TRUE; + GmmConfig->ClkGatingSb = TRUE; + GmmConfig->ClkGatingSbClkTrunk = TRUE; + GmmConfig->ClkGatingSbClkPartition = TRUE; + GmmConfig->ClkGatingCore = TRUE; + GmmConfig->ClkGatingDma = TRUE; + GmmConfig->ClkGatingRegAccess = TRUE; + GmmConfig->ClkGatingHost = TRUE; + GmmConfig->ClkGatingPartition = TRUE; + GmmConfig->ClkGatingTrunk = TRUE; + GmmConfig->SvPwrGatingHwAutoEnable = TRUE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadPmConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_PM_CONFIG *PmConfig; + + PmConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PmConfig->Header.Guid = %g\n", &PmConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "PmConfig->Header.Size = 0x%x\n", PmConfig->Header.Size)); + + PmConfig->PciClockRun = TRUE; + PmConfig->Timer8254ClkGateEn = TRUE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadLockDownConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_LOCK_DOWN_CONFIG *LockDownConfig; + + LockDownConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "LockDownConfig->Header.Guid = %g\n", &LockDownConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "LockDownConfig->Header.Size = 0x%x\n", LockDownConfig->Header.Size)); + + LockDownConfig->GlobalSmi = TRUE; + // + // Flash Security Recommendations, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + // Here we always enable this as a Policy. + // + LockDownConfig->BiosInterface = TRUE; + LockDownConfig->RtcLock = TRUE; + LockDownConfig->BiosLockSwSmiNumber = SW_SMI_BIOS_LOCK; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadSerialIrqConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_LPC_SIRQ_CONFIG *SerialIrqConfig; + + SerialIrqConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.Guid = %g\n", &SerialIrqConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.Size = 0x%x\n", SerialIrqConfig->Header.Size)); + + SerialIrqConfig->SirqEnable = TRUE; + SerialIrqConfig->SirqMode = ScQuietMode; + SerialIrqConfig->StartFramePulse = ScSfpw4Clk; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadLpssConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_LPSS_CONFIG *LpssConfig; + UINT8 Index; + + LpssConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "LpssConfig->Header.Guid = %g\n", &LpssConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "LpssConfig->Header.Size = 0x%x\n", LpssConfig->Header.Size)); + + LpssConfig->I2c0Enable = ScPciMode; + LpssConfig->I2c1Enable = ScPciMode; + LpssConfig->I2c2Enable = ScPciMode; + LpssConfig->I2c3Enable = ScPciMode; + LpssConfig->I2c4Enable = ScPciMode; + LpssConfig->I2c5Enable = ScPciMode; + LpssConfig->I2c6Enable = ScPciMode; + LpssConfig->I2c7Enable = ScPciMode; + LpssConfig->Hsuart0Enable = ScPciMode; + LpssConfig->Hsuart1Enable = ScPciMode; + LpssConfig->Hsuart2Enable = ScPciMode; + LpssConfig->Hsuart3Enable = ScPciMode; + LpssConfig->Spi0Enable = ScPciMode; + LpssConfig->Spi1Enable = ScPciMode; + LpssConfig->Spi2Enable = ScPciMode; + + for (Index = 0; Index < LPSS_I2C_DEVICE_NUM; Index++) { + LpssConfig->I2cClkGateCfg[Index] = TRUE; + } + + for (Index = 0; Index < LPSS_HSUART_DEVICE_NUM; Index++) { + LpssConfig->HsuartClkGateCfg[Index] = TRUE; + } + + for (Index = 0; Index < LPSS_SPI_DEVICE_NUM; Index++) { + LpssConfig->SpiClkGateCfg[Index] = TRUE; + } +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadScsConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_SCS_CONFIG *ScsConfig; + + ScsConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "ScsConfig->Header.Guid = %g\n", &ScsConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "ScsConfig->Header.Size = 0x%x\n", ScsConfig->Header.Size)); + + ScsConfig->SdcardEnable = ScPciMode; + ScsConfig->SdioEnable = ScPciMode; + ScsConfig->EmmcEnable = ScPciMode; + ScsConfig->EmmcHostMaxSpeed = SccEmmcHs400; + ScsConfig->GppLock = 0; + ScsConfig->SccEmmcTraceLength = SCC_EMMC_LONG_TRACE_LEN; + ScsConfig->SdioRegDllConfig.TxCmdCntl = 0x505; + ScsConfig->SdioRegDllConfig.TxDataCntl1 = 0xE; + ScsConfig->SdioRegDllConfig.TxDataCntl2 = 0x22272828; + ScsConfig->SdioRegDllConfig.RxCmdDataCntl1 = 0x16161616; + ScsConfig->SdioRegDllConfig.RxCmdDataCntl2 = 0x10000; + ScsConfig->SdcardRegDllConfig.TxCmdCntl = 0x505; + if (GetBxtSeries () == Bxt) { + ScsConfig->SdcardRegDllConfig.TxDataCntl1 = 0xA12; + ScsConfig->SdcardRegDllConfig.TxDataCntl2 = 0x26272727; + ScsConfig->SdcardRegDllConfig.RxCmdDataCntl1 = 0x0B483B3B; + } else { + ScsConfig->SdcardRegDllConfig.TxDataCntl1 = 0xA13; + ScsConfig->SdcardRegDllConfig.TxDataCntl2 = 0x24242828; + ScsConfig->SdcardRegDllConfig.RxCmdDataCntl1 = 0x73A3637; + } + ScsConfig->SdcardRegDllConfig.RxStrobeCntl = 0x0; + ScsConfig->SdcardRegDllConfig.RxCmdDataCntl2 = 0x10000; + + if (ScsConfig->SccEmmcTraceLength == SCC_EMMC_SHORT_TRACE_LEN) { + // + // Configure DLL settings for short trace length + // + ScsConfig->EmmcRegDllConfig.TxCmdCntl = 0x505; + ScsConfig->EmmcRegDllConfig.TxDataCntl1 = 0xC15; + ScsConfig->EmmcRegDllConfig.TxDataCntl2 = 0x1C1C1C00; + ScsConfig->EmmcRegDllConfig.RxCmdDataCntl1 = 0x1C1C1C00; + ScsConfig->EmmcRegDllConfig.RxStrobeCntl = 0x0a0a; + ScsConfig->EmmcRegDllConfig.RxCmdDataCntl2 = 0x1001C; + ScsConfig->EmmcRegDllConfig.MasterSwCntl = 0x001; + } else { + // + // Configure DLL settings for long trace length + // + ScsConfig->EmmcRegDllConfig.TxCmdCntl = 0x505; + ScsConfig->EmmcRegDllConfig.TxDataCntl1 = 0xC11; + ScsConfig->EmmcRegDllConfig.TxDataCntl2 = 0x1C2A2927; + ScsConfig->EmmcRegDllConfig.RxCmdDataCntl1 = 0x000D162F; + ScsConfig->EmmcRegDllConfig.RxStrobeCntl = 0x0a0a; + ScsConfig->EmmcRegDllConfig.RxCmdDataCntl2 = 0x1003b; + ScsConfig->EmmcRegDllConfig.MasterSwCntl = 0x001; + } +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadVtdConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_VTD_CONFIG *VtdConfig; + + VtdConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "VtdConfig->Header.Guid = %g\n", &VtdConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "VtdConfig->Header.Size = 0x%x\n", VtdConfig->Header.Size)); + + VtdConfig->RmrrUsbBaseAddr = 0; + VtdConfig->RmrrUsbLimit = 0; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadIshConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_ISH_CONFIG *IshConfig; + + IshConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "IshConfig->Header.Guid = %g\n", &IshConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "IshConfig->Header.Size = 0x%x\n", IshConfig->Header.Size)); + + IshConfig->Enable = TRUE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadFlashProtectionConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + + FlashProtectionConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.Guid = %g\n", &FlashProtectionConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.Size = 0x%x\n", FlashProtectionConfig->Header.Size)); +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadDciConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_DCI_CONFIG *DciConfig; + + DciConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "DciConfig->Header.Guid = %g\n", &DciConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "DciConfig->Header.Size = 0x%x\n", DciConfig->Header.Size)); + + DciConfig->DciAutoDetect = TRUE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadP2sbConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_P2SB_CONFIG *P2sbConfig; + + P2sbConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "P2sbConfig->Header.Guid = %g\n", &P2sbConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "P2sbConfig->Header.Size = 0x%x\n", P2sbConfig->Header.Size)); + + P2sbConfig->P2sbUnhide = 0; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadInterruptConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINT8 IntConfigTableEntries; + UINT8 DirectIrqTableEntries; + SC_INTERRUPT_CONFIG *InterruptConfig; + + InterruptConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "InterruptConfig->Header.Guid = %g\n", &InterruptConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "InterruptConfig->Header.Size = 0x%x\n", InterruptConfig->Header.Size)); + + DirectIrqTableEntries = sizeof (mDirectIrqTable) / sizeof (PRIVATE_PCICFGCTRL); + ASSERT (DirectIrqTableEntries <= SC_MAX_DIRECT_IRQ_CONFIG); + InterruptConfig->NumOfDirectIrqTable = DirectIrqTableEntries; + CopyMem ( + InterruptConfig->DirectIrqTable, + mDirectIrqTable, + sizeof (mDirectIrqTable) + ); + + IntConfigTableEntries = sizeof (mDevIntConfig) / sizeof (SC_DEVICE_INTERRUPT_CONFIG); + ASSERT (IntConfigTableEntries <= SC_MAX_DEVICE_INTERRUPT_CONFIG); + InterruptConfig->NumOfDevIntConfig = IntConfigTableEntries; + CopyMem ( + InterruptConfig->DevIntConfig, + mDevIntConfig, + sizeof (mDevIntConfig) + ); + + InterruptConfig->PxRcRouting[0] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ3; // R_ITSS_SB_PARC PIRQA->IRQx Routing Control + InterruptConfig->PxRcRouting[1] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ4; // R_ITSS_SB_PBRC PIRQB->IRQx Routing Control + InterruptConfig->PxRcRouting[2] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ5; // R_ITSS_SB_PCRC PIRQC->IRQx Routing Control + InterruptConfig->PxRcRouting[3] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ6; // R_ITSS_SB_PDRC PIRQD->IRQx Routing Control + InterruptConfig->PxRcRouting[4] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ7; // R_ITSS_SB_PERC PIRQE->IRQx Routing Control + InterruptConfig->PxRcRouting[5] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ9; // R_ITSS_SB_PFRC PIRQF->IRQx Routing Control + InterruptConfig->PxRcRouting[6] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ10; // R_ITSS_SB_PGRC PIRQG->IRQx Routing Control + InterruptConfig->PxRcRouting[7] = V_ITSS_SB_REN_ENABLE + V_ITSS_SB_IR_IRQ11; // R_ITSS_SB_PHRC PIRQH->IRQx Routing Control +} + +static IP_BLOCK_ENTRY mScIpBlocks [] = { + {&gScGeneralConfigGuid, sizeof (SC_GENERAL_CONFIG), SC_GENERAL_CONFIG_REVISION, LoadScGeneralConfigDefault}, + {&gSataConfigGuid, sizeof (SC_SATA_CONFIG), SATA_CONFIG_REVISION, LoadSataConfigDefault}, + {&gPcieRpConfigGuid, sizeof (SC_PCIE_CONFIG), PCIE_RP_CONFIG_REVISION, LoadPcieConfigDefault}, + {&gUsbConfigGuid, sizeof (SC_USB_CONFIG), USB_CONFIG_REVISION, LoadUsbConfigDefault}, + {&gHpetConfigGuid, sizeof (SC_HPET_CONFIG), HPET_CONFIG_REVISION, LoadHpetConfigDefault}, + {&gSmbusConfigGuid, sizeof (SC_SMBUS_CONFIG), SMBUS_CONFIG_REVISION, LoadSmbusConfigDefault}, + {&gIoApicConfigGuid, sizeof (SC_IOAPIC_CONFIG), IOAPIC_CONFIG_REVISION, LoadIoApicConfigDefault}, + {&gHdAudioConfigGuid, sizeof (SC_HDAUDIO_CONFIG), HDAUDIO_CONFIG_REVISION, LoadHdaConfigDefault}, + {&gGmmConfigGuid, sizeof (SC_GMM_CONFIG), GMM_CONFIG_REVISION, LoadGmmConfigDefault}, + {&gPmConfigGuid, sizeof (SC_PM_CONFIG), PM_CONFIG_REVISION, LoadPmConfigDefault}, + {&gLockDownConfigGuid, sizeof (SC_LOCK_DOWN_CONFIG), LOCK_DOWN_CONFIG_REVISION, LoadLockDownConfigDefault}, + {&gSerialIrqConfigGuid, sizeof (SC_LPC_SIRQ_CONFIG), SERIAL_IRQ_CONFIG_REVISION, LoadSerialIrqConfigDefault}, + {&gLpssConfigGuid, sizeof (SC_LPSS_CONFIG), LPSS_CONFIG_REVISION, LoadLpssConfigDefault}, + {&gScsConfigGuid, sizeof (SC_SCS_CONFIG), SCS_CONFIG_REVISION, LoadScsConfigDefault}, + {&gVtdConfigGuid, sizeof (SC_VTD_CONFIG), VTD_CONFIG_REVISION, LoadVtdConfigDefault}, + {&gIshConfigGuid, sizeof (SC_ISH_CONFIG), ISH_CONFIG_REVISION, LoadIshConfigDefault}, + {&gFlashProtectionConfigGuid, sizeof (SC_FLASH_PROTECTION_CONFIG), FLASH_PROTECTION_CONFIG_REVISION, LoadFlashProtectionConfigDefault}, + {&gDciConfigGuid, sizeof (SC_DCI_CONFIG), DCI_CONFIG_REVISION, LoadDciConfigDefault}, + {&gP2sbConfigGuid, sizeof (SC_P2SB_CONFIG), P2SB_CONFIG_REVISION, LoadP2sbConfigDefault}, + {&gInterruptConfigGuid, sizeof (SC_INTERRUPT_CONFIG), INTERRUPT_CONFIG_REVISION, LoadInterruptConfigDefault}, +}; + + +/** + Get SC config block table total size. + + @retval Size of SC config block table + +**/ +UINT32 +EFIAPI +ScGetConfigBlockTotalSize ( + VOID + ) +{ + UINT32 TotalBlockCount; + UINT32 TotalBlockSize; + UINT32 ConfigBlockHdrSize; + UINT32 BlockCount; + + TotalBlockCount = sizeof (mScIpBlocks) / sizeof (IP_BLOCK_ENTRY); + TotalBlockSize = 0; + for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) { + TotalBlockSize += (UINT32)mScIpBlocks[BlockCount].Size; + DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize)); + } + ConfigBlockHdrSize = GetSizeOfConfigBlockTableHeaders ((UINT16) TotalBlockCount); + + // + // Because CreateConfigBlockTable has the padding for each config block, + // we need extra size, which is TotalBlockCount * 3, to create the table + // + return ConfigBlockHdrSize + TotalBlockSize + (TotalBlockCount * 3); +} + + +/** + CreateConfigBlocks generates the config blocks of SC Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] ScPolicyPpi The pointer to get SC Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScCreateConfigBlocks ( + OUT SC_POLICY_PPI **ScPolicyPpi + ) +{ + UINT16 TotalBlockCount; + UINT16 BlockCount; + VOID *ConfigBlockPointer; + CONFIG_BLOCK ConfigBlockBuf; + EFI_STATUS Status; + SC_POLICY_PPI *InitPolicy; + UINT32 RequiredSize; + + DEBUG ((DEBUG_INFO, "SC CreateConfigBlocks\n")); + + InitPolicy = NULL; + TotalBlockCount = sizeof (mScIpBlocks) / sizeof (IP_BLOCK_ENTRY); + DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount)); + + RequiredSize = ScGetConfigBlockTotalSize (); + + Status = CreateConfigBlockTable ((VOID *) &InitPolicy, TotalBlockCount, RequiredSize); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Policy Revision + // + InitPolicy->TableHeader.Header.Revision = SC_POLICY_REVISION; + // + // Initialize ConfigBlockPointer to NULL + // + ConfigBlockPointer = NULL; + // + // Loop to identify each config block from mScIpBlocks[] Table and add each of them + // + for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) { + CopyMem (&(ConfigBlockBuf.Header.Guid), mScIpBlocks[BlockCount].Guid, sizeof (EFI_GUID)); + ConfigBlockBuf.Header.Size = mScIpBlocks[BlockCount].Size; + ConfigBlockBuf.Header.Revision = mScIpBlocks[BlockCount].Revision; + ConfigBlockPointer = (VOID *) &ConfigBlockBuf; + Status = AddConfigBlock ((VOID *) InitPolicy, (VOID *) &ConfigBlockPointer); + ASSERT_EFI_ERROR (Status); + mScIpBlocks[BlockCount].LoadDefault (ConfigBlockPointer); + } + // + // Assignment for returning Policy config block base address + // + *ScPolicyPpi = InitPolicy; + return EFI_SUCCESS; +} + + +/** + ScInstallPolicyPpi installs ScPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] ScPolicyPpi The pointer to SC Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScInstallPolicyPpi ( + IN SC_POLICY_PPI *ScPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *ScPolicyPpiDesc; + + ScPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (ScPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + ScPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + ScPolicyPpiDesc->Guid = &gScPolicyPpiGuid; + ScPolicyPpiDesc->Ppi = ScPolicyPpi; + + // + // Print whole SC_POLICY_PPI and serial out. + // + ScPrintPolicyPpi (ScPolicyPpi); + + // + // Install SC Policy PPI + // + Status = PeiServicesInstallPpi (ScPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.inf new file mode 100644 index 0000000000..a81fe726a2 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLib.inf @@ -0,0 +1,77 @@ +## @file +# Library for the PeiScPolicy. +# +# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiScPolicyLib + FILE_GUID = BB1AC992-B2CA-4744-84B7-915C185576C5 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = PeiScPolicyLib + +[Sources] + PeiScPolicyLib.c + PeiScPreMemPolicyLib.c + PeiScPolicyLibrary.h + ScPrintPolicy.c + ScPrintPolicyPreMem.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + DebugLib + IoLib + PeiServicesLib + BaseMemoryLib + MemoryAllocationLib + ScPlatformLib + ConfigBlockLib + PcdLib + +[Guids] + gLpcPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gScGeneralConfigGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gHpetConfigGuid + gSmbusConfigGuid + gUsbConfigGuid + gIoApicConfigGuid + gHdAudioConfigGuid + gGmmConfigGuid + gPmConfigGuid + gLockDownConfigGuid + gSerialIrqConfigGuid + gLpssConfigGuid + gScsConfigGuid + gVtdConfigGuid + gIshConfigGuid + gFlashProtectionConfigGuid + gDciConfigGuid + gP2sbConfigGuid + gInterruptConfigGuid + +[Ppis] + gScPolicyPpiGuid ## PRODUCES + gScPreMemPolicyPpiGuid ## PRODUCES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress + gEfiBxtTokenSpaceGuid.PcdP2SBBaseAddress + gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLibrary.h new file mode 100644 index 0000000000..2802528e28 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPolicyLibrary.h @@ -0,0 +1,51 @@ +/** @file + Header file for the PeiScPolicy library. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_SC_POLICY_LIB_H_ +#define _PEI_SC_POLICY_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SC_SMBUS_BASE_ADDRESS 0xEFA0 +#define SC_HPET_BASE_ADDRESS 0xFED00000 +#define SW_SMI_BIOS_LOCK 0xA9 + +typedef +VOID +(*LOAD_DEFAULT_FUNCTION) ( + IN VOID *ConfigBlockPointer + ); + +typedef struct { + EFI_GUID *Guid; + UINT16 Size; + UINT8 Revision; + LOAD_DEFAULT_FUNCTION LoadDefault; +} IP_BLOCK_ENTRY; + +#endif // _PEI_SC_POLICY_LIB_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPreMemPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPreMemPolicyLib.c new file mode 100644 index 0000000000..8566a4f70f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/PeiScPreMemPolicyLib.c @@ -0,0 +1,201 @@ +/** @file + This file is PeiScPreMemPolicy library. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiScPolicyLibrary.h" + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadLpcPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_LPC_PREMEM_CONFIG *LpcPreMemConfig; + + LpcPreMemConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "LpcPreMemConfig->Header.Guid = %g\n", &LpcPreMemConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "LpcPreMemConfig->Header.Size = 0x%x\n", LpcPreMemConfig->Header.Size)); + + LpcPreMemConfig->EnhancePort8xhDecoding = TRUE; +} + + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block + +**/ +VOID +LoadPciePreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SC_PCIE_PREMEM_CONFIG *PciePreMemConfig; + PciePreMemConfig = ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PciePreMemConfig->Header.Guid = %g\n", &PciePreMemConfig->Header.Guid)); + DEBUG ((DEBUG_INFO, "PciePreMemConfig->Header.Size = 0x%x\n", PciePreMemConfig->Header.Size)); +} + +static IP_BLOCK_ENTRY mScIpBlocks [] = { + {&gPcieRpPreMemConfigGuid, sizeof (SC_PCIE_PREMEM_CONFIG), PCIE_RP_PREMEM_CONFIG_REVISION, LoadPciePreMemConfigDefault}, + {&gLpcPreMemConfigGuid, sizeof (SC_LPC_PREMEM_CONFIG), LPC_PREMEM_CONFIG_REVISION, LoadLpcPreMemConfigDefault}, +}; + +/** + Get SC PREMEM config block table total size. + + @retval Size of SC PREMEM config block table + +**/ +UINT32 +EFIAPI +ScGetPreMemConfigBlockTotalSize ( + VOID + ) +{ + UINT32 TotalBlockCount; + UINT32 TotalBlockSize; + UINT32 ConfigBlockHdrSize; + UINT32 BlockCount; + + TotalBlockCount = sizeof (mScIpBlocks) / sizeof (IP_BLOCK_ENTRY); + TotalBlockSize = 0; + for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) { + TotalBlockSize += (UINT32) mScIpBlocks[BlockCount].Size; + DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize)); + } + ConfigBlockHdrSize = GetSizeOfConfigBlockTableHeaders ((UINT16) TotalBlockCount); + + // + // Because CreateConfigBlockTable has the padding for each config block, + // we need extra size, which is TotalBlockCount * 3, to create the table + // + return ConfigBlockHdrSize + TotalBlockSize + (TotalBlockCount * 3); +} + + +/** + CreatePreMemConfigBlocks generates the config blocks of SC Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] ScPreMemPolicyPpi The pointer to get SC PREMEM Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScCreatePreMemConfigBlocks ( + OUT SC_PREMEM_POLICY_PPI **ScPreMemPolicyPpi + ) +{ + UINT16 TotalBlockCount; + UINT16 BlockCount; + VOID *ConfigBlockPointer; + CONFIG_BLOCK ConfigBlockBuf; + EFI_STATUS Status; + SC_PREMEM_POLICY_PPI *InitPolicy; + UINT32 RequiredSize; + + DEBUG ((DEBUG_INFO, "SC CreateConfigBlocks\n")); + + InitPolicy = NULL; + TotalBlockCount = sizeof (mScIpBlocks) / sizeof (IP_BLOCK_ENTRY); + DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount)); + + RequiredSize = ScGetPreMemConfigBlockTotalSize (); + + Status = CreateConfigBlockTable ((VOID *) &InitPolicy, TotalBlockCount, RequiredSize); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Policy Revision + // + InitPolicy->TableHeader.Header.Revision = SC_PREMEM_POLICY_REVISION; + // + // Initialize ConfigBlockPointer to NULL + // + ConfigBlockPointer = NULL; + // + // Loop to identify each config block from mScIpBlocks[] Table and add each of them + // + for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) { + CopyMem (&(ConfigBlockBuf.Header.Guid), mScIpBlocks[BlockCount].Guid, sizeof (EFI_GUID)); + ConfigBlockBuf.Header.Size = mScIpBlocks[BlockCount].Size; + ConfigBlockBuf.Header.Revision = mScIpBlocks[BlockCount].Revision; + ConfigBlockPointer = (VOID *) &ConfigBlockBuf; + Status = AddConfigBlock ((VOID *) InitPolicy, (VOID *) &ConfigBlockPointer); + ASSERT_EFI_ERROR (Status); + mScIpBlocks[BlockCount].LoadDefault (ConfigBlockPointer); + } + // + // Assignment for returning Policy config block base address + // + *ScPreMemPolicyPpi = InitPolicy; + return EFI_SUCCESS; +} + + +/** + ScInstallPreMemPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] ScPreMemPolicyPpi The pointer to SC PREMEM Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer + +**/ +EFI_STATUS +EFIAPI +ScInstallPreMemPolicyPpi ( + IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *ScPreMemPolicyPpiDesc; + + ScPreMemPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (ScPreMemPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + ScPreMemPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + ScPreMemPolicyPpiDesc->Guid = &gScPreMemPolicyPpiGuid; + ScPreMemPolicyPpiDesc->Ppi = ScPreMemPolicyPpi; + + // + // Print whole SC_PREMEM_POLICY_PPI and serial out. + // + ScPreMemPrintPolicyPpi (ScPreMemPolicyPpi); + + // + // Install PREMEM Policy PPI + // + Status = PeiServicesInstallPpi (ScPreMemPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicy.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicy.c new file mode 100644 index 0000000000..7ccf1d2495 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicy.c @@ -0,0 +1,699 @@ +/** @file + Print whole SC_POLICY_PPI and serial out. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiScPolicyLibrary.h" + +/** + Print SC_INTERRUPT_CONFIG and serial out + + @param[in] InterruptConfig Pointer to Interrupt Configuration structure + +**/ +VOID +PrintInterruptConfig ( + IN CONST SC_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINTN Index; + // + // Print interrupt information + // + DEBUG ((DEBUG_INFO, "------------------ Interrupt Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Interrupt assignment:\n")); + DEBUG ((DEBUG_INFO, " Dxx:Fx INTx IRQ\n")); + for (Index = 0; Index < InterruptConfig->NumOfDevIntConfig; Index++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DevIntConfig[Index].Device, + InterruptConfig->DevIntConfig[Index].Function, + InterruptConfig->DevIntConfig[Index].IntX, + InterruptConfig->DevIntConfig[Index].Irq)); + } + DEBUG ((DEBUG_INFO, " Direct Irq Table:\n")); + for (Index = 0; Index < InterruptConfig->NumOfDirectIrqTable; Index++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DirectIrqTable[Index].Port, + InterruptConfig->DirectIrqTable[Index].PciCfgOffset, + InterruptConfig->DirectIrqTable[Index].PciIrqNumber, + InterruptConfig->DirectIrqTable[Index].IrqPin)); + } + + DEBUG ((DEBUG_INFO, " Legacy Interrupt Routing:\n")); + for (Index = 0; Index < SC_MAX_PXRC_CONFIG; Index++) { + DEBUG ((DEBUG_INFO, "PxRcRouting[%x] = %x \n", Index ,InterruptConfig->PxRcRouting[Index])); + } +} + + +/** + Print SC_USB_CONFIG and serial out. + + @param[in] UsbConfig Pointer to a SC_USB_CONFIG that provides the platform setting + +**/ + +VOID +PrintUsbConfig ( + IN CONST SC_USB_CONFIG *UsbConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ USB Config ------------------\n")); + DEBUG ((DEBUG_INFO, " DisableComplianceMode= %x\n", UsbConfig->DisableComplianceMode)); + DEBUG ((DEBUG_INFO, " UsbPerPortCtl = %x\n", UsbConfig->UsbPerPortCtl)); + DEBUG ((DEBUG_INFO, " Mode = %x\n", UsbConfig->Usb30Settings.Mode)); + + for (Index = 0; Index < GetScXhciMaxUsb2PortNum (); Index++) { + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled= %x\n", Index, UsbConfig->PortUsb20[Index].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin= OC%x\n", Index, UsbConfig->PortUsb20[Index].OverCurrentPin)); + } + for (Index = 0; Index < GetScXhciMaxUsb3PortNum (); Index++) { + DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled= %x\n", Index, UsbConfig->PortUsb30[Index].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin= OC%x\n", Index, UsbConfig->PortUsb30[Index].OverCurrentPin)); + } + DEBUG ((DEBUG_INFO, " xDCI Enable = %x\n", UsbConfig->XdciConfig.Enable)); + + for (Index = 0; Index < XHCI_MAX_HSIC_PORTS; Index++) { + DEBUG ((DEBUG_INFO, " HsicPort[%d].Enable = %x\n", Index, UsbConfig->HsicConfig.HsicPort[Index].Enable)); + } + for (Index = 0; Index < XHCI_MAX_SSIC_PORTS; Index++) { + DEBUG ((DEBUG_INFO, " SsicPort[%d].Enable = %x\n", Index, UsbConfig->SsicConfig.SsicPort[Index].Enable)); + DEBUG ((DEBUG_INFO, " SsicPort[%d].Rate = %x\n", Index, UsbConfig->SsicConfig.SsicPort[Index].Rate)); + } + DEBUG ((DEBUG_INFO, " SSIC DlanePwrGating = %x\n", UsbConfig->SsicConfig.DlanePwrGating)); + + return; +} + + +/** + Print SC_PCIE_CONFIG and serial out. + + @param[in] PcieConfig Pointer to a SC_PCIE_CONFIG that provides the platform setting + +**/ +VOID +PrintPcieConfig ( + IN CONST SC_PCIE_CONFIG *PcieConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCIe Config ------------------\n")); + for (i = 0; i < GetScMaxPciePortNum (); i++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] Enabled = %x\n", i, PcieConfig->RootPort[i].Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Hide = %x\n", i, PcieConfig->RootPort[i].Hide)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotImplemented = %x\n", i, PcieConfig->RootPort[i].SlotImplemented)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug = %x\n", i, PcieConfig->RootPort[i].HotPlug)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci = %x\n", i, PcieConfig->RootPort[i].PmSci)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync = %x\n", i, PcieConfig->RootPort[i].ExtSync)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqSupported = %x\n", i, PcieConfig->RootPort[i].ClkReqSupported)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqNumber = %x\n", i, PcieConfig->RootPort[i].ClkReqNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport = %x\n", i, PcieConfig->RootPort[i].UnsupportedRequestReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport = %x\n", i, PcieConfig->RootPort[i].FatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport = %x\n", i, PcieConfig->RootPort[i].NoFatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport = %x\n", i, PcieConfig->RootPort[i].CorrectableErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmeInterrupt = %x\n", i, PcieConfig->RootPort[i].PmeInterrupt)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError = %x\n", i, PcieConfig->RootPort[i].SystemErrorOnFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError = %x\n", i, PcieConfig->RootPort[i].SystemErrorOnNonFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError = %x\n", i, PcieConfig->RootPort[i].SystemErrorOnCorrectableError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled = %x\n", i, PcieConfig->RootPort[i].AcsEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting = %x\n", i, PcieConfig->RootPort[i].AdvancedErrorReporting)); + DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing = %x\n", i, PcieConfig->RootPort[i].TransmitterHalfSwing)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed = %x\n", i, PcieConfig->RootPort[i].PcieSpeed)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber = %x\n", i, PcieConfig->RootPort[i].PhysicalSlotNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout = %x\n", i, PcieConfig->RootPort[i].CompletionTimeout)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SelectableDeemphasis = %x\n", i, PcieConfig->RootPort[i].SelectableDeemphasis)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm = %x\n", i, PcieConfig->RootPort[i].Aspm)); + DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates = %x\n", i, PcieConfig->RootPort[i].L1Substates)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable = %x\n", i, PcieConfig->RootPort[i].LtrEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock = %x\n", i, PcieConfig->RootPort[i].LtrConfigLock)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency = %x\n", i, PcieConfig->RootPort[i].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency = %x\n", i, PcieConfig->RootPort[i].LtrMaxNoSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode = %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier = %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue = %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode = %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier = %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue = %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale = %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitScale)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue = %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitValue)); + } + DEBUG ((DEBUG_INFO, " EnablePort8xhDecode = %x\n", PcieConfig->EnablePort8xhDecode)); + DEBUG ((DEBUG_INFO, " ScPciePort8xhDecodePortIndex = %x\n", PcieConfig->ScPciePort8xhDecodePortIndex)); + DEBUG ((DEBUG_INFO, " DisableRootPortClockGating = %x\n", PcieConfig->DisableRootPortClockGating)); + DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite = %x\n", PcieConfig->EnablePeerMemoryWrite)); + DEBUG ((DEBUG_INFO, " AspmSwSmiNumber = %x\n", PcieConfig->AspmSwSmiNumber)); + DEBUG ((DEBUG_INFO, " ComplianceTestMode = %x\n", PcieConfig->ComplianceTestMode)); +} + + +/** + Print SC_SATA_CONFIG and serial out. + + @param[in] SataConfig Pointer to a SC_SATA_CONFIG that provides the platform setting + +**/ +VOID +PrintSataConfig ( + IN CONST SC_SATA_CONFIG *SataConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ SATA Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable = %x\n", SataConfig->Enable)); + DEBUG ((DEBUG_INFO, " SataMode = %x\n", SataConfig->SataMode)); + + for (i = 0; i < SC_MAX_SATA_PORTS; i++) { + DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled = %x\n", i, SataConfig->PortSettings[i].Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug = %x\n", i, SataConfig->PortSettings[i].HotPlug)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw = %x\n", i, SataConfig->PortSettings[i].InterlockSw)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] External = %x\n", i, SataConfig->PortSettings[i].External)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp = %x\n", i, SataConfig->PortSettings[i].SpinUp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive = %x\n", i, SataConfig->PortSettings[i].SolidStateDrive)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp = %x\n", i, SataConfig->PortSettings[i].DevSlp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig = %x\n", i, SataConfig->PortSettings[i].EnableDitoConfig)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal = %x\n", i, SataConfig->PortSettings[i].DmVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal = %x\n", i, SataConfig->PortSettings[i].DitoVal)); + } + DEBUG ((DEBUG_INFO, " SpeedSupport = %x\n", SataConfig->SpeedLimit)); + DEBUG ((DEBUG_INFO, " eSATASpeedLimit = %x\n", SataConfig->eSATASpeedLimit)); + DEBUG ((DEBUG_INFO, " TestMode = %x\n", SataConfig->TestMode)); + DEBUG ((DEBUG_INFO, " SalpSupport = %x\n", SataConfig->SalpSupport)); + DEBUG ((DEBUG_INFO, " PwrOptEnable = %x\n", SataConfig->PwrOptEnable)); +} + + +/** + Print SC_IOAPIC_CONFIG and serial out. + + @param[in] IoApicConfig Pointer to a SC_IOAPIC_CONFIG that provides the platform setting + +**/ +VOID +PrintIoApicConfig ( + IN CONST SC_IOAPIC_CONFIG *IoApicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ IOAPIC Config ------------------\n")); + DEBUG ((DEBUG_INFO, " BdfValid = %x\n", IoApicConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber = %x\n", IoApicConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber = %x\n", IoApicConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber = %x\n", IoApicConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " IoApicId = %x\n", IoApicConfig->IoApicId)); + DEBUG ((DEBUG_INFO, " ApicRangeSelect = %x\n", IoApicConfig->ApicRangeSelect)); + DEBUG ((DEBUG_INFO, " IoApicEntry24_119 = %x\n", IoApicConfig->IoApicEntry24_119)); +} + + +/** + Print SC_HPET_CONFIG and serial out. + + @param[in] HpetConfig Pointer to a SC_HPET_CONFIG that provides the platform setting + +**/ +VOID +PrintHpetConfig ( + IN CONST SC_HPET_CONFIG *HpetConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ HPET Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable = %x\n", HpetConfig->Enable)); + DEBUG ((DEBUG_INFO, " BdfValid = %x\n", HpetConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber = %x\n", HpetConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber = %x\n", HpetConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber = %x\n", HpetConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " Base = %x\n", HpetConfig->Base)); +} + + +/** + Print PCH_LOCK_DOWN_CONFIG and serial out. + + @param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that provides the platform setting + +**/ +VOID +PrintLockDownConfig ( + IN CONST SC_LOCK_DOWN_CONFIG *LockDownConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ Lock Down Config ------------------\n")); + DEBUG ((DEBUG_INFO, " GlobalSmi = %x\n", LockDownConfig->GlobalSmi)); + DEBUG ((DEBUG_INFO, " BiosInterface = %x\n", LockDownConfig->BiosInterface)); + DEBUG ((DEBUG_INFO, " RtcLock = %x\n", LockDownConfig->RtcLock)); + DEBUG ((DEBUG_INFO, " BiosLock = %x\n", LockDownConfig->BiosLock)); + DEBUG ((DEBUG_INFO, " SpiEiss = %x\n", LockDownConfig->SpiEiss)); + DEBUG ((DEBUG_INFO, " BiosLockSwSmiNumbe = %x\n", LockDownConfig->BiosLockSwSmiNumber)); + DEBUG ((DEBUG_INFO, " TcoTimerLock = %x\n", LockDownConfig->TcoLock)); +} + +/** + Print SC_SMBUS_CONFIG and serial out. + + @param[in] SmbusConfig Pointer to a SC_SMBUS_CONFIG that provides the platform setting + +**/ +VOID +PrintSmbusConfig ( + IN CONST SC_SMBUS_CONFIG *SmbusConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ SMBus Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable = %x\n", SmbusConfig->Enable)); + DEBUG ((DEBUG_INFO, " ArpEnable = %x\n", SmbusConfig->ArpEnable)); + DEBUG ((DEBUG_INFO, " DynamicPowerGating = %x\n", SmbusConfig->DynamicPowerGating)); + DEBUG ((DEBUG_INFO, " SmbusIoBase = %x\n", SmbusConfig->SmbusIoBase)); + DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses = %x\n", SmbusConfig->NumRsvdSmbusAddresses)); + DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable = {")); + for (i = 0; i < SmbusConfig->NumRsvdSmbusAddresses; ++i) { + DEBUG ((DEBUG_INFO, " %02xh", SmbusConfig->RsvdSmbusAddressTable[i])); + } + DEBUG ((DEBUG_INFO, " }\n")); +} + + +/** + Print SC_HDAUDIO_CONFIG and serial out. + + @param[in] HdaConfig Pointer to a SC_HDAUDIO_CONFIG that provides the platform setting + +**/ +VOID +PrintHdAudioConfig ( + IN CONST SC_HDAUDIO_CONFIG *HdaConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ HD-Audio Config ------------------\n")); + DEBUG ((DEBUG_INFO, " HDA Enable = %x\n", HdaConfig->Enable)); + DEBUG ((DEBUG_INFO, " DSP Enable = %x\n", HdaConfig->DspEnable)); + DEBUG ((DEBUG_INFO, " Pme = %x\n", HdaConfig->Pme)); + DEBUG ((DEBUG_INFO, " I/O Buffer Ownership = %x\n", HdaConfig->IoBufferOwnership)); + DEBUG ((DEBUG_INFO, " I/O Buffer Voltage = %x\n", HdaConfig->IoBufferVoltage)); + DEBUG ((DEBUG_INFO, " VC Type = %x\n", HdaConfig->VcType)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask = %x\n", HdaConfig->DspFeatureMask)); + DEBUG ((DEBUG_INFO, " DSP PP Module Mask = %x\n", HdaConfig->DspPpModuleMask)); + DEBUG ((DEBUG_INFO, " ResetWaitTimer = %x\n", HdaConfig->ResetWaitTimer)); + DEBUG ((DEBUG_INFO, " VcType = %x\n", HdaConfig->VcType)); + DEBUG ((DEBUG_INFO, " HD-A Link Frequency = %x\n", HdaConfig->HdAudioLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link Frequency = %x\n", HdaConfig->IDispLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link T-Mode = %x\n", HdaConfig->IDispLinkTmode)); + DEBUG ((DEBUG_INFO, " DSP Endpoint DMIC = %x\n", HdaConfig->DspEndpointDmic)); + DEBUG ((DEBUG_INFO, " DSP Endpoint I2S SKP = %x\n", HdaConfig->DspEndpointI2sSkp)); + DEBUG ((DEBUG_INFO, " DSP Endpoint I2S HP = %x\n", HdaConfig->DspEndpointI2sHp)); + DEBUG ((DEBUG_INFO, " DSP Endpoint BT = %x\n", HdaConfig->DspEndpointBluetooth)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask = %x\n", HdaConfig->DspFeatureMask)); + DEBUG ((DEBUG_INFO, " DSP PP Module Mask = %x\n", HdaConfig->DspPpModuleMask)); + DEBUG ((DEBUG_INFO, " CSME Memory Transfers = %x\n", HdaConfig->Mmt)); + DEBUG ((DEBUG_INFO, " Host Memory Transfers = %x\n", HdaConfig->Hmt)); + DEBUG ((DEBUG_INFO, " BIOS Configuration Lock Down = %x\n", HdaConfig->BiosCfgLockDown)); + DEBUG ((DEBUG_INFO, " Power Gating = %x\n", HdaConfig->PwrGate)); + DEBUG ((DEBUG_INFO, " Clock Gating = %x\n", HdaConfig->ClkGate)); +} + + +/** + Print SC_PM_CONFIG and serial out. + + @param[in] PmConfig Pointer to a SC_PM_CONFIG that provides the platform setting + +**/ +VOID +PrintPmConfig ( + IN CONST SC_PM_CONFIG *PmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PM Config ------------------\n")); + DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis = %x\n", PmConfig->WakeConfig.PmeB0S5Dis)); + DEBUG ((DEBUG_INFO, " PciClockRun = %x\n", PmConfig->PciClockRun)); + DEBUG ((DEBUG_INFO, " Timer8254ClkGateEn = %x\n", PmConfig->Timer8254ClkGateEn)); + DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod = %x\n", PmConfig->PwrBtnOverridePeriod)); + DEBUG ((DEBUG_INFO, " DisableNativePowerButton = %x\n", PmConfig->DisableNativePowerButton)); + DEBUG ((DEBUG_INFO, " PowerButterDebounceMode = %x\n", PmConfig->PowerButterDebounceMode)); +} + +/** + Print SC_LPC_SIRQ_CONFIG and serial out. + + @param[in] SerialIrqConfig Pointer to a SC_LPC_SIRQ_CONFIG that provides the platform setting + +**/ +VOID +PrintSerialIrqConfig ( + IN CONST SC_LPC_SIRQ_CONFIG *SerialIrqConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ Serial IRQ Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SirqEnable = %x\n", SerialIrqConfig->SirqEnable)); + DEBUG ((DEBUG_INFO, " SirqMode = %x\n", SerialIrqConfig->SirqMode)); + DEBUG ((DEBUG_INFO, " StartFramePulse = %x\n", SerialIrqConfig->StartFramePulse)); +} + + +/** + Print SC_GMM_CONFIG and serial out. + + @param[in] GmmConfig Pointer to a SC_GMM_CONFIG that provides the platform setting + +**/ +VOID +PrintGmmConfig ( + IN CONST SC_GMM_CONFIG *GmmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ GMM Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable = %x\n", GmmConfig->Enable)); + DEBUG ((DEBUG_INFO, " ClkGatingPgcbClkTrunk = %x\n", GmmConfig->ClkGatingPgcbClkTrunk)); + DEBUG ((DEBUG_INFO, " ClkGatingSb = %x\n", GmmConfig->ClkGatingSb)); + DEBUG ((DEBUG_INFO, " ClkGatingSbClkTrunk = %x\n", GmmConfig->ClkGatingSbClkTrunk)); + DEBUG ((DEBUG_INFO, " ClkGatingSbClkPartition = %x\n", GmmConfig->ClkGatingSbClkPartition)); + DEBUG ((DEBUG_INFO, " ClkGatingCore = %x\n", GmmConfig->ClkGatingCore)); + DEBUG ((DEBUG_INFO, " ClkGatingDma = %x\n", GmmConfig->ClkGatingDma)); + DEBUG ((DEBUG_INFO, " ClkGatingRegAccess = %x\n", GmmConfig->ClkGatingRegAccess)); + DEBUG ((DEBUG_INFO, " ClkGatingHost = %x\n", GmmConfig->ClkGatingHost)); + DEBUG ((DEBUG_INFO, " ClkGatingPartition = %x\n", GmmConfig->ClkGatingPartition)); + DEBUG ((DEBUG_INFO, " ClkGatingTrunk = %x\n", GmmConfig->ClkGatingTrunk)); + DEBUG ((DEBUG_INFO, " SvPwrGatingHwAutoEnable = %x\n", GmmConfig->SvPwrGatingHwAutoEnable)); + DEBUG ((DEBUG_INFO, " SvPwrGatingD3HotEnable = %x\n", GmmConfig->SvPwrGatingD3HotEnable)); + DEBUG ((DEBUG_INFO, " SvPwrGatingI3Enable = %x\n", GmmConfig->SvPwrGatingI3Enable)); + DEBUG ((DEBUG_INFO, " SvPwrGatingPmcReqEnable = %x\n", GmmConfig->SvPwrGatingPmcReqEnable)); + + return; +} + + +/** + Print SC_LPSS_CONFIG and serial out. + + @param[in] LpssConfig Pointer to a SC_LPSS_CONFIG that provides the platform setting + +**/ + +VOID +PrintLpssConfig ( + IN CONST SC_LPSS_CONFIG *LpssConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ LPSS Config ------------------\n")); + DEBUG ((DEBUG_INFO, " I2c0Enable = %x\n", LpssConfig->I2c0Enable)); + DEBUG ((DEBUG_INFO, " I2c1Enable = %x\n", LpssConfig->I2c1Enable)); + DEBUG ((DEBUG_INFO, " I2c2Enable = %x\n", LpssConfig->I2c2Enable)); + DEBUG ((DEBUG_INFO, " I2c3Enable = %x\n", LpssConfig->I2c3Enable)); + DEBUG ((DEBUG_INFO, " I2c4Enable = %x\n", LpssConfig->I2c4Enable)); + DEBUG ((DEBUG_INFO, " I2c5Enable = %x\n", LpssConfig->I2c5Enable)); + DEBUG ((DEBUG_INFO, " I2c6Enable = %x\n", LpssConfig->I2c6Enable)); + DEBUG ((DEBUG_INFO, " I2c7Enable = %x\n", LpssConfig->I2c7Enable)); + DEBUG ((DEBUG_INFO, " Hsuart0Enable = %x\n", LpssConfig->Hsuart0Enable)); + DEBUG ((DEBUG_INFO, " Hsuart1Enable = %x\n", LpssConfig->Hsuart1Enable)); + DEBUG ((DEBUG_INFO, " Hsuart2Enable = %x\n", LpssConfig->Hsuart2Enable)); + DEBUG ((DEBUG_INFO, " Hsuart3Enable = %x\n", LpssConfig->Hsuart3Enable)); + DEBUG ((DEBUG_INFO, " Spi0Enable = %x\n", LpssConfig->Spi0Enable)); + DEBUG ((DEBUG_INFO, " Spi1Enable = %x\n", LpssConfig->Spi1Enable)); + DEBUG ((DEBUG_INFO, " Spi2Enable = %x\n", LpssConfig->Spi2Enable)); + DEBUG ((DEBUG_INFO, " Uart2KernelDebugBaseAddress = %x\n", LpssConfig->Uart2KernelDebugBaseAddress)); + + for (Index = 0; Index < LPSS_I2C_DEVICE_NUM; Index++) { + DEBUG ((DEBUG_INFO, " I2cClkGateCfg[%d] = %x\n", Index, LpssConfig->I2cClkGateCfg[Index])); + } + + for (Index = 0; Index < LPSS_HSUART_DEVICE_NUM; Index++) { + DEBUG ((DEBUG_INFO, " HsuartClkGateCfg[%d] = %x\n", Index, LpssConfig->HsuartClkGateCfg[Index])); + } + + for (Index = 0; Index < LPSS_SPI_DEVICE_NUM; Index++) { + DEBUG ((DEBUG_INFO, " SpiClkGateCfg[%d] = %x\n", Index, LpssConfig->SpiClkGateCfg[Index])); + } + + DEBUG ((DEBUG_INFO, " S0ixEnable = %x\n", LpssConfig->S0ixEnable)); + DEBUG ((DEBUG_INFO, " OsDbgEnable = %x\n", LpssConfig->OsDbgEnable)); +} + + +/** + Print SC_SCS_CONFIG and serial out. + + @param[in] ScsConfig Pointer to a SC_SCS_CONFIG that provides the platform setting + +**/ +VOID +PrintScsConfig ( + IN CONST SC_SCS_CONFIG *ScsConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ SCS Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SdcardEnable = %x\n", ScsConfig->SdcardEnable)); + DEBUG ((DEBUG_INFO, " EmmcEnable = %x\n", ScsConfig->EmmcEnable)); + DEBUG ((DEBUG_INFO, " UfsEnable = %x\n", ScsConfig->UfsEnable)); + DEBUG ((DEBUG_INFO, " SdioEnable = %x\n", ScsConfig->SdioEnable)); + DEBUG ((DEBUG_INFO, " EmmcHostMaxSpeed = %x\n", ScsConfig->EmmcHostMaxSpeed)); + DEBUG ((DEBUG_INFO, " GppLock = %x\n", ScsConfig->GppLock)); + DEBUG ((DEBUG_INFO, " SccEmmcTraceLength = %x\n", ScsConfig->SccEmmcTraceLength)); + DEBUG ((DEBUG_INFO, " SdioTxCmdCntl = %x\n", ScsConfig->SdioRegDllConfig.TxCmdCntl)); + DEBUG ((DEBUG_INFO, " SdioTxDataCntl1 = %x\n", ScsConfig->SdioRegDllConfig.TxDataCntl1)); + DEBUG ((DEBUG_INFO, " SdioTxDataCntl2 = %x\n", ScsConfig->SdioRegDllConfig.TxDataCntl2)); + DEBUG ((DEBUG_INFO, " SdioRxCmdDataCntl1 = %x\n", ScsConfig->SdioRegDllConfig.RxCmdDataCntl1)); + DEBUG ((DEBUG_INFO, " SdioRxStrobeCntl = %x\n", ScsConfig->SdioRegDllConfig.RxCmdDataCntl2)); + DEBUG ((DEBUG_INFO, " SdcardTxCmdCntl = %x\n", ScsConfig->SdcardRegDllConfig.TxCmdCntl)); + DEBUG ((DEBUG_INFO, " SdcardTxDataCntl1 = %x\n", ScsConfig->SdcardRegDllConfig.TxDataCntl1)); + DEBUG ((DEBUG_INFO, " SdcardTxDataCntl2 = %x\n", ScsConfig->SdcardRegDllConfig.TxDataCntl2)); + DEBUG ((DEBUG_INFO, " SdcardRxCmdDataCntl1 = %x\n", ScsConfig->SdcardRegDllConfig.RxCmdDataCntl1)); + DEBUG ((DEBUG_INFO, " SdcardRxStrobeCntl = %x\n", ScsConfig->SdcardRegDllConfig.RxStrobeCntl)); + DEBUG ((DEBUG_INFO, " SdcardRxCmdDataCntl1 = %x\n", ScsConfig->SdcardRegDllConfig.RxCmdDataCntl2)); + DEBUG ((DEBUG_INFO, " EmmcTxCmdCntl = %x\n", ScsConfig->EmmcRegDllConfig.TxCmdCntl)); + DEBUG ((DEBUG_INFO, " EmmcTxDataCntl1 = %x\n", ScsConfig->EmmcRegDllConfig.TxDataCntl1)); + DEBUG ((DEBUG_INFO, " EmmcTxDataCntl2 = %x\n", ScsConfig->EmmcRegDllConfig.TxDataCntl2)); + DEBUG ((DEBUG_INFO, " EmmcRxCmdDataCntl1 = %x\n", ScsConfig->EmmcRegDllConfig.RxCmdDataCntl1)); + DEBUG ((DEBUG_INFO, " EmmcRxStrobeCntl = %x\n", ScsConfig->EmmcRegDllConfig.RxStrobeCntl)); + DEBUG ((DEBUG_INFO, " EmmcRxCmdDataCntl2 = %x\n", ScsConfig->EmmcRegDllConfig.RxCmdDataCntl2)); + DEBUG ((DEBUG_INFO, " EmmcMasterSwCntl = %x\n", ScsConfig->EmmcRegDllConfig.MasterSwCntl)); +} + + +/** + Print SC_VTD_CONFIG and serial out. + + @param[in] VtdConfig Pointer to a SC_VTD_CONFIG that provides the platform setting + +**/ + +VOID +PrintVtdConfig ( + IN CONST SC_VTD_CONFIG *VtdConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ Vtd Config ------------------\n")); + DEBUG ((DEBUG_INFO, " VtdEnable = %x\n", VtdConfig->VtdEnable)); + + return; +} + + +/** + Print SC_GENERAL_CONFIG and serial out. + + @param[in] ScConfig Pointer to a SC_GENERAL_CONFIG that provides the platform setting +**/ +VOID +PrintGeneralConfig ( + IN CONST SC_GENERAL_CONFIG *ScGeneralConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ General Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SubSystemVendorId = %x\n", ScGeneralConfig->SubSystemVendorId)); + DEBUG ((DEBUG_INFO, " SubSystemId = %x\n", ScGeneralConfig->SubSystemId)); + DEBUG ((DEBUG_INFO, " AcpiBase = %x\n", ScGeneralConfig->AcpiBase)); + DEBUG ((DEBUG_INFO, " PmcBase = %x\n", ScGeneralConfig->PmcBase)); + DEBUG ((DEBUG_INFO, " P2sbBase = %x\n", ScGeneralConfig->P2sbBase)); + DEBUG ((DEBUG_INFO, " Crid = %x\n", ScGeneralConfig->Crid)); + DEBUG ((DEBUG_INFO, " ResetSelect = %x\n", ScGeneralConfig->ResetSelect)); +} + + +/** + Print SC_ISH_CONFIG and serial out. + + @param[in] IshConfig Pointer to a SC_ISH_CONFIG that provides the platform setting + +**/ +VOID +PrintIshConfig ( + IN CONST SC_ISH_CONFIG *IshConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ ISH Config ------------------\n")); + DEBUG ((DEBUG_INFO, "Enable = %x\n", IshConfig->Enable)); +} + + +/** + Print SC_FLASH_PROTECTION_CONFIG and serial out. + + @param[in] FlashProtectConfig Pointer to a SC_FLASH_PROTECTION_CONFIG that provides the platform setting + +**/ +VOID +PrintFlashProtectionConfig ( + IN CONST SC_FLASH_PROTECTION_CONFIG *FlashProtectConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ SC Flash Protection Config ------------------\n")); + for (Index = 0; Index < SC_FLASH_PROTECTED_RANGES; ++Index) { + DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].WriteProtectionEnable)); + DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ReadProtectionEnable)); + DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeLimit)); + DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeBase)); + } +} + + +/** + Print SC_DCI_CONFIG and serial out. + + @param[in] IshConfig Pointer to a SC_DCI_CONFIG that provides the platform setting + +**/ +VOID +PrintDciConfig ( + IN CONST SC_DCI_CONFIG *DciConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ DCI Config ------------------\n")); + DEBUG ((DEBUG_INFO, "DciEn = %x\n", DciConfig->DciEn)); + DEBUG ((DEBUG_INFO, "DciAutoDetect = %x\n", DciConfig->DciAutoDetect)); +} + + +/** + Print SC_P2SB_CONFIG and serial out. + + @param[in] IshConfig Pointer to a SC_DCI_CONFIG that provides the platform setting + +**/ +VOID +PrintP2sbConfig ( + IN CONST SC_P2SB_CONFIG *P2sbConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ P2SB Config ------------------\n")); + DEBUG ((DEBUG_INFO, " P2sbUnhide = %x\n", P2sbConfig->P2sbUnhide)); +} + + +/** + Print whole SC config blocks and serial out. + + @param[in] ScPolicyPpi The RC Policy PPI instance + +**/ +VOID +ScPrintPolicyPpi ( + IN SC_POLICY_PPI *ScPolicyPpi + ) +{ + EFI_STATUS Status; + SC_GENERAL_CONFIG *ScGeneralConfig; + SC_SATA_CONFIG *SataConfig; + SC_PCIE_CONFIG *PcieRpConfig; + SC_SMBUS_CONFIG *SmbusConfig; + SC_HPET_CONFIG *HpetConfig; + SC_IOAPIC_CONFIG *IoApicConfig; + SC_USB_CONFIG *UsbConfig; + SC_HDAUDIO_CONFIG *HdaConfig; + SC_GMM_CONFIG *GmmConfig; + SC_PM_CONFIG *PmConfig; + SC_LOCK_DOWN_CONFIG *LockDownConfig; + SC_LPC_SIRQ_CONFIG *SerialIrqConfig; + SC_LPSS_CONFIG *LpssConfig; + SC_SCS_CONFIG *ScsConfig; + SC_VTD_CONFIG *VtdConfig; + SC_ISH_CONFIG *IshConfig; + SC_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + SC_DCI_CONFIG *DciConfig; + SC_P2SB_CONFIG *P2sbConfig; + SC_INTERRUPT_CONFIG *InterruptConfig; + + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gScGeneralConfigGuid, (VOID *) &ScGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gSataConfigGuid, (VOID *) &SataConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gHpetConfigGuid, (VOID *) &HpetConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gSmbusConfigGuid, (VOID *) &SmbusConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gIoApicConfigGuid, (VOID *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gUsbConfigGuid, (VOID *) &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gHdAudioConfigGuid, (VOID *) &HdaConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gGmmConfigGuid, (VOID *) &GmmConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gPmConfigGuid, (VOID *) &PmConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gLockDownConfigGuid, (VOID *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gLpssConfigGuid, (VOID *) &LpssConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gScsConfigGuid, (VOID *) &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gVtdConfigGuid, (VOID *) &VtdConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gIshConfigGuid, (VOID *) &IshConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gDciConfigGuid, (VOID *) &DciConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gP2sbConfigGuid, (VOID *) &P2sbConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gInterruptConfigGuid, (VOID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "------------------------ SC Print Policy Start ------------------------\n")); + PrintGeneralConfig (ScGeneralConfig); + PrintSataConfig (SataConfig); + PrintPcieConfig (PcieRpConfig); + PrintHpetConfig (HpetConfig); + PrintSmbusConfig (SmbusConfig); + PrintIoApicConfig (IoApicConfig); + PrintUsbConfig (UsbConfig); + PrintHdAudioConfig (HdaConfig); + PrintGmmConfig (GmmConfig); + PrintPmConfig (PmConfig); + PrintLockDownConfig (LockDownConfig); + PrintSerialIrqConfig (SerialIrqConfig); + PrintLpssConfig (LpssConfig); + PrintScsConfig (ScsConfig); + PrintVtdConfig (VtdConfig); + PrintIshConfig (IshConfig); + PrintFlashProtectionConfig (FlashProtectionConfig); + PrintDciConfig (DciConfig); + PrintP2sbConfig (P2sbConfig); + PrintInterruptConfig (InterruptConfig); + + DEBUG ((DEBUG_INFO, "------------------------ SC Print Policy End ------------------------\n")); +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicyPreMem.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicyPreMem.c new file mode 100644 index 0000000000..44d71202f1 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiScPolicyLib/ScPrintPolicyPreMem.c @@ -0,0 +1,75 @@ +/** @file + This file is PeiScPolicyLib library for printing PREMEM Policy settings. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiScPolicyLibrary.h" + +VOID +PrintPciePreMemConfig ( + IN CONST SC_PCIE_PREMEM_CONFIG *PciePreMemConfig + ) +{ + UINT8 i; + + DEBUG ((DEBUG_INFO, "--- PCIe Config ---\n")); + for (i = 0; i < GetScMaxPciePortNum (); i++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] PERST = %x\n", i, PciePreMemConfig->RootPort[i].Perst)); + } + DEBUG ((DEBUG_INFO, " StartTimerTickerOfPerstAssert = %x\n", i, PciePreMemConfig->StartTimerTickerOfPfetAssert)); +} + + +/** + Print SC_LPC_PREMEM_CONFIG and serial out. + + @param[in] LpcConfig Pointer to a SC_LPC_CONFIG that provides the platform setting + +**/ +VOID +PrintLpcPreMemConfig ( + IN CONST SC_LPC_PREMEM_CONFIG *LpcConfig + ) +{ + DEBUG ((DEBUG_INFO, "--- LPC Config ---\n")); + DEBUG ((DEBUG_INFO, " EnhancePort8xhDecoding = %x\n", LpcConfig->EnhancePort8xhDecoding)); +} + + +/** + Print whole SC_PREMEM_POLICY_PPI and serial out. + + @param[in] ScPreMemPolicyPpi The RC Policy PPI instance + +**/ +VOID +EFIAPI +ScPreMemPrintPolicyPpi ( + IN SC_PREMEM_POLICY_PPI *ScPreMemPolicyPpi + ) +{ + SC_PCIE_PREMEM_CONFIG *PciePreMemConfig; + SC_LPC_PREMEM_CONFIG *LpcPreMemConfig; + EFI_STATUS Status; + + Status = GetConfigBlock ((VOID *) ScPreMemPolicyPpi, &gPcieRpPreMemConfigGuid, (VOID *) &PciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) ScPreMemPolicyPpi, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "--- SC Print PreMem Policy Start ---\n")); + PrintPciePreMemConfig (PciePreMemConfig); + PrintLpcPreMemConfig (LpcPreMemConfig); + DEBUG ((DEBUG_INFO, "--- SC Print PreMem Policy End ---\n")); +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/DxeScHdaLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/DxeScHdaLib.inf new file mode 100644 index 0000000000..2013054fdb --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/DxeScHdaLib.inf @@ -0,0 +1,46 @@ +## @file +# Component information file for SC HD Audio Library. +# +# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeScHdaLib + FILE_GUID = DA915B7F-EE08-4C1D-B3D0-DE7C52AB155A + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = ScHdaLib + +[LibraryClasses] + BaseLib + DebugLib + MemoryAllocationLib + BaseMemoryLib + ScPlatformLib + SteppingLib + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonSiPkg/BroxtonSiPrivate.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES + +[Sources] + ScHdaLib.c + ScHdaEndpoints.c diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaEndpoints.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaEndpoints.c new file mode 100644 index 0000000000..59add2d2fc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/DxeScHdaLib/ScHdaEndpoints.c @@ -0,0 +1,497 @@ +/** @file + This file contains HD Audio NHLT Endpoints definitions. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz16bitFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 192000, + 4, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 16, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz24bitFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 24, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz32bitFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 32, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch4_48kHz16bitFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 4, + 48000, + 384000, + 8, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 16, + KSAUDIO_SPEAKER_QUAD, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch4_48kHz32bitFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 4, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 32, + KSAUDIO_SPEAKER_QUAD, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE NarrowbandFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 1, + 8000, + 16000, + 2, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 16, + KSAUDIO_SPEAKER_MONO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE WidebandFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 1, + 16000, + 32000, + 2, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 16, + KSAUDIO_SPEAKER_MONO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE A2dpFormat = +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + 24, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicStereo16BitFormatConfig[] = +{ + 0x00000001, + 0xFFFF3210, + 0xFFFFFF10, + 0xFFFFFF32, + 0xFFFFFFFF, + 0x00000003, + 0x00000003, + 0x00300003, + 0x00300003 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicStereo32BitFormatConfig[] = +{ + 0x00000001, + 0xFFFF3210, + 0xFFFFFF10, + 0xFFFFFF32, + 0xFFFFFFFF, + 0x00000003, + 0x00000003, + 0x00380003, + 0x00380003 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicQuad16BitFormatConfig[] = +{ + 0x00000001, + 0xFFFF3210, + 0xFFFFFF10, + 0xFFFFFF32, + 0xFFFFFFFF, + 0x00000003, + 0x00000003, + 0x00320003, + 0x00320003 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicQuad32BitFormatConfig[] = +{ + 0x00000001, + 0xFFFF3210, + 0xFFFFFF10, + 0xFFFFFF32, + 0xFFFFFFFF, + 0x00000003, + 0x00000003, + 0x003A0003, + 0x003A0003 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicFormatConfigSize = sizeof (DmicStereo16BitFormatConfig); + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicCommonFormatConfig[] = +{ + 0x00000003, + // + // PDM_SETTINGS + // + 0x0001, 0x08000F00, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x401a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03b1, 0, 0, 0, 0, 0, 0, + // + // FIR A coefficients + // + 0x00006, 0xfffc2, 0xfff4a, 0xffe76, 0xffd3d, 0xffbb1, 0xffa06, 0xff891, 0xff7b5, 0xff7d0, 0xff91a, 0xffb89, 0xffec7, 0x00232, 0x00501, 0x00674, 0x0060f, 0x003c8, 0x0001f, 0xffc0e, + 0xff8c8, 0xff76b, 0xff89b, 0xffc48, 0x00192, 0x006fd, 0x00ad0, 0x00ba2, 0x008d3, 0x002db, 0xffb45, 0xff451, 0xff04f, 0xff0de, 0xff654, 0xfff79, 0x009c4, 0x01204, 0x01559, 0x0122f, + 0x008e0, 0xffbcc, 0xfeec8, 0xfe607, 0xfe4c4, 0xfec1d, 0xffa84, 0x00bfe, 0x01b34, 0x0230f, 0x02062, 0x0131d, 0xffe9a, 0xfe8d0, 0xfd8a1, 0xfd3b3, 0xfdc86, 0xff162, 0x00c8d, 0x025d6, + 0x03504, 0x03479, 0x02332, 0x00574, 0xfe3d0, 0xfc8b1, 0xfbd30, 0xfc60d, 0xfe1e3, 0x0092c, 0x0303b, 0x04ab2, 0x04f5b, 0x03b53, 0x01350, 0xfe2a8, 0xfb81f, 0xfa174, 0xfa6ff, 0xfc8be, + 0xffdd5, 0x036d4, 0x0622f, 0x07195, 0x05e9d, 0x02d32, 0xfeae9, 0xfab52, 0xf8238, 0xf7d85, 0xfa0ad, 0xfe310, 0x03207, 0x0761d, 0x099fa, 0x09101, 0x05b91, 0x00783, 0xfaca0, 0xf65ea, + 0xf499f, 0xf6261, 0xfab80, 0x011b3, 0x0782e, 0x0c0b9, 0x0d485, 0x0ab24, 0x04d99, 0xfd470, 0xf6145, 0xf157b, 0xf08ad, 0xf419d, 0xfb3aa, 0x041a3, 0x0c550, 0x119b3, 0x1253d, 0x0e125, + 0x05bdc, 0xfb5dc, 0xf1998, 0xeb0a6, 0xe98ed, 0xedca7, 0xf6f50, 0x0303a, 0x0f22e, 0x18623, 0x1c671, 0x19fbb, 0x1158d, 0x041b8, 0xf4ea6, 0xe6e38, 0xdcf55, 0xd9485, 0xdcd8e, 0xe7549, + 0xf73b4, 0x0a398, 0x1da21, 0x2eec7, 0x3c1e2, 0x440c0, 0x466ea, 0x43ca0, 0x3d36f, 0x341bc, 0x29e6b, 0x1fd4d, 0x16cef, 0x0f5cd, 0x09ac4, 0x05a55, 0x03040, 0x0171e, 0x00999, 0x0033a, + 0x000be, + // + // FIR B coefficients + // + 0xffff5, 0x007c7, 0x00726, 0x00a22, 0x00db5, 0x011d6, 0x01676, 0x01b80, 0x020d4, 0x02648, 0x02baa, 0x030c4, 0x03557, 0x03924, 0x03be9, 0x03d69, 0x03d6c, 0x03bc5, 0x03854, 0x03309, + 0x02be4, 0x022fe, 0x01882, 0x00cb5, 0xfffec, 0xff294, 0xfe526, 0xfd82b, 0xfcc2f, 0xfc1c0, 0xfb967, 0xfb3a1, 0xfb0d7, 0xfb158, 0xfb556, 0xfbcdd, 0xfc7d4, 0xfd5f7, 0xfe6dc, 0xff9f0, + 0x00e7f, 0x023b7, 0x038af, 0x04c77, 0x05e19, 0x06ca8, 0x07750, 0x07d58, 0x07e34, 0x0798a, 0x06f3a, 0x05f66, 0x04a6d, 0x030f5, 0x013db, 0xff438, 0xfd34d, 0xfb280, 0xf9346, 0xf771b, + 0xf5f64, 0xf4d73, 0xf425a, 0xf3efb, 0xf43de, 0xf513f, 0xf66f2, 0xf8476, 0xfa8dd, 0xfd2ef, 0x00113, 0x03183, 0x06234, 0x09112, 0x0bbf5, 0x0e0d9, 0x0fdd1, 0x11149, 0x119ee, 0x116eb, + 0x107cf, 0x0ecbd, 0x0c64d, 0x095a8, 0x05c67, 0x01c9d, 0xfd8b2, 0xf935b, 0xf4f70, 0xf0fe0, 0xed781, 0xea8fe, 0xe86ae, 0xe7280, 0xe6de0, 0xe799f, 0xe95f0, 0xec252, 0xefda0, 0xf4606, + 0xf9922, 0xff404, 0x0535e, 0x0b38a, 0x110c8, 0x16749, 0x1b36d, 0x1f1d1, 0x21f8e, 0x23a37, 0x24019, 0x2302a, 0x20a3e, 0x1cee6, 0x17f93, 0x11e6e, 0x0ae61, 0x032e8, 0xfb00a, 0xf2a20, + 0xea5c4, 0xe2795, 0xdb421, 0xd4faa, 0xcfe13, 0xcc2ad, 0xca02a, 0xc9877, 0xcacbc, 0xcdd42, 0xd2982, 0xd901f, 0xe0efb, 0xea344, 0xf4996, 0xffe0c, 0x0bc6f, 0x1804f, 0x24528, 0x3068b, + 0x3c039, 0x46e45, 0x50d2f, 0x599f7, 0x61231, 0x67412, 0x6be71, 0x6f0ca, 0x70b3a, 0x70e72, 0x6fbac, 0x6d497, 0x69b45, 0x65213, 0x5fb93, 0x59a75, 0x53172, 0x4c336, 0x4524e, 0x3e116, + 0x371b3, 0x305ff, 0x29f8c, 0x23f9b, 0x1e71b, 0x196b1, 0x14eb4, 0x10f3e, 0x0d828, 0x0a91e, 0x081a1, 0x06117, 0x046cd, 0x03207, 0x02204, 0x01605, 0x00d56, 0x009c9, + // + // PDM_SETTINGS + // + 0x0001, 0x08000F00, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x401a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03b1, 0, 0, 0, 0, 0, 0, + // + // FIR A coefficients + // + 0x00006, 0xfffc2, 0xfff4a, 0xffe76, 0xffd3d, 0xffbb1, 0xffa06, 0xff891, 0xff7b5, 0xff7d0, 0xff91a, 0xffb89, 0xffec7, 0x00232, 0x00501, 0x00674, 0x0060f, 0x003c8, 0x0001f, 0xffc0e, + 0xff8c8, 0xff76b, 0xff89b, 0xffc48, 0x00192, 0x006fd, 0x00ad0, 0x00ba2, 0x008d3, 0x002db, 0xffb45, 0xff451, 0xff04f, 0xff0de, 0xff654, 0xfff79, 0x009c4, 0x01204, 0x01559, 0x0122f, + 0x008e0, 0xffbcc, 0xfeec8, 0xfe607, 0xfe4c4, 0xfec1d, 0xffa84, 0x00bfe, 0x01b34, 0x0230f, 0x02062, 0x0131d, 0xffe9a, 0xfe8d0, 0xfd8a1, 0xfd3b3, 0xfdc86, 0xff162, 0x00c8d, 0x025d6, + 0x03504, 0x03479, 0x02332, 0x00574, 0xfe3d0, 0xfc8b1, 0xfbd30, 0xfc60d, 0xfe1e3, 0x0092c, 0x0303b, 0x04ab2, 0x04f5b, 0x03b53, 0x01350, 0xfe2a8, 0xfb81f, 0xfa174, 0xfa6ff, 0xfc8be, + 0xffdd5, 0x036d4, 0x0622f, 0x07195, 0x05e9d, 0x02d32, 0xfeae9, 0xfab52, 0xf8238, 0xf7d85, 0xfa0ad, 0xfe310, 0x03207, 0x0761d, 0x099fa, 0x09101, 0x05b91, 0x00783, 0xfaca0, 0xf65ea, + 0xf499f, 0xf6261, 0xfab80, 0x011b3, 0x0782e, 0x0c0b9, 0x0d485, 0x0ab24, 0x04d99, 0xfd470, 0xf6145, 0xf157b, 0xf08ad, 0xf419d, 0xfb3aa, 0x041a3, 0x0c550, 0x119b3, 0x1253d, 0x0e125, + 0x05bdc, 0xfb5dc, 0xf1998, 0xeb0a6, 0xe98ed, 0xedca7, 0xf6f50, 0x0303a, 0x0f22e, 0x18623, 0x1c671, 0x19fbb, 0x1158d, 0x041b8, 0xf4ea6, 0xe6e38, 0xdcf55, 0xd9485, 0xdcd8e, 0xe7549, + 0xf73b4, 0x0a398, 0x1da21, 0x2eec7, 0x3c1e2, 0x440c0, 0x466ea, 0x43ca0, 0x3d36f, 0x341bc, 0x29e6b, 0x1fd4d, 0x16cef, 0x0f5cd, 0x09ac4, 0x05a55, 0x03040, 0x0171e, 0x00999, 0x0033a, + 0x000be, + // + // FIR B coefficients + // + 0xffff5, 0x007c7, 0x00726, 0x00a22, 0x00db5, 0x011d6, 0x01676, 0x01b80, 0x020d4, 0x02648, 0x02baa, 0x030c4, 0x03557, 0x03924, 0x03be9, 0x03d69, 0x03d6c, 0x03bc5, 0x03854, 0x03309, + 0x02be4, 0x022fe, 0x01882, 0x00cb5, 0xfffec, 0xff294, 0xfe526, 0xfd82b, 0xfcc2f, 0xfc1c0, 0xfb967, 0xfb3a1, 0xfb0d7, 0xfb158, 0xfb556, 0xfbcdd, 0xfc7d4, 0xfd5f7, 0xfe6dc, 0xff9f0, + 0x00e7f, 0x023b7, 0x038af, 0x04c77, 0x05e19, 0x06ca8, 0x07750, 0x07d58, 0x07e34, 0x0798a, 0x06f3a, 0x05f66, 0x04a6d, 0x030f5, 0x013db, 0xff438, 0xfd34d, 0xfb280, 0xf9346, 0xf771b, + 0xf5f64, 0xf4d73, 0xf425a, 0xf3efb, 0xf43de, 0xf513f, 0xf66f2, 0xf8476, 0xfa8dd, 0xfd2ef, 0x00113, 0x03183, 0x06234, 0x09112, 0x0bbf5, 0x0e0d9, 0x0fdd1, 0x11149, 0x119ee, 0x116eb, + 0x107cf, 0x0ecbd, 0x0c64d, 0x095a8, 0x05c67, 0x01c9d, 0xfd8b2, 0xf935b, 0xf4f70, 0xf0fe0, 0xed781, 0xea8fe, 0xe86ae, 0xe7280, 0xe6de0, 0xe799f, 0xe95f0, 0xec252, 0xefda0, 0xf4606, + 0xf9922, 0xff404, 0x0535e, 0x0b38a, 0x110c8, 0x16749, 0x1b36d, 0x1f1d1, 0x21f8e, 0x23a37, 0x24019, 0x2302a, 0x20a3e, 0x1cee6, 0x17f93, 0x11e6e, 0x0ae61, 0x032e8, 0xfb00a, 0xf2a20, + 0xea5c4, 0xe2795, 0xdb421, 0xd4faa, 0xcfe13, 0xcc2ad, 0xca02a, 0xc9877, 0xcacbc, 0xcdd42, 0xd2982, 0xd901f, 0xe0efb, 0xea344, 0xf4996, 0xffe0c, 0x0bc6f, 0x1804f, 0x24528, 0x3068b, + 0x3c039, 0x46e45, 0x50d2f, 0x599f7, 0x61231, 0x67412, 0x6be71, 0x6f0ca, 0x70b3a, 0x70e72, 0x6fbac, 0x6d497, 0x69b45, 0x65213, 0x5fb93, 0x59a75, 0x53172, 0x4c336, 0x4524e, 0x3e116, + 0x371b3, 0x305ff, 0x29f8c, 0x23f9b, 0x1e71b, 0x196b1, 0x14eb4, 0x10f3e, 0x0d828, 0x0a91e, 0x081a1, 0x06117, 0x046cd, 0x03207, 0x02204, 0x01605, 0x00d56, 0x009c9 +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicCommonFormatConfigSize = sizeof (DmicCommonFormatConfig); + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 I2sFormatConfigRender[] = {0x0, 0xFFFFFF10, 0xFFFFFF32, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x83d00337, 0xc0700000, 0x0, 0x2010005, 0xf, 0xf, 0x4002, 0x4, 0x7070f00, 0x20, 0x1, 0x0 }; /// + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Returns pointer to Endpoint ENDPOINT_DESCRIPTOR structure. + + @param[in] NhltTable Endpoint for which Format address is retrieved + @param[in] FormatIndex Index of Format to be retrieved + + @retval Pointer to ENDPOINT_DESCRIPTOR structure with given index + +**/ +ENDPOINT_DESCRIPTOR * +GetNhltEndpoint ( + IN CONST NHLT_ACPI_TABLE *NhltTable, + IN CONST UINT8 EndpointIndex + ) +{ + UINT8 i; + ENDPOINT_DESCRIPTOR *Endpoint; + + Endpoint = (ENDPOINT_DESCRIPTOR *) (NhltTable->EndpointDescriptors); + + if (EndpointIndex > NhltTable->EndpointCount) { + return NULL; + } + + for (i = 0; i < EndpointIndex; i++) { + Endpoint = (ENDPOINT_DESCRIPTOR*) ((UINT8 *) (Endpoint) + Endpoint->EndpointDescriptorLength); + } + + return Endpoint; +} + + +/** + Returns pointer to Endpoint Specific Configuration SPECIFIC_CONFIG structure. + + @param[in] Endpoint Endpoint for which config address is retrieved + + @retval Pointer to SPECIFIC_CONFIG structure with endpoint's capabilities + +**/ +SPECIFIC_CONFIG * +GetNhltEndpointDeviceCapabilities ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + return (SPECIFIC_CONFIG *) (&Endpoint->EndpointConfig); +} + + +/** + Returns pointer to all Formats Configuration FORMATS_CONFIG structure. + + @param[in] Endpoint Endpoint for which Formats address is retrieved + + @retval Pointer to FORMATS_CONFIG structure + +**/ +FORMATS_CONFIG * +GetNhltEndpointFormatsConfig ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + FORMATS_CONFIG *FormatsConfig; + + FormatsConfig = (FORMATS_CONFIG *) ((UINT8 *) (&Endpoint->EndpointConfig) + + sizeof (Endpoint->EndpointConfig.CapabilitiesSize) + + Endpoint->EndpointConfig.CapabilitiesSize); + + return FormatsConfig; +} + + +/** + Returns pointer to Format Configuration FORMAT_CONFIG structure. + + @param[in] Endpoint Endpoint for which Format address is retrieved + @param[in] FormatIndex Index of Format to be retrieved + + @retval Pointer to FORMAT_CONFIG structure with given index + +**/ +FORMAT_CONFIG * +GetNhltEndpointFormat ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT8 FormatIndex + ) +{ + UINT8 i; + UINT32 Length; + FORMATS_CONFIG *FormatsConfig; + FORMAT_CONFIG *Format; + + Length = 0; + FormatsConfig = GetNhltEndpointFormatsConfig (Endpoint); + Format = FormatsConfig->FormatsConfiguration; + + if (FormatIndex > FormatsConfig->FormatsCount) { + return NULL; + } + + for (i = 0; i < FormatIndex; i++) { + Length = sizeof (Format->Format) + Format->FormatConfiguration.CapabilitiesSize + + sizeof (Format->FormatConfiguration.CapabilitiesSize); + Format = (FORMAT_CONFIG *) ((UINT8 *) (Format) + Length); + } + + return Format; +} + + +/** + Returns pointer to OED Configuration SPECIFIC_CONFIG structure. + + @param[in] NhltTable NHLT table for which OED address is retrieved + + @retval Pointer to SPECIFIC_CONFIG structure with NHLT capabilities + +**/ +SPECIFIC_CONFIG * +GetNhltOedConfig ( + IN CONST NHLT_ACPI_TABLE *NhltTable + ) +{ + ENDPOINT_DESCRIPTOR *Endpoint; + SPECIFIC_CONFIG *OedConfig; + + Endpoint = GetNhltEndpoint (NhltTable, (NhltTable->EndpointCount)); + OedConfig = (SPECIFIC_CONFIG *) ((UINT8 *) (Endpoint)); + + return OedConfig; +} + + +/** + Prints Format configuration. + + @param[in] *Format Format to be printed + + @retval None + +**/ +VOID +NhltFormatDump ( + IN CONST FORMAT_CONFIG *Format + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------------------- FORMAT -------------------------------\n")); + DEBUG ((DEBUG_INFO, " Format->Format.Format.wFormatTag = 0x%x\n", Format->Format.Format.wFormatTag)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nChannels = %d\n", Format->Format.Format.nChannels)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nSamplesPerSec = %d\n", Format->Format.Format.nSamplesPerSec)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nAvgBytesPerSec = %d\n", Format->Format.Format.nAvgBytesPerSec)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nBlockAlign = %d\n", Format->Format.Format.nBlockAlign)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.wBitsPerSample = %d\n", Format->Format.Format.wBitsPerSample)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.cbSize = %d\n", Format->Format.Format.cbSize)); + DEBUG ((DEBUG_INFO, " Format->Format.Samples = %d\n", Format->Format.Samples)); + DEBUG ((DEBUG_INFO, " Format->Format.dwChannelMask = 0x%x\n", Format->Format.dwChannelMask)); + DEBUG ((DEBUG_INFO, " Format->Format.SubFormat = %g\n", Format->Format.SubFormat)); + + DEBUG ((DEBUG_INFO, " Format->FormatConfiguration.CapabilitiesSize = %d B\n", Format->FormatConfiguration.CapabilitiesSize)); + DEBUG ((DEBUG_INFO, " Format->FormatConfiguration.Capabilities:")); + for (i = 0; i < ( Format->FormatConfiguration.CapabilitiesSize ) ; i++) { + if(i % 16 == 0) DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "0x%02x, ", Format->FormatConfiguration.Capabilities[i])); + } + DEBUG ((DEBUG_INFO, "\n")); +} + + +/** + Prints Endpoint configuration. + + @param[in] Endpoint Endpoint to be printed + + @retval None + +**/ +VOID +NhltEndpointDump ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + UINT8 i; + FORMATS_CONFIG *FormatsConfigs; + FORMAT_CONFIG *Format; + + DEBUG ((DEBUG_INFO, "------------------------------ ENDPOINT ------------------------------\n")); + DEBUG ((DEBUG_INFO, " Endpoint->DeviceDescriptorLength = %d B\n", Endpoint->EndpointDescriptorLength)); + DEBUG ((DEBUG_INFO, " Endpoint->LinkType = 0x%x\n", Endpoint->LinkType)); + DEBUG ((DEBUG_INFO, " Endpoint->InstanceId = 0x%x\n", Endpoint->InstanceId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwVendorId = 0x%x\n", Endpoint->HwVendorId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwDeviceId = 0x%x\n", Endpoint->HwDeviceId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwRevisionId = 0x%x\n", Endpoint->HwRevisionId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwSubsystemId = 0x%x\n", Endpoint->HwSubsystemId)); + DEBUG ((DEBUG_INFO, " Endpoint->DeviceType = 0x%x\n", Endpoint->DeviceType)); + DEBUG ((DEBUG_INFO, " Endpoint->Direction = 0x%x\n", Endpoint->Direction)); + DEBUG ((DEBUG_INFO, " Endpoint->VirtualBusId = 0x%x\n", Endpoint->VirtualBusId)); + + DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.CapabilitiesSize = %d B\n", Endpoint->EndpointConfig.CapabilitiesSize)); + DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.Capabilities:")); + for (i = 0; i < (Endpoint->EndpointConfig.CapabilitiesSize ) ; i++) { + if (i % 16 == 0) DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "0x%02x, ", Endpoint->EndpointConfig.Capabilities[i])); + } + + FormatsConfigs = GetNhltEndpointFormatsConfig(Endpoint); + + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, " Endpoint->FormatsConfig.FormatsCount = %d\n", FormatsConfigs->FormatsCount)); + for (i = 0; i < FormatsConfigs->FormatsCount; i++) { + Format = GetNhltEndpointFormat (Endpoint, i); + NhltFormatDump (Format); + } + + DEBUG ((DEBUG_INFO, "\n")); +} + + +/** + Prints OED (Offload Engine Driver) configuration. + + @param[in] OedConfig OED to be printed + + @retval None + +**/ +VOID +NhltOedConfigDump ( + IN CONST SPECIFIC_CONFIG *OedConfig + ) +{ + UINT8 i; + + DEBUG ((DEBUG_INFO, "-------------------------- OED CONFIGURATION -------------------------\n")); + DEBUG ((DEBUG_INFO, " OedConfig->CapabilitiesSize = %d B\n", OedConfig->CapabilitiesSize)); + DEBUG ((DEBUG_INFO, " OedConfig->Capabilities:")); + for (i = 0; i < (OedConfig->CapabilitiesSize) ; i++) { + if(i % 16 == 0) DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "0x%02x, ", OedConfig->Capabilities[i])); + } + + DEBUG ((DEBUG_INFO, "\n")); +} + + +/** + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offload Engine Driver) Configuration Table). + + @param[in] NhltTable The NHLT table to print + + @retval None + +**/ +VOID +NhltAcpiTableDump ( + IN NHLT_ACPI_TABLE *NhltTable + ) +{ + + UINT8 i; + + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "--- NHLT ACPI Table Dump [OED (Offload Engine Driver) Configuration] ---\n")); + + DEBUG ((DEBUG_INFO, "sizeof NHLT_ACPI_TABLE = %d B\n", sizeof (NHLT_ACPI_TABLE))); + DEBUG ((DEBUG_INFO, "sizeof EFI_ACPI_DESCRIPTION_HEADER = %d B\n", sizeof (EFI_ACPI_DESCRIPTION_HEADER))); + DEBUG ((DEBUG_INFO, "sizeof ENDPOINT_DESCRIPTOR = %d B\n", sizeof (ENDPOINT_DESCRIPTOR))); + DEBUG ((DEBUG_INFO, "sizeof SPECIFIC_CONFIG = %d B\n", sizeof (SPECIFIC_CONFIG))); + DEBUG ((DEBUG_INFO, "sizeof FORMATS_CONFIG = %d B\n", sizeof (FORMATS_CONFIG))); + DEBUG ((DEBUG_INFO, "sizeof FORMAT_CONFIG = %d B\n", sizeof (FORMAT_CONFIG))); + DEBUG ((DEBUG_INFO, "sizeof WAVEFORMATEXTENSIBLE = %d B\n", sizeof (WAVEFORMATEXTENSIBLE))); + + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Signature = 0x%08x\n", NhltTable->Header.Signature)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Length = 0x%08x\n", NhltTable->Header.Length)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Revision = 0x%02x\n", NhltTable->Header.Revision)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Checksum = 0x%02x\n", NhltTable->Header.Checksum)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemId = %a\n", NhltTable->Header.OemId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemTableId = 0x%lx\n", NhltTable->Header.OemTableId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemRevision = 0x%08x\n", NhltTable->Header.OemRevision)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.CreatorId = 0x%08x\n", NhltTable->Header.CreatorId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.CreatorRevision = 0x%08x\n", NhltTable->Header.CreatorRevision)); + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE EndpointCount = %d\n", NhltTable->EndpointCount)); + for (i = 0; i < NhltTable->EndpointCount; i++) { + NhltEndpointDump (GetNhltEndpoint (NhltTable, i)); + } + + NhltOedConfigDump (GetNhltOedConfig (NhltTable)); + DEBUG ((DEBUG_INFO, "----------------------------------------------------------------------\n")); +} + + +/** + Constructs FORMATS_CONFIGS structure based on given formats list. + + @param[in, out] Endpoint Endpoint for which format structures are created + @param[in] FormatBitmask Bitmask of formats supported for given endpoint + + @retval Size of created FORMATS_CONFIGS structure + +**/ +UINT32 +NhltFormatsConstructor ( + IN OUT ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT32 FormatsBitmask, + IN NHLT_ENDPOINT EndpointType + ) +{ + FORMATS_CONFIG *FormatsConfig; + FORMAT_CONFIG *Format; + UINT8 FormatIndex; + UINT32 FormatsConfigLength; + + DEBUG ((DEBUG_INFO, "NhltFormatsConstructor() Start, FormatsBitmask = 0x%08x\n", FormatsBitmask)); + + FormatsConfig = NULL; + FormatIndex = 0; + FormatsConfigLength = 0; + + if (!FormatsBitmask) { + DEBUG ((DEBUG_WARN, "No supported format found!\n")); + return 0; + } + + FormatsConfig = GetNhltEndpointFormatsConfig (Endpoint); + FormatsConfig->FormatsCount = 0; + + if (FormatsBitmask & B_HDA_2CH_48KHZ_16BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_2CH_48KHZ_16BIT_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL){ + CopyMem (&(Format->Format), &Ch2_48kHz16bitFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = DmicFormatConfigSize + DmicCommonFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicStereo16BitFormatConfig, DmicFormatConfigSize); + CopyMem ((Format->FormatConfiguration.Capabilities + DmicFormatConfigSize), DmicCommonFormatConfig, DmicCommonFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_2CH_48KHZ_24BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_2CH_48KHZ_24BIT_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL){ + CopyMem (&(Format->Format), &Ch2_48kHz24bitFormat, sizeof (WAVEFORMATEXTENSIBLE)); + if ((EndpointType == HdaI2sRenderHP) || (EndpointType == HdaI2sRenderSKP)){ + // + // For BXT-P, [HSD 1206654234]: Audio: BIOS I2S blobs need to change for proper I2S render and capture + // + if (GetBxtSeries() == BxtP) { + Format->FormatConfiguration.CapabilitiesSize = I2sFormatConfigRenderSize_Bxtp; + CopyMem(Format->FormatConfiguration.Capabilities, I2sFormatConfigRender_Bxtp, I2sFormatConfigRenderSize_Bxtp); + DEBUG ((DEBUG_INFO, "For BXT-P, Audio: BIOS I2S blobs need to change for proper I2S render and capture.\n")); + } else { + Format->FormatConfiguration.CapabilitiesSize = I2sFormatConfigRenderSize; + CopyMem(Format->FormatConfiguration.Capabilities, I2sFormatConfigRender, I2sFormatConfigRenderSize); + } + } else if ((EndpointType == HdaI2sCaptureHP) || (EndpointType == HdaI2sCaptureSKP) ){ + // + // For BXT-P, [HSD 1206654234]: Audio: BIOS I2S blobs need to change for proper I2S render and capture + // + if (GetBxtSeries() == BxtP) { + Format->FormatConfiguration.CapabilitiesSize = I2sFormatConfigCaptureSize_Bxtp; + CopyMem(Format->FormatConfiguration.Capabilities, I2sFormatConfigCapture_Bxtp, I2sFormatConfigCaptureSize_Bxtp); + DEBUG ((DEBUG_INFO, "For BXT-P, Audio: BIOS I2S blobs need to change for proper I2S render and capture.\n")); + } else { + Format->FormatConfiguration.CapabilitiesSize = I2sFormatConfigCaptureSize; + CopyMem(Format->FormatConfiguration.Capabilities, I2sFormatConfigCapture, I2sFormatConfigCaptureSize); + } + } + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_2CH_48KHZ_32BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_2CH_48KHZ_32BIT_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL) { + CopyMem (&(Format->Format), &Ch2_48kHz32bitFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = DmicFormatConfigSize + DmicCommonFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicStereo32BitFormatConfig, DmicFormatConfigSize); + CopyMem ((Format->FormatConfiguration.Capabilities + DmicFormatConfigSize), DmicCommonFormatConfig, DmicCommonFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_4CH_48KHZ_16BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_4CH_48KHZ_16BIT_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL){ + CopyMem (&(Format->Format), &Ch4_48kHz16bitFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = DmicFormatConfigSize + DmicCommonFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicQuad16BitFormatConfig, DmicFormatConfigSize); + CopyMem ((Format->FormatConfiguration.Capabilities + DmicFormatConfigSize), DmicCommonFormatConfig, DmicCommonFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_4CH_48KHZ_32BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_4CH_48KHZ_32BIT_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL){ + CopyMem (&(Format->Format), &Ch4_48kHz32bitFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = DmicFormatConfigSize + DmicCommonFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicQuad32BitFormatConfig, DmicFormatConfigSize); + CopyMem ((Format->FormatConfiguration.Capabilities + DmicFormatConfigSize), DmicCommonFormatConfig, DmicCommonFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_NARROWBAND_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_NARROWBAND_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL) { + CopyMem (&(Format->Format), &NarrowbandFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = BtFormatConfigSize; + CopyMem(Format->FormatConfiguration.Capabilities, BtFormatConfig, BtFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_WIDEBAND_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_WIDEBAND_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if(Format != NULL){ + CopyMem (&(Format->Format), &WidebandFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = BtFormatConfigSize; + CopyMem(Format->FormatConfiguration.Capabilities, BtFormatConfig, BtFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_A2DP_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_A2DP_FORMAT\n")); + + Format = GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format != NULL){ + CopyMem (&(Format->Format), &A2dpFormat, sizeof (WAVEFORMATEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize = BtFormatConfigSize; + CopyMem(Format->FormatConfiguration.Capabilities, BtFormatConfig, BtFormatConfigSize); + + FormatsConfigLength += sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + DEBUG ((DEBUG_INFO, "NhltFormatsConstructor() End, FormatsCount = %d, FormatsConfigLength = %d B\n", FormatsConfig->FormatsCount, FormatsConfigLength)); + return FormatsConfigLength; +} + + +/** + Constructs NHLT_ENDPOINT structure based on given endpoint type. + + @param[in, out] NhltTable NHLT table for which endpoint is created + @param[in] EndpointType Type of endpoint to be created + @param[in] EndpointIndex Endpoint index in NHLT table + + @retval Size of created NHLT_ENDPOINT structure + +**/ +UINT32 +NhltEndpointConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN NHLT_ENDPOINT EndpointType, + IN UINT8 EndpointIndex + ) +{ + + ENDPOINT_DESCRIPTOR *Endpoint; + SPECIFIC_CONFIG *EndpointConfig; + CONST UINT8 *EndpointConfigBuffer; + UINT32 EndpointConfigBufferSize; + UINT32 EndpointFormatsBitmask; + UINT32 EndpointDescriptorLength; + + DEBUG ((DEBUG_INFO, "NhltEndpointConstructor() Start, EndpointIndex = %d\n", EndpointIndex)); + + EndpointDescriptorLength = 0; + Endpoint = GetNhltEndpoint (NhltTable, EndpointIndex); + EndpointDescriptorLength = sizeof (ENDPOINT_DESCRIPTOR) + - sizeof (SPECIFIC_CONFIG) + - sizeof (FORMAT_CONFIG); + + switch (EndpointType) { + case HdaDmicX2: + DEBUG ((DEBUG_INFO, "Endpoint: HdaDmicX2\n")); + CopyMem (Endpoint, &HdaEndpointDmicX2, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = DmicX2Config; + EndpointConfigBufferSize = DmicX2ConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_16BIT_FORMAT | B_HDA_2CH_48KHZ_32BIT_FORMAT; + break; + case HdaDmicX4: + DEBUG ((DEBUG_INFO, "Endpoint: HdaDmicX4\n")); + CopyMem (Endpoint, &HdaEndpointDmicX4, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = DmicX4Config; + EndpointConfigBufferSize = DmicX4ConfigSize; + EndpointFormatsBitmask = B_HDA_4CH_48KHZ_16BIT_FORMAT | B_HDA_4CH_48KHZ_32BIT_FORMAT; + break; + case HdaBtRender: + DEBUG ((DEBUG_INFO, "Endpoint: HdaBtRender\n")); + if (GetBxtSeries() == BxtP) { + HdaEndpointBtRender.VirtualBusId = 2; + DEBUG ((DEBUG_INFO, "For BXT-P, HdaEndpointBtRender.VirtualBusId Change to 0x%02x.\n", HdaEndpointBtRender.VirtualBusId)); + } + CopyMem (Endpoint, &HdaEndpointBtRender, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = BtConfig; + EndpointConfigBufferSize = BtConfigSize; + EndpointFormatsBitmask = B_HDA_NARROWBAND_FORMAT | B_HDA_WIDEBAND_FORMAT | B_HDA_A2DP_FORMAT; + break; + case HdaBtCapture: + DEBUG ((DEBUG_INFO, "Endpoint: HdaBtCapture\n")); + if (GetBxtSeries() == BxtP) { + HdaEndpointBtCapture.VirtualBusId = 2; + DEBUG ((DEBUG_INFO, "For BXT-P, HdaEndpointBtCapture.VirtualBusId Change to 0x%02x.\n", HdaEndpointBtCapture.VirtualBusId)); + } + CopyMem (Endpoint, &HdaEndpointBtCapture, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = BtConfig; + EndpointConfigBufferSize = BtConfigSize; + EndpointFormatsBitmask = B_HDA_NARROWBAND_FORMAT | B_HDA_WIDEBAND_FORMAT; + break; + case HdaI2sRenderSKP: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sRenderSKP\n")); + // + // For BXT-P, Virtual Bus ID is 5, while it is 0 for BXTM + // + if (GetBxtSeries() == BxtP) { + HdaEndpointI2sRenderSKP.VirtualBusId = 5; + DEBUG ((DEBUG_INFO, "For BXT-P, Endpoint: HdaI2sRenderSKP virtual bus ID is 5.\n")); + } + CopyMem (Endpoint, &HdaEndpointI2sRenderSKP, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = I2sConfigSKP; + EndpointConfigBufferSize = I2sConfigSKPSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaI2sCaptureSKP: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sCaptureSKP\n")); + CopyMem (Endpoint, &HdaEndpointI2sCapture, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = I2sConfig; + EndpointConfigBufferSize = I2sConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaI2sRenderHP: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sRenderHP\n")); + // + // For BXT-P, Virtual Bus ID is 5, while it is 0 for BXTM + // + if (GetBxtSeries() == BxtP) { + HdaEndpointI2sRenderHP.VirtualBusId = 5; + DEBUG ((DEBUG_INFO, "For BXT-P, Endpoint: HdaI2sRenderHP virtual bus ID is 5.\n")); + } + CopyMem (Endpoint, &HdaEndpointI2sRenderHP, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = I2sConfig; + EndpointConfigBufferSize = I2sConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaI2sCaptureHP: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sCaptureHP\n")); + // + // For BXT-P, Virtual Bus ID is 5, while it is 0 for BXTM + // + if (GetBxtSeries() == BxtP) { + HdaEndpointI2sCapture.VirtualBusId = 5; + DEBUG ((DEBUG_INFO, "For BXT-P, Endpoint: HdaI2sCaptureHP virtual bus ID is 5.\n")); + } + CopyMem (Endpoint, &HdaEndpointI2sCapture, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = I2sConfig; + EndpointConfigBufferSize = I2sConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaModem1Render: + DEBUG ((DEBUG_INFO, "Endpoint: HdaModem1Render\n")); + CopyMem (Endpoint, &HdaEndpointModem1Render, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = Modem1Config; + EndpointConfigBufferSize = Modem1ConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaModem1Capture: + DEBUG ((DEBUG_INFO, "Endpoint: HdaModem1Capture\n")); + CopyMem (Endpoint, &HdaEndpointModem1Capture, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = Modem1Config; + EndpointConfigBufferSize = Modem1ConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaModem2Render: + DEBUG ((DEBUG_INFO, "Endpoint: HdaModem2Render\n")); + CopyMem (Endpoint, &HdaEndpointModem2Render, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = Modem2Config; + EndpointConfigBufferSize = Modem2ConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + case HdaModem2Capture: + DEBUG ((DEBUG_INFO, "Endpoint: HdaModem2Capture\n")); + CopyMem (Endpoint, &HdaEndpointModem2Capture, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer = Modem2Config; + EndpointConfigBufferSize = Modem2ConfigSize; + EndpointFormatsBitmask = B_HDA_2CH_48KHZ_24BIT_FORMAT; + break; + default: + DEBUG ((DEBUG_WARN, "Unknown endpoint!\n")); + return 0; + } + + EndpointConfig = GetNhltEndpointDeviceCapabilities (Endpoint); + EndpointConfig->CapabilitiesSize = EndpointConfigBufferSize; + CopyMem (EndpointConfig->Capabilities, EndpointConfigBuffer, EndpointConfig->CapabilitiesSize); + EndpointDescriptorLength += sizeof (*EndpointConfig) + - sizeof (EndpointConfig->Capabilities) + + EndpointConfig->CapabilitiesSize; + + EndpointDescriptorLength += NhltFormatsConstructor (Endpoint,EndpointFormatsBitmask,EndpointType); + Endpoint->EndpointDescriptorLength = EndpointDescriptorLength; + + DEBUG ((DEBUG_INFO, "NhltEndpointConstructor() End, EndpointDescriptorLength = %d B\n", Endpoint->EndpointDescriptorLength)); + return Endpoint->EndpointDescriptorLength; +} + + +/** + Constructs SPECIFIC_CONFIG structure for OED configuration. + + @param[in, out] NhltTable NHLT table for which OED config is created + + @retval Size of created SPECIFIC_CONFIG structure + +**/ +UINT32 +NhltOedConfigConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable + ) +{ + SPECIFIC_CONFIG *OedConfig; + UINT32 OedConfigLength; + + OedConfigLength = 0; + OedConfig = GetNhltOedConfig (NhltTable); + + OedConfig->CapabilitiesSize = NhltConfigurationSize; + CopyMem (OedConfig->Capabilities, (UINT8 *) NhltConfiguration, NhltConfigurationSize); + + OedConfigLength = sizeof (*OedConfig) + - sizeof (OedConfig->Capabilities) + + OedConfig->CapabilitiesSize; + + return OedConfigLength; +} + + +/** + Constructs NHLT_ACPI_TABLE structure based on given Endpoints list. + + @param[in] EndpointTable List of endpoints for NHLT + @param[in, out] NhltTable NHLT table to be created + @param[in, out] NhltTableSize Size of created NHLT table + + @retval EFI_SUCCESS NHLT created successfully + @retval EFI_BAD_BUFFER_SIZE Not enough resources to allocate NHLT + +**/ +EFI_STATUS +NhltConstructor ( + IN SC_HDA_NHLT_ENDPOINTS *EndpointTable, + IN OUT NHLT_ACPI_TABLE **NhltTable, + IN OUT UINT32 *NhltTableSize + ) +{ + EFI_STATUS Status; + UINT8 Index; + UINT32 TableSize; + UINT32 EndpointDescriptorsLength; + UINT32 OedConfigLength; + NHLT_ACPI_TABLE *Table; + + Status = EFI_SUCCESS; + TableSize = SC_HDA_NHLT_TABLE_SIZE; + EndpointDescriptorsLength = 0; + OedConfigLength = 0; + + Table = AllocateZeroPool (TableSize); + + if (Table == NULL) { + return EFI_BAD_BUFFER_SIZE; + } + + Table->EndpointCount = 0; + + for (Index = 0; Index < HdaEndpointMax; Index++) { + if (EndpointTable[Index].Enable == TRUE) { + EndpointDescriptorsLength += NhltEndpointConstructor (Table, EndpointTable[Index].EndpointType, Table->EndpointCount++); + } + } + DEBUG ((DEBUG_INFO, "NhltConstructor: EndpointCount = %d, All EndpointDescriptorsLength = %d B\n", Table->EndpointCount, EndpointDescriptorsLength)); + + OedConfigLength = NhltOedConfigConstructor (Table); + DEBUG ((DEBUG_INFO, "NhltConstructor: OedConfigLength = %d B\n", OedConfigLength)); + + TableSize = EndpointDescriptorsLength + OedConfigLength; + + *NhltTableSize = TableSize; + *NhltTable = Table; + + return Status; +} + + +/** + Constructs EFI_ACPI_DESCRIPTION_HEADER structure for NHLT table. + + @param[in, out] NhltTable NHLT table for which header will be created + @param[in] NhltTableSize Size of NHLT table + + @retval None + +**/ +VOID +NhltAcpiHeaderConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN UINT32 NhltTableSize + ) +{ + DEBUG ((DEBUG_INFO, "NhltAcpiHeaderConstructor() Start\n")); + + // + // Header + // + NhltTable->Header.Signature = NHLT_ACPI_TABLE_SIGNATURE; + NhltTable->Header.Length = (UINT32) (NhltTableSize + sizeof (NHLT_ACPI_TABLE) - sizeof (ENDPOINT_DESCRIPTOR) - sizeof (SPECIFIC_CONFIG)); + NhltTable->Header.Revision = 0x0; + NhltTable->Header.Checksum = 0x0; + + CopyMem (NhltTable->Header.OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (NhltTable->Header.OemId)); + NhltTable->Header.OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId); + NhltTable->Header.OemRevision = PcdGet32 (PcdAcpiDefaultOemRevision); + NhltTable->Header.CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId); + NhltTable->Header.CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision); + + DEBUG ((DEBUG_INFO, "NhltAcpiHeaderConstructor(), NhltAcpiTable->Header.Length = %d B\n", NhltTable->Header.Length)); +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/PeiDxeSmmScPciExpressHelpersLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/PeiDxeSmmScPciExpressHelpersLib.inf new file mode 100644 index 0000000000..e22dc3abbc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/PeiDxeSmmScPciExpressHelpersLib.inf @@ -0,0 +1,45 @@ +## @file +# PeiDxeSmmPchPciExpressHelpersLib. +# +# Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiDxeSmmPchPciExpressHelpersLib + FILE_GUID = 07E3F76D-6D26-419d-9053-58696A15B519 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PeiDxeSmmScPciExpressHelpersLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + ScPciExpressHelpersLibrary.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPrivate.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + IoLib + DebugLib + ScPlatformLib + SideBandLib + SteppingLib + + [Pcd] diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c new file mode 100644 index 0000000000..44b62db3ff --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.c @@ -0,0 +1,2096 @@ +/** @file + This file contains routines that support PCI Express initialization. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ScPciExpressHelpersLibrary.h" + +// +// Tpower-on Scale +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mPcieL1sTposMultiplier[] = {2, 10, 100}; +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mPclkdL1trefCfg[] = {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 60, 70, 80, 90, 100}; + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 = PCI Power Management Interface + 0x04 = Slot Identification + 0x05 = MSI Capability + 0x10 = PCI Express Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID + +**/ +UINT8 +PcieFindCapId ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ) +{ + UINT8 CapHeaderOffset; + UINT8 CapHeaderId; + UINTN DeviceBase; + + DeviceBase = MmPciBase (Bus, Device, Function); +#ifdef EFI_DEBUG + DEBUG ((DEBUG_INFO,"PcieFindCapId () BDF %0x: %0x :%0x, CapId = %0x \n", Bus, Device, Function, CapId)); +#endif + if ((MmioRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_STATUS_CAPABILITY) == 0x00) { + // + // Function has no capability pointer + // + return 0; + } else { + // + // Check the header layout to determine the Offset of Capabilities Pointer Register + // + if ((MmioRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) { + // + // If CardBus bridge, start at Offset 0x14 + // + CapHeaderOffset = EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR; + } else { + // + // Otherwise, start at Offset 0x34 + // + CapHeaderOffset = PCI_CAPBILITY_POINTER_OFFSET; + } + // + // Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list. + // + CapHeaderId = 0; + CapHeaderOffset = MmioRead8 (DeviceBase + CapHeaderOffset) & ((UINT8) ~(BIT0 | BIT1)); + while (CapHeaderOffset != 0 && CapHeaderId != 0xFF) { + CapHeaderId = MmioRead8 (DeviceBase + CapHeaderOffset); + if (CapHeaderId == CapId) { + if (CapHeaderOffset > PCI_MAXLAT_OFFSET) { + // + // Return valid capability offset + // + return CapHeaderOffset; + } else { + ASSERT((FALSE)); + return 0; + } + } + // + // Each capability must be DWORD aligned. + // The bottom two bits of all pointers (including the initial pointer at 34h) are reserved + // and must be implemented as 00b although software must mask them to allow for future uses of these bits. + // + CapHeaderOffset = MmioRead8 (DeviceBase + CapHeaderOffset + 1) & ((UINT8) ~(BIT0 | BIT1)); + } + return 0; + } +} + + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 = Advanced Error Reporting Capability + 0x0002 = Virtual Channel Capability + 0x0003 = Device Serial Number Capability + 0x0004 = Power Budgeting Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID + +**/ +UINT16 +PcieFindExtendedCapId ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ) +{ + UINT16 CapHeaderOffset; + UINT16 CapHeaderId; + UINTN DeviceBase; + + DeviceBase = MmPciBase (Bus, Device, Function); + + // + // Start to search at Offset 0x100 + // Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list. + // + CapHeaderId = 0; + CapHeaderOffset = R_PCH_PCIE_EXCAP_OFFSET; + while (CapHeaderOffset != 0 && CapHeaderId != DEVICE_ID_NOCARE) { + CapHeaderId = MmioRead16 (DeviceBase + CapHeaderOffset); + if (CapHeaderId == CapId) { + return CapHeaderOffset; + } + // + // Each capability must be DWORD aligned. + // The bottom two bits of all pointers are reserved and must be implemented as 00b + // although software must mask them to allow for future uses of these bits. + // + CapHeaderOffset = (MmioRead16 (DeviceBase + CapHeaderOffset + 2) >> 4) & ((UINT16) ~(BIT0 | BIT1)); + } + + return 0; +} + + +/** + This function returns PID according to Root Port Number + + @param[in] RpPort Root Port Number + + @retval SC_SBI_PID Returns PID for SBI Access + +**/ +SC_SBI_PID +GetRpSbiPid ( + IN UINTN RpPort + ) +{ + if (RpPort < 2) { + return 0xB3; + } else { + return 0xB4; + } +} + + +/** + This function reads Pci Config register via SBI Access + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[out] Data32 Value of Config register + + @retval EFI_SUCCESS SBI Read successful. + +**/ +EFI_STATUS +PchSbiRpPciRead32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + OUT UINT32 *Data32 + ) +{ + EFI_STATUS Status; + UINT8 Response; + UINT16 Fid; + + if (RpPort < 2) { + Fid = (UINT16) ((RpDevice << 3) | RpPort); + } else { + Fid = (UINT16) ((RpDevice << 3) | (RpPort - 2 )); + } + Status = PchSbiExecutionEx ( + GetRpSbiPid (RpPort), + Offset, + PciConfigRead, + FALSE, + 0xF, + 0, + Fid, + Data32, + &Response + ); + if (Status != EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR,"Side band Read Failed\n")); + } + return Status; +} + + +/** + This function And then Or Pci Config register via SBI Access + + @param[in] RpDevice Root Port Device Number + @param[in] RpPort Root Port Number + @param[in] Offset Offset of Config register + @param[in] Data32And Value of Config register to be And-ed + @param[in] Data32AOr Value of Config register to be Or-ed + + @retval EFI_SUCCESS SBI Read and Write successful. + +**/ +EFI_STATUS +PchSbiRpPciAndThenOr32 ( + IN UINTN RpDevice, + IN UINTN RpPort, + IN UINTN Offset, + IN UINT32 Data32And, + IN UINT32 Data32Or + ) +{ + EFI_STATUS Status; + UINT32 Data32; + UINT8 Response; + UINT16 Fid; + + Status = PchSbiRpPciRead32 (RpDevice, RpPort, Offset, &Data32); + if (Status == EFI_SUCCESS) { + Data32 &= Data32And; + Data32 |= Data32Or; + if (RpPort < 2) { + Fid = (UINT16) ((RpDevice << 3) | RpPort); + } else { + Fid = (UINT16) ((RpDevice << 3) | (RpPort - 2 )); + } + Status = PchSbiExecutionEx ( + GetRpSbiPid (RpPort), + Offset, + PciConfigWrite, + FALSE, + 0xF, + 0, + Fid, + &Data32, + &Response + ); + if (Status != EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Side band Write Failed\n")); + } + } + + return Status; +} + + +/** + This function returns the maximum number of ClkReq signals available + + @retval UINT8 Returns maximum number of ClkReq signals + +**/ +UINT8 +GetClkReqMax () +{ + return SC_PCIE_MAX_CLK_REQ; +} + + +/** + This returns ClkReq Number from Port Number + + @param[in] PortIndex PCIe Port Number (Zero Base) + + @retval ClkReq Number + +**/ +UINT8 +GetPortClkReqNumber ( + IN UINT8 PortIndex + ) +{ + UINT8 ClkReqNum; + + if (GetBxtSeries () == BxtP) { + if (PortIndex < 2) { + PortIndex += 4; + } else { + PortIndex -= 2; + } + } + PchPcrRead8 (0xB0, 0x100 + (PortIndex / 2), &ClkReqNum); + if (PortIndex % 2 == 0) { + ClkReqNum &= 0x0F; + } else { + ClkReqNum = ClkReqNum >> 4; + } + + return ClkReqNum; +} + + +/** + This function assigns a ClkReq signal to Pcie ports and returns updated ClkReq Number + + @param[in] PcieConfig PCH Pcie Configuration + @param[in] PortIndex PCIe Port Number (Zero Base) + + @retval EFI_SUCCESS Successfully set ClkReq Number to Root Port + +**/ +EFI_STATUS +SetPortClkReqNumber ( + IN SC_PCIE_CONFIG *PcieConfig, + IN UINT8 PortIndex + ) +{ +#ifdef EFI_DEBUG + UINT32 Drcrm1; +#endif + EFI_STATUS Status; + UINT8 ClkReqNum; + + Status = EFI_SUCCESS; + + ClkReqNum = (UINT8) PcieConfig->RootPort[PortIndex].ClkReqNumber; + // + // CLKREQ to Root Port Mapping + // The mapping of the PCIeExpress Ports to the CLKREQ# pins can be + // specified through the DRCRM{x} registers + // + if (GetBxtSeries () == BxtP) { + if (PortIndex < 2) { + PortIndex += 4; + } else { + PortIndex -= 2; + } + } + if (PortIndex % 2 == 0) { + PchPcrAndThenOr8 (0xB0, 0x100 + (PortIndex / 2), 0xF0, ClkReqNum); + } else { + PchPcrAndThenOr8 (0xB0, 0x100 + (PortIndex / 2), 0x0F, (ClkReqNum) << 4); + } +#ifdef EFI_DEBUG + PchPcrRead32 (0xB0, 0x100, &Drcrm1); + DEBUG ((DEBUG_INFO, "AssignClkReq = %0x\n", Drcrm1)); +#endif + + return Status; +} + + +/** + Set Common clock to Root port and Endpoint PCI device + + @param[in] Bus1 Root port Pci Bus Number + @param[in] Device1 Root port Pci Device Number + @param[in] Function1 Root port Pci Function Number + @param[in] Bus2 Endpoint Pci Bus Number + @param[in] Device2 Endpoint Pci Device Number + + @retval EFI_UNSUPPORTED Unsupported operation. + @retval EFI_SUCCESS VC mapping correctly initialized + +**/ +EFI_STATUS +PcieSetCommonClock ( + IN UINT8 Bus1, + IN UINT8 Device1, + IN UINT8 Function1, + IN UINT8 Bus2, + IN UINT8 Device2 + ) +{ + UINT8 CapOffset1; + UINT8 CapOffset2; + BOOLEAN CommonClockSupport; + EFI_STATUS Status; + UINTN DeviceBase1; + UINTN DeviceBase2; + UINT16 RegData16; + UINT8 FunctionIndex; + UINT8 Function2; + + DeviceBase1 = MmPciBase (Bus1, Device1, Function1); + + // + // Get the pointer to the Port PCI Express Capability Structure. + // + CommonClockSupport = FALSE; + CapOffset1 = PcieFindCapId (Bus1, Device1, Function1, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (CapOffset1 == 0) { + return EFI_UNSUPPORTED; + } + // + // Check the Port Slot Clock Configuration Bit. + // + if ((MmioRead16 (DeviceBase1 + CapOffset1 + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_SCC) == 0) { + return EFI_UNSUPPORTED; + } + + DeviceBase2 = MmPciBase (Bus2, Device2, 0); + // + // Check if EndPoint device is Multi-Function Device + // + if (MmioRead8 (DeviceBase2 + PCI_HEADER_TYPE_OFFSET) & HEADER_TYPE_MULTI_FUNCTION) { + // + // If multi-function Device, check function 0-7 + // + Function2 = PCI_MAX_FUNC; + } else { + // + // Otherwise, check function 0 only + // + Function2 = 0; + } + + for (FunctionIndex = 0; FunctionIndex <= Function2; FunctionIndex++) { + DeviceBase2 = MmPciBase (Bus2, Device2, FunctionIndex); + // + // Check the Endpoint Slot Clock Configuration Bit. + // + CapOffset2 = PcieFindCapId (Bus2, Device2, FunctionIndex, EFI_PCI_CAPABILITY_ID_PCIEXP); + if ((CapOffset2 != 0) && ((MmioRead16 (DeviceBase2 + CapOffset2 + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_SCC) != 0)) { + // + // Common clock is supported, set common clock bit on root port + // and the endpoint + // + if (CommonClockSupport == FALSE) { + MmioOr8 (DeviceBase1 + CapOffset1 + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_CCC); + CommonClockSupport = TRUE; + } + MmioOr8 (DeviceBase2 + CapOffset2 + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_CCC); + } + } + // + // If common clock not supported on root port and endpoint, return EFI_UNSUPPORTED + // + if (CommonClockSupport == FALSE) { + Status = EFI_UNSUPPORTED; + } else { + Status = EFI_SUCCESS; + } + // + // Retrain the Link per PCI Express Specification. + // + MmioOr8 (DeviceBase1 + CapOffset1 + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_RL); + + // + // Wait until Re-Training has completed. + // + do { + RegData16 = MmioRead16 (DeviceBase1 + CapOffset1 + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_LT; + } while (RegData16 != 0); + + return Status; +} + + +/** + This function checks whether PHY lane power gating is enable on the port. + + @param[in] RpBase Root Port base address + + @retval TRUE PHY power gating is enabled + @retval FALSE PHY power gating disabled + +**/ +STATIC +BOOLEAN +PcieIsPhyLanePgEnabled ( + IN UINTN RpBase + ) +{ + UINT32 Data32; + + Data32 = MmioRead32 (RpBase + 0x420); + return (Data32 & BIT30) != 0; +} + + +/** + This function enables the CLKREQ# PM on all the end point functions + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] RootDevice Rootport Device Number + @param[in] RootFunction Rootport Function Number + + @retval None + +**/ +VOID +PcieSetClkreq ( + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice, + IN UINT8 RootDevice, + IN UINT8 RootFunction + ) +{ + UINT8 CapOffset; + UINTN DeviceBase; + UINT8 FunctionIndex; + UINT8 Function; + BOOLEAN ClkreqPerPortSupported; + + DeviceBase = MmPciBase (EndPointBus, EndPointDevice, 0); + ClkreqPerPortSupported = TRUE; + + // + // Check if EndPoint device is Multi-Function Device + // + if (MmioRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_TYPE_MULTI_FUNCTION) { + // + // If multi-function Device, check function 0-7 + // + Function = PCI_MAX_FUNC; + } else { + // + // Otherwise, check function 0 only + // + Function = 0; + } + // + // Parse thro all the functions of the endpoint and find the PCIe Cap ID (offset 10h) and if + // exists then enable the CLKREQ# bit (BIT8) on that function + // + for (FunctionIndex = 0; FunctionIndex <= Function; FunctionIndex++) { + // + // Find the PCIe Cap Id (offset 10h) + // + CapOffset = PcieFindCapId (EndPointBus, EndPointDevice, FunctionIndex, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (CapOffset == 0) { + continue; + } + + DeviceBase = MmPciBase (EndPointBus, EndPointDevice, FunctionIndex); + // + // Check if CLKREQ# is supported by the endpoints + // + if ((MmioRead32 (DeviceBase + CapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_CPM) == 0) { + // + // CLKREQ# is not supported so dont do anything + // + ClkreqPerPortSupported = FALSE; + break; + } + } + + if (ClkreqPerPortSupported == FALSE) { + return; + } + // + // Now enable the CLKREQ# + // + for (FunctionIndex = 0; FunctionIndex <= Function; FunctionIndex++) { + // + // Find the PCIe Cap Id (offset 10h) + // + CapOffset = PcieFindCapId (EndPointBus, EndPointDevice, FunctionIndex, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (CapOffset == 0) { + continue; + } + + DeviceBase = MmPciBase (EndPointBus, EndPointDevice, FunctionIndex); + MmioOr16 (DeviceBase + CapOffset + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_ECPM); + } +} + + +/** + This function get or set the Max Payload Size on all the end point functions + + @param[in] EndPointBus The Bus Number of the Endpoint + @param[in] EndPointDevice The Device Number of the Endpoint + @param[in, out] MaxPayload The Max Payolad Size of the root port + @param[in] Operation True: Set the Max Payload Size on all the end point functions + False: Get the Max Payload Size on all the end point functions + + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +PcieMaxPayloadSize ( + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice, + IN OUT UINT16 *MaxPayload, + IN BOOLEAN Operation + ) +{ + UINTN DeviceBase; + UINT8 PcieCapOffset; + UINT16 EndPointMaxPayload; + UINT8 FunctionIndex; + UINT8 EndPointFunction; + + // + // Obtain the Max Payload Size for all the end point functions + // + DeviceBase = MmPciBase (EndPointBus, EndPointDevice, 0); + + // + // Check if EndPoint device is Multi-Function Device + // + if (MmioRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_TYPE_MULTI_FUNCTION) { + // + // If multi-function Device, check function 0-7 + // + EndPointFunction = PCI_MAX_FUNC; + } else { + // + // Otherwise, check function 0 only + // + EndPointFunction = 0; + } + + for (FunctionIndex = 0; FunctionIndex <= EndPointFunction; FunctionIndex++) { + DeviceBase = MmPciBase (EndPointBus, EndPointDevice, FunctionIndex); + if (MmioRead16 (DeviceBase + PCI_VENDOR_ID_OFFSET) != DEVICE_ID_NOCARE) { + // + // Get the pointer to the Endpoint PCI Express Capability Structure. + // + PcieCapOffset = PcieFindCapId (EndPointBus, EndPointDevice, FunctionIndex, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (PcieCapOffset == 0) { + continue; + } + + if (Operation == TRUE) { + // + // Set the Max Payload Size of the end point function + // + MmioAndThenOr16 ( + DeviceBase + PcieCapOffset + R_PCIE_DCTL_OFFSET, + (UINT16)~(BIT7 | BIT6 | BIT5), + *MaxPayload << 5 + ); + } else { + // + // Get the end point function Max Payload Size support + // + EndPointMaxPayload = MmioRead16 (DeviceBase + PcieCapOffset + R_PCIE_DCAP_OFFSET) & B_PCIE_DCAP_MPS; + // + // Obtain the minimum Max Payload Size between the PCIE root Port and the end point functions + // + if (*MaxPayload > EndPointMaxPayload) { + *MaxPayload = EndPointMaxPayload; + } + } + } + } + + return EFI_SUCCESS; +} + + +/** + This function disable the forwarding of EOI messages unless it discovers + an IOAPIC behind this root port. + + @param[in] RootBus The Bus Number of the root port + @param[in] RootDevice The Device Number of the root port + @param[in] RootFunction The Function Number of the root port + @param[in] EndPointBus The Bus Number of the Endpoint + @param[in] EndPointDevice The Device Number of the Endpoint + + @retval EFI_UNSUPPORTED Unsupported operation. + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +PcieSetEoiFwdDisable ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice + ) +{ + return 0; +} + +typedef enum { + CalculateAspm, + ManualAspm, + SetAspm +} OPERATION; + + +/** + This function compares the actual latency in LatencyValue1 + with actual latency in LatencyValue2 and stores the minimum + back to LatencyValue1, in the required format. + If this is the first call, then LatencyValue1 will be replaced by LatencyValue2. + + @param[in, out] LatencyValue1 Current latency value + @param[in] LatencyValue2 Latency value from the Table + + @retval None + +**/ +VOID +DetermineLatencyValue ( + IN OUT UINT16 *LatencyValue1, + IN UINT16 LatencyValue2 + ) +{ + ASSERT (LTR_SCALE_VALUE (*LatencyValue1) < 6); + ASSERT (LTR_SCALE_VALUE (LatencyValue2) < 6); + + // + // If there are more than one device behind a bridge that are part of the override table, + // store the lower latency value and corresponding scale bits back to LatencyValue1 + // + if ((LTR_LATENCY_NS (*LatencyValue1) == 0) || (LTR_LATENCY_NS (*LatencyValue1) > LTR_LATENCY_NS (LatencyValue2))) { + *LatencyValue1 = LatencyValue2; + } +} + + +/** + This function checks exit latency of L1 and L0s and disables the ASPM state if it is longer than + the acceptable latency. + + @param[in] EndPointBase End Point Base Address + @param[in] EndPointPcieCapOffset The pointer to the End Point PCI Express Capability Structure + @param[in] RootDeviceBase The Root Port PCI Express Base address + @param[in] RootPcieCapOffset The pointer to the Root Port PCI Express Capability Structure + @param[in, out] EndPointAspm End Point ASPM setting + + @retval None + +**/ +VOID AspmCheckExitLatency ( + IN UINTN EndPointBase, + IN UINT8 EndPointPcieCapOffset, + IN UINTN RootDeviceBase, + IN UINT32 RootPcieCapOffset, + IN OUT UINT16* EndPointAspm + ) +{ + UINT32 PortLxLat; + UINT32 EndPointLxLat; + UINT32 LxLat; + + // + // Check if L1 should be enabled based on port and endpoint L1 exit latency. + // + if ((*EndPointAspm) & BIT1) { + PortLxLat = MmioRead32 (RootDeviceBase + RootPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_EL1; + EndPointLxLat = MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_EL1; + + LxLat = PortLxLat; + if (PortLxLat < EndPointLxLat) { + LxLat = EndPointLxLat; + } + // + // check if the value is bigger than endpoint L1 acceptable exit latency, if it is + // larger than accepted value, then we should disable L1 + // + LxLat >>= N_PCIE_LCAP_EL1; + if (LxLat > ((MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_DCAP_OFFSET) & B_PCIE_DCAP_E1AL) >> N_PCIE_DCAP_E1AL)) { + (*EndPointAspm) &= ~BIT1; + } + } + // + // Check if L0s should be enabled based on port and endpoint L0s exit latency. + // + if ((*EndPointAspm) & BIT0) { + PortLxLat = MmioRead32 (RootDeviceBase + RootPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_EL0; + EndPointLxLat = MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_EL0; + + LxLat = PortLxLat; + if (PortLxLat < EndPointLxLat) { + LxLat = EndPointLxLat; + } + // + // check if the value is bigger than endpoint L0s acceptable exit latency, if it is + // larger than accepted value, then we should disable L0s + // + LxLat >>= N_PCIE_LCAP_EL0; + if (LxLat > ((MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_DCAP_OFFSET) & B_PCIE_DCAP_E0AL) >> N_PCIE_DCAP_E0AL)) { + (*EndPointAspm) &= ~BIT0; + } + } + + return; +} + + +/** + This function gets override Aspm values if the end point is found in the override look up table + + @param[in] EndPointBase End Point Base Address + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] EndPointVendorId End Point Vendor Id + @param[in] EndPointDeviceId End Point Device Id + @param[in] EndPointRevId End Point Revision Id + @param[in, out] EndPointAspm End Point ASPM setting + + @retval None + +**/ + +VOID GetOverrideAspm ( + IN UINTN EndPointBase, + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT16 EndPointVendorId, + IN UINT16 EndPointDeviceId, + IN UINT8 EndPointRevId, + IN OUT UINT16 *EndPointAspm + ) +{ + UINT8 EndPointBaseClassCode; + UINT8 EndPointSubClassCode; + UINT8 PcieDeviceIndex; + + // + // Mask APMC with values from lookup table. + // RevID of 0xFF applies to all steppings. + // + EndPointBaseClassCode = MmioRead8 (EndPointBase + R_PCI_BCC_OFFSET); + EndPointSubClassCode = MmioRead8 (EndPointBase + R_PCI_SCC_OFFSET); + for (PcieDeviceIndex = 0; PcieDeviceIndex < NumOfDevAspmOverride; PcieDeviceIndex++) { + if (((DevAspmOverride[PcieDeviceIndex].OverrideConfig & ScPcieL1L2Override) == ScPcieL1L2Override) && + ((DevAspmOverride[PcieDeviceIndex].VendorId == EndPointVendorId) || + (DevAspmOverride[PcieDeviceIndex].VendorId == 0xFFFF)) && + ((DevAspmOverride[PcieDeviceIndex].DeviceId == EndPointDeviceId) || + (DevAspmOverride[PcieDeviceIndex].DeviceId == 0xFFFF)) && + ((DevAspmOverride[PcieDeviceIndex].RevId == EndPointRevId) || + (DevAspmOverride[PcieDeviceIndex].RevId == 0xFF)) && + ((DevAspmOverride[PcieDeviceIndex].BaseClassCode == EndPointBaseClassCode) || + (DevAspmOverride[PcieDeviceIndex].BaseClassCode == 0xFF)) && + ((DevAspmOverride[PcieDeviceIndex].SubClassCode == EndPointSubClassCode) || + (DevAspmOverride[PcieDeviceIndex].SubClassCode == 0xFF))) { + *EndPointAspm = DevAspmOverride[PcieDeviceIndex].EndPointAspm; + break; + } + } +} + + +/** + This function gets override L1 Substate Capability offset pointer + if the end point is found in the override look up table + + @param[in] EndPointBase End Point Base Address + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] EndPointVendorId End Point Vendor Id + @param[in] EndPointDeviceId End Point Device Id + @param[in] EndPointRevId End Point Revision Id + @param[in, out] EndPointL1SubStateCapOffset Pointer to L1 Substate Capability Structure + @param[in, out] EndPointL1SubStateCapMask L1 Substate Capability Mask + + @retval None + +**/ + +VOID GetOverrideL1sCapOffset ( + IN UINTN EndPointBase, + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT16 EndPointVendorId, + IN UINT16 EndPointDeviceId, + IN UINT8 EndPointRevId, + IN OUT UINT16* EndPointL1SubStateCapOffset, + IN OUT UINT32* EndPointL1SubStateCapMask + ) +{ + UINT8 PcieDeviceIndex; + + // + // Get the endpoint supports L1 Substates Capabilities from Override Table + // + for (PcieDeviceIndex = 0; PcieDeviceIndex < NumOfDevAspmOverride; PcieDeviceIndex++) { + if (((DevAspmOverride[PcieDeviceIndex].OverrideConfig & ScPcieL1SubstatesOverride) == ScPcieL1SubstatesOverride) && + (EndPointVendorId == DevAspmOverride[PcieDeviceIndex].VendorId) && + (EndPointDeviceId == DevAspmOverride[PcieDeviceIndex].DeviceId) && + ((EndPointRevId == DevAspmOverride[PcieDeviceIndex].RevId) || + (DevAspmOverride[PcieDeviceIndex].RevId == 0xFF))) { + + if ((EndPointVendorId == V_INTEL_VENDOR_ID) && + ((EndPointDeviceId == 0x08B1) || (EndPointDeviceId == 0x08B2) || + (EndPointDeviceId == 0x08B3) || (EndPointDeviceId == 0x08B4)) + && ((MmioRead32(EndPointBase + DevAspmOverride[PcieDeviceIndex].L1SubstatesCapOffset) & 0xFFFF) != 0xCAFE)){ + continue; + } + *EndPointL1SubStateCapOffset = + DevAspmOverride[PcieDeviceIndex].L1SubstatesCapOffset; + *EndPointL1SubStateCapMask = + DevAspmOverride[PcieDeviceIndex].L1SubstatesCapMask; + break; + } + } +} + + +/** + This function configures the L1 Substates. + It can be used for Rootport and endpoint devices. + + @param[in] RootPortConfig Rootport PCI Express Configuration + @param[in] Bus Rootport/Endpoint Bus Number + @param[in] Device Rootport/Endpoint Device Number + @param[in] Function Rootport/Endpoint Function Number + @param[in] EndPointL1SubStateCapOffset Pointer to L1 Substate Capability Structure + @param[in] PortCommonModeRestoreTime Common Mode Restore Time + @param[in] PortTpowerOnValue Tpower_on Power On Wait Time + @param[in] PortTpowerOnScale Tpower-on Scale + + @retval None + +**/ +VOID ConfigureL1s ( + IN const SC_PCIE_ROOT_PORT_CONFIG* RootPortConfig, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINTN DeviceBase, + IN UINT16 L1SubstateExtCapOffset, + IN UINT32 PortCommonModeRestoreTime, + IN UINT32 PortTpowerOnValue, + IN UINT32 PortTpowerOnScale + ) +{ + UINT32 Data32Or; + UINT32 Data32; + UINT32 Tpoweron; + UINT8 ClkReqNum; + UINTN PortIndex; + + // + // Step 6 + // a. Set L1 Sub-States Extended Capability Offset + 0x08[4:0] to 01111b for both Pcie root port and device + // + Data32Or = (BIT3 | BIT2 | BIT1 | BIT0); + if (RootPortConfig->L1Substates == ScPcieL1SubstatesL1_1) { + Data32Or &= (UINT32) ~(BIT0); + } + if (RootPortConfig->L1Substates == ScPcieL1SubstatesL1_2) { + Data32Or &= (UINT32) ~(BIT1); + } + MmioAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, + (UINT32) ~(BIT4 | BIT3 | BIT2 | BIT1 | BIT0), + Data32Or + ); + // + // b. Read L1 Sub-States Extended Capability Offset + 0x04[15:8], and Set the highest value advertised + // between PCIe rootport and device to L1 Sub-States Extended Capability Offset + 0x08[15:8] on both + // Pcie root port and device. + // + MmioAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, + (UINT32) ~(0xFF00), + (UINT32) PortCommonModeRestoreTime << 8 + ); + // + // c. Read L1 Sub-States Extended Capability Offset + 0x04[23:19] and [17:16], and Set the highest value + // advertised between PCIe root port and device to L1 Sub-States Extended Capability Offset + 0x0C [7:0] on + // both Pcie root port and device. + // + MmioAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_OFFSET, + 0xFFFFFF04, + (UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerOnScale) + ); + // + // d. Set L1 Sub-States Extended Capability Offset + 0x08[31:29] to 010b for both Pcie root port and device + // e. Set L1 Sub-States Extended Capability Offset + 0x08[25:16] to 0010100000b for both Pcie root port and device + // + MmioAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, + (UINT32) ~(0xE3FF0000), + (UINT32) (BIT30 | BIT23 | BIT21) + ); + + // + // If Root port, + // + if (Bus == DEFAULT_PCI_BUS_NUMBER_SC) { + GetScPcieRpNumber (Device, Function, &PortIndex); + ClkReqNum = GetPortClkReqNumber ((UINT8) PortIndex); + // + // f. Set Dxx:Fn:420h[0] to 1b prior to L1 enabling + // + MmioOr32 (DeviceBase + 0x420, BIT0); + // + // g. Set PCR[PCLKD] +1010h[23:0] to a value (in time unit) bigger than Tpoweron from step c. + // For the hotplug port but empty, set it to 45us just in case SMI is not enabled to handle this. + // + Tpoweron = PortTpowerOnValue * mPcieL1sTposMultiplier[PortTpowerOnScale]; + Data32 = 0; + if ((MmioRead16 (DeviceBase + R_PCH_PCIE_SLSTS) & B_PCIE_SLSTS_PDS) != 0) { + while ((Tpoweron > mPclkdL1trefCfg[Data32]) && (Data32 < 15)) { + Data32++; + } + } else { + Data32 = 9; + } + Data32 = (Data32 << (4 * ClkReqNum)); + SideBandAndThenOr32 (0xB6, 0x1010, ~0u, Data32); + } +} + + +/** + This function gets the Latency Tolerance Reporting settings from override table + if the end point is found in the override look up table + + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] EndPointVendorId End Point Vendor Id + @param[in] EndPointDeviceId End Point Device Id + @param[in] EndPointRevId End Point Revision Id + @param[in, out] LtrOverrideVal Snoop and Non Snoop Latency Values + + @retval None + +**/ +VOID GetLtrOverride ( + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT16 EndPointVendorId, + IN UINT16 EndPointDeviceId, + IN UINT8 EndPointRevId, + IN OUT UINT32 *LtrOverrideVal + ) +{ + UINT8 PcieDeviceIndex; + UINT16 Data16; + UINT32 Data32; + + // + // For each device detected, scan the LTR override table + // If there are endpoints connected directly to the rootport then + // LtrOverrideVal will be replaced by the value from the table for that endpoint + // If there are endpoints that are behind a bridge and that are also part of the table then + // LtrOverrideVal will maintain the minimum of all such values. + // A non zero value of LtrOverrideVal will indicate: + // i):That there is atleast one entry in the LTR override Table + // ii):The final value to be programmed in offset 0x400. This value will be applied for all the devices + // connected to this root port + // + Data32 = *LtrOverrideVal; + for (PcieDeviceIndex = 0; PcieDeviceIndex < NumOfDevAspmOverride; PcieDeviceIndex++) { + if (((DevAspmOverride[PcieDeviceIndex].OverrideConfig & ScPcieLtrOverride) == ScPcieLtrOverride) && + (DevAspmOverride[PcieDeviceIndex].VendorId == EndPointVendorId) && + ((DevAspmOverride[PcieDeviceIndex].DeviceId == EndPointDeviceId) || + (DevAspmOverride[PcieDeviceIndex].DeviceId == 0xFFFF)) && + ((DevAspmOverride[PcieDeviceIndex].RevId == EndPointRevId) || + (DevAspmOverride[PcieDeviceIndex].RevId == 0xFF))) { + // + // Get the Non-Snoop latency value from the table, compare and store the minimum + // + if (DevAspmOverride[PcieDeviceIndex].NonSnoopLatency & BIT15) { + Data16 = (UINT16) ((Data32 & 0xFFFF0000) >> 16); + DetermineLatencyValue ( + &Data16, + DevAspmOverride[PcieDeviceIndex].NonSnoopLatency); + Data32 = (Data32 & 0xFFFF) | ((UINT32) (Data16 << 16)); + } + // + // Get the Snoop latency value from the table, compare and store the minimum + // + if (DevAspmOverride[PcieDeviceIndex].SnoopLatency & BIT15) { + Data16 = (UINT16) (Data32 & 0xFFFF); + DetermineLatencyValue ( + &Data16, + DevAspmOverride[PcieDeviceIndex].SnoopLatency); + Data32 = (Data32 & 0xFFFF0000) | (UINT32) Data16; + } + *LtrOverrideVal = Data32; + break; + } + } + + return; +} + + +/** + This function configures the Latency Tolerance Reporting Settings for endpoint devices + + @param[in] RootPortConfig Rootport PCI Express Configuration + @param[in] EndPointBus Endpoint Bus Number + @param[in] EndPointDevice Endpoint Device Number + @param[in] EndPointFunction Endpoint Function Number + @param[in] EndPointBase Endpoint PCI Express Address + @param[in] EndPointPcieCapOffset Pointer to Endpoint PCI Express Capability Structure + @param[in] DeviceCapabilities2 Endpoint Value of Device Capabilities 2 Register (PciE Cap offset + 0x24) + @param[in] PchSeries Pch Series + @param[in] LtrOverrideVal Snoop and Non Snoop Latency Values + + @retval None + +**/ +VOID ConfigureLtr ( + IN const SC_PCIE_ROOT_PORT_CONFIG* RootPortConfig, + IN UINT8 EndPointBus, + IN UINT8 EndPointDevice, + IN UINT8 EndPointFunction, + IN UINTN EndPointBase, + IN UINT8 EndPointPcieCapOffset, + IN UINT32 DeviceCapabilities2, + IN UINT32* LtrOverrideVal + ) +{ + UINT32 Data32; + UINT16 Data16; + UINT16 LtrExtendedCapOffset; + UINT16 DefaultMaxLatency; + + DefaultMaxLatency = 0; + + // + // Step 3 + // If Endpoint device supports LTR, Device Capabilities 2 Register Offset 24h [11] = 1b, + // + if ((DeviceCapabilities2 & B_PCIE_DCAP2_LTRMS) && (RootPortConfig->LtrEnable == TRUE)) { + // + // Step 3.1 + // Program Endpoint LTR Mechanism Enable, Device Control 2 Register Offset 28h [10] = 1b + // when device supports LTR but is not found in override table (table listing correct + // latency requirements for devices that supports LTR and also for devices that do not + // support LTR). + // + MmioOr16 (EndPointBase + EndPointPcieCapOffset + R_PCIE_DCTL2_OFFSET, B_PCIE_DCTL2_LTREN); + } + // + // Get the pointer to the Endpoint PCI Express Extended Capability Structure + // and configure the Max Snoop and Max No-Snoop Latency for the endpoint + // + LtrExtendedCapOffset = PcieFindExtendedCapId (EndPointBus, + EndPointDevice, + EndPointFunction, + R_PCH_PCIE_LTRECH_CID); + if (LtrExtendedCapOffset != 0) { + Data32 = *LtrOverrideVal; + // + // Step 3.2 + // If B0:Dxx:Fn + 400h is not programmed with snoop latency override value, + // program endpoint max snoop latency register, Latency Tolerance Reporting (LTR) + // Capability Offset 04h [15:0] = 1003h + // + DefaultMaxLatency = RootPortConfig->LtrMaxSnoopLatency; + Data16 = (UINT16) (Data32 & 0xFFFF); + // + // Set the max snoop latency to either the default max snoop latency or to the snoop latency override value + // that is being programmed for this root port + // + DetermineLatencyValue (&Data16, DefaultMaxLatency); + MmioAndThenOr16 (EndPointBase + LtrExtendedCapOffset + R_PCH_PCIE_LTRECH_MSLR_OFFSET, + (UINT16) (~0x1FFF), + Data16); + // + // Step 3.3 + // If B0:Dxx:Fn + 400h is not programmed with non-snoop latency override value, + // program endpoint max non-snoop Latency Register, Latency Tolerance Reporting (LTR) + // Capability Offset 06h [15:0] = 1003h + // + DefaultMaxLatency = RootPortConfig->LtrMaxNoSnoopLatency; + Data16 = (UINT16) ((Data32 & 0xFFFF0000) >> 16); + DetermineLatencyValue (&Data16, DefaultMaxLatency); + MmioAndThenOr16 ( + EndPointBase + LtrExtendedCapOffset + R_PCH_PCIE_LTRECH_MNSLR_OFFSET, + (UINT16) (~0x1FFF), + Data16); + // + // Step 4 + // If not all devices support LTR + // Program PWRMBASE + 20h = 00010003h + // (Note this register should be saved and restored during S3 transitions) + // Done in PchPcieSmm.c PchPciePmIoTrapSmiCallback () + // + } +} + + +/** + Calculate/Set EndPoint device Power management settings + + @param[in] RootDeviceBase The Root Port PCI Express address + @param[in] RootPcieCapOffset The pointer to the Root Port PCI Express Capability Structure + @param[in] EndPointBus The Bus Number of the Endpoint + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in, out] LinkAspmVal Resulting Link ASPM value programmed + @param[in] Operation Operation Types + @param[in, out] LtrOverrideVal Resulting LTR override value to be programmed + @param[in] RootL1SubstateExtCapOffset The register offset of Root Port L1 Substates + @param[in, out] L1SubstatesSupported Input and return the result of L1 Substates support + @param[in, out] PortCommonModeRestoreTime Input and return common mode restore time of L1 Substate setting + @param[in, out] PortTpowerOnValue Input and return power on value of L1 Substate setting + @param[in, out] PortTpowerOnScale Input and return power on scale of L1 Substate setting + @param[in] RootPortConfig Pcie Power Optimizer Configuration + @param[in, out] AspmOverride Input and return the Aspm Override enable for pre-1.1 devices + @param[in, out] ClkreqPerPortSupported Input to check if clkreq per port is supportted + @param[in, out] RpAndEndPointsLtrSupported Input to check if LTR per port is supportted + @param[in] PolicyRevision Policy revision for codes compatibility + + @retval EFI_SUCCESS Successfully completed + @retval EFI_NOT_FOUND Can not find device + + @retval EFI_OUT_OF_RESOURCES The endpoint device is a bridge, but the Subordinate Bus Number of + the root port is not greater than its Secondary Bus Number. You may + get this error if PCI emulation is not done before this function gets + called and the Policy settings of "TempRootPortBusNumMax" and + "TempRootPortBusNumMin" do not provide enough resource for temp bus + number usage. +**/ +EFI_STATUS +PcieEndPointPm ( + IN UINTN RootDeviceBase, + IN UINT32 RootPcieCapOffset, + IN UINT8 EndPointBus, + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN OUT UINT16 *LinkAspmVal, + IN OPERATION Operation, + IN OUT UINT32 *LtrOverrideVal, + IN UINT16 RootL1SubstateExtCapOffset, + IN OUT BOOLEAN *L1SubstatesSupported, + IN OUT UINT32 *PortCommonModeRestoreTime, + IN OUT UINT32 *PortTpowerOnValue, + IN OUT UINT32 *PortTpowerOnScale, + IN CONST SC_PCIE_ROOT_PORT_CONFIG *RootPortConfig, + IN OUT BOOLEAN *AspmOverride, + IN BOOLEAN *ClkreqPerPortSupported, + IN OUT BOOLEAN *RpAndEndPointsLtrSupported, + IN UINT8 PolicyRevision + ) +{ + EFI_STATUS Status; + UINTN EndPointBase; + UINT8 EndPointFunction; + UINT8 EndPointPcieCapOffset; + UINT16 EndPointAspm; + UINT16 EndPointVendorId; + UINT16 EndPointDeviceId; + UINT8 EndPointRevId; + UINT8 DownStreamBusMin; + UINT8 ClassCode; + UINT8 RootDevSubBusNum; + BOOLEAN BusAssign; + UINT8 DeviceIndex; + UINT8 FunctionIndex; + UINT32 DeviceCapabilities2; + UINT16 EndPointL1SubStateCapOffset; + UINT32 RootDeviceL1Substates; + UINT32 EndPointL1Substates; + UINT8 EndPointPortCommonModeRestoreTime; + UINT8 EndPointTpowerOnScale; + UINT8 EndPointTpowerOnValue; + UINT32 Multiplier[4] = {2, 10, 100, 0}; + UINT32 EndPointL1SubStateCapMask; + + DEBUG ((DEBUG_INFO, "PcieEndPointPm () Start EndPointBus %0x\n", EndPointBus)); + for (DeviceIndex = 0; DeviceIndex <= PCI_MAX_DEVICE; DeviceIndex++) { + EndPointBase = MmPciBase (EndPointBus, DeviceIndex, 0); + if (MmioRead16 (EndPointBase + PCI_VENDOR_ID_OFFSET) == DEVICE_ID_NOCARE) { + continue; + } + // + // Check if EndPoint device is Multi-Function Device + // + if (MmioRead8 (EndPointBase + PCI_HEADER_TYPE_OFFSET) & HEADER_TYPE_MULTI_FUNCTION) { + // + // If multi-function Device, check function 0-7 + // + EndPointFunction = PCI_MAX_FUNC; + } else { + // + // Otherwise, check function 0 only + // + EndPointFunction = 0; + } + + for (FunctionIndex = 0; FunctionIndex <= EndPointFunction; FunctionIndex++) { + EndPointBase = MmPciBase (EndPointBus, DeviceIndex, FunctionIndex); + if (MmioRead16 (EndPointBase + PCI_VENDOR_ID_OFFSET) == DEVICE_ID_NOCARE) { + continue; + } + // + // Get the pointer to the Endpoint PCI Express Capability Structure. + // + EndPointPcieCapOffset = PcieFindCapId (EndPointBus, DeviceIndex, FunctionIndex, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (EndPointPcieCapOffset == 0) { + return EFI_NOT_FOUND; + } + EndPointVendorId = MmioRead16 (EndPointBase + PCI_VENDOR_ID_OFFSET); + EndPointDeviceId = MmioRead16 (EndPointBase + PCI_DEVICE_ID_OFFSET); + EndPointRevId = MmioRead8 (EndPointBase + PCI_REVISION_ID_OFFSET); + EndPointL1SubStateCapOffset = 0; + EndPointL1SubStateCapMask = 0x0000001F; + RootDeviceL1Substates = 0; + EndPointL1Substates = 0; + // + // Get the endpoint supports L1 Substates Capabilities + // + GetOverrideL1sCapOffset ( + EndPointBase, + NumOfDevAspmOverride, + DevAspmOverride, + EndPointVendorId, + EndPointDeviceId, + EndPointRevId, + &EndPointL1SubStateCapOffset, + &EndPointL1SubStateCapMask + ); + if (EndPointL1SubStateCapOffset == 0) { + EndPointL1SubStateCapOffset = PcieFindExtendedCapId ( + EndPointBus, + DeviceIndex, + FunctionIndex, + V_PCIE_EX_L1S_CID + ); + } + if (EndPointL1SubStateCapOffset != 0) { + RootDeviceL1Substates = MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET); + EndPointL1Substates = MmioRead32 (EndPointBase + EndPointL1SubStateCapOffset + R_PCIE_EX_L1SCAP_OFFSET); + } + DeviceCapabilities2 = MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_DCAP2_OFFSET); + if (((DeviceCapabilities2 & B_PCIE_DCAP2_LTRMS) == 0) || (RootPortConfig->LtrEnable != TRUE)) { + *RpAndEndPointsLtrSupported = FALSE; + } + // + // Configure downstream device if present. + // + if (Operation == CalculateAspm || Operation == ManualAspm) { + if ((MmioRead32 (EndPointBase + EndPointPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_CPM) != B_PCIE_LCAP_CPM) { + *ClkreqPerPortSupported = FALSE; + } + EndPointAspm = (MmioRead16 (EndPointBase + EndPointPcieCapOffset + R_PCIE_LCAP_OFFSET) >> N_PCIE_LCAP_APMS) & 3; + DEBUG ((DEBUG_INFO, "Endpoint Device %0x Capability ASPM: %0x\n", DeviceIndex, EndPointAspm)); + if (Operation == CalculateAspm) { + // + // Check endpoint for pre-1.1 devices based on the Role based Error Reporting Capability bit + // and enable Aspm Override + // + if (!(MmioRead16 (EndPointBase + EndPointPcieCapOffset + R_PCIE_DCAP_OFFSET) & BIT15)) { + DEBUG((DEBUG_INFO, "Override root port ASPM to L1 for pre-1.1 devices\n")); + *AspmOverride = TRUE; + } + GetOverrideAspm ( + EndPointBase, + NumOfDevAspmOverride, + DevAspmOverride, + EndPointVendorId, + EndPointDeviceId, + EndPointRevId, + &EndPointAspm + ); + + AspmCheckExitLatency ( + EndPointBase, + EndPointPcieCapOffset, + RootDeviceBase, + RootPcieCapOffset, + &EndPointAspm + ); + } + + *LinkAspmVal &= EndPointAspm; + DEBUG ((DEBUG_INFO, "Calculate Endpoint Device %0x Aspm Value: %0x\n", DeviceIndex, EndPointAspm)); + // + // Check if the endpoint supports L1 Substates Capabilities + // + if ((EndPointL1SubStateCapOffset != 0) && (RootL1SubstateExtCapOffset != 0)) { + // + // If both Root and endpoint's L1 Sub-States Extended Capability Offset + 0x04[4:0] are 11111b, + // a. Read L1 Sub-States Extended Capability Offset + 0x04[15:8], and program the highest value advertised + // between PCIe rootport and device to L1 Sub-States Extended Capability Offset + 0x08[15:8] on + // Pcie root port. + // b. Read L1 Sub-States Extended Capability Offset + 0x04[23:19] and [17:16], and program the highest value + // advertised between PCIe root port and device.to L1 Sub-States Extended Capability Offset + 0x08 [7:0] on + // both Pcie root port and device. + // c. Program L1 Sub-States Extended Capability Offset + 0x08[31:29] to 010b for both Pcie root port and device + // d. Program L1 Sub-States Extended Capability Offset + 0x08[25:16] to 0010100000b for both Pcie root port and device + // e. Program L1 Sub-States Extended Capability Offset + 0x08[4:0] to 01111b for both Pcie root port and device + // + if (((RootDeviceL1Substates & 0x1F) == 0x1F) && + ((EndPointL1Substates & EndPointL1SubStateCapMask) == EndPointL1SubStateCapMask) && + (RootPortConfig->L1Substates != ScPcieL1SubstatesDisabled)) + { + *L1SubstatesSupported = TRUE; + EndPointPortCommonModeRestoreTime = (EndPointL1Substates >> 8) & 0xFF; + EndPointTpowerOnScale = (EndPointL1Substates >> 16) & 0x3; + EndPointTpowerOnValue = (EndPointL1Substates >> 19) & 0x1F; + + if (EndPointPortCommonModeRestoreTime > *PortCommonModeRestoreTime) { + *PortCommonModeRestoreTime = EndPointPortCommonModeRestoreTime; + } + + if ((EndPointTpowerOnValue * Multiplier[EndPointTpowerOnScale]) > + (*PortTpowerOnValue * Multiplier[*PortTpowerOnScale])) { + *PortTpowerOnValue = EndPointTpowerOnValue; + *PortTpowerOnScale = EndPointTpowerOnScale; + } + } + } + // + // For each device detected, scan the LTR override table + // If there are endpoints connected directly to the rootport then + // LtrOverrideVal will be replaced by the value from the table for that endpoint + // If there are endpoints that are behind a bridge and that are also part of the table then + // LtrOverrideVal will maintain the minimum of all such values. + // A non zero value of LtrOverrideVal will indicate: + // i):That there is atleast one entry in the LTR override Table + // ii):The final value to be programmed in offset 0x400. This value will be applied for all the devices + // connected to this root port + // + GetLtrOverride ( + NumOfDevAspmOverride, + DevAspmOverride, + EndPointVendorId, + EndPointDeviceId, + EndPointRevId, + LtrOverrideVal + ); + } else if (Operation == SetAspm) { + if ((EndPointL1SubStateCapOffset != 0) && (*L1SubstatesSupported)) { + if (((RootDeviceL1Substates & 0x1F) == 0x1F) && + ((EndPointL1Substates & EndPointL1SubStateCapMask) == EndPointL1SubStateCapMask)) { + ConfigureL1s ( + RootPortConfig, + EndPointBus, + DeviceIndex, + FunctionIndex, + EndPointBase, + EndPointL1SubStateCapOffset, + *PortCommonModeRestoreTime, + *PortTpowerOnValue, + *PortTpowerOnScale + ); + } + } + // + // Write it to the Link Control register + // + DEBUG ((DEBUG_INFO, "Program Endpoint Device %0x Aspm Value: %0x\n", DeviceIndex, *LinkAspmVal)); + MmioAndThenOr16 (EndPointBase + EndPointPcieCapOffset + R_PCIE_LCTL_OFFSET, (UINT16)~B_PCIE_LCTL_ASPM, *LinkAspmVal); + // + // Step 3 + // + ConfigureLtr ( + RootPortConfig, + EndPointBus, + DeviceIndex, + FunctionIndex, + EndPointBase, + EndPointPcieCapOffset, + DeviceCapabilities2, + LtrOverrideVal + ); + + } + // + // Check if this device is a bridge + // + ClassCode = MmioRead8 (EndPointBase + R_PCI_BCC_OFFSET); + + if (ClassCode == PCI_CLASS_BRIDGE) { + // + // Get the downstream Bus number + // + DownStreamBusMin = MmioRead8 (EndPointBase + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + // + // If the Secondary Bus Number of endpoint device is not assigned + // + if (DownStreamBusMin == 0) { + RootDevSubBusNum = MmioRead8 (RootDeviceBase + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); + // + // If the endpoint device is a bridge, the Subordinate Bus Number of the root port will need to be greater + // than the Secondary Bus Number of the root port (the Bus Number of endpoint device). + // + if (RootDevSubBusNum > EndPointBus) { + // + // Assign the Primary, Secondary and Subordinate Bus Number to endpoint device + // + MmioAndThenOr32 ( + EndPointBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, + 0xFF000000, + EndPointBus | (((UINT32) (EndPointBus + 1) << 8)) | ((UINT32) (RootDevSubBusNum << 16)) + ); + DownStreamBusMin = EndPointBus + 1; + } else { + return EFI_OUT_OF_RESOURCES; + } + + BusAssign = FALSE; + } else { + BusAssign = TRUE; + } + + if (DownStreamBusMin > EndPointBus) { + Status = PcieEndPointPm ( + RootDeviceBase, + RootPcieCapOffset, + DownStreamBusMin, + NumOfDevAspmOverride, + DevAspmOverride, + LinkAspmVal, + Operation, + LtrOverrideVal, + RootL1SubstateExtCapOffset, + L1SubstatesSupported, + PortCommonModeRestoreTime, + PortTpowerOnValue, + PortTpowerOnScale, + RootPortConfig, + AspmOverride, + ClkreqPerPortSupported, + RpAndEndPointsLtrSupported, + PolicyRevision + ); + if (Status == EFI_NOT_FOUND) { + DEBUG ((DEBUG_INFO, "Check DownStreamBus:%d and no device found!\n", DownStreamBusMin)); + } + + if (BusAssign == FALSE) { + // + // Clear Bus Numbers. + // + MmioAnd32 (EndPointBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, 0xFF000000); + } + } + } + } + } + + return EFI_SUCCESS; +} + + +/** + This function checks if the root port and downstream device support Clkreq per port, ASPM L1 and L1 substates + + @param[in] RootBus Pci Bus Number of the root port + @param[in] RootDevice Pci Device Number of the root port + @param[in] RootFunction Pci Function Number of the root port + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary + bus number) and its down stream switches + @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate + bus number) and its down stream switches + @param[in] RootPortConfig Pcie Power Optimizer Configuration + @param[in, out] L1SubstatesSupported Flag to indicate if L1 Substates are supported + @param[in] PolicyRevision Revision of the policy + @param[in, out] AspmVal Aspm value for both rootport and end point devices + @param[in, out] ClkreqPerPortSupported Clkreq support for both rootport and endpoint devices + @param[out] LtrSupported Check and return if all endpoints support LTR + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found + +**/ +EFI_STATUS +PcieCheckPmConfig ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT32 NumOfDevAspmOverride, + IN SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT8 TempBusNumberMin, + IN UINT8 TempBusNumberMax, + IN CONST SC_PCIE_ROOT_PORT_CONFIG *RootPortConfig, + IN OUT BOOLEAN *L1SubstatesSupported, + IN UINT8 PolicyRevision, + IN OUT UINT16 *AspmVal, + IN OUT BOOLEAN *ClkreqPerPortSupported, + OUT BOOLEAN *LtrSupported + ) +{ + EFI_STATUS Status; + UINTN RootDeviceBase; + UINT32 RootPcieCapOffset; + UINT8 EndPointBus; + OPERATION Operation; + UINT16 SlotStatus; + BOOLEAN BusAssign; + UINT32 LtrOvrVal; + UINT16 RootL1SubstateExtCapOffset; + UINT32 PortCommonModeRestoreTime; + UINT32 PortTpowerOnValue; + UINT32 PortTpowerOnScale; + BOOLEAN AspmOverride; + + DEBUG ((DEBUG_INFO, "PcieCheckPmConfig () Start BDF: %0x : %0x : %0x\n", RootBus, RootDevice, RootFunction)); + Status = EFI_SUCCESS; + RootDeviceBase = MmPciBase (RootBus, RootDevice, RootFunction); + PortCommonModeRestoreTime = 0; + PortTpowerOnValue = 0; + PortTpowerOnScale = 0; + *L1SubstatesSupported = FALSE; + AspmOverride = FALSE; + *ClkreqPerPortSupported = FALSE; + + if (MmioRead16 (RootDeviceBase + PCI_VENDOR_ID_OFFSET) == DEVICE_ID_NOCARE) { + return EFI_NOT_FOUND; + } + + // + // Assume CLKREQ# is supported on the port if PHY lane power gating is already enabled. + // + *ClkreqPerPortSupported = PcieIsPhyLanePgEnabled (RootDeviceBase); + + // + // Get the pointer to the Port PCI Express Capability Structure. + // + RootPcieCapOffset = PcieFindCapId (RootBus, RootDevice, RootFunction, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (RootPcieCapOffset == 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + *AspmVal = (MmioRead16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_LCAP_OFFSET) >> N_PCIE_LCAP_APMS) & 3; + if (RootPortConfig->Aspm == ScPcieAspmAutoConfig) { + Operation = CalculateAspm; + } else { + Operation = ManualAspm; + *AspmVal &= RootPortConfig->Aspm; + } + + // + // Get the downstream Bus number + // + EndPointBus = MmioRead8 (RootDeviceBase + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + + // + // If the Secondary Bus Number of the root port is not assigned + // Note: + // It will be better that PCI emulation has been done before PcieSetPm(). Or, you will need to assign + // a larger number to TempRootPortBusNumMax to support the specific card which has many bridges behind. + // If it is not, the Policy settings of "TempRootPortBusNumMax" and "TempRootPortBusNumMin" + // will be assigned to the Subordinate and Secondary Bus Number of the root ports. + // The assigned bus number will be cleared in the end of PcieSetPm(). + // + if (EndPointBus == 0) { + MmioAndThenOr32 ( + RootDeviceBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, + 0xFF0000FF, + ((UINT32) (TempBusNumberMin << 8)) | ((UINT32) (TempBusNumberMax << 16)) + ); + EndPointBus = TempBusNumberMin; + BusAssign = FALSE; + } else { + BusAssign = TRUE; + } + + // + // Check whether the slot has a device connected + // + SlotStatus = MmioRead16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_SLSTS_OFFSET); + LtrOvrVal = 0; + + RootL1SubstateExtCapOffset = 0; + RootL1SubstateExtCapOffset = PcieFindExtendedCapId (RootBus, RootDevice, RootFunction, V_PCIE_EX_L1S_CID); + if (RootL1SubstateExtCapOffset != 0) { + PortCommonModeRestoreTime = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 8) & 0xFF; + PortTpowerOnScale = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 16) & 0x3; + PortTpowerOnValue = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 19) & 0x1F; + } + + // + // Obtain initial ASPM settings from respective port capability registers. + // Scan LTR override table for device match and calculate the lowest override + // value to be programmed into PCIE RP PCI offset 400h + // + if (EndPointBus != 0 && (SlotStatus & BIT6) != 0) { + Status = PcieEndPointPm ( + RootDeviceBase, + RootPcieCapOffset, + EndPointBus, + NumOfDevAspmOverride, + DevAspmOverride, + AspmVal, + Operation, + &LtrOvrVal, + RootL1SubstateExtCapOffset, + L1SubstatesSupported, + &PortCommonModeRestoreTime, + &PortTpowerOnValue, + &PortTpowerOnScale, + RootPortConfig, + &AspmOverride, + ClkreqPerPortSupported, + LtrSupported, + PolicyRevision + ); + } + + if (BusAssign == FALSE) { + // + // Clear Bus Numbers. + // + MmioAnd32 (RootDeviceBase + 0x018, 0xFF0000FF); + } + return Status; +} + + +/** + This function performs the Power Management settings for root port and downstream device + + @param[in] RootBus Pci Bus Number of the root port + @param[in] RootDevice Pci Device Number of the root port + @param[in] RootFunction Pci Function Number of the root port + @param[in] NumOfDevAspmOverride Number of Device specific ASPM policy override items + @param[in] DevAspmOverride Pointer to array of Device specific ASPM policy override items + @param[in] TempBusNumberMin Minimal temp bus number that can be assigned to the root port (as secondary + bus number) and its down stream switches + @param[in] TempBusNumberMax Maximal temp bus number that can be assigned to the root port (as subordinate + bus number) and its down stream switches + @param[in] RootPortConfig Pcie Power Optimizer Configuration + @param[in, out] L1SubstatesSupported Flag to indicate if L1 Substates are supported + @param[in] PolicyRevision Policy revision for codes compatibility + @param[in] FirstRpToSetPm Indicates if this is the first root port to be set + @param[in] L1SupportedInAllEnabledPorts Check if L1 is supported in all enabled ports + @param[in] ClkreqSupportedInAllEnabledPorts Check if clkreq is supported in all enabled ports + @param[out] LtrSupported Check and return if all endpoints support LTR + @param[in] AllowRpAspmProgramming Allow fine grain control on when the RP ASPM programming is to be done, + particularly used by the RST PCIe storage remapping feature + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_UNSUPPORTED The pointer to the Port PCI Express Capability Structure is not found + +**/ +EFI_STATUS +PcieSetPm ( + IN UINT8 RootBus, + IN UINT8 RootDevice, + IN UINT8 RootFunction, + IN UINT32 NumOfDevAspmOverride, + IN CONST SC_PCIE_DEVICE_OVERRIDE *DevAspmOverride, + IN UINT8 TempBusNumberMin, + IN UINT8 TempBusNumberMax, + IN CONST SC_PCIE_ROOT_PORT_CONFIG *RootPortConfig, + IN OUT BOOLEAN *L1SubstatesSupported, + IN UINT8 PolicyRevision, + IN BOOLEAN FirstRPToSetPm, + IN BOOLEAN L1SupportedInAllEnabledPorts, + IN BOOLEAN ClkreqSupportedInAllEnabledPorts, + OUT BOOLEAN *LtrSupported, + IN BOOLEAN AllowRpAspmProgramming + ) +{ + UINT16 AspmVal; + EFI_STATUS Status; + UINTN RootDeviceBase; + UINT32 RootPcieCapOffset; + UINT8 EndPointBus; + OPERATION Operation; + UINT16 SlotStatus; + BOOLEAN BusAssign; + UINT32 DeviceCapabilities2; + UINT32 LtrOvrVal; + UINT32 Data32And; + UINT32 Data32Or; + BOOLEAN ClkreqPerPortSupported; + UINT16 RootL1SubstateExtCapOffset; + UINT32 PortCommonModeRestoreTime; + UINT32 PortTpowerOnValue; + UINT32 PortTpowerOnScale; + BOOLEAN AspmOverride; + UINTN PortIndex; + UINT8 FirstRpIndex; + + DEBUG ((DEBUG_INFO, "PcieSetPm () Start BDF: %0x : %0x : %0x\n", RootBus, RootDevice, RootFunction)); + Status = EFI_SUCCESS; + RootDeviceBase = MmPciBase (RootBus, RootDevice, RootFunction); + PortCommonModeRestoreTime = 0; + PortTpowerOnValue = 0; + PortTpowerOnScale = 0; + *L1SubstatesSupported = FALSE; + AspmOverride = FALSE; + ClkreqPerPortSupported = FALSE; + + if (MmioRead16 (RootDeviceBase + PCI_VENDOR_ID_OFFSET) == DEVICE_ID_NOCARE) { + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + + // + // Assume CLKREQ# is supported on the port if PHY lane power gating is already enabled. + // + ClkreqPerPortSupported = PcieIsPhyLanePgEnabled (RootDeviceBase); + + // + // Get the pointer to the Port PCI Express Capability Structure. + // + RootPcieCapOffset = PcieFindCapId (RootBus, RootDevice, RootFunction, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (RootPcieCapOffset == 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + DeviceCapabilities2 = MmioRead32 (RootDeviceBase + RootPcieCapOffset + R_PCIE_DCAP2_OFFSET); + + // + // Enable LTR mechanism for this root port if it is capable + // + if ((DeviceCapabilities2 & B_PCIE_DCAP2_LTRMS) && (RootPortConfig->LtrEnable == TRUE)) { + MmioOr16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_DCTL2_OFFSET, B_PCIE_DCTL2_LTREN); + } + + AspmVal = (MmioRead16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_APMS) >> N_PCIE_LCAP_APMS; + if (RootPortConfig->Aspm == ScPcieAspmAutoConfig) { + Operation = CalculateAspm; + } else { + Operation = ManualAspm; + AspmVal &= RootPortConfig->Aspm; + } + + // + // Get the downstream Bus number + // + EndPointBus = MmioRead8 (RootDeviceBase + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + + // + // If the Secondary Bus Number of the root port is not assigned + // Note: + // It will be better that PCI enumeration has been done before PcieSetPm(). Or, you will need to assign + // a larger number to TempRootPortBusNumMax to support the specific card which has many bridges behind. + // If it is not, the Policy settings of "TempRootPortBusNumMax" and "TempRootPortBusNumMin" + // will be assigned to the Subordinate and Secondary Bus Number of the root ports. + // The assigned bus number will be cleared in the end of PcieSetPm(). + // + if (EndPointBus == 0) { + MmioAndThenOr32 ( + RootDeviceBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, + 0xFF0000FF, + ((UINT32) (TempBusNumberMin << 8)) | ((UINT32) (TempBusNumberMax << 16)) + ); + EndPointBus = TempBusNumberMin; + BusAssign = FALSE; + } else { + BusAssign = TRUE; + } + + // + // Check whether the slot has a device connected + // + SlotStatus = MmioRead16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_SLSTS_OFFSET); + LtrOvrVal = 0; + + RootL1SubstateExtCapOffset = 0; + RootL1SubstateExtCapOffset = PcieFindExtendedCapId (RootBus, RootDevice, RootFunction, V_PCIE_EX_L1S_CID); + if (RootL1SubstateExtCapOffset != 0) { + PortCommonModeRestoreTime = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 8) & 0xFF; + PortTpowerOnScale = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 16) & 0x3; + PortTpowerOnValue = (MmioRead32 (RootDeviceBase + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET) >> 19) & 0x1F; + } + + // + // Obtain initial ASPM settings from respective port capability registers. + // Scan LTR override table for device match and calculate the lowest override + // value to be programmed into PCIE RP PCI offset 400h + // + if (EndPointBus != 0 && (SlotStatus & BIT6) != 0) { + Status = PcieEndPointPm ( + RootDeviceBase, + RootPcieCapOffset, + EndPointBus, + NumOfDevAspmOverride, + DevAspmOverride, + &AspmVal, + Operation, + &LtrOvrVal, + RootL1SubstateExtCapOffset, + L1SubstatesSupported, + &PortCommonModeRestoreTime, + &PortTpowerOnValue, + &PortTpowerOnScale, + RootPortConfig, + &AspmOverride, + &ClkreqPerPortSupported, + LtrSupported, + PolicyRevision + ); + if (RootPortConfig->LtrEnable == TRUE) { + if (RootPortConfig->SnoopLatencyOverrideMode == 1) { + LtrOvrVal &= 0xFFFF0000; + LtrOvrVal |= (UINT32) BIT15 | + (UINT32) (RootPortConfig->SnoopLatencyOverrideMultiplier << 10) | + (UINT32) (RootPortConfig->SnoopLatencyOverrideValue); + } + + if (RootPortConfig->NonSnoopLatencyOverrideMode == 1) { + LtrOvrVal &= 0x0000FFFF; + LtrOvrVal |= (UINT32) BIT31 | + (UINT32) (RootPortConfig->NonSnoopLatencyOverrideMultiplier << 26) | + (UINT32) (RootPortConfig->NonSnoopLatencyOverrideValue << 16); + } + if (LtrOvrVal != 0) { + // + // Program PCIE RP PCI offset 400h only if we find a device in the LTR override table + // + MmioWrite32 (RootDeviceBase + 0x400, LtrOvrVal); + // + // Step 1.1 + // If B0:Dxx:Fn + 400h is programmed, BIOS will also program B0:Dxx:Fn + 404h [1:0] = 11b, + // to enable these override values. + // - Fn refers to the function number of the root port that has a device attached to it. + // - Default override value for B0:Dxx:Fn + 400h should be 880F880Fh + // - Also set 404h[2] to lock down the configuration + // + Data32Or = BIT1 | BIT0; + if (RootPortConfig->SnoopLatencyOverrideMode == 0) { + Data32Or &= (UINT32) ~BIT0; + } + if (RootPortConfig->NonSnoopLatencyOverrideMode == 0) { + Data32Or &= (UINT32) ~BIT1; + } + + if (RootPortConfig->LtrConfigLock == TRUE) { + // + // Set the lock bit + // + Data32Or |= BIT2; + } + MmioWrite32 (RootDeviceBase + 0x404, Data32Or); + } + } + } + // + // Step 6 + // If both Root and endpoint's L1 Sub-States Extended Capability Offset + 0x04[4:0] are 11111b, + // + if (*L1SubstatesSupported) { + ConfigureL1s ( + RootPortConfig, + RootBus, + RootDevice, + RootFunction, + RootDeviceBase, + RootL1SubstateExtCapOffset, + PortCommonModeRestoreTime, + PortTpowerOnValue, + PortTpowerOnScale + ); + } + // + // Step 7 + // If L1.SNOOZ and L1.OFF (L1 Sub-States) are not supported, + // and per-port CLKREQ# is supported, and LTR is supported: + // + if ((!(*L1SubstatesSupported)) && ClkreqPerPortSupported) { + if ((DeviceCapabilities2 & BIT11) && (RootPortConfig->LtrEnable == TRUE)) { + // + // Set Dxx:Fn:420[13:4] = 32h + // + MmioAndThenOr32 ( + RootDeviceBase + 0x420, + (UINT32) ~(BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4), + (0x32 << 4) + ); + // + // Enable L1.LOW by setting Dxx:Fn:420[17] = 1b + // + MmioOr32 (RootDeviceBase + 0x420, (UINT32)BIT17); + // + // Set Dxx:Fn:420h[0] to 1b + // + if ((AspmVal & V_PCIE_LCTL_ASPM_L1) == V_PCIE_LCTL_ASPM_L1) { + MmioOr32 (RootDeviceBase + 0x420, BIT0); + } + } + } + + if ((AspmVal & V_PCIE_LCTL_ASPM_L1) == V_PCIE_LCTL_ASPM_L1) { + + Data32Or = (BIT4 << 16); + // + // If dedicated CLKREQ# per-port is supported on all enabled ports, + // set Dxx:F0:E1h[6] = 1b prior to enabling ASPM L1. + // + if (ClkreqSupportedInAllEnabledPorts) { + Data32Or |= (B_PCH_PCIE_RPDCGEN_PTOCGE << 8); + } + // + // Note: for each PCIe controller, only its first root port register field E2h[4] and E1h[6] value are used, + // thus program them using sideband access + // + GetScPcieRpNumber (RootDevice, RootFunction, &PortIndex); + if (PortIndex < 2) { + FirstRpIndex = 0; + } else { + FirstRpIndex = 2; + } + Status = PchSbiRpPciAndThenOr32 (RootDevice, FirstRpIndex, 0xE0, (UINT32)(~(0)),Data32Or); + Data32Or = 0; + Data32And = (UINT32)~0; + if (ClkreqPerPortSupported) { + // + // If L1.SNOOZ and L1.OFF (L1 Sub-States) are supported , set Dxx:F0:420[30, 29] = [1b, 1b], + // + if (*L1SubstatesSupported) { + // + // If L1.SNOOZ and L1.OFF (L1 Sub-States) are supported, then disable L1.LOW by setting Dxx:Fn:420h[17] = 0b + // + Data32And = (UINT32)~BIT17; + Data32Or = BIT30 | BIT29; + } + MmioAndThenOr32 (RootDeviceBase + 0x420, Data32And, Data32Or); + } + } + // + // Set Root Port Aspm and enable LTR capability of the device if the Root Port's ASPM programming is allowed + // + if (AllowRpAspmProgramming == TRUE) { + MmioAndThenOr16 (RootDeviceBase + RootPcieCapOffset + R_PCIE_LCTL_OFFSET, (UINT16)~B_PCIE_LCTL_ASPM, AspmVal); + } + + // + // Based on the Role based Error Reporting Capability bit, for pre-1.1 devices, + // program root port 0xD4[4] to 1 and 0xD4[3:2] to 10. + // + if (AspmOverride) { + MmioAndThenOr8 (RootDeviceBase + R_PCH_PCIE_MPC2, + (UINT8)~(B_PCH_PCIE_MPC2_ASPMCOEN | B_PCH_PCIE_MPC2_ASPMCO), + (B_PCH_PCIE_MPC2_ASPMCOEN | V_PCH_PCIE_MPC2_ASPMCO_L1) + ); + } else { + MmioAnd8 (RootDeviceBase + R_PCH_PCIE_MPC2, (UINT8)~(B_PCH_PCIE_MPC2_ASPMCOEN | B_PCH_PCIE_MPC2_ASPMCO)); + } + // + // Step 1 + // Enable support Latency Tolerance Reporting (LTR) + // + if (EndPointBus != 0 && (SlotStatus & BIT6) != 0) { + // + // Set Endpoint Aspm and LTR capabilities + // + Status = PcieEndPointPm ( + RootDeviceBase, + RootPcieCapOffset, + EndPointBus, + NumOfDevAspmOverride, + DevAspmOverride, + &AspmVal, + SetAspm, + &LtrOvrVal, + RootL1SubstateExtCapOffset, + L1SubstatesSupported, + &PortCommonModeRestoreTime, + &PortTpowerOnValue, + &PortTpowerOnScale, + RootPortConfig, + &AspmOverride, + &ClkreqPerPortSupported, + LtrSupported, + PolicyRevision + ); + } + + if (BusAssign == FALSE) { + // + // Clear Bus Numbers. + // + MmioAnd32 (RootDeviceBase + 0x018, 0xFF0000FF); + } + + return Status; +} + + + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h new file mode 100644 index 0000000000..9d20fb6797 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeSmmScPciExpressHelpersLib/ScPciExpressHelpersLibrary.h @@ -0,0 +1,48 @@ +/** @file + Header file for PCI Express helps library implementation. + + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PCI_EXPRESS_HELPERS_LIBRARY_H_ +#define _PCH_PCI_EXPRESS_HELPERS_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LTR_VALUE_MASK (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7 + BIT8 + BIT9) +#define LTR_SCALE_MASK (BIT10 + BIT11 + BIT12) + +#ifndef SLE_FLAG + #define CONFIG_WRITE_LOOP_COUNT 100000 +#else // SLE_FLAG + #define CONFIG_WRITE_LOOP_COUNT 10 +#endif // SLE_FLAG + +// +// LTR related macros +// +#define LTR_LATENCY_VALUE(x) ((x) & LTR_VALUE_MASK) +#define LTR_SCALE_VALUE(x) (((x) & LTR_SCALE_MASK) >> 10) +#define LTR_LATENCY_NS(x) (LTR_LATENCY_VALUE(x) * (1 << (5 * LTR_SCALE_VALUE(x)))) + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf new file mode 100644 index 0000000000..1df68e706a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/PeiDxeUsbCommonLib.inf @@ -0,0 +1,53 @@ +## @file +# USB common lib. +# +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiDxeUsbCommonLib + FILE_GUID = 7A06ED7D-8E15-40a4-8539-22E86992DBE1 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = UsbCommonLib | PEIM DXE_DRIVER + +[Sources] + UsbCommonLib.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonSiPkg/BroxtonSiPrivate.dec + +[LibraryClasses] + S3BootScriptLib # Link this S3BootScriptLib to a NULL library for PEI usage. + BaseLib + IoLib + DebugLib + TimerLib + MmPciLib + SteppingLib + TimerLib + ConfigBlockLib + ScPlatformLib + +[Guids] + gUsbConfigGuid + gSiPolicyHobGuid + +[Ppis] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## SOMETIMES_CONSUMES + gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress ## SOMETIMES_CONSUMES + gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress ## SOMETIMES_CONSUMES diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c new file mode 100644 index 0000000000..f7a2a4af0b --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/Private/PeiDxeUsbCommonLib/UsbCommonLib.c @@ -0,0 +1,1172 @@ +/** @file + Initializes USB Controllers. + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION; + + +/** + Set UNUSED bit to "1" if the port has no physical SSIC Device connected. + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + + @retval EFI_INVALID_PARAMETER The parameter of ScPolicy is invalid + @retval EFI_SUCCESS The function completed successfully + +**/ +VOID +XhciSsicInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN EFI_BOOT_MODE BootMode + ); + +/** + Program Xhci Port Disable Override + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase XHCI Memory Space Address + + @retval None + +**/ +VOID +XhciPortDisableOverride ( + IN SC_USB_CONFIG *UsbConfig, + IN UINTN XhciMmioBase + ); + +/** + Setup XHCI Over-Current Mapping + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciOverCurrentMapping ( + IN SC_USB_CONFIG *UsbConfig, + IN UINTN XhciPciMmBase + ); + +/** + Configures SC USB controller + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] BusNumber PCI Bus Number of the SC device + @param[in] FuncDisableReg Function Disable Register + @param[in] BootMode current boot mode + + @retval EFI_INVALID_PARAMETER The parameter of ScPolicy is invalid + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +EFIAPI +CommonUsbInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINT8 BusNumber, + IN OUT UINT32 *FuncDisableReg, + IN EFI_BOOT_MODE BootMode + ) +{ + UINTN XhciPciMmBase; + + DEBUG ((DEBUG_INFO, "CommonUsbInit() - Start\n")); + mBootMode = BootMode; + + XhciPciMmBase = MmPciBase ( + BusNumber, + PCI_DEVICE_NUMBER_XHCI, + PCI_FUNCTION_NUMBER_XHCI + ); + // + // If xHCI is disabled by fuse or soft-strap, + // set the function disable bit and then return. + // + if (MmioRead32 ((UINTN) (XhciPciMmBase)) == 0xFFFFFFFF) { + DEBUG ((EFI_D_INFO , "xHCI not present, skipping.\n")); + UsbConfig->Usb30Settings.Mode = XHCI_MODE_OFF; + *FuncDisableReg |= B_PMC_FUNC_DIS_USB_XHCI; + return EFI_SUCCESS; + } + + // + // To disable a host controller, the System BIOS must first place the + // xHCI controller in RTD3Hot state by program PM_CS.PS, D21:F0:0x74 [1:0] = 11b + // and then set the Function Disable register to disable the xHCI controller. + // + if (UsbConfig->Usb30Settings.Mode == XHCI_MODE_OFF) { + + // + // Putting xHCI into D3 Hot State + // + DEBUG ((EFI_D_INFO , "Putting xHCI into D3 Hot State.\n")); + MmioOr32 ((UINTN) (XhciPciMmBase + R_XHCI_PWR_CNTL_STS), B_XHCI_PWR_CNTL_STS_PWR_STS); + + SideBandAndThenOr32 ( + 0xA9, + (0x0600 + 0x001C), + 0xFFFFFFFF, + BIT8 + ); + *FuncDisableReg |= B_PMC_FUNC_DIS_USB_XHCI; + return EFI_SUCCESS; + } + + // + // Assign memory resources + // + XhciMemorySpaceOpen ( + UsbConfig, + XhciMmioBase, + XhciPciMmBase + ); + + CommonXhciHcInit ( + UsbConfig, + XhciMmioBase, + XhciPciMmBase, + BootMode + ); + + XhciSsicInit ( + UsbConfig, + XhciMmioBase, + BootMode + ); + + // + // Setup USB Over-Current Mapping. + // + XhciOverCurrentMapping ( + UsbConfig, + XhciPciMmBase + ); + + // + // Program USB Port Disable Override Capability + // + XhciPortDisableOverride ( + UsbConfig, + XhciMmioBase + ); + + // + // Clear memory resources + // + XhciMemorySpaceClose ( + UsbConfig, + XhciMmioBase, + XhciPciMmBase + ); + + DEBUG ((EFI_D_INFO, "CommonUsbInit() - End\n")); + + return EFI_SUCCESS; +} + + +/** + Set UNUSED bit to "1" if the port has no physical SSIC Device connected. + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + + @retval EFI_INVALID_PARAMETER The parameter of ScPolicy is invalid + @retval EFI_SUCCESS The function completed successfully + +**/ +VOID +XhciSsicInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN EFI_BOOT_MODE BootMode + ) +{ + UINT32 Data32; + UINT32 Iteration; + + DEBUG ((DEBUG_INFO, "XhciSsicInit() - Start\n")); + + if (UsbConfig->SsicConfig.SsicPort[0].Enable == TRUE) { + Data32 = B_XHCI_PROG_DONE; + } else { + // + // Set UNUSED bit to "1" if the port has no physical SSIC Device connected. + // + Data32 = B_XHCI_SSIC_PORT_UNUSED | B_XHCI_PROG_DONE; + } + MmioOr32 ( + XhciMmioBase + R_XHCI_SSIC_CFG_2_PORT1, + Data32 + ); + + if (UsbConfig->SsicConfig.SsicPort[1].Enable == TRUE) { + Data32 = B_XHCI_PROG_DONE; + } else { + // + // Set UNUSED bit to "1" if the port has no physical SSIC Device connected. + // + Data32 = B_XHCI_SSIC_PORT_UNUSED | B_XHCI_PROG_DONE; + } + MmioOr32 ( + XhciMmioBase + R_XHCI_SSIC_CFG_2_PORT2, + Data32 + ); + + DEBUG ((DEBUG_INFO, "XhciSsicInit:base:0x%x\n",XhciMmioBase)); + Data32 = MmioRead32(XhciMmioBase+R_XHCI_SSIC_CFG_2_PORT1); + DEBUG ((DEBUG_INFO, "0x%x:0x%x\n", (XhciMmioBase+R_XHCI_SSIC_CFG_2_PORT1), Data32)); + + Data32 = MmioRead32(XhciMmioBase+R_XHCI_SSIC_CFG_2_PORT2); + DEBUG ((DEBUG_INFO, "0x%x:0x%x\n", (XhciMmioBase+R_XHCI_SSIC_CFG_2_PORT2), Data32)); + + if ((UsbConfig->SsicConfig.SsicPort[0].Enable == TRUE) || + (UsbConfig->SsicConfig.SsicPort[1].Enable == TRUE)) { + if (BootMode == BOOT_ON_S5_RESUME) { + DEBUG ((DEBUG_INFO, "Boot on S5 resume...\n")); + MicroSecondDelay (100); // 100us + // + // Clear SSIC ports PP bits + // + if (GetBxtSeries () == BxtP) { + // + // Clear SSIC ports PP bits + // + MmioAnd32 ( + XhciMmioBase + R_BXTP_XHCI_PORTSC2USB3, + (UINT32) ~(B_XHCI_PORTSCXUSB3_PP) + ); + MmioAnd32 ( + XhciMmioBase + R_BXTP_XHCI_PORTSC3USB3, + (UINT32) ~(B_XHCI_PORTSCXUSB3_PP) + ); + // + // Wait for 150ms for Host to complete the DSP Disconnect protocol + // + MicroSecondDelay (150 * 1000); + + MmioOr32 ( + XhciMmioBase + R_BXTP_XHCI_PORTSC2USB3, + (UINT32) B_XHCI_PORTSCXUSB3_PP + ); + + MmioOr32 ( + XhciMmioBase + R_BXTP_XHCI_PORTSC3USB3, + (UINT32) B_XHCI_PORTSCXUSB3_PP + ); + } else { + MmioAnd32 ( + XhciMmioBase + R_BXT_XHCI_PORTSC2USB3, + (UINT32) ~(B_XHCI_PORTSCXUSB3_PP) + ); + MmioAnd32 ( + XhciMmioBase + R_BXT_XHCI_PORTSC3USB3, + (UINT32) ~(B_XHCI_PORTSCXUSB3_PP) + ); + // + // Wait for 150ms for Host to complete the DSP Disconnect protocol + // + MicroSecondDelay (150 * 1000); + + MmioOr32 ( + XhciMmioBase + R_BXT_XHCI_PORTSC2USB3, + (UINT32) B_XHCI_PORTSCXUSB3_PP + ); + MmioOr32 ( + XhciMmioBase + R_BXT_XHCI_PORTSC3USB3, + (UINT32) B_XHCI_PORTSCXUSB3_PP + ); + } + // + // Set HCRST after S5, HCRST is cleared by HW when reset process is complete + // + MmioOr32 ( + XhciMmioBase + R_XHCI_USBCMD, + (UINT32) B_XHCI_USBCMD_HCRST + ); + // + // Waiting for reset complete + // The controller requires that its MMIO space not be accessed for a minimum of 1 ms after + // an HCRST is triggered which includes reading the HCRST bit + // + MicroSecondDelay (1000); // 1ms + for (Iteration = 0; Iteration < 8000; Iteration++) { + if ((MmioRead32 (XhciMmioBase + R_XHCI_USBCMD) & B_XHCI_USBCMD_HCRST) == 0) { + break; + } + MicroSecondDelay (100); // 100us + } + } + } + + DEBUG ((DEBUG_INFO, "XhciSsicInit() - End\n")); + + return; +} + + +/** + Performs basic configuration of SC USB3 (xHCI) controller. + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of xHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +CommonXhciHcInit ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase, + IN EFI_BOOT_MODE BootMode + ) +{ + EFI_STATUS Status; + UINT32 BitMask; + UINT32 BitValue; + BXT_STEPPING BxtStep; + UINT32 Data32And; + UINT32 Data32Or; + + Status = EFI_TIMEOUT; + BitMask = 0; + BitValue = 0; + BxtStep = BxtStepping (); + + // + // Set xHCI MSI_NEXT to 0x90 to point to the DevIdle capability structure + // + MmioAndThenOr32(XhciPciMmBase + R_XHCI_MSI_CAPID, 0xFFFF00FF, V_XHCI_MSI_NEXT << 8); + + // + // HCSPARAMS1 - Structural Parameters 1 + // Address Offset: 0x04 - 0x07 + // + BitValue = MmioRead32 (XhciMmioBase + R_XHCI_XECP_SUPP_USB3_2); + BitValue = ((BitValue >> 8) & 0xff) + ((BitValue & 0xff) - 1); + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HCSPARAMS1), + (UINT32) 0x00FFFFFF, + (UINT32) (BitValue << 24) + ); + BitValue = 0; + // + // HCSPARAMS3 - Structural Parameters 3 + // Address Offset: 0x0C - 0x0F + // Set xHCIBAR + 0Ch[7:0] = 0Ah and [31:16] = 200h + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HCSPARAMS3), + (UINT32) 0x0000FF00, + (UINT32) 0x0200000A + ); + + // + // XHCC2 - XHC System Bus Configuration 2 + // Address Offset: 44-47h + // Value: [25] 1b, [24:22] 111b, [19:14] 3fh, [11] 0b, [10] 1b, [9:8] 10b, [7:6] 10b, [5:3] 001b, [2:0] 111b + // + Data32And = 0xFC303000; + Data32Or = 0x03CFC68F; + if (BxtStep == BxtPA0 && BootMode == BOOT_ON_S3_RESUME) { + + Data32Or = 0x000FC688; + } + MmioAndThenOr32 ( + XhciPciMmBase + R_XHCI_XHCC2, + Data32And, + Data32Or + ); + + + if (GetBxtSeries() == BxtP) { + // + // PCE - Power Control Enables + // Address Offset: A2h - A3h + // Value: [5] 0b, [3] 1b, [2] 1b, [1] 1b, [0] 0b + MmioAndThenOr16 ( + XhciPciMmBase + R_XHCI_PCE, + (UINT16)~(B_XHCI_PCE_SPE | B_XHCI_PCE_HAE), + (UINT16)(B_XHCI_PCE_SE | B_XHCI_PCE_D3HE | B_XHCI_PCE_I3E) + ); + } else { + // + // PCE - Power Control Enables + // Address Offset: A2h - A3h + // Value: [5] 1b, [3] 1b, [2] 1b, [1] 1b, [0] 0b + // + MmioAndThenOr16 ( + XhciPciMmBase + R_XHCI_PCE, + (UINT16) ~(B_XHCI_PCE_SPE), + (UINT16) (B_XHCI_PCE_SE | B_XHCI_PCE_D3HE | B_XHCI_PCE_I3E | B_XHCI_PCE_HAE) + ); + } + + // + // HSCFG2 - High Speed Configuration 2 + // Address Offset: A4h - A5h + // Value: [15] 0b, [14] 0b, [13] 0b, [12:11] 11b + // + MmioAndThenOr16 ( + XhciPciMmBase + R_XHCI_HSCFG2, + (UINT16) ~(B_XHCI_HSCFG2_HSAAIM | B_XHCI_HSCFG2_HSOAAPEPM | B_XHCI_HSCFG2_HSIAAPEPM), + (UINT16) (B_XHCI_HSCFG2_HSIIPAPC) + ); + + // + // SSCFG1 - SuperSpeed Configuration 1 + // Address Offset: A8h - ABh + // Value: [17] 1b, [14] 1b + // + MmioAndThenOr32 ( + XhciPciMmBase + R_XHCI_SSCFG1, + 0xFFFFFFFF, + (UINT32) (B_XHCI_SSCFG1_LFPS | B_XHCI_SSCFG1_PHY_U3) + ); + + // + // XECP_CMDM_CTRL_REG1 - Command Manager Control 1 + // Address Offset: 818C-818Fh + // Value: [20] 0b, [16] 1b, [8] 0b + // + MmioAndThenOr32 ( + (XhciMmioBase+R_XHCI_XECP_CMDM_CTRL_REG1), + (UINT32) ~(B_XHCI_XECP_MAX_EP | B_XHCI_XECP_CLR_CTX_ENSLOT), + (UINT32) (B_XHCI_XECP_TSP) + ); + + // + // XECP_CMDM_CTRL_REG3 - Command Manager Control 3 + // Address Offset: 8194-8197h + // Value: [25] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase+R_XHCI_XECP_CMDM_CTRL_REG3), + 0xFFFFFFFF, + (UINT32) (B_XHCI_XECP_STOP_EP) + ); + + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CTRL_BW_MAX_REG + 4), + 0xFFFF000F, + (UINT32) (V_XHCI_HOST_CTRL_BW_MAX_REG_TT << 4) + ); + + // + // PMCTRL - Power Management Control + // Address Offset: 80A4-80A7h + // Value: [31] 0b, [30] 1b, [29] 0b, [25:22] 1111b, [16] 1b, [7:4] 9h, [3] 1 for BXTA0, 0 for all BXT [2] 1b + // + Data32And = 0x143EFF03; + if (BxtStep <= BxtA1) { + Data32Or = 0x4BC1009C; + } else { + Data32Or = 0x4BC10094; + } + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_PMCTRL), + Data32And, + Data32Or + ); + + // + // PGCBCTRL - PGCB Control + // Address Offset: 80A8-80ABh + // Value: [24] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_PGCBCTRL), + ~0u, + (UINT32) (B_XHCI_PGCBCTRL_RESET_PREP_DIS) + ); + + // + // SSPE - Super Speed Port Enables + // Address Offset: 0x80B8 - 0x80BC + // Value: [30] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CONTROLLER_SSPE), + ~0u, + (UINT32) (B_XHCI_ENCLCCS) + ); + + // + // AUX_CTRL_REG1 - AUX Power Management Control + // Address Offset: 80E0-80E3h + // Value: [22] 0b, [16] 0b, [9] 0b, [6] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase+R_XHCI_AUX_CTRL_REG1), + (UINT32) ~(B_XHCI_AUX_ISOLATION | B_XHCI_AUX_PORT_CG | B_XHCI_AUX_CG), + (UINT32) (B_XHCI_AUX_P2) + ); + + // + // HOST_CTRL_SCH_REG - Host Control Scheduler + // Address Offset: 8094-8097h + // Value: [23] 1b, [22] 1b, [21] 0b, [14] 0b, [6] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CTRL_SCH_REG), + (UINT32) ~(B_XHCI_HOST_CTRL_DIS_SCH_PKT | B_XHCI_HOST_CTRL_DIS_PKT_CHK), + (UINT32) (B_XHCI_HOST_CTRL_DIS_ASYNC | B_XHCI_HOST_CTRL_EN_EP_PPL | B_XHCI_HOST_CTRL_EN_1P_EP_PPL) + ); + + // + // HOST_CTRL_PORT_LINK_REG - SuperSpeed Port Link Control + // Address Offset: 0x80EC - 0x80EF + // Value: [19] 1b, [17] 1b + // + Data32And = ~0u; + Data32Or = (UINT32) (B_XHCI_HOST_CTRL_EN_TS_EXIT | B_XHCI_HOST_CTRL_PORT_INIT_TIMEOUT); + if (UsbConfig->DisableComplianceMode == TRUE) { + Data32Or |= B_XHCI_DIS_LINK_CM; + } + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CTRL_PORT_LINK_REG), + Data32And, + Data32Or + ); + // + // USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 + // Address Offset: 0x80F0 - 0x80FF [121] 1b, [20] 0b + // [127:96] is mapped to DW4 at offset 80FCh-80FFh [25] 1b + // [31:0] is mapped to DW1 at offset 80F0h-80F3h [20] 0b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_USB2_LINK_MGR_CTRL_REG1), + (UINT32) ~(B_XHCI_USB2_LINK_L1_EXIT), + 0x0 + ); + + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_USB2_LINK_MGR_CTRL_REG1_CONTROL4), + 0xFFFFFFFF, + (UINT32)(B_XHCI_USB2_LINK_PRV_L1_ENTRY) + ); + + // + // HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2 + // Address Offset: 8110-8113h + // Value: [2] 0b, [20] 1b, [11] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CTRL_TRM_REG2), + (UINT32) ~(B_XHCI_HOST_CTRL_REDEEM), + (UINT32) (B_XHCI_HOST_CTRL_MAX_BURST_CHK | B_XHCI_HOST_CTRL_TRF_PIPE) + ); + + // + // Set xHCIBAR + 8154h[31, 21,13] to 1b, 0b, 1b + // + MmioAndThenOr32( + (XhciMmioBase + R_XHCI_AUX_CTRL_REG2), + (UINT32)~(B_XHCI_AUX2_P2_D3HOT), + (UINT32) (B_XHCI_AUX2_L1P2_EXIT|B_XHCI_AUX2_PHY_P3) + ); + + // + // xHCI Aux Clock Control Register + // Address Offset: 0x816C - 0x816F + // [13:12] 00b, [11:8] 0h + // [19] 1b, [18] 1b, [17] 1b, [14] 1b, [5] 0b, [4] 1b, [3] 1b, [2] 1b, + // + + Data32And = 0xFFF180C3; + Data32Or = 0x0002401C; + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_AUX_CLOCK_CTRL_REG), + Data32And, + Data32Or + ); + + // + // HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0 + // Address Offset: 8140-8143h + // Value: [31:24] 0xFF, [11:0] 0x03C + // [23:12] 0x080 for BXT A step + // [23:12] 0x00F for all others steppings + // + Data32And = 0; + Data32Or = 0xFF00F03C; + if (BxtStep <= BxtA1) { + Data32Or = 0xFF08003C; + } + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_IF_PWR_CTRL_REG0), + Data32And, + Data32Or + ); + // + // HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1 + // Address Offset: 8144-8147h + // Value: [8] 1b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_IF_PWR_CTRL_REG1), + ~0u, + (UINT32) (B_XHCI_HSII) + ); + + // + // xHC Latency Tolerance Parameters - LTV Control + // Address Offset: 0x8174 - 0x8177 + // Value: [24] 1b, 0b for BXTPA0 [11:0] 0xC0A + // + Data32And = (UINT32) ~(B_XHCI_USB2_PORT_L0_LTV | B_XHCI_XLTRE); + Data32Or = 0x01000C0A; + if (BxtStep <= BxtPA0){ + Data32Or = 0x00000C0A; + } + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_LATENCY_TOLERANCE_PARAMETERS_LTV_CONTROL), + Data32And, + Data32Or + ); + // + // xHC Latency Tolerance Parameters - High Idle Time Control + // Address Offset: 0x817C - 0x817F + // Value: [28:16] 0x0332, [12:0] 0x00A3 + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_LATENCY_TOLERANCE_PARAMETERS_HIGH_IDLE_TIME_CONTROL), + 0xE000E000, + 0x033200A3 + ); + + // + // xHC Latency Tolerance Parameters - Medium Idle Time Control + // Address Offset: 0x8180 - 0x8183 + // Value: [28:16] 0x00CB, [12:0] 0x0028 + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_LATENCY_TOLERANCE_PARAMETERS_MEDIUM_IDLE_TIME_CONTROL), + 0xE000E000, + 0x00CB0028 + ); + + // + // xHC Latency Tolerance Parameters - Low Idle Time Control + // Address Offset: 0x8184 - 0x8187 + // Value: [28:16] 0x0064, [12:0] 0x001E + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_LATENCY_TOLERANCE_PARAMETERS_LOW_IDLE_TIME_CONTROL), + 0xE000E000, + 0x0064001E + ); + + // + // USB2 PHY Power Management Control + // Address Offset: 8164-8167h + // Value: [7:0] 11111100b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_USB2_PHY_POWER_MANAGEMENT_CONTROL), + (UINT32) ~(B_XHCI_RX_BIAS_CHT_DIS | B_XHCI_TX_BIAS_CHT_DIS), + (UINT32) (B_XHCI_CMAI | B_XHCI_TTEAI | B_XHCI_IDMAAI | B_XHCI_ODMAAI | B_XHCI_TMAI | B_XHCI_SAI) + ); + + // + // Host Controller Misc Reg + // Address Offset: 0x80B0 - 0x80B3 + // Value: [24:23] 01b, [18:16] 000b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CONTROLLER_MISC_REG), + (UINT32) ~(B_XHCI_EXTRA_UFRAME | B_XHCI_LATE_FID_CHK_DIS), + (UINT32) (B_XHCI_LATE_FID_TTE_DIS) + ); + + // + // Host Controller Misc Reg 2 + // Address Offset: 0x80B4 - 0x80B7 + // Value: [2] 1b + // 0b for BXT-P B0 and above + // [5] 1b for BXT A0 step + // [5] 0b for all others steppings + // + if (BxtStep == BxtA0) { + MmioOr32 ( + (XhciMmioBase + R_XHCI_HOST_CONTROLLER_MISC2REG), + (UINT32) (B_XHCI_FRAME_TIM_SEL | B_XHCI_WARM_PORT_RESET_ON_DISC_PORT_DIS) + ); + } else if (BxtStep >= BxtPB0) { + MmioAnd32 ( + (XhciMmioBase + R_XHCI_HOST_CONTROLLER_MISC2REG), + (UINT32) ~(B_XHCI_FRAME_TIM_SEL | B_XHCI_WARM_PORT_RESET_ON_DISC_PORT_DIS) + ); + } else { + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_HOST_CONTROLLER_MISC2REG), + (UINT32) ~(B_XHCI_FRAME_TIM_SEL), + (UINT32) (B_XHCI_WARM_PORT_RESET_ON_DISC_PORT_DIS) + ); + } + // + // LFPSONCOUNT - LFPS On Count + // Address Offset: 0x81B8 - 0x81BB + // Value: [15:10] 02h, [9:0] 02h + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_LFPS_ON_COUNT), + (UINT32) ~(B_XHCI_XLFPSONCNTSSIC | B_XHCI_XLFPSONCNTSS), + (UINT32) (0x0802) + ); + + // + // D0I2CTRL - D0I2 Control Register + // Address Offset: 81BC-81BFh + // Value: [31] 1b, [29:26] 04h, [25:22] 04h, [21] 0b, [20:16] 04h, [15:4] 20h, [3:0] 0h + // + + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_D0I2_CONTROL), + 0x40000000, + 0x91040200 + ); + + // + // D0I2SchAlarmCtrl - D0i2 Scheduler Alram Control Reg + // Address Offset: 81C0-81C3h + // Value: [28:16] 0Fh, [12:0] 05h + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_D0I2_SCH_ALARM_CTRL), + 0xE000E000, + 0x000F0005 + ); + + // + // USB2PMCTRL - USB2 Power Management Control + // Address Offset: 0x81C4 - 0x81C7 + // Value: [11] 1b, [10:8] 001b, [3:2] 00b, [1:0] 11b + // + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_USB2_PM_CTRL), + (UINT32) ~(B_XHCI_U2PSPGEHC | B_XHCI_U2PSUSPGP), + (UINT32) (B_XHCI_U2PSPGPSCBP | BIT8 | B_XHCI_U2PSUSPGP_Shadow) + ); + + // + // Set xHCIBAR + 8178h[12:0] to 0h + // + MmioAndThenOr32 ( + (XhciMmioBase + 0x8178), + (UINT32)~(0xFFFFE000), + (UINT32) (0x00) + ); + + if (UsbConfig->XdciConfig.Enable != ScDisabled) { + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG0), + 0, + (UINT32) BIT24 + ); + + MmioAndThenOr32 ( + (XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG0), + 0, + (UINT32) (BIT21 | BIT20) + ); + // + // Step 2 + // Poll xHCI BAR + DUAL_ROLE_CFG1 [29] until it reads 0b or else 5ms timeout. + // + BitMask = (UINT32) (BIT29); + BitValue = 0; + Status = ScMmioPoll32 ( + (UINTN) (XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG1), + BitMask, + BitValue, + 50 + ); + if (Status == EFI_TIMEOUT) { + DEBUG ((DEBUG_ERROR | DEBUG_INFO, "USBCommonlib.c Timeout while polling on xHCI BAR + R_XHCI_MEM_DUAL_ROLE_CFG1 [29] for 0b\n")); + } + } + DEBUG ((DEBUG_INFO, "R_XHCI_MEM_DUAL_ROLE_CFG0=%x\n", MmioRead32(XhciMmioBase + R_XHCI_MEM_DUAL_ROLE_CFG0))); +} + + +/** + Initialization XHCI Clock Gating registers + + @retval None + +**/ +VOID +ConfigureXhciClockGating ( + VOID + ) +{ + UINTN XhciPciMmBase; + UINT32 Data32And; + UINT32 Data32Or; + BXT_STEPPING BxtStep; + + XhciPciMmBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_XHCI, + PCI_FUNCTION_NUMBER_XHCI + ); + + if (XhciPciMmBase == 0xFFFFFFFF) { // controller absence or function disable + DEBUG ((DEBUG_INFO , "XHCI controller absence or function disable, skip setting clock gating.\n")); + return; + } + + BxtStep = BxtStepping (); + + // + // XHCC1 - XHC System Bus Configuration 1 + // Address Offset: 40-43h + // Value: [21:19] 110b, [18] 1b, [8] 1b + // Writes to this registers needs to be performed per bytes to avoid touching bit 31 + // Bit 31 is used to lock RW/L bits and can be writen once. + // + MmioOr8 ( + XhciPciMmBase + R_XHCI_XHCC1 + 1, + BIT0 + ); + MmioOr8 ( + XhciPciMmBase + R_XHCI_XHCC1 + 2, + (BIT5 | BIT4 | BIT2) + ); + + // + // HSCFG1 - High Speed Configuration 1 + // Address Offset: AC-AFh + // Value: [19] 0b, [18] 1b + // + MmioAndThenOr32 ( + (UINTN) (XhciPciMmBase + R_XHCI_HSCFG1), + (UINT32) ~(B_XHCI_HSCFG1_UTMI_SUSPEND_CG), + (UINT32) (B_XHCI_HSCFG1_UTMI_SPEED_CG) + ); + + // + // XHCLKGTEN - Clock Gating + // Address Offset: 50-53h + // Value: [28] 0b, [27:24] 1111b, [23:20] 1100b, [19:16] 1110b, [15:8] 01101110b, [7:0] 01011111b + // + Data32And = 0xE0000000; + if (BxtStep == BxtPA0 && mBootMode == BOOT_ON_S3_RESUME) { + + Data32Or = 0x0FDF6D3F; + MmioAndThenOr32 ( + (UINTN) (XhciPciMmBase + R_XHCI_XHCLKGTEN), + Data32And, + Data32Or + ); + DEBUG ((DEBUG_INFO , "Putting xHCI into D3 Hot State.\n")); + MmioOr32 ((UINT32) (XhciPciMmBase + R_XHCI_PWR_CNTL_STS), B_XHCI_PWR_CNTL_STS_PWR_STS); + MicroSecondDelay (20); + DEBUG ((DEBUG_INFO , "Putting xHCI into D0 State.\n")); + MmioAnd32 ((UINT32) (XhciPciMmBase + R_XHCI_PWR_CNTL_STS), (UINT32) ~ (B_XHCI_PWR_CNTL_STS_PWR_STS)); + } else { + Data32Or = 0x0FCE6E5F; + MmioAndThenOr32 ( + (UINTN) (XhciPciMmBase + R_XHCI_XHCLKGTEN), + Data32And, + Data32Or + ); + } +} + + +/** + Lock USB registers before boot + + @param[in] ScPolicy The SC Policy + + @retval None + +**/ +VOID +UsbInitBeforeBoot ( + IN SI_POLICY_HOB *SiPolicyHob, + IN SC_POLICY_HOB *ScPolicyHob + ) +{ + UINTN XhciPciMmBase; + SC_USB_CONFIG *UsbConfig; + EFI_STATUS Status; + + XhciPciMmBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_XHCI, + PCI_FUNCTION_NUMBER_XHCI + ); + Status = GetConfigBlock ((VOID *) ScPolicyHob, &gUsbConfigGuid, (VOID *) &UsbConfig); + ASSERT_EFI_ERROR (Status); + + if (UsbConfig->Usb30Settings.Mode != XHCI_MODE_OFF) { + // + // Set xHCI MSI_MCTL According to OS: + // Windows: D3 Supported - Set to 1h to enable MSI + // Android: D0i3/DevIdle Supported (legacy interrupts used in D0i3 flows) - Set to 0h to disable MSI + // + if (MmioRead32((UINTN)(XhciPciMmBase)) != 0xFFFFFFFF) { + if (SiPolicyHob->OsSelection == SiAndroid) { + // + // MSI capability structure must not be reported for Android to use line based interrupts. + // Linux driver will use MSI if reported and wake flows require line based interrupts. + // + MmioAnd16(XhciPciMmBase + R_XHCI_MSI_MCTL, (UINT16)~(B_XHCI_MSI_MCTL_MSIENABLE)); + } else { + MmioOr16(XhciPciMmBase + R_XHCI_MSI_MCTL, B_XHCI_MSI_MCTL_MSIENABLE); + } + } else { + DEBUG ((EFI_D_ERROR, "xHCI not present, cannot disable the xHCI MSI capability structure for Android.\n")); + } + + MmioOr32 (XhciPciMmBase + R_XHCI_XHCC2, B_XHCI_XHCC2_OCCFDONE); + INIT_COMMON_SCRIPT_MEM_WRITE ( + EFI_ACPI_S3_RESUME_SCRIPT_TABLE, + EfiBootScriptWidthUint32, + (UINTN) (XhciPciMmBase + R_XHCI_XHCC2), + 1, + (VOID *) (UINTN) (XhciPciMmBase + R_XHCI_XHCC2) + ); + + MmioOr32 (XhciPciMmBase + R_XHCI_XHCC1, B_XHCI_XHCC1_ACCTRL | B_XHCI_XHCC1_URD); + INIT_COMMON_SCRIPT_MEM_WRITE ( + EFI_ACPI_S3_RESUME_SCRIPT_TABLE, + EfiBootScriptWidthUint32, + (UINTN) (XhciPciMmBase + R_XHCI_XHCC1), + 1, + (VOID *) (UINTN) (XhciPciMmBase + R_XHCI_XHCC1) + ); + } +} + + +/** + Setup XHCI Over-Current Mapping + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciOverCurrentMapping ( + IN SC_USB_CONFIG *UsbConfig, + IN UINTN XhciPciMmBase + ) +{ + // + // BIOS responsibility on Overcurrent protection. + // ---------------------------------------------- + // The max can be total 8 overcurrent pins + // OC0: Used for the OTG port (port 0) + // OC1: Used for the 2 host walk-up ports (ports 1 to 5) + // It is ok to map multiple ports to a single pin. + // It is not ok to map a single ports to a multiple pins. + // All USB ports routed out of the package must have Overcurrent protection. + // USB Ports not routed out from the package should not be assigned OC pins. + // + UINT32 Index; + UINT32 U2OCMBuf[V_XHCI_NUMBER_OF_OC_PINS] = {0}; + UINT32 U3OCMBuf[V_XHCI_NUMBER_OF_OC_PINS] = {0}; + UINT32 OCPin; + + for (Index = 0; Index < GetScXhciMaxUsb3PortNum (); Index++) { + if (UsbConfig->PortUsb30[Index].OverCurrentPin == ScUsbOverCurrentPinSkip) { + // + // No OC pin assigned, skip this port + // + } else { + OCPin = UsbConfig->PortUsb30[Index].OverCurrentPin; + ASSERT (OCPin < V_XHCI_NUMBER_OF_OC_PINS); + U3OCMBuf[OCPin] |= (UINT32) (BIT0 << Index); + } + } + for (Index = 0; Index < V_XHCI_NUMBER_OF_OC_PINS; Index++) { + MmioWrite32 (XhciPciMmBase + R_XHCI_U3OCM + (Index * 4), U3OCMBuf[Index]); + } + + for (Index = 0; Index < GetScXhciMaxUsb2PortNum (); Index++) { + if (UsbConfig->PortUsb20[Index].OverCurrentPin == ScUsbOverCurrentPinSkip) { + // + // No OC pin assigned, skip this port + // + } else { + OCPin = UsbConfig->PortUsb20[Index].OverCurrentPin; + ASSERT (OCPin < V_XHCI_NUMBER_OF_OC_PINS); + U2OCMBuf[OCPin] |= (UINT32) (BIT0 << Index); + } + } + + for (Index = 0; Index < V_XHCI_NUMBER_OF_OC_PINS; Index++) { + MmioWrite32 (XhciPciMmBase + R_XHCI_U2OCM + (Index * 4), U2OCMBuf[Index]); + } + +} + + +/** + Program Xhci Port Disable Override + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None +**/ +VOID +XhciPortDisableOverride ( + IN SC_USB_CONFIG *UsbConfig, + IN UINTN XhciMmioBase + ) +{ + UINT32 Index; + UINT32 XhciUsb2Pdo = 0; + UINT32 XhciUsb3Pdo = 0; + BXT_SERIES BxtSeries; + + BxtSeries = GetBxtSeries (); + switch (BxtSeries) { + case Bxt: + XhciUsb2Pdo = MmioRead32 (XhciMmioBase + R_XHCI_USB2PDO) & B_XHCI_BXT_USB2PDO_MASK; + XhciUsb3Pdo = MmioRead32 (XhciMmioBase + R_XHCI_USB3PDO) & B_XHCI_BXT_USB3PDO_MASK; + break; + case BxtP: + XhciUsb2Pdo = MmioRead32 (XhciMmioBase + R_XHCI_USB2PDO) & B_XHCI_BXTP_USB2PDO_MASK; + XhciUsb3Pdo = MmioRead32 (XhciMmioBase + R_XHCI_USB3PDO) & B_XHCI_BXTP_USB3PDO_MASK; + break; + default: + break; + } + // + // XHCI PDO for HS + // + for (Index = 0; Index < GetScXhciMaxUsb2PortNum(); Index++) { + if (UsbConfig->PortUsb20[Index].Enable == FALSE) { + XhciUsb2Pdo |= (UINT32) (B_XHCI_USB2PDO_DIS_PORT0 << Index); + } else { + XhciUsb2Pdo &= (UINT32)~(B_XHCI_USB2PDO_DIS_PORT0 << Index); + } + } + // + // XHCI PDO for SS + // + for (Index = 0; Index < GetScXhciMaxUsb3PortNum(); Index++) { + if (UsbConfig->PortUsb30[Index].Enable == FALSE) { + XhciUsb3Pdo |= (UINT32) (B_XHCI_USB3PDO_DIS_PORT0 << Index); + } else { + XhciUsb3Pdo &= (UINT32)~(B_XHCI_USB3PDO_DIS_PORT0 << Index); + } + } + // + // USB2PDO and USB3PDO are Write-Once registers and bits in them are in the SUS Well. + // + MmioWrite32 (XhciMmioBase + R_XHCI_USB2PDO, XhciUsb2Pdo); + MmioWrite32 (XhciMmioBase + R_XHCI_USB3PDO, XhciUsb3Pdo); +} + + +/** + Program and enable XHCI Memory Space + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciMemorySpaceOpen ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase + ) +{ + // + // Assign memory resources + // + MmioAnd16 ( + XhciPciMmBase + R_XHCI_COMMAND_REGISTER, + (UINT16)~(B_XHCI_COMMAND_MSE | B_XHCI_COMMAND_BME) + ); + MmioWrite32 (XhciPciMmBase + R_XHCI_MEM_BASE, XhciMmioBase); + MmioOr16 ( + XhciPciMmBase + R_XHCI_COMMAND_REGISTER, + (UINT16) (B_XHCI_COMMAND_MSE | B_XHCI_COMMAND_BME) + ); +} + + +/** + Clear and disable XHCI Memory Space + + @param[in] UsbConfig The SC Policy for USB configuration + @param[in] XhciMmioBase Memory base address of XHCI Controller + @param[in] XhciPciMmBase XHCI PCI Base Address + + @retval None + +**/ +VOID +XhciMemorySpaceClose ( + IN SC_USB_CONFIG *UsbConfig, + IN UINT32 XhciMmioBase, + IN UINTN XhciPciMmBase + ) +{ + // + // Clear memory resources + // + MmioAnd16 ( + XhciPciMmBase + R_XHCI_COMMAND_REGISTER, + (UINT16)~(B_XHCI_COMMAND_MSE | B_XHCI_COMMAND_BME) + ); + + MmioWrite32 ((XhciPciMmBase + R_XHCI_MEM_BASE), 0); + +} + +/** + Initialization USB Clock Gating registers + + @retval None + +**/ +VOID +ConfigureUsbClockGating ( + VOID + ) +{ + ConfigureXhciClockGating (); +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScCycleDecoding.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScCycleDecoding.c new file mode 100644 index 0000000000..65ee993a9c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScCycleDecoding.c @@ -0,0 +1,739 @@ +/** @file + Access to SC relevant IP base addresses. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ScPlatformLibrary.h" + +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ) +{ + return EFI_SUCCESS; +} + +/** + Get PCH ACPI base address. + + @param[in] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. + +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + IN UINT16 *Address + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ) +{ + return EFI_SUCCESS; +} + +/** + Get PCH PWRM base address. + + @param[in] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. + +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + IN UINT32 *Address + ) +{ + return EFI_SUCCESS; +} + +/** + Set TCO base address for legacy Smbus + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +SetTcoBase ( + IN UINT16 Address + ) +{ + UINTN SmbusBase; + + if ((Address & B_SMBUS_TCOBASE_BAR) == 0) { + DEBUG ((DEBUG_ERROR, "SetTcoBase Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + SmbusBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_SMBUS, + PCI_FUNCTION_NUMBER_SMBUS + ); + if (MmioRead16 (SmbusBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Verify TCO base is not locked. + // + if ((MmioRead8 (SmbusBase + R_SMBUS_TCOCTL) & R_SMBUS_TCOCTL_TCO_BASE_LOCK) != 0) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + // + // Disable TCO in SMBUS Device first before changing base address. + // + MmioAnd16 ( + SmbusBase + R_SMBUS_TCOCTL, + (UINT16) ~B_SMBUS_TCOCTL_TCO_BASE_EN + ); + // + // Program TCO in SMBUS Device + // + MmioAndThenOr16 ( + SmbusBase + R_SMBUS_TCOBASE, + (UINT16) (~B_SMBUS_TCOBASE_BAR), + Address + ); + // + // Enable TCO in SMBUS Device + // + MmioOr16 ( + SmbusBase + R_SMBUS_TCOCTL, + B_SMBUS_TCOCTL_TCO_BASE_EN + ); + + return EFI_SUCCESS; +} + + +/** + Get TCO base address. + + @param[in] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. + +**/ +EFI_STATUS +EFIAPI +GetTcoBase ( + IN UINT16 *Address + ) +{ + UINTN SmbusBase; + + if (Address == NULL) { + DEBUG((DEBUG_ERROR, "GetTcoBase Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + SmbusBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_SMBUS, + PCI_FUNCTION_NUMBER_SMBUS + ); + if (MmioRead16 (SmbusBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + *Address = MmioRead16 (SmbusBase + R_SMBUS_TCOBASE) & B_SMBUS_TCOBASE_BAR; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ) +{ + EFI_STATUS Status; + PCH_LPC_GEN_IO_RANGE_LIST LpcGenIoRangeList; + UINTN LpcBase; + UINTN Index; + UINTN BaseAddr; + UINTN MaskLength; + UINTN TempMaxAddr; + UINT32 Data32; + UINTN ArraySize; + static struct EXCEPT_RANGE { + UINT8 Start; + UINT8 Length; + } ExceptRanges[] = { {0x00, 0x20}, {0x44, 0x08}, {0x54, 0x0C}, {0x68, 0x08}, {0x80, 0x10}, {0x90, 0x10}, {0xC0, 0x40} }; + + if (((Length & (Length - 1)) != 0) || + ((Address & (UINT16)~B_PCH_LPC_GENX_DEC_IOBAR) != 0) || + (Length > 256)) + { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (Address < 0x100) { + ArraySize = sizeof (ExceptRanges) / sizeof (struct EXCEPT_RANGE); + for (Index = 0; Index < ArraySize; Index++) { + if ((Address >= ExceptRanges[Index].Start) && + ((Address + Length) <= ((UINTN) ExceptRanges[Index].Start + (UINTN) ExceptRanges[Index].Length))) { + break; + } + } + if (Index >= ArraySize) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + } + + // + // check if range overlap + // + Status = PchLpcGenIoRangeGet (&LpcGenIoRangeList); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr = LpcGenIoRangeList.Range[Index].BaseAddr; + MaskLength = LpcGenIoRangeList.Range[Index].Length; + if (BaseAddr == 0) { + continue; + } + if (((Address >= BaseAddr) && (Address < (BaseAddr + MaskLength))) || + (((Address + Length) > BaseAddr) && ((Address + Length) <= (BaseAddr + MaskLength)))) { + if ((Address >= BaseAddr) && (Length <= MaskLength)) { + // + // return SUCCESS while range is covered. + // + return EFI_SUCCESS; + } + + if ((Address + Length) > (BaseAddr + MaskLength)) { + TempMaxAddr = Address + Length; + } else { + TempMaxAddr = BaseAddr + MaskLength; + } + if (Address > BaseAddr) { + Address = (UINT16) BaseAddr; + } + Length = TempMaxAddr - Address; + break; + } + } + // + // If no range overlap + // + if (Index >= PCH_LPC_GEN_IO_RANGE_MAX) { + // + // Find a empty register + // + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr = LpcGenIoRangeList.Range[Index].BaseAddr; + if (BaseAddr == 0) { + break; + } + } + if (Index >= PCH_LPC_GEN_IO_RANGE_MAX) { + return EFI_OUT_OF_RESOURCES; + } + } + // + // Program LPC/eSPI generic IO range register accordingly. + // + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + Data32 = (UINT32) (((Length - 1) << 16) & B_PCH_LPC_GENX_DEC_IODRA); + Data32 |= (UINT32) Address; + Data32 |= B_PCH_LPC_GENX_DEC_EN; + // + // Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + // + MmioWrite32 ( + LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4, + Data32 + ); + + return EFI_SUCCESS; +} + + +/** + Get PCH LPC/eSPI generic IO range list. + This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + ) +{ + UINTN Index; + UINTN LpcBase; + UINT32 Data32; + + if (LpcGenIoRangeList == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + Data32 = MmioRead32 (LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4); + LpcGenIoRangeList->Range[Index].BaseAddr = Data32 & B_PCH_LPC_GENX_DEC_IOBAR; + LpcGenIoRangeList->Range[Index].Length = ((Data32 & B_PCH_LPC_GENX_DEC_IODRA) >> 16) + 4; + LpcGenIoRangeList->Range[Index].Enable = Data32 & B_PCH_LPC_GENX_DEC_EN; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + ) +{ + UINTN LpcBase; + + if ((Address & (~B_PCH_LPC_LGMR_MA)) != 0) { + DEBUG ((DEBUG_ERROR, "PchLpcMemRangeSet Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + // + // Program LPC/eSPI PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address. + // + MmioAnd32 ( + LpcBase + R_PCH_LPC_LGMR, + (UINT32) ~B_PCH_LPC_LGMR_LMRD_EN + ); + + // + // Program LPC/eSPI PCI Offset 98h [31:16, 0] to [Address, 1]. + // + MmioWrite32 ( + LpcBase + R_PCH_LPC_LGMR, + (Address | B_PCH_LPC_LGMR_LMRD_EN) + ); + + return EFI_SUCCESS; +} + + +/** + Get PCH LPC/eSPI memory range decoding address. + + @param[in] Address Address of LPC/eSPI memory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + IN UINT32 *Address + ) +{ + UINTN LpcBase; + + if (Address == NULL) { + DEBUG ((DEBUG_ERROR, "PchLpcMemRangeGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + *Address = MmioRead32 (LpcBase + R_PCH_LPC_LGMR) & B_PCH_LPC_LGMR_MA; + + return EFI_SUCCESS; +} + + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnable. + 2. program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC or SPI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ) +{ + UINTN BaseAddr; + UINT8 Bbs; + + BaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + Bbs = MmioRead8(BaseAddr + R_PCH_LPC_BC) & B_PCH_LPC_BC_BBS; + // + // Check General Control and Status (GCS) [10] + // '0': SPI + // '1': LPC/eSPI + // + if (Bbs == 0) { + BaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_SPI, + PCI_FUNCTION_NUMBER_SPI + ); + // + // if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + // + MmioWrite16 (BaseAddr + R_SPI_BDE, BiosDecodeEnable); + } else { + BaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // if GCS.BBS is 1 (LPC/eSPI), program LPC offset D8h to BiosDecodeEnable. + // + MmioWrite16 (BaseAddr + R_PCH_LPC_BDE, BiosDecodeEnable); + } + + return EFI_SUCCESS; +} + + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINTN LpcBaseAddr; + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // check if setting is identical + // + if (LpcIoDecodeRanges == MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD)) { + return EFI_SUCCESS; + } + + // + // program LPC/eSPI PCI offset 80h. + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOD, LpcIoDecodeRanges); + + return EFI_SUCCESS; +} + + +/** + Set PCH LPC/eSPI IO enable decoding. + Setup LPC/eSPI I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC/eSPI PCI offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ) +{ + UINTN LpcBaseAddr; + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + if (LpcIoEnableDecoding == MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE)) { + return EFI_SUCCESS; + } + // + // program LPC/eSPI PCI offset 82h. + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOE, LpcIoEnableDecoding); + + return EFI_SUCCESS; +} + + +/** + Set PCH TraceHub base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program TraceHub PCI Offset 0x70~0x77 to the 64-bit base address. + 2. Program PCR[PSF3] + TraceHub RS0 offset 0x000 and 0x004 to TraceHub 64-bit base address. + 3. Manually write 1 to MSEN, PCR[PSF3] + TraceHub RS0 offset 0x01C[1] to activate the shadow. + + @param[in] AddressHi High 32-bits for TraceHub base address. + @param[in] AddressLo Low 32-bits for TraceHub base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. + +**/ +EFI_STATUS +EFIAPI +PchTraceHubBaseSet ( + IN UINT32 AddressHi, + IN UINT32 AddressLo + ) +{ + return EFI_SUCCESS; +} + +// +// PCH-LP RPR destination ID table +// +UINT16 PchLpRprDidTable[] = { + 0x2188, ///< Dest ID of RP1 + 0x2189, ///< Dest ID of RP2 + 0x218A, ///< Dest ID of RP3 + 0x218B, ///< Dest ID of RP4 + 0x2198, ///< Dest ID of RP5 + 0x2199, ///< Dest ID of RP6 + 0x219A, ///< Dest ID of RP7 + 0x219B, ///< Dest ID of RP8 + 0x21A8, ///< Dest ID of RP9 + 0x21A9, ///< Dest ID of RP10 + 0x21AA, ///< Dest ID of RP11 + 0x21AB ///< Dest ID of RP12 +}; + +// +// PCH-H RPR destination ID table +// +UINT16 PchHRprDidTable[] = { + 0x2180, ///< Dest ID of RP1 + 0x2181, ///< Dest ID of RP2 + 0x2182, ///< Dest ID of RP3 + 0x2183, ///< Dest ID of RP4 + 0x2188, ///< Dest ID of RP5 + 0x2189, ///< Dest ID of RP6 + 0x218A, ///< Dest ID of RP7 + 0x218B, ///< Dest ID of RP8 + 0x2198, ///< Dest ID of RP9 + 0x2199, ///< Dest ID of RP10 + 0x219A, ///< Dest ID of RP11 + 0x219B, ///< Dest ID of RP12 + 0x21A8, ///< Dest ID of RP13 + 0x21A9, ///< Dest ID of RP14 + 0x21AA, ///< Dest ID of RP15 + 0x21AB, ///< Dest ID of RP16 + 0x21B8, ///< Dest ID of RP17 + 0x21B9, ///< Dest ID of RP18 + 0x21BA, ///< Dest ID of RP19 + 0x21BB, ///< Dest ID of RP20 +}; + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus enumeration. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. + +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ) +{ + return EFI_SUCCESS; +} + +/** + return SPI linear Base address of descriptor region section + + @param[in] RegNum FLREG number of region section defined in the descriptor + + @retval UINT32 Base address of the FLREG +**/ +UINT32 +GetSpiFlashRegionBase ( + IN UINTN RegNum + ) +{ + UINTN SpiPciBase; + UINT32 SpiBar0; + UINT32 FlashRegBase; + UINT16 TempCmd; + + SpiPciBase = MmPciBase ( DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SPI, PCI_FUNCTION_NUMBER_SPI); + SpiBar0 = MmioRead32 (SpiPciBase + R_SPI_BASE) & B_SPI_BASE_BAR; + TempCmd = MmioRead16 (SpiPciBase + PCI_COMMAND_OFFSET); + MmioOr16 (SpiPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + FlashRegBase = MmioRead32 (SpiBar0 + R_SPI_FREG0_FLASHD + RegNum * 4) & B_SPI_FREG0_BASE_MASK; + if (FlashRegBase == V_SPI_FLREG_DISABLED) { + FlashRegBase = 0; + DEBUG((DEBUG_ERROR, "SPI FLREG%d is disabled!!!\n", RegNum)); + } + FlashRegBase <<= N_SPI_FREG0_BASE; + + DEBUG ((DEBUG_INFO, "SPI FLREG%d base = 0x%x\n", RegNum, FlashRegBase)); + MmioWrite16 (SpiPciBase + PCI_COMMAND_OFFSET, TempCmd); + + return FlashRegBase; +} + + +/** + return SPI linear Base address of descriptor region section + + @param[in] RegNum FLREG number of region section defined in the descriptor + + @retval UINTN Base address of the FLREG + +**/ +UINT32 +GetSpiFlashRegionLimit ( + UINTN RegNum + ) +{ + UINTN SpiPciBase; + UINT32 SpiBar0; + UINT32 FlashRegLimit; + UINT16 TempCmd; + + SpiPciBase = MmPciBase ( DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_SPI, PCI_FUNCTION_NUMBER_SPI); + SpiBar0 = MmioRead32 (SpiPciBase + R_SPI_BASE) & B_SPI_BASE_BAR; + TempCmd = MmioRead16 (SpiPciBase + PCI_COMMAND_OFFSET); + MmioOr16 (SpiPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + FlashRegLimit = MmioRead32 (SpiBar0 + R_SPI_FREG0_FLASHD + RegNum * 4) & B_SPI_FREG0_LIMIT_MASK; + FlashRegLimit >>= N_SPI_FREG1_LIMIT; + + if (FlashRegLimit == V_SPI_FLREG_DISABLED) { + FlashRegLimit = 0; + DEBUG((DEBUG_ERROR, "SPI FLREG%d is disabled!!!\n", RegNum)); + } + + DEBUG ((DEBUG_INFO, "SPI FLREG%d limit = 0x%x\n", RegNum, FlashRegLimit)); + MmioWrite16 (SpiPciBase + PCI_COMMAND_OFFSET, TempCmd); + + return FlashRegLimit; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLib.inf new file mode 100644 index 0000000000..83a2c4bcaf --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLib.inf @@ -0,0 +1,46 @@ +## @file +# Library for ScPlatform. +# +# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = ScPlatformLib + FILE_GUID = 32F89CBC-305D-4bdd-8B2C-9C65592E66AC + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ScPlatformLib + +[sources.common] + ScPlatformLibrary.h + ScPlatformLibrary.c + ScCycleDecoding.c + ScSbiAccess.c + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + BaseLib + PciLib + PcdLib + IoLib + DebugLib + SideBandLib + MmPciLib + SteppingLib + +[Pcd] + gEfiBxtTokenSpaceGuid.PcdScAcpiIoPortBaseAddress ## SOMETIMES_CONSUMES + gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress ## SOMETIMES_CONSUMES diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c new file mode 100644 index 0000000000..afc744ac39 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.c @@ -0,0 +1,843 @@ +/** @file + SC Platform Lib implementation. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ScPlatformLibrary.h" +#include + +// +// For BXT-P, it supports two express port controllers: +// Controller 1: +// Port 1-2, Device 20, function 0-1 +// Controller 2: +// Port 3-6, Device 19, function 0-3 +// For BXT-X, it supports one express port controllers: +// Controller 1: +// Port 1-4, Device 19, function 0-3 +// For BXT-0/1, it supports one express port controllers: +// Controller 1: +// Port 1-2, Device 20, function 0-1 +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCIE_CONTROLLER_INFO mPcieControllerInfo[] = { + { PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_1, 0xB3, 0 }, + { PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_2, 0xB4, 2 } +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mPcieControllerInfoSize = sizeof (mPcieControllerInfo) / sizeof (mPcieControllerInfo[0]); + + +/** + Get Sc Maximum Pcie Root Port Number + + @retval UINT8 Sc Maximum Pcie Root Port Number +**/ +UINT8 +EFIAPI +GetScMaxPciePortNum ( + VOID + ) +{ + BXT_SERIES BxtSeries; + + BxtSeries = GetBxtSeries (); + switch (BxtSeries) { + case BxtX: + return SC_BXTX_PCIE_MAX_ROOT_PORTS; + case BxtP: + return SC_BXTP_PCIE_MAX_ROOT_PORTS; + case Bxt1: + return SC_BXT_PCIE_MAX_ROOT_PORTS; + default: + return 0; + } +} + + +/** + Delay for at least the request number of microseconds. + This function would be called by runtime driver, please do not use any MMIO marco here. + + @param[in] Microseconds Number of microseconds to delay. + +**/ +VOID +EFIAPI +ScPmTimerStall ( + IN UINTN Microseconds + ) +{ + UINTN Ticks; + UINTN Counts; + UINTN CurrentTick; + UINTN OriginalTick; + UINTN RemainingTick; + UINT16 AcpiBaseAddr; + + if (Microseconds == 0) { + return; + } + + // + // Read ACPI Base Address + // + AcpiBaseAddr = (UINT16)PcdGet16(PcdScAcpiIoPortBaseAddress); + + OriginalTick = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL; + CurrentTick = OriginalTick; + + // + // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks + // + Ticks = Microseconds * 358 / 100 + OriginalTick + 1; + + // + // The loops needed by timer overflow + // + Counts = Ticks / V_ACPI_PM1_TMR_MAX_VAL; + + // + // Remaining clocks within one loop + // + RemainingTick = Ticks % V_ACPI_PM1_TMR_MAX_VAL; + + // + // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra + // one I/O operation, and maybe generate SMI + // + while ((Counts != 0) || (RemainingTick > CurrentTick)) { + CurrentTick = IoRead32 ((UINTN) (AcpiBaseAddr + R_ACPI_PM1_TMR)) & B_ACPI_PM1_TMR_VAL; + // + // Check if timer overflow + // + if ((CurrentTick < OriginalTick)) { + if (Counts != 0) { + Counts--; + } else { + // + // If timer overflow and Counts equ to 0, that means we already stalled more than + // RemainingTick, break the loop here + // + break; + } + } + + OriginalTick = CurrentTick; + } +} + + +/** + Check whether SPI is in descriptor mode + + @param[in] SpiBase The SC SPI Base Address + + @retval TRUE SPI is in descriptor mode + @retval FALSE SPI is not in descriptor mode + +**/ +BOOLEAN +EFIAPI +ScIsSpiDescriptorMode ( + IN UINTN SpiBase + ) +{ + if ((MmioRead16 (SpiBase + R_SPI_HSFS) & B_SPI_HSFS_FDV) == B_SPI_HSFS_FDV) { + MmioAndThenOr32 ( + SpiBase + R_SPI_FDOC, + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLVALSIG) + ); + if ((MmioRead32 (SpiBase + R_SPI_FDOD)) == V_SPI_FDBAR_FLVALSIG) { + return TRUE; + } else { + return FALSE; + } + } else { + return FALSE; + } +} + + +/** + This function can be called to poll for certain value within a time given. + + @param[in] MmioAddress The Mmio Address. + @param[in] BitMask Bits to be masked. + @param[in] BitValue Value to be polled. + @param[in] DelayTime Delay time in terms of 100 micro seconds. + + @retval EFI_SUCCESS Successfully polled the value. + @retval EFI_TIMEOUT Timeout while polling the value. + +**/ +EFI_STATUS +EFIAPI +ScMmioPoll32 ( + IN UINTN MmioAddress, + IN UINT32 BitMask, + IN UINT32 BitValue, + IN UINT16 DelayTime + ) +{ + UINT32 LoopTime; + UINT8 PollSuccess; + + LoopTime = 0; + PollSuccess = 0; + + for (LoopTime = 0; LoopTime < DelayTime; LoopTime++) { + if ((MmioRead32 (MmioAddress) & BitMask) == BitValue) { + PollSuccess = 1; + break; + } else { + ScPmTimerStall (100); + } + } + + if (PollSuccess) { + return EFI_SUCCESS; + } else { + return EFI_TIMEOUT; + } +} + + +/** + Determine if the specificed device is available + + @param[in] RpDev Device number + + @retval FALSE Device is not available. + TRUE Device is available. + +**/ +BOOLEAN +IsPcieControllerAvailable ( + IN UINTN *RpDev +) +{ + UINT32 FuncDisableReg; + UINT32 FuncDisableMask; + + if (*RpDev == PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_1) { + FuncDisableReg = MmioRead32 (PMC_BASE_ADDRESS + R_PMC_FUNC_DIS); + FuncDisableMask = (B_PMC_FUNC_DIS_PCIE0_P1 | B_PMC_FUNC_DIS_PCIE0_P0); + } else { + FuncDisableReg = MmioRead32 (PMC_BASE_ADDRESS + R_PMC_FUNC_DIS_1); + FuncDisableMask = (B_PMC_FUNC_DIS_1_PCIE1_P3 | B_PMC_FUNC_DIS_1_PCIE1_P2 | B_PMC_FUNC_DIS_1_PCIE1_P1 | B_PMC_FUNC_DIS_1_PCIE1_P0); + } + + if ((FuncDisableReg & FuncDisableMask) == FuncDisableMask) { + return FALSE; + } else { + return TRUE; + } +} + + +/** + Get Sc Pcie Root Port Device and Function Number by Root Port physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device number. + @param[out] RpFun Return corresponding root port function number. + + @retval EFI_SUCCESS Root port device and function is retrieved + @retval EFI_INVALID_PARAMETER RpNumber is invalid + +**/ +EFI_STATUS +EFIAPI +GetScPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ) +{ + UINTN Index; + UINTN FuncIndex; + UINT32 PciePcd; + + // + // if BXT SC , RpNumber must be < 6. + // + if (RpNumber >= GetScMaxPciePortNum ()) { + DEBUG ((DEBUG_ERROR, "GetScPcieRpDevFun invalid RpNumber %x\n", RpNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (RpNumber >= 2) { + Index = 1; + }else { + Index = 0; + } + FuncIndex = RpNumber - mPcieControllerInfo[Index].RpNumBase; + *RpDev = mPcieControllerInfo[Index].DevNum; + + // + // Before doing the actual PCD read, ensure the device is available + // + if (IsPcieControllerAvailable (RpDev) == TRUE) { + PchPcrRead32 (mPcieControllerInfo[Index].Pid, 0x0000, &PciePcd); + *RpFun = (PciePcd >> (FuncIndex * 4)) & (BIT2 | BIT1 | BIT0); + } else { + *RpFun = FuncIndex; + } + + return EFI_SUCCESS; +} + +/** + Get Root Port physical Number by Sc Pcie Root Port Device and Function Number + + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding Root port physical number. + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port + +**/ +EFI_STATUS +EFIAPI +GetScPcieRpNumber ( + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ) +{ + UINTN Index; + UINTN FuncIndex; + UINT32 PciePcd; + + // + // if BXT SC, must be Dev == 19 and Fun < 4, or Dev == 20 and Fun < 2. + // + if (!((RpDev == PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_1) && (RpFun < 2)) && + !((RpDev == PCI_DEVICE_NUMBER_SC_PCIE_DEVICE_2) && (RpFun < 4))) { + DEBUG ((DEBUG_ERROR, "GetPchPcieRpNumber invalid RpDev %x RpFun %x", RpDev, RpFun)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + for (Index = 0; Index < mPcieControllerInfoSize; Index++) { + if (mPcieControllerInfo[Index].DevNum == RpDev) { + PchPcrRead32 (mPcieControllerInfo[Index].Pid, 0x0000, &PciePcd); + for (FuncIndex = 0; FuncIndex < 4; FuncIndex ++) { + if (RpFun == ((PciePcd >> (FuncIndex * 4)) & (BIT2 | BIT1 | BIT0))) { + break; + } + } + if (FuncIndex < 4) { + *RpNumber = mPcieControllerInfo[Index].RpNumBase + FuncIndex; + break; + } + } + } + if (Index >= mPcieControllerInfoSize) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + + +/** + Read PCR register. (This is internal function) + It returns PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +STATIC +EFI_STATUS +PchPcrRead ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + OUT UINT32 *OutData + ) +{ + if ((Offset & (Size - 1)) != 0) { + DEBUG ((DEBUG_ERROR, "PchPcrRead error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + switch (Size) { + case 4: + *(UINT32 *) OutData = MmioRead32 (SC_PCR_ADDRESS (Pid, Offset)); + break; + case 2: + *(UINT16 *) OutData = MmioRead16 (SC_PCR_ADDRESS (Pid, Offset)); + break; + case 1: + *(UINT8 *) OutData = MmioRead8 (SC_PCR_ADDRESS (Pid, Offset)); + break; + default: + break; + } + + return EFI_SUCCESS; +} + + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 4, (UINT32*) OutData); +} + + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 2, (UINT32*) OutData); +} + + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrRead8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 1, (UINT32*) OutData); +} + + +#ifdef EFI_DEBUG +/** + Check if the port ID is available for sideband mmio read/write + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval TRUE available for sideband Mmio read/write method + @retval FALSE inavailable for sideband Mmio read/write method + +**/ +BOOLEAN +PchPcrWriteMmioCheck ( + IN SC_SBI_PID Pid, + IN UINT16 Offset + ) +{ + return TRUE; +} +#endif + + +/** + Write PCR register. (This is internal function) + It programs PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +STATIC +EFI_STATUS +PchPcrWrite ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + IN UINT32 InData + ) +{ + if ((Offset & (Size - 1)) != 0) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +#ifdef EFI_DEBUG + if (!PchPcrWriteMmioCheck (Pid, Offset)) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Pid: %x Offset: %x should access through SBI interface", Pid, Offset)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +#endif + + // + // Write the PCR register with provided data + // Then read back PCR register to prevent from back to back write. + // + switch (Size) { + case 4: + MmioWrite32 (SC_PCR_ADDRESS (Pid, Offset), (UINT32)InData); + break; + case 2: + MmioWrite16 (SC_PCR_ADDRESS (Pid, Offset), (UINT16)InData); + break; + case 1: + MmioWrite8 (SC_PCR_ADDRESS (Pid, Offset), (UINT8) InData); + break; + default: + break; + } + + return EFI_SUCCESS; +} + + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ) +{ + return PchPcrWrite (Pid, Offset, 4, InData); +} + + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ) +{ + return PchPcrWrite (Pid, Offset, 2, InData); +} + + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrWrite8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ) +{ + return PchPcrWrite (Pid, Offset, 1, InData); +} + + +/** + Reads an 4-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 4-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + EFI_STATUS Status; + UINT32 Data32; + + Status = PchPcrRead (Pid, Offset, 4, &Data32); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 &= AndData; + Data32 |= OrData; + Status = PchPcrWrite (Pid, Offset, 4, Data32); + + return Status; +} + + +/** + Reads an 2-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 2-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + EFI_STATUS Status; + UINT16 Data16; + + Status = PchPcrRead (Pid, Offset, 2, (UINT32*) &Data16); + if (EFI_ERROR (Status)) { + return Status; + } + Data16 &= AndData; + Data16 |= OrData; + Status = PchPcrWrite (Pid, Offset, 2, Data16); + + return Status; +} + + +/** + Reads an 1-byte Pcr register, performs a bitwise AND followed by a bitwise + inclusive OR, and writes the result back to the 1-byte Pcr register. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. + +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN SC_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + EFI_STATUS Status; + UINT8 Data8; + + Status = PchPcrRead (Pid, Offset, 1, (UINT32 *) &Data8); + if (EFI_ERROR (Status)) { + return Status; + } + Data8 &= AndData; + Data8 |= OrData; + Status = PchPcrWrite (Pid, Offset, 1, Data8); + + return Status; +} + + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controller. + + @retval EFI_SUCCESS Always return success. + +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ) +{ + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + return EFI_SUCCESS; +} + + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not after. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controller. + @param[out] OrgStatus Original P2SB hidding/unhidden status + + @retval EFI_SUCCESS Always return success. + +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ) +{ + BOOLEAN DevicePresent; + + DevicePresent = (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + if (OrgStatus != NULL) { + *OrgStatus = DevicePresent; + } + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + + return EFI_SUCCESS; +} + + +/** + Get Sc Maximum Usb3 Port Number of XHCI Controller + + @retval UINT8 Sc Maximum Usb3 Port Number of XHCI Controller + +**/ +UINT8 +EFIAPI +GetScXhciMaxUsb3PortNum ( + VOID + ) +{ + BXT_SERIES BxtSeries; + + BxtSeries = GetBxtSeries (); + switch (BxtSeries) { + case Bxt: + case Bxt1: + return SC_BXT_MAX_USB3_PORTS; + + case BxtP: + return SC_BXTP_MAX_USB3_PORTS; + + default: + return 0; + } +} + + +/** + Get Sc Maximum Usb2 Port Number of XHCI Controller + + @retval UINT8 Sc Maximum Usb2 Port Number of XHCI Controller + +**/ +UINT8 +EFIAPI +GetScXhciMaxUsb2PortNum ( + VOID + ) +{ + BXT_SERIES BxtSeries; + + BxtSeries = GetBxtSeries (); + switch (BxtSeries) { + case Bxt: + case Bxt1: + return SC_BXT_MAX_USB2_PORTS; + + case BxtP: + return SC_BXTP_MAX_USB2_PORTS; + + default: + return 0; + } +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.h new file mode 100644 index 0000000000..9015afd312 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScPlatformLibrary.h @@ -0,0 +1,32 @@ +/** @file + Header file for SC Platform Lib implementation. + + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SC_PLATFORM_LIBRARY_IMPLEMENTATION_H_ +#define _SC_PLATFORM_LIBRARY_IMPLEMENTATION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScSbiAccess.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScSbiAccess.c new file mode 100644 index 0000000000..9741479d08 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/ScPlatformLib/ScSbiAccess.c @@ -0,0 +1,297 @@ +/** @file + Program SC SBI register. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ScPlatformLibrary.h" + +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN SC_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + // + // Check address valid + // + if (((UINT32) Offset & 0x3) != 0) { + // + // Warning message for the address not DWORD alignment. + // + DEBUG ((DEBUG_INFO, "PchSbiExecution: Be careful that the address is not DWORD alignment.\n")); + } + + return PchSbiExecutionEx ( + Pid, + Offset, + Opcode, + Posted, + 0x000F, + 0x0000, + 0x0000, + Data32, + Response + ); +} + +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN SC_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + EFI_STATUS Status; + UINTN P2sbBase; + BOOLEAN P2sbOrgStatus; + UINTN Timeout; + UINT16 SbiStat; + + // + // Check opcode valid + // + switch (Opcode) { + case PciConfigRead: + case PciConfigWrite: + case PrivateControlRead: + case PrivateControlWrite: + case GpioLockUnlock: + break; + default: + return EFI_INVALID_PARAMETER; + break; + } + + P2sbOrgStatus = FALSE; + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + PchRevealP2sb (P2sbBase, &P2sbOrgStatus); + + Timeout = 0xFFFFFFF; + while (Timeout > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + Timeout--; + } + if (Timeout == 0) { + Status = EFI_DEVICE_ERROR; + goto ExitPchSbiExecutionEx; + } + // + // Initial Response status + // + *Response = SBI_INVALID_RESPONSE; + Status = EFI_SUCCESS; + SbiStat = 0; + + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR, (UINT32) ((Pid << 24) | (UINT16)Offset)); + + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, (UINT32) RShiftU64 (Offset, 16)); + + MmioAndThenOr16 ( + (P2sbBase + R_PCH_P2SB_SBISTAT), + (UINT16) ~(B_PCH_P2SB_SBISTAT_OPCODE | B_PCH_P2SB_SBISTAT_POSTED), + (UINT16) ((Opcode << 8) | (Posted << 7)) + ); + + MmioWrite16 ( + (P2sbBase + R_PCH_P2SB_SBIRID), + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) + ); + + switch (Opcode) { + case PciConfigWrite: + case PrivateControlWrite: + case GpioLockUnlock: + + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), *Data32); + break; + default: + + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), 0); + break; + } + + MmioOr16 (P2sbBase + R_PCH_P2SB_SBISTAT, (UINT16) B_PCH_P2SB_SBISTAT_INITRDY); + // + // Poll SBISTAT[0] = 0b, Polling for Busy bit + // + Timeout = 0xFFFFFFF; + while (Timeout > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + Timeout--; + } + if (Timeout == 0) { + // + // If timeout, it's fatal error. + // + Status = EFI_DEVICE_ERROR; + } else { + *Response = (UINT8) ((SbiStat & B_PCH_P2SB_SBISTAT_RESPONSE) >> N_PCH_P2SB_SBISTAT_RESPONSE); + if (*Response == SBI_SUCCESSFUL) { + switch (Opcode) { + case PciConfigRead: + case PrivateControlRead: + *Data32 = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA); + break; + default: + break; + } + Status = EFI_SUCCESS; + } else { + Status = EFI_DEVICE_ERROR; + } + } + +ExitPchSbiExecutionEx: + if (!P2sbOrgStatus) { + PchHideP2sb (P2sbBase); + } + + return Status; +} + + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. + +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] = 0b + // + Timeout = 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + } + if (Timeout == 0) { + return EFI_DEVICE_ERROR; + } + // + // Save original SBI registers + // + PchSbiRegister->SbiAddr = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIADDR); + PchSbiRegister->SbiExtAddr = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR); + PchSbiRegister->SbiData = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA); + PchSbiRegister->SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + PchSbiRegister->SbiRid = MmioRead16 (P2sbBase + R_PCH_P2SB_SBIRID); + + return EFI_SUCCESS; +} + + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. + +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] = 0b + // + Timeout = 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + } + if (Timeout == 0) { + return EFI_DEVICE_ERROR; + } + // + // Restore original SBI registers + // + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR , PchSbiRegister->SbiAddr); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, PchSbiRegister->SbiExtAddr); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIDATA , PchSbiRegister->SbiData); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBISTAT , PchSbiRegister->SbiStat); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBIRID , PchSbiRegister->SbiRid); + + return EFI_SUCCESS; +} + -- cgit v1.2.3