From f5e2c28c29be23070b88e71bb1f0acb6a7a4a252 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 16 Feb 2017 11:24:18 +0800 Subject: Fix MRC restore issue MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang Reviewed-by: zwei4 --- .../BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h | 2 ++ .../MemoryInit/BXT/Include/MrcEfiDefinitions.h | 3 ++- .../Mmrc/ProjectIndependent/Include/MmrcData.h | 24 +++++++++++++++++++++- 3 files changed, 27 insertions(+), 2 deletions(-) (limited to 'Silicon') diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h index 7eb0e923db..a2da161290 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h @@ -56,10 +56,12 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; + UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h index b19d6a05c6..5d36a6d3a5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h @@ -64,10 +64,12 @@ typedef struct { UINT8 RmtMode; UINT8 RmtCheckRun; UINT16 RmtMarginCheckScaleHighThreshold; + UINT8 Reserved1; UINT32 MsgLevelMask; UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES]; UINT8 ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]; DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS]; + UINT8 Reserved2; UINT8 DebugMsgLevel; UINT8 reserved[13]; } DRAM_POLICY_PPI; @@ -79,7 +81,6 @@ typedef struct { typedef enum { Bxt = 0x00, Bxt1, - BxtX, BxtP, BxtSeriesMax = 0xFF } BXT_SERIES; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h index 0d64528c45..eb0f973a29 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h @@ -52,6 +52,25 @@ typedef union { UINT8 Data8[4]; } MrcVersion; +typedef union { + UINT8 Data; + struct { + + UINT8 RankSelectInterleavingEnable : 1; + + UINT8 BankAddressHashingEnable : 1; + + UINT8 Ch1ClkDisable : 1; + + UINT8 Reserved : 1; + + UINT8 AddressMapping : 2; + + UINT8 Reserved0 : 2; + } Bits; +} CHANNEL_OPTION; + + #ifndef ABSOLUTE #define ABSOLUTE 1 #define RELATIVE 2 @@ -104,6 +123,9 @@ typedef enum { #define BIT31 0x80000000 #endif + +#pragma pack(1) + typedef enum { Pfct = 0, PfctT, @@ -212,6 +234,7 @@ typedef struct { UINT8 OdtHigh; UINT16 LP4_MR0VALUE; UINT16 LP4_MR4VALUE; + CHANNEL_OPTION ChOption; } CHANNEL; typedef struct { @@ -242,7 +265,6 @@ typedef struct { BOOT_VARIABLE_NV_DATA BootVariableNvData; } MRC_NV_DATA_FRAME; -#pragma pack() #pragma pack(pop) #endif -- cgit v1.2.3