From a8f7592e4e1ae1f80f6ee847a91c7012ea3073cc Mon Sep 17 00:00:00 2001 From: Michael Kinney Date: Tue, 17 Nov 2015 05:10:45 +0000 Subject: UefiCpuPkg: SmmCpuFeaturesLib: Add MSR_SMM_FEATURE_CONTROL support Add support for the reading and writing MSR_SMM_FEATURE_CONTROL through the SmmCpuFeaturesIsSmmRegisterSupported(), SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister() functions. This MSR is supported if the Family/Model is 06_3C, 06_45, or 06_46. (Sync patch r18690 from main trunk.) Cc: "Yao, Jiewen" Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney Reviewed-by: "Yao, Jiewen" git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18846 6f19259b-4bc3-4df7-8a09-765794883524 --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'UefiCpuPkg/Library') diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 4f2f9b65fa..0c1610d977 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -33,12 +33,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1 #define EFI_MSR_SMRR_MASK 0xFFFFF000 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11 +#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0 // // Set default value to assume SMRR is not supported // BOOLEAN mSmrrSupported = FALSE; +// +// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported +// +BOOLEAN mSmmFeatureControlSupported = FALSE; + // // Set default value to assume IA-32 Architectural MSRs are used // @@ -125,6 +131,20 @@ SmmCpuFeaturesLibConstructor ( } } + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM) + // Processor Family + // + // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation + // Intel(R) Core(TM) Processor Family MSRs + // + if (FamilyId == 0x06) { + if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) { + mSmmFeatureControlSupported = TRUE; + } + } + // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 34.4.2 SMRAM Caching @@ -457,6 +477,9 @@ SmmCpuFeaturesIsSmmRegisterSupported ( IN SMM_REG_NAME RegName ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + return TRUE; + } return FALSE; } @@ -479,6 +502,9 @@ SmmCpuFeaturesGetSmmRegister ( IN SMM_REG_NAME RegName ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); + } return 0; } @@ -501,6 +527,9 @@ SmmCpuFeaturesSetSmmRegister ( IN UINT64 Value ) { + if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { + AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); + } } /** -- cgit v1.2.3