From 881520ea6778953c57d975ca2a9cf3f2114f99c4 Mon Sep 17 00:00:00 2001 From: "Yao, Jiewen" Date: Mon, 30 Nov 2015 19:57:40 +0000 Subject: UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default So that we can use write-protection for code later. This is REPOST. It includes the bug fix from "Paolo Bonzini" : Title: fix generation of 32-bit PAE page tables "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table Entries (PDPTEs); see Table 4-8 in the SDM. With VMX extended page tables, the processor notices and fails the VM entry as soon as CR0.PG is set to 1." And thanks "Laszlo Ersek" to validate the fix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" Signed-off-by: "Paolo Bonzini" Reviewed-by: Michael Kinney Tested-by: Laszlo Ersek Cc: "Fan, Jeff" Cc: "Kinney, Michael D" Cc: "Laszlo Ersek" Cc: "Paolo Bonzini" git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524 --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c') diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index a7d790fd8a..5b11e5eb48 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -113,7 +113,7 @@ SmmInitPageTable ( // // Generate PAE page table for the first 4GB memory space // - Pages = Gen4GPageTable (PAGE_TABLE_PAGES + 1); + Pages = Gen4GPageTable (PAGE_TABLE_PAGES + 1, FALSE); // // Set IA32_PG_PMNT bit to mask this entry @@ -127,7 +127,7 @@ SmmInitPageTable ( // Fill Page-Table-Level4 (PML4) entry // PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1)); - *PTEntry = Pages + IA32_PG_P; + *PTEntry = Pages + PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); // // Set sub-entries number @@ -591,7 +591,7 @@ SmiDefaultPFHandler ( // // If the entry is not present, allocate one page from page pool for it // - PageTable[PTIndex] = AllocPage () | IA32_PG_RW | IA32_PG_P; + PageTable[PTIndex] = AllocPage () | PAGE_ATTRIBUTE_BITS; } else { // // Save the upper entry address @@ -621,7 +621,7 @@ SmiDefaultPFHandler ( // Fill the new entry // PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) | - PageAttribute | IA32_PG_A | IA32_PG_RW | IA32_PG_P; + PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS; if (UpperEntry != NULL) { SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1); } -- cgit v1.2.3