From 8268a01d2ca41cddbcccac9a4559d37e782eedc2 Mon Sep 17 00:00:00 2001 From: Shifei Lu Date: Tue, 10 Mar 2015 03:16:48 +0000 Subject: Add code to identify D0 stepping ValleyView SoC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu Reviewed-by: David Wei git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17034 6f19259b-4bc3-4df7-8a09-765794883524 --- .../ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h') diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h index 29629890c0..bf3c3c86c3 100644 --- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h @@ -119,6 +119,8 @@ typedef enum { #define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27) #define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17) #define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27) +#define V_PCH_LPC_RID_E 0x10 // D0 Stepping (17 x 17) +#define V_PCH_LPC_RID_F 0x11 // D0 Stepping (25 x 27) #define R_PCH_LPC_MLT 0x0D // Master Latency Timer #define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count -- cgit v1.2.3