From 3cbfba02fef9dae07a041fdbf2e89611d72d6f90 Mon Sep 17 00:00:00 2001 From: David Wei Date: Mon, 12 Jan 2015 09:37:20 +0000 Subject: Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei Reviewed-by: Mike Wu Reviewed-by: Hot Tian git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524 --- .../SouthCluster/Include/Protocol/ActiveBios.h | 129 +++++ .../Include/Protocol/ActiveBiosProtocol.h | 131 +++++ .../Include/Protocol/DxePchPolicyUpdateProtocol.h | 57 +++ .../Include/Protocol/EmmcCardInfoProtocol.h | 48 ++ .../SouthCluster/Include/Protocol/Gpio.h | 167 +++++++ .../Include/Protocol/HwWatchdogTimer.h | 300 +++++++++++ .../SouthCluster/Include/Protocol/I2cBus.h | 170 +++++++ .../Include/Protocol/PchExtendedReset.h | 90 ++++ .../SouthCluster/Include/Protocol/PchInfo.h | 66 +++ .../Include/Protocol/PchPlatformPolicy.h | 556 +++++++++++++++++++++ .../SouthCluster/Include/Protocol/PchReset.h | 120 +++++ .../SouthCluster/Include/Protocol/PchS3Support.h | 138 +++++ .../SouthCluster/Include/Protocol/SdHostIo.h | 415 +++++++++++++++ .../Include/Protocol/SmbiosSlotPopulation.h | 53 ++ .../Include/Protocol/SmmIchnDispatchEx.h | 165 ++++++ .../SouthCluster/Include/Protocol/SmmSmbus.h | 45 ++ .../SouthCluster/Include/Protocol/Spi.h | 266 ++++++++++ .../SouthCluster/Include/Protocol/TcoReset.h | 94 ++++ 18 files changed, 3010 insertions(+) create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h (limited to 'Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol') diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h new file mode 100644 index 0000000000..4f45d8b661 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h @@ -0,0 +1,129 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + ActiveBios.h + + @brief + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + + This protocol is EFI compatible. + + E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped + to PCI, SPI, or FWH. + +**/ +#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_ +#define _EFI_ACTIVE_BIOS_PROTOCOL_H_ + + + + +// +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { \ + 0xebbe2d1b, 0x1647, 0x4bda, 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \ + } +extern EFI_GUID gEfiActiveBiosProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL; + +/// +/// Protocol definitions +/// +typedef enum { + ActiveBiosStateSpi, + ActiveBiosStatePci, /// Obsolete since VLV + ActiveBiosStateLpc, + ActiveBiosStateMax +} EFI_ACTIVE_BIOS_STATE; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN EFI_ACTIVE_BIOS_STATE DesiredState, + IN UINTN Key + ) +/** + + @brief + Change the current active BIOS settings to the requested state. + The caller is responsible for requesting a supported state from + the EFI_ACTIVE_BIOS_STATE selections. + This will fail if someone has locked the interface and the correct key is + not provided. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] DesiredState The requested state to configure the system for. + @param[in] Key If the interface is locked, Key must be the Key + returned from the LockState function call. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_ACCESS_DENIED The interface is currently locked. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN BOOLEAN Lock, + IN OUT UINTN *Key + ); + +/** + + @brief + Lock the current active BIOS state from further changes. This allows a + caller to implement a critical section. This is optionally supported + functionality. Size conscious implementations may choose to require + callers cooperate without support from this protocol. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] Lock TRUE to lock the current state, FALSE to unlock. + @param[in] Key If Lock is TRUE, then a key will be returned. If + Lock is FALSE, the key returned from the prior call + to lock the protocol must be provided to unlock the + protocol. The value of Key is undefined except that + it cannot be 0. + + @retval EFI_SUCCESS Command succeed. + @exception EFI_UNSUPPORTED The function is not supported. + @retval EFI_ACCESS_DENIED The interface is currently locked. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. + +**/ + +/// +/// Protocol definition +/// +/// Note that some functions are optional. This means that they may be NULL. +/// Caller is required to verify that an optional function is defined by checking +/// that the value is not NULL. +/// +struct _EFI_ACTIVE_BIOS_PROTOCOL { + EFI_ACTIVE_BIOS_STATE State; + EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; + EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h new file mode 100644 index 0000000000..e59cfc09f5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h @@ -0,0 +1,131 @@ +/** + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + + This protocol is EFI compatible. + + E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped + to PCI, SPI, or FWH. + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + + +#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_ +#define _EFI_ACTIVE_BIOS_PROTOCOL_H_ + +// +// Define the protocol GUID +// +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { 0xebbe2d1b, 0x1647, 0x4bda, {0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a} } + +typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL; + +// +// Protocol definitions +// +typedef enum { + ActiveBiosStateSpi, + ActiveBiosStatePci, + ActiveBiosStateLpc, + ActiveBiosStateMax +} EFI_ACTIVE_BIOS_STATE; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL *This, + IN EFI_ACTIVE_BIOS_STATE DesiredState, + IN UINTN Key + ); +/*++ + +Routine Description: + + Change the current active BIOS settings to the requested state. + The caller is responsible for requesting a supported state from + the EFI_ACTIVE_BIOS_STATE selections. + + This will fail if someone has locked the interface and the correct key is + not provided. + +Arguments: + + This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + DesiredState The requested state to configure the system for. + Key If the interface is locked, Key must be the Key + returned from the LockState function call. + +Returns: + + EFI_SUCCESS Command succeed. + EFI_ACCESS_DENIED The interface is currently locked. + EFI_DEVICE_ERROR Device error, command aborts abnormally. + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL *This, + IN BOOLEAN Lock, + IN OUT UINTN *Key + ); +/*++ + +Routine Description: + + Lock the current active BIOS state from further changes. This allows a + caller to implement a critical section. This is optionally supported + functionality. Size conscious implementations may choose to require + callers cooperate without support from this protocol. + +Arguments: + + This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + Lock TRUE to lock the current state, FALSE to unlock. + Key If Lock is TRUE, then a key will be returned. If + Lock is FALSE, the key returned from the prior call + to lock the protocol must be provided to unlock the + protocol. The value of Key is undefined except that it + will never be 0. + +Returns: + + EFI_SUCCESS Command succeed. + EFI_UNSUPPORTED The function is not supported. + EFI_ACCESS_DENIED The interface is currently locked. + EFI_DEVICE_ERROR Device error, command aborts abnormally. + +--*/ + +// +// Protocol definition +// +// Note that some functions are optional. This means that they may be NULL. +// Caller is required to verify that an optional function is defined by checking +// that the value is not NULL. +// +struct _EFI_ACTIVE_BIOS_PROTOCOL { + EFI_ACTIVE_BIOS_STATE State; + EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; + EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; +}; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiActiveBiosProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h new file mode 100644 index 0000000000..25dbb502ac --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h @@ -0,0 +1,57 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + DxePchPolicyUpdateProtocol.h + +Abstract: + + PCH policy update protocol. This protocol is consumed by the PchDxePolicyInit driver + +--*/ +#ifndef _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_ +#define _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_ + +#include "PchRegs.h" + + +#ifdef ECP_FLAG +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \ + { \ + 0x1a819e49, 0xd8ee, 0x48cb, 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \ + } +#else +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \ + { \ + 0x1a819e49, 0xd8ee, 0x48cb, \ + { \ + 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \ + } \ + } +#endif + +extern EFI_GUID gDxePchPolicyUpdateProtocolGuid; +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1 1 + +// +// ------------ General PCH policy Update protocol definition ------------ +// +struct _DXE_PCH_POLICY_UPDATE_PROTOCOL { + UINT8 Revision; +}; + +typedef struct _DXE_PCH_POLICY_UPDATE_PROTOCOL DXE_PCH_POLICY_UPDATE_PROTOCOL; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h new file mode 100644 index 0000000000..718ddbcc7f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h @@ -0,0 +1,48 @@ +/*++ + +Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ +Module Name: + + EmmcCardInfoProtocol.h + +Abstract: + + Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL + +--*/ + + +#ifndef _EMMC_CARD_INFO_H_ +#define _EMMC_CARD_INFO_H_ + +#define EFI_EMMC_CARD_INFO_PROTOCOL_GUID \ + { \ + 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd } \ + } + +typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL; + + +// +// EMMC Card info Structures +// +struct _EFI_EMMC_CARD_INFO_PROTOCOL { + CARD_DATA *CardData; +}; + +extern EFI_GUID gEfiEmmcCardInfoProtocolGuid; +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h new file mode 100644 index 0000000000..030fb83d74 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h @@ -0,0 +1,167 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Gpio.h + +Abstract: + +EFI 2.0 PEIM to provide platform specific information to other +modules and to do some platform specific initialization. + +--*/ + +#ifndef _PEI_GPIO_H +#define _PEI_GPIO_H + +//#include "Efi.h" +//#include "EfiCommonLib.h" +//#include "Pei.h" +//#include "Numbers.h" + +//// +//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint) +//// +//// Field Descriptions: +//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode. +//// I/O: Defines whether GPIOs are inputs (I) or outputs (O). +//// (Note: Only meaningful for pins used as GPIOs.) +//// LVL: This field gives you the initial value for "output" GPIO's. +//// (Note: The output level is dependent upon whether the pin is inverted.) +//// INV: Defines whether Input GPIOs activation level is inverted. +//// (Note: Only affects the level sent to the GPE logic and does not +//// affect the level read through the GPIO registers.) +//// +//// Notes: +//// 1. BoardID is GPIO [8:38:34] +//// +////Signal UsedAs USE I/O LVL INV +////-------------------------------------------------------------------------- +////GPIO0 Nonfunction G O H - +////GPIO1 SMC_RUNTIME_SCI# G I - I +////PIRQE#/GPIO2 Nonfunction G O H - +////PIRQF#/GPIO3 Nonfunction G O H - +////PIRQG#/GPIO4 Nonfunction G O H - +////PIRQH#/GPIO5 Nonfunction G O H - +////GPIO6 unused G O L - +////GPIO7 unused G O L - +////GPIO8 BOARD ID2 G I - - +////GPIO9 unused G O L - +////GPIO10 SMC_EXTSMI# G I - I +////GPIO11 Nonfunction G O H - +////GPIO12 unused G O L - +////GPIO13 SMC_WAKE_SCI# G I - I +////GPIO14 unused G O L - +////GPIO15 unused G O L - +////GPIO16 PM_DPRSLPVR N - - - +////GNT5#/GPIO17 GNT5# N - - - +////STPPCI#/GPIO18 PM_STPPCI# N - - - +////STPCPU#/GPIO20 PM_STPCPU# N - - - +////GPIO22 CRT_RefClk G I - - +////GPIO23 unused G O L - +////GPIO24 unused G O L - +////GPIO25 DMI strap G O L - +////GPIO26 unused G O L - +////GPIO27 unused G O L - +////GPIO28 RF_KILL# G O H - +////OC5#/GPIO29 OC N - - - +////OC6#/GPIO30 OC N - - - +////OC7#/GPIO31 OC N - - - +////CLKRUN#/GPIO32 PM_CLKRUN# N - - - +////GPIO33 NC G O L - +////GPIO34 BOARD ID0 G I - - +////GPIO36 unused G O L - +////GPIO38 BOARD ID1 G I - - +////GPIO39 unused G O L - +////GPIO48 unused G O L - +////CPUPWRGD/GPIO49 H_PWRGD N - - - +// +//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal +//#define GPIO_USE_SEL2_VAL 0x000100D6 +//#define GPIO_IO_SEL_VAL 0x00402502 +//#define GPIO_IO_SEL2_VAL 0x00000044 +//#define GPIO_LVL_VAL 0x1800083D +//#define GPIO_LVL2_VAL 0x00000000 +//#define GPIO_INV_VAL 0x00002402 +//#define GPIO_BLNK_VAL 0x00000000 +//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1)) + +// +// GPIO Register Settings for CedarRock and CedarFalls platforms +// +// GPIO Register Settings for NB10_CRB +//--------------------------------------------------------------------------------- +//Signal Used As USE I/O LVL +//--------------------------------------------------------------------------------- +// +// GPIO0 FP_AUDIO_DETECT G I +// GPIO1 SMC_RUNTIME_SCI# G I +// GPIO2 INT_PIRQE_N N I +// GPIO3 INT_PIRQF_N N I +// GPIO4 INT_PIRQG_N N I +// GPIO5 INT_PIRQH_N N I +// GPIO6 +// GPIO7 +// GPIO8 +// GPIO9 LPC_SIO_PME G I +// GPIO10 SMC_EXTSMI_N G I +// GPIO11 SMBALERT- pullup N +// GPIO12 ICH_GP12 G I +// GPIO13 SMC_WAKE_SCI_N G I +// GPIO14 LCD_PID0 G O H +// GPIO15 CONFIG_MODE_N G I +// GPIO16 PM_DPRSLPVR N +// GPIO17 SPI_SELECT_STRAP1 +// /L_BKLTSEL0_N G I +// GPIO18 PM_STPPCI_N N +// GPIO19 +// GPIO20 PM_STPCPU_N N +// GPIO21 +// GPIO22 REQ4B G I +// GPIO23 L_DRQ1_N N +// GPIO24 CRB_SV_DET_N G O H +// GPIO25 DMI strap +// / L_BKLTSEL1_N G O H +// GPIO26 LCD_PID1 G O H +// GPIO27 TPEV_DDR3L_DETECT G O H +// GPIO28 RF_KILL G O H:enable +// GPIO29 OC N +// GPIO30 OC N +// GPIO31 OC N +// GPIO32 PM_CLKRUN_N Native +// GPIO33 MFG_MODE_N G I +// GPIO34 BOARD ID0 G I +// GPIO35 +// GPIO36 SV_SET_UP G O H +// GPIO37 +// GPIO38 BOARD ID1 G I +// GPIO39 BOARD ID2 G I +// GPIO48 FLASH_SEL0 N +// GPIO49 H_PWRGD N + +#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2)))) +#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2)))) + +#define GPIO_USE_SEL_VAL 0X1F42F7C3 +#define GPIO_USE_SEL2_VAL 0X000000D6 +#define GPIO_IO_SEL_VAL 0X1042B73F +#define GPIO_IO_SEL2_VAL 0X000100C6 +#define GPIO_LVL_VAL 0X1F15F601 +#define GPIO_LVL2_VAL 0X000200D7 +#define GPIO_INV_VAL 0x00002602 +#define GPIO_BLNK_VAL 0x00040000 +#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1)) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h new file mode 100644 index 0000000000..61cde2f3dc --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h @@ -0,0 +1,300 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + HwWatchdogTimer.h + +Abstract: + + +--*/ + +#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ +#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ + +#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \ + { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } + +#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \ + { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf } + + +#include + +// +// General Purpose Constants +// +#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48. +#define B_INSTAFLUSH BIT4 +// +// Other Watchdog timer values +// +#define WDT_COUNTDOWN_VALUE 0x14 +#define BDS_WDT_COUNTDOWN_VALUE 0x35 + + +// +// Prototypes for the Watchdog Timer Driver Protocol +// + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_START_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service begins the Watchdog Timer countdown. If the countdown completes prior to + Stop Timer or Restart Timer the system will reset. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_RESET_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service resets the Watchdog Timer countdown and should only be called after the + Start Timer function. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service restarts the Watchdog Timer countdown and should only be called after the + Start Timer function. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_STOP_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) ( + OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) ( + IN BOOLEAN ForceTimeout, + IN UINT8 ResetType + ); +/*++ + + Routine Description: + This service forces a reboot of the system due to a reset of the POWERGOOD_PS, + POWERGOOD_CLK, and the BSEL Override + + Arguments: + None + + Returns: + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) ( + IN BOOLEAN AllowReset + ); +/*++ + + Routine Description: + This service notifies the Watchdog Timer of the fact that a known reset is occuring. + + Arguments: + AllowReset - TRUE if a Reset is currently expected + FALSE if a Reset is not currently expected + + Returns: + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 *CountdownValue + ); +/*++ + + Routine Description: + This service reads the current Watchdog Timer countdown reload value. + + Arguments: + CountdownValue - pointer to UINT32 to return the value of the reload register. + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 CountdownValue + ); +/*++ + + Routine Description: + This service reads the current Watchdog Timer countdown reload value. + + Arguments: + CountdownValue - Value to set the reload register. + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) ( + ); +/*++ + + Routine Description: + This service clears the state that indicates the Watchdog Timer fired. + + Arguments: + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) ( + IN BOOLEAN Stall + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. It also closes the recurring restart event + if the event exists. + + Arguments: + Stall - TRUE = Stop the timer countdown + FALSE = Start the timer countdown + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL { + EFI_WATCHDOG_START_TIMER StartWatchdogTimer; + PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout; + EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer; + EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer; + EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout; + EFI_WATCHDOG_FORCE_REBOOT ForceReboot; + EFI_WATCHDOG_KNOWN_RESET AllowKnownReset; + EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod; + EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod; + PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState; + EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown; +} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL; + +extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid; +extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h new file mode 100644 index 0000000000..685e563095 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h @@ -0,0 +1,170 @@ +/** @file + I2C bus interface + + This layer provides I/O access to an I2C device. + + Copyright (c) 2012, Intel Corporation + All rights reserved. This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __I2C_BUS_H__ +#define __I2C_BUS_H__ + +#include + +/// +/// I2C bus protocol +/// +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL; + + +/** + Perform an I2C operation on the device + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + N.B. The typical consumers of this API are the third party I2C + drivers. Extreme care must be taken by other consumers of this + API to prevent confusing the third party I2C drivers due to a + state change at the I2C device which the third party I2C drivers + did not initiate. I2C platform drivers may use this API within + these guidelines. + + This routine queues an operation to the I2C controller for execution + on the I2C bus. + + As an upper layer driver writer, the following need to be provided + to the platform vendor: + + 1. ACPI CID value or string - this is used to connect the upper layer + driver to the device. + 2. Slave address array guidance when the I2C device uses more than one + slave address. This is used to access the blocks of hardware within + the I2C device. + + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL + structure + @param[in] SlaveAddressIndex Index into an array of slave addresses for + the I2C device. The values in the array are + specified by the board designer, with the + I2C device driver writer providing the slave + address order. + + For devices that have a single slave address, + this value must be zero. If the I2C device + uses more than one slave address then the third + party (upper level) I2C driver writer needs to + specify the order of entries in the slave address + array. + + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers" + section in I2cMaster.h. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller can not distinguish + when the NACK occurred. + @retval EFI_NOT_FOUND I2C slave address exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_BUS_START_REQUEST) ( + IN CONST EFI_I2C_BUS_PROTOCOL *This, + IN UINTN SlaveAddressIndex, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// The I2C bus protocol enables access to a specific device on the I2C bus. +/// +/// Each I2C device is described as an ACPI node (HID, UID and CID) within the +/// platform layer. The I2C bus protocol enumerates the I2C devices in the +/// platform and creates a unique handle and device path for each I2C device. +/// +/// I2C slave addressing is abstracted to validate addresses and limit operation +/// to the specified I2C device. The third party providing the I2C device support +/// provides an ordered list of slave addresses for the I2C device to the team +/// building the platform layer. The platform team must preserve the order of the +/// supplied list. SlaveAddressCount is the number of entries in this list or +/// array within the platform layer. The third party device support references +/// a slave address using an index into the list or array in the range of zero +/// to SlaveAddressCount - 1. +/// +struct _EFI_I2C_BUS_PROTOCOL { + /// + /// Start an I2C operation on the bus + /// + EFI_I2C_BUS_START_REQUEST StartRequest; + + /// + /// The maximum number of slave addresses for the I2C device. The caller may + /// validate this value as a check on the platform layer's configuration. Slave + /// address selection uses an index value in the range of zero to SlaveAddressCount - 1. + /// + UINTN SlaveAddressCount; + + /// + /// Hardware revision - Matches the ACPI _HRV value + /// + /// The HardwareRevision value allows a single driver to support multiple hardware + /// revisions and implement the necessary workarounds for limitations within the + /// hardware. + /// + UINT32 HardwareRevision; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to send on the I2C bus. + /// + UINT32 MaximumTransmitBytes; + + /// + /// The maximum number of bytes in the I2C bus transaction. + /// + UINT32 MaximumTotalBytes; +}; + +/// +/// GUID for the I2C bus protocol +/// +extern EFI_GUID gEfiI2cBusProtocolGuid; + +#endif // __I2C_BUS_H__ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h new file mode 100644 index 0000000000..574fc3e19c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h @@ -0,0 +1,90 @@ +/*++ + +Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchExtendedReset.h + +Abstract: + + PCH Extended Reset Protocol + +--*/ +#ifndef _EFI_PCH_EXTENDED_RESET_H_ +#define _EFI_PCH_EXTENDED_RESET_H_ + + + +// +#define EFI_PCH_EXTENDED_RESET_PROTOCOL_GUID \ + { \ + 0xf0bbfca0, 0x684e, 0x48b3, 0xba, 0xe2, 0x6c, 0x84, 0xb8, 0x9e, 0x53, 0x39 \ + } +extern EFI_GUID gEfiPchExtendedResetProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_PCH_EXTENDED_RESET_PROTOCOL EFI_PCH_EXTENDED_RESET_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Extended Reset Types +// +typedef struct { + UINT8 PowerCycle : 1; // 0: Disabled*; 1: Enabled + UINT8 GlobalReset : 1; // 0: Disabled*; 1: Enabled + UINT8 SusPwrDnAck : 1; // 0: Do Nothing; + // 1: GPIO[30](SUS_PWR_DN_ACK) level is set low prior to Global Reset(for systems with an embedded controller) + UINT8 RsvdBits : 5; // Reserved fields for future expansion w/o protocol change +} PCH_EXTENDED_RESET_TYPES; + +// +// Member functions +// +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_EXTENDED_RESET) ( + IN EFI_PCH_EXTENDED_RESET_PROTOCOL * This, + IN PCH_EXTENDED_RESET_TYPES PchExtendedResetTypes + ); + +/*++ + +Routine Description: + + Execute Pch Extended Reset from the host controller. + +Arguments: + + This - Pointer to the EFI_PCH_EXTENDED_RESET_PROTOCOL instance. + PchExtendedResetTypes - Pch Extended Reset Types which includes PowerCycle, Globalreset. + +Returns: + + Does not return if the reset takes place. + EFI_INVALID_PARAMETER - If ResetType is invalid. + +--*/ + +// +// Interface structure for the Pch Extended Reset Protocol +// +struct _EFI_PCH_EXTENDED_RESET_PROTOCOL { + EFI_PCH_EXTENDED_RESET Reset; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h new file mode 100644 index 0000000000..2a3e2b26da --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h @@ -0,0 +1,66 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchInfo.h + + @brief + This file defines the PCH Info Protocol. + +**/ +#ifndef _PCH_INFO_H_ +#define _PCH_INFO_H_ + + +#define EFI_PCH_INFO_PROTOCOL_GUID \ + { \ + 0xd31f0400, 0x7d16, 0x4316, 0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b \ + } +extern EFI_GUID gEfiPchInfoProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define PCH_INFO_PROTOCOL_REVISION_1 1 +#define PCH_INFO_PROTOCOL_REVISION_2 2 + +/// +/// RCVersion[7:0] is the release number. +/// For example: +/// VlvFramework 0.6.0-01 should be 00 06 00 01 (0x00060001) +/// VlvFramework 0.6.2 should be 00 06 02 00 (0x00060200) +/// +#define PCH_RC_VERSION 0x01000000 + +/// +/// Protocol definition +/// +struct _EFI_PCH_INFO_PROTOCOL { + UINT8 Revision; + UINT8 BusNumber; + UINT32 RCVersion; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h new file mode 100644 index 0000000000..0205c01b82 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h @@ -0,0 +1,556 @@ +/** +**/ +/** + +Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchPlatformPolicy.h + + @brief + PCH policy protocol produced by a platform driver specifying various + expected PCH settings. This protocol is consumed by the PCH drivers. + +**/ +#ifndef _PCH_PLATFORM_POLICY_H_ +#define _PCH_PLATFORM_POLICY_H_ + + +// +#include "PchRegs.h" +#ifndef ECP_FLAG +#include "Uefi.h" +#endif + +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \ + } +extern EFI_GUID gDxePchPlatformPolicyProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12 + +/// +/// Generic definitions for device enabling/disabling used by PCH code. +/// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +/// +/// ---------------------------- Device Enabling ------------------------------ +/// +/// PCH Device enablings +/// +typedef struct { + UINT8 Lan : 1; /// 0: Disable; 1: Enable + UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto + UINT8 Sata : 1; /// 0: Disable; 1: Enable + UINT8 Smbus : 1; /// 0: Disable; 1: Enable + UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode + UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change +} PCH_DEVICE_ENABLING; + +/// +/// ---------------------------- USB Config ----------------------------- +/// +/// +/// Overcurrent pins +/// +typedef enum { + PchUsbOverCurrentPin0 = 0, + PchUsbOverCurrentPin1, + PchUsbOverCurrentPin2, + PchUsbOverCurrentPin3, + PchUsbOverCurrentPin4, + PchUsbOverCurrentPin5, + PchUsbOverCurrentPin6, + PchUsbOverCurrentPin7, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinMax +} PCH_USB_OVERCURRENT_PIN; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled + UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port. + UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port. + UINT8 Rsvdbits : 5; +} PCH_USB_PORT_SETTINGS; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 7; +} PCH_USB20_CONTROLLER_SETTINGS; + +typedef struct { + UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode + UINT8 Rsvdbits : 6; +} PCH_USBOTG_CONTROLLER_SETTINGS; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 +#define PCH_XHCI_MODE_AUTO 2 +#define PCH_XHCI_MODE_SMARTAUTO 3 + +#define PCH_EHCI_DEBUG_OFF 0 +#define PCH_EHCI_DEBUG_ON 1 + +#define PCH_USB_FRONT_PANEL 1 +#define PCH_USB_BACK_PANEL 0 + +typedef struct { + UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto + UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available + UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 4; +} PCH_USB30_CONTROLLER_SETTINGS; + +typedef struct { + UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control + UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR + UINT8 RsvdBits : 6; + PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS]; + PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax]; + PCH_USB30_CONTROLLER_SETTINGS Usb30Settings; + PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings; + PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS]; + PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS]; + /// + /// The length of Usb Port to configure the USB transmitter, + /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point. + /// + UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS]; + UINT16 EhciDebug; + UINT16 UsbXhciLpmSupport; + +} PCH_USB_CONFIG; + +/// +/// ---------------------------- PCI Express Config ---------------------- +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCI_EXPRESS_ASPM_CONTROL; + +/// +/// Refer to PCH EDS for the PCH implementation values corresponding +/// to below PCI-E spec defined ranges +/// +typedef enum { + PchPciECompletionTO_Default, + PchPciECompletionTO_50_100us, + PchPciECompletionTO_1_10ms, + PchPciECompletionTO_16_55ms, + PchPciECompletionTO_65_210ms, + PchPciECompletionTO_260_900ms, + PchPciECompletionTO_1_3P5s, + PchPciECompletionTO_4_13s, + PchPciECompletionTO_17_64s, + PchPciECompletionTO_Disabled +} PCH_PCIE_COMPLETION_TIMEOUT; + +typedef struct { + UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable. + UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port + UINT8 SlotImplemented : 1; + UINT8 HotPlug : 1; + UINT8 PmSci : 1; + UINT8 ExtSync : 1; /// Extended Synch + UINT8 Rsvdbits : 2; + /// + /// Error handlings + /// + UINT8 UnsupportedRequestReport : 1; + UINT8 FatalErrorReport : 1; + UINT8 NoFatalErrorReport : 1; + UINT8 CorrectableErrorReport : 1; + UINT8 PmeInterrupt : 1; + UINT8 SystemErrorOnFatalError : 1; + UINT8 SystemErrorOnNonFatalError : 1; + UINT8 SystemErrorOnCorrectableError : 1; + + UINT8 AdvancedErrorReporting : 1; + UINT8 TransmitterHalfSwing : 1; + UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change + + UINT8 FunctionNumber; /// The function number this root port is mapped to. + UINT8 PhysicalSlotNumber; + PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout; + PCH_PCI_EXPRESS_ASPM_CONTROL Aspm; +} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG; + +typedef struct { + /** + VendorId + + The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + + DeviceId + + The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + + RevId + + The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + + BaseClassCode + + The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + + SubClassCode + + The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + + + EndPointAspm + + The override ASPM setting from End point + **/ + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevId; + UINT8 BaseClassCode; + UINT8 SubClassCode; + PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm; +} PCH_PCIE_DEVICE_ASPM_OVERRIDE; + +typedef struct { + UINT16 VendorId; ///< PCI configuration space offset 0 + UINT16 DeviceId; ///< PCI configuration space offset 2 + UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + **/ + UINT16 NonSnoopLatency; +} PCH_PCIE_DEVICE_LTR_OVERRIDE; + +typedef struct { + /// + /// Temp Bus Number range available to be assigned to + /// each root port and its downstream devices for initialization + /// of these devices before PCI Bus enumeration + /// + UINT8 TempRootPortBusNumMin; + UINT8 TempRootPortBusNumMax; + PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS]; + BOOLEAN RootPortClockGating; + UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override + PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override + UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318. +} PCH_PCI_EXPRESS_CONFIG; + + +/// +/// ---------------------------- SATA Config ----------------------------- +/// +typedef enum { + PchSataSpeedSupportGen1 = 1, + PchSataSpeedSupportGen2 +} PCH_SATA_SPEED_SUPPORT; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable + UINT8 HotPlug : 1; /// 0: Disable; 1: Enable + UINT8 MechSw : 1; /// 0: Disable; 1: Enable + UINT8 External : 1; /// 0: Disable; 1: Enable + UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change +} PCH_SATA_PORT_SETTINGS; + +typedef struct { + PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS]; + UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable + UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0 + UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1 + UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10 + UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5 + UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology + UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER + UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled + + UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports + UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management + UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode + UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support + /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2) + + UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change +} PCH_SATA_CONFIG; +/// +/// --------------------------- AZALIA Config ------------------------------ +/// +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; /// 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} PCH_AZALIA_VERB_TABLE; + +typedef struct { + UINT8 Pme : 1; /// 0: Disable; 1: Enable + UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached + UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable + UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 3; + UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform + PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds +} PCH_AZALIA_CONFIG; + +/// +/// --------------------------- Smbus Config ------------------------------ +/// +typedef struct { + UINT8 NumRsvdSmbusAddresses; + UINT8 *RsvdSmbusAddressTable; +} PCH_SMBUS_CONFIG; + +/// +/// --------------------------- Miscellaneous PM Config ------------------------------ +/// +typedef struct { + UINT8 MeWakeSts : 1; + UINT8 MeHrstColdSts : 1; + UINT8 MeHrstWarmSts : 1; + UINT8 MeHostPowerDn : 1; + UINT8 WolOvrWkSts : 1; + UINT8 Rsvdbits : 3; +} PCH_POWER_RESET_STATUS; + +typedef struct { + UINT8 PmeB0S5Dis : 1; + UINT8 WolEnableOverride : 1; + UINT8 Rsvdbits : 6; +} PCH_WAKE_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef struct { + /// + /// Specify which Power/Reset bits need to be cleared by + /// the PCH Init Driver. + /// Usually platform drivers take care of these bits, but if + /// not, let PCH Init driver clear the bits. + /// + PCH_POWER_RESET_STATUS PowerResetStatusClear; + /// + /// Specify Wake Policy + /// + PCH_WAKE_CONFIG WakeConfig; + /// + /// SLP_XX Minimum Assertion Width Policy + /// + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; + UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up + UINT8 SlpLanLowDc : 1; + UINT8 Rsvdbits : 6; +} PCH_MISC_PM_CONFIG; + +/// +/// --------------------------- Subsystem Vendor ID / Subsystem ID Config ----- +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} PCH_DEFAULT_SVID_SID; + +/// +/// --------------------------- Lock Down Config ------------------------------ +/// +typedef struct { + UINT8 GlobalSmi : 1; + UINT8 BiosInterface : 1; + UINT8 RtcLock : 1; + UINT8 BiosLock : 1; + UINT8 Rsvdbits : 4; + UINT8 PchBiosLockSwSmiNumber; +} PCH_LOCK_DOWN_CONFIG; +// +// --------------------------- Serial IRQ Config ------------------------------ +// +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// + +typedef struct { + BOOLEAN SirqEnable; /// Determines if enable Serial IRQ + PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select +} PCH_LPC_SIRQ_CONFIG; + +/// +/// --------------------------- Power Optimizer Config ------------------------------ +/// +typedef struct { + UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table + PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table +} PCH_PWR_OPT_CONFIG; + +/// +/// --------------------- Low Power Input Output Config ------------------------ +/// +typedef struct { + UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled + UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled + UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled + UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled + UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled + UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled + UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled + UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled + UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled + UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled + UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled + UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled + UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled + UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled + UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled + UINT8 Rsvdbits : 2; +} PCH_LPSS_CONFIG; + +/// +/// ----------------------------- SCC Config -------------------------------- +/// +typedef struct { + UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled + UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled + UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled + UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled + UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled + UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5 + UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5 + UINT8 Rsvdbits : 1; + UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card + UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card + UINT8 Rsvdbits1 : 6; + UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value. +} PCH_SCC_CONFIG; + +/// +/// ------------ General PCH Platform Policy protocol definition ------------ +/// +struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + UINT8 BusNumber; /// PCI Bus Number of the PCH device + PCH_DEVICE_ENABLING *DeviceEnabling; + PCH_USB_CONFIG *UsbConfig; + PCH_PCI_EXPRESS_CONFIG *PciExpressConfig; + + PCH_SATA_CONFIG *SataConfig; + PCH_AZALIA_CONFIG *AzaliaConfig; + PCH_SMBUS_CONFIG *SmbusConfig; + PCH_MISC_PM_CONFIG *MiscPmConfig; + PCH_DEFAULT_SVID_SID *DefaultSvidSid; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + PCH_PWR_OPT_CONFIG *PwrOptConfig; + PCH_LPSS_CONFIG *LpssConfig; + PCH_SCC_CONFIG *SccConfig; + UINT8 IdleReserve; + UINT8 EhciPllCfgEnable; + UINT8 AcpiHWRed; //Hardware Reduced Mode +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..45e2860fce --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h @@ -0,0 +1,120 @@ +/** +**/ +/** + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchReset.h + + @brief + PCH Reset Protocol + +**/ +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + + +// +#define PCH_RESET_PROTOCOL_GUID \ + { \ + 0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \ + } +#define PCH_RESET_CALLBACK_PROTOCOL_GUID \ + { \ + 0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \ + } +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// PCH Reset Types +/// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc +} PCH_RESET_TYPE; + +/// +/// Member functions +/// +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL * This, + IN PCH_RESET_TYPE PchResetType + ) +/** + + @brief + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ) +/** + + @brief + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH + +**/ +; + +/// +/// Interface structure for the Pch Reset Protocol +/// +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; +}; + +/// +/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition +/// +struct _PCH_RESET_CALLBACK_PROTOCOL { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h new file mode 100644 index 0000000000..ca263c66e7 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h @@ -0,0 +1,138 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchS3Support.h + + @brief + This file defines the PCH S3 support Protocol. + +**/ +#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_ +#define _PCH_S3_SUPPORT_PROTOCOL_H_ + +#ifndef ECP_FLAG +#include +#endif + +#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \ + { \ + 0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \ + } + +#include + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gEfiPchS3SupportProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL; + +typedef enum { + PchS3ItemTypeSendCodecCommand, + PchS3ItemTypePollStatus, + PchS3ItemTypeInitPcieRootPortDownstream, + PchS3ItemTypePcieSetPm, + PchS3ItemTypePmTimerStall, + PchS3ItemTypeMax +} EFI_PCH_S3_DISPATCH_ITEM_TYPE; + +/// +/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI +/// plug 4 to ParameterSize in PEIM if you really need it +/// +typedef struct { + UINT32 HdaBar; + UINT32 CodecCmdData; +} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND; + +typedef struct { + UINT64 MmioAddress; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT64 Mask; + UINT64 Value; + UINT32 Timeout; // us +} EFI_PCH_S3_PARAMETER_POLL_STATUS; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; +} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm; + UINT8 NumOfDevAspmOverride; + UINT32 DevAspmOverrideAddr; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; + UINT8 NumOfDevLtrOverride; + UINT32 DevLtrOverrideAddr; +} EFI_PCH_S3_PARAMETER_PCIE_SET_PM; + +typedef struct { + UINT32 DelayTime; // us +} EFI_PCH_S3_PARAMETER_PM_TIMER_STALL; + +typedef struct { + EFI_PCH_S3_DISPATCH_ITEM_TYPE Type; + VOID *Parameter; +} EFI_PCH_S3_DISPATCH_ITEM; + +/// +/// Member functions +/// +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL * This, + IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem, + OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint + ); + +/** + + @brief + Set an item to be dispatched at S3 resume time. At the same time, the entry point + of the PCH S3 support image is returned to be used in subsequent boot script save + call + + @param[in] This Pointer to the protocol instance. + @param[in] DispatchItem The item to be dispatched. + @param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. + +**/ + +/// +/// Protocol definition +/// +struct _EFI_PCH_S3_SUPPORT_PROTOCOL { + EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h new file mode 100644 index 0000000000..6f6dd342cd --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h @@ -0,0 +1,415 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ +Module Name: + + SdHostIo.h + +Abstract: + + Interface definition for EFI_SD_HOST_IO_PROTOCOL + +--*/ + +#ifndef _SD_HOST_IO_H +#define _SD_HOST_IO_H + + +// Global ID for the EFI_SD_HOST_IO_PROTOCOL +// {B63F8EC7-A9C9-4472-A4C0-4D8BF365CC51} +// +#define EFI_SD_HOST_IO_PROTOCOL_GUID \ + { 0xb63f8ec7, 0xa9c9, 0x4472, { 0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51 } } + +typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL; + +// +// TODO: Move to Pci22.h +// +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_IF_STANDARD_HOST_NO_DMA 0x00 +#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01 + +// +// TODO: Retire +// +#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01 + +// +// TODO: Do these belong in an Industry Standard include file? +// +// MMIO Registers definition for MMC/SDIO controller +// +#define MMIO_DMAADR 0x00 +#define MMIO_BLKSZ 0x04 +#define MMIO_BLKCNT 0x06 +#define MMIO_CMDARG 0x08 +#define MMIO_XFRMODE 0x0C +#define MMIO_SDCMD 0x0E +#define MMIO_RESP 0x10 +#define MMIO_BUFDATA 0x20 +#define MMIO_PSTATE 0x24 +#define MMIO_HOSTCTL 0x28 +#define MMIO_PWRCTL 0x29 +#define MMIO_BLKGAPCTL 0x2A +#define MMIO_WAKECTL 0x2B +#define MMIO_CLKCTL 0x2C +#define MMIO_TOCTL 0x2E +#define MMIO_SWRST 0x2F +#define MMIO_NINTSTS 0x30 +#define MMIO_ERINTSTS 0x32 +#define MMIO_NINTEN 0x34 +#define MMIO_ERINTEN 0x36 +#define MMIO_NINTSIGEN 0x38 +#define MMIO_ERINTSIGEN 0x3A +#define MMIO_AC12ERRSTS 0x3C +#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2 +#define MMIO_CAP 0x40 +#define MMIO_CAP2 0x44 //hphang <- New in VLV2 +#define MMIO_MCCAP 0x48 +#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2 +#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2 +#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2 +#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2 +#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2 +#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2 +#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2 +#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2 +#define MMIO_SLTINTSTS 0xFC +#define MMIO_CTRLRVER 0xFE + +typedef enum { + ResponseNo = 0, + ResponseR1, + ResponseR1b, + ResponseR2, + ResponseR3, + ResponseR4, + ResponseR5, + ResponseR5b, + ResponseR6, + ResponseR7 +} RESPONSE_TYPE; + +typedef enum { + NoData = 0, + InData, + OutData +} TRANSFER_TYPE; + +typedef enum { + Reset_Auto = 0, + Reset_DAT, + Reset_CMD, + Reset_DAT_CMD, + Reset_All, + Reset_HW +} RESET_TYPE; + + +typedef enum { + SDMA = 0, + ADMA2, + PIO +} DMA_MOD; + +typedef struct { + UINT32 HighSpeedSupport: 1; //High speed supported + UINT32 V18Support: 1; //1.8V supported + UINT32 V30Support: 1; //3.0V supported + UINT32 V33Support: 1; //3.3V supported + UINT32 SDR50Support: 1; + UINT32 SDR104Support: 1; + UINT32 DDR50Support: 1; + UINT32 Reserved0: 1; + UINT32 BusWidth4: 1; // 4 bit width + UINT32 BusWidth8: 1; // 8 bit width + UINT32 Reserved1: 6; + UINT32 SDMASupport: 1; + UINT32 ADMA2Support: 1; + UINT32 DmaMode: 2; + UINT32 ReTuneTimer: 4; + UINT32 ReTuneMode: 2; + UINT32 Reserved2: 6; + UINT32 BoundarySize; +} HOST_CAPABILITY; + +/*++ + + Routine Description: + The main function used to send the command to the card inserted into the SD host + slot. + It will assemble the arguments to set the command register and wait for the command + and transfer completed until timeout. Then it will read the response register to fill + the ResponseData + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + CommandIndex - The command index to set the command index field of command register + Argument - Command argument to set the argument field of command register + DataType - TRANSFER_TYPE, indicates no data, data in or data out + Buffer - Contains the data read from / write to the device + BufferSize - The size of the buffer + ResponseType - RESPONSE_TYPE + TimeOut - Time out value in 1 ms unit + ResponseData - Depending on the ResponseType, such as CSD or card status + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + EFI_OUT_OF_RESOURCES + EFI_TIMEOUT + EFI_DEVICE_ERROR + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData OPTIONAL + ); + +/*++ + + Routine Description: + Set max clock frequency of the host, the actual frequency + may not be the same as MaxFrequency. It depends on + the max frequency the host can support, divider, and host + speed mode. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + MaxFrequency - Max frequency in HZ + + Returns: + EFI_SUCCESS + EFI_TIMEOUT +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 MaxFrequency + ); + +/*++ + + Routine Description: + Set bus width of the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BusWidth - Bus width in 1, 4, 8 bits + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BusWidth + ); + +/*++ + + Routine Description: + Set voltage which could supported by the host. + Support 0(Power off the host), 1.8V, 3.0V, 3.3V + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Voltage - Units in 0.1 V + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 Voltage + ); + +/*++ + + Routine Description: + Set Host High Speed + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + HighSpeed - True for High Speed Mode set, false for normal mode + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 HighSpeed + ); + +/*++ + + Routine Description: + Set High Speed Mode + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + SetHostDdrMode - True for DDR Mode set, false for normal mode + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 DdrMode + ); + + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + ResetAll - TRUE to reset all + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN RESET_TYPE ResetType + ); + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Enable - TRUE to enable, FALSE to disable + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + +/*++ + + Routine Description: + Find whether these is a card inserted into the slot. If so + init the host. If not, return EFI_NOT_FOUND. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + + Returns: + EFI_SUCCESS + EFI_NOT_FOUND + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This + ); + +/*++ + + Routine Description: + Set the Block length + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BlockLength - card supportes block length + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BlockLength + ); + +typedef EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)( + IN EFI_SD_HOST_IO_PROTOCOL *This + ); + + + +// +// Interface structure for the EFI SD Host I/O Protocol +// +struct _EFI_SD_HOST_IO_PROTOCOL { + UINT32 Revision; + HOST_CAPABILITY HostCapability; + EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand; + EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency; + EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode; + EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost; + EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd; + EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost; + EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength; + EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode; +}; + +extern EFI_GUID gEfiSdHostIoProtocolGuid; + +#endif + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h new file mode 100644 index 0000000000..7ba9ea3d25 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h @@ -0,0 +1,53 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmbiosSlotPopulation.h + +Abstract: + + EFI SMBIOS slot structure control code. + +GUID: + {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0} + 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 + +Revision History + +--*/ + +#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_ +#define _EFI_SMBIOS_SLOT_POPULATION_H_ + +// +// Slot Population Protocol GUID +// +#define EFI_SMBIOS_SLOT_POPULATION_GUID \ + { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } + +typedef struct { + UINT16 SmbiosSlotId; // SMBIOS Slot ID + BOOLEAN InUse; // Does the slot have a card in it + BOOLEAN Disabled; // Should the slot information be in SMBIOS +} EFI_SMBIOS_SLOT_ENTRY; + +typedef struct { + UINT32 NumberOfEntries; + EFI_SMBIOS_SLOT_ENTRY *SlotEntries; +} EFI_SMBIOS_SLOT_POPULATION_INFO; + +extern EFI_GUID gEfiSmbiosSlotPopulationGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h new file mode 100644 index 0000000000..840015653c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h @@ -0,0 +1,165 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + SmmIchnDispatchEx.h + + @brief + SmmIchnDispatch Extended Protocol + +**/ +#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_ +#define _EFI_SMM_ICHN_DISPATCH_EX_H_ + +#ifdef ECP_FLAG +#include +#else +#include +#endif + +#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \ + { \ + 0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \ + } +extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// Ichn Dispatch Extended Types +/// +typedef enum { + IchnExPciExpress = NUM_ICHN_TYPES + 1, + IchnExMonitor, + IchnExSpi, + IchnExQRT, + IchnExGpioUnlock, + IchnExTmrOverflow, + IchnExPcie0Hotplug, + IchnExPcie1Hotplug, + IchnExPcie2Hotplug, + IchnExPcie3Hotplug, + IchnExPcie0LinkActive, + IchnExPcie1LinkActive, + IchnExPcie2LinkActive, + IchnExPcie3LinkActive, + /// + /// INSERT NEW ITEMS JUST BEFORE THIS LINE + /// + IchnExTypeMAX /// the maximum number of items in this enumeration +} EFI_SMM_ICHN_EX_SMI_TYPE; + +typedef struct { + EFI_SMM_ICHN_EX_SMI_TYPE Type; +} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT; + +/// +/// Member functions +/// +typedef +VOID +(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext + ); + +/** + + @brief + Dispatch function for a ICH n Extended specific SMI handler. + + @param[in] DispatchHandle Handle of this dispatch function. + @param[in] DispatchContext Pointer to the dispatch function's context. + The DispatchContext fields are filled in + by the dispatching driver prior to + invoking this dispatch function. + + @retval None + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext, + OUT EFI_HANDLE * DispatchHandle + ); + +/** + + @brief + Register a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] DispatchContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the ICHN SMI source for which the dispatch + function should be invoked. + @param[in] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this + child. + @retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value + is not within valid range. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + + @brief + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval Others TBD + +**/ + +/// +/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol +/// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL { + EFI_SMM_ICHN_EX_REGISTER Register; + EFI_SMM_ICHN_EX_UNREGISTER UnRegister; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h new file mode 100644 index 0000000000..3ee6a3a7a5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h @@ -0,0 +1,45 @@ +/*++ + +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmmSmbus.h + +Abstract: + + SmmSmbus Protocol + +--*/ +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +// +// GUID for the SmmSmbus Protocol +// +// EDK and EDKII have different GUID formats +// + +#define EFI_SMM_SMBUS_PROTOCOL_GUID \ + { \ + 0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \ + } + +// +// Resuse the DXE definition, and use another GUID. +// +typedef EFI_SMBUS_HC_PROTOCOL SMM_SMBUS_HC_PROTOCOL; + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h new file mode 100644 index 0000000000..f73ef65870 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h @@ -0,0 +1,266 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + Spi.h + + @brief + This file defines the EFI SPI Protocol which implements the + Intel(R) ICH SPI Host Controller Compatibility Interface. + +**/ +#ifndef _EFI_SPI_H_ +#define _EFI_SPI_H_ + + +// +#define EFI_SPI_PROTOCOL_GUID \ + { \ + 0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \ + } +#define EFI_SMM_SPI_PROTOCOL_GUID \ + { \ + 0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \ + } +extern EFI_GUID gEfiSpiProtocolGuid; +extern EFI_GUID gEfiSmmSpiProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL; + +/// +/// SPI protocol data structures and definitions +/// +/// +/// Number of Prefix Opcodes allowed on the SPI interface +/// +#define SPI_NUM_PREFIX_OPCODE 2 + +/// +/// Number of Opcodes in the Opcode Menu +/// +#define SPI_NUM_OPCODE 8 + +/// +/// Opcode Type +/// EnumSpiOpcodeCommand: Command without address +/// EnumSpiOpcodeRead: Read with address +/// EnumSpiOpcodeWrite: Write with address +/// +typedef enum { + EnumSpiOpcodeReadNoAddr, + EnumSpiOpcodeWriteNoAddr, + EnumSpiOpcodeRead, + EnumSpiOpcodeWrite, + EnumSpiOpcodeMax +} SPI_OPCODE_TYPE; + +typedef enum { + EnumSpiCycle20MHz, + EnumSpiCycle33MHz, + EnumSpiCycle66MHz, /// Not supported by VLV + EnumSpiCycle50MHz, + EnumSpiCycleMax +} SPI_CYCLE_FREQUENCY; + +typedef enum { + EnumSpiRegionAll, + EnumSpiRegionBios, + EnumSpiRegionSeC, + EnumSpiRegionDescriptor, + EnumSpiRegionPlatformData, + EnumSpiRegionMax +} SPI_REGION_TYPE; + +/// +/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware +/// Sequencing Commands and Opcode Requirements" +/// +typedef enum { + EnumSpiOperationWriteStatus, + EnumSpiOperationProgramData_1_Byte, + EnumSpiOperationProgramData_64_Byte, + EnumSpiOperationReadData, + EnumSpiOperationWriteDisable, + EnumSpiOperationReadStatus, + EnumSpiOperationWriteEnable, + EnumSpiOperationFastRead, + EnumSpiOperationEnableWriteStatus, + EnumSpiOperationErase_256_Byte, + EnumSpiOperationErase_4K_Byte, + EnumSpiOperationErase_8K_Byte, + EnumSpiOperationErase_64K_Byte, + EnumSpiOperationFullChipErase, + EnumSpiOperationJedecId, + EnumSpiOperationDualOutputFastRead, + EnumSpiOperationDiscoveryParameters, + EnumSpiOperationOther, + EnumSpiOperationMax +} SPI_OPERATION; + +/// +/// SPI Command Configuration +/// Frequency The expected frequency to be used (value to be programmed to the SSFC +/// Register) +/// Operation Which Hardware Sequencing required operation this opcode respoinds to. +/// The required operations are listed in EDS Table 5-55: "Hardware +/// Sequencing Commands and Opcode Requirements" +/// If the opcode does not corresponds to any operation listed, use +/// EnumSpiOperationOther, and provides TYPE and Code for it in +/// SpecialOpcodeEntry. +/// +typedef struct _SPI_OPCODE_MENU_ENTRY { + SPI_OPCODE_TYPE Type; + UINT8 Code; + SPI_CYCLE_FREQUENCY Frequency; + SPI_OPERATION Operation; +} SPI_OPCODE_MENU_ENTRY; + +// +// Initialization data table loaded to the SPI host controller +// VendorId Vendor ID of the SPI device +// DeviceId0 Device ID0 of the SPI device +// DeviceId1 Device ID1 of the SPI device +// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller +// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu +// BiosStartOffset The offset of the start of the BIOS image relative to the flash device. +// Please note this is a Flash Linear Address, NOT a memory space address. +// This value is platform specific and depends on the system flash map. +// This value is only used on non Descriptor mode. +// BiosSize The the BIOS Image size in flash. This value is platform specific +// and depends on the system flash map. Please note BIOS Image size may +// be smaller than BIOS Region size (in Descriptor Mode) or the flash size +// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be +// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash +// (in Non Descriptor Mode) +// +typedef struct _SPI_INIT_TABLE { + UINT8 VendorId; + UINT8 DeviceId0; + UINT8 DeviceId1; + UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE]; + SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE]; + UINTN BiosStartOffset; + UINTN BiosSize; +} SPI_INIT_TABLE; + +// +// Protocol member functions +// +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_INIT) ( + IN EFI_SPI_PROTOCOL * This, + IN SPI_INIT_TABLE * InitTable + ); + +/** + + @brief + Initializes the host controller to execute SPI commands. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] InitData Pointer to caller-allocated buffer containing the SPI + interface initialization table. + + @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed. + @retval EFI_ACCESS_DENIED The SPI configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + +**/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_LOCK) ( + IN EFI_SPI_PROTOCOL * This + ); +/** + + @brief + Initializes the host controller to execute SPI commands. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] InitData Pointer to caller-allocated buffer containing the SPI + interface initialization table. + + @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed. + @retval EFI_ACCESS_DENIED The SPI configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + +**/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_EXECUTE) ( + IN EFI_SPI_PROTOCOL * This, + IN UINT8 OpcodeIndex, + IN UINT8 PrefixOpcodeIndex, + IN BOOLEAN DataCycle, + IN BOOLEAN Atomic, + IN BOOLEAN ShiftOut, + IN UINTN Address, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer, + IN SPI_REGION_TYPE SpiRegionType + ); +/** + + @brief + Execute SPI commands from the host controller. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] OpcodeIndex Index of the command in the OpCode Menu. + @param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence. + @param[in] DataCycle TRUE if the SPI cycle contains data + @param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed. + @param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in. + @param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform + Region, this value specifies the offset from the Region Base; for BIOS Region, + this value specifies the offset from the start of the BIOS Image. In Non + Descriptor Mode, this value specifies the offset from the start of the BIOS Image. + Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor + Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is + supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or + the flash (in Non Descriptor Mode) + @param[in] DataByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle. + @param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe, + EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in + Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode + and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative + to base of the 1st flash device (i.e., it is a Flash Linear Address). + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @exception EFI_UNSUPPORTED Command not supported. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. + +**/ + +/// +/// Protocol definition +/// +struct _EFI_SPI_PROTOCOL { + EFI_SPI_INIT Init; + EFI_SPI_LOCK Lock; + EFI_SPI_EXECUTE Execute; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h new file mode 100644 index 0000000000..4cb7dba1d4 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h @@ -0,0 +1,94 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + TcoReset.h + +Abstract: + + Protocol to communicate with ICH TCO. + +GUID Info: + {A6A79162-E325-4c30-BCC3-59373064EFB3} + 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3); + + +--*/ + +#ifndef _TCO_RESET_H_ +#define _TCO_RESET_H_ + + +#define EFI_TCO_RESET_PROTOCOL_GUID \ + {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3} + +typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) ( + IN UINT32 *RcrbGcsSaveValue + ) +/*++ + +Routine Description: + + Enables the TCO timer to reset the system in case of a system hang. This is + used when writing the clock registers. + +Arguments: + + RcrbGcsSaveValue - This is the value of the RCRB GCS register before it is + changed by this procedure. This will be used to restore + the settings of this register in PpiDisableTcoReset. + +Returns: + + EFI_STATUS + +--*/ +; + +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) ( + OUT UINT32 RcrbGcsRestoreValue + ) +/*++ + +Routine Description: + + Disables the TCO timer. This is used after writing the clock registers. + +Arguments: + + RcrbGcsRestoreValue - Value saved in PpiEnableTcoReset so that it can + restored. + +Returns: + + EFI_STATUS + +--*/ +; + +typedef struct _EFI_TCO_RESET_PROTOCOL { + EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset; + EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset; +} EFI_TCO_RESET_PROTOCOL; + +extern EFI_GUID gEfiTcoResetProtocolGuid; + +#endif -- cgit v1.2.3