From 3cbfba02fef9dae07a041fdbf2e89611d72d6f90 Mon Sep 17 00:00:00 2001 From: David Wei Date: Mon, 12 Jan 2015 09:37:20 +0000 Subject: Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei Reviewed-by: Mike Wu Reviewed-by: Hot Tian git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524 --- .../Include/AlertStandardFormatTable.h | 127 ++ Vlv2TbltDevicePkg/Include/ChipsetAccess.h | 33 + Vlv2TbltDevicePkg/Include/CommonIncludes.h | 120 ++ Vlv2TbltDevicePkg/Include/CpuType.h | 64 + Vlv2TbltDevicePkg/Include/FileHandleLib.h | 504 ++++++++ Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h | 35 + .../Include/Guid/AlertStandardFormat.h | 91 ++ Vlv2TbltDevicePkg/Include/Guid/BiosId.h | 35 + Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h | 219 ++++ Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h | 161 +++ Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h | 66 + .../Include/Guid/HwWatchdogTimerHob.h | 139 ++ Vlv2TbltDevicePkg/Include/Guid/IdccData.h | 109 ++ Vlv2TbltDevicePkg/Include/Guid/ItkData.h | 75 ++ Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h | 37 + Vlv2TbltDevicePkg/Include/Guid/OsSelection.h | 90 ++ Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h | 44 + Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h | 185 +++ Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h | 437 +++++++ .../Include/Guid/SensorInfoVariable.h | 284 ++++ Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h | 1351 ++++++++++++++++++++ Vlv2TbltDevicePkg/Include/Hpet.h | 45 + Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h | 109 ++ Vlv2TbltDevicePkg/Include/Library/CpuIA32.h | 350 +++++ Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h | 201 +++ Vlv2TbltDevicePkg/Include/Library/Esrt.h | 79 ++ Vlv2TbltDevicePkg/Include/Library/Fd.h | 269 ++++ Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h | 127 ++ .../Include/Library/I2cMmioConfigLib.h | 28 + .../Include/Library/I2cPort_platform.h | 31 + Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h | 55 + Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h | 28 + Vlv2TbltDevicePkg/Include/Library/SpiFlash.H | 244 ++++ Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h | 45 + .../Include/Library/UsbDeviceModeLib.h | 186 +++ Vlv2TbltDevicePkg/Include/Mcfg.h | 74 ++ Vlv2TbltDevicePkg/Include/McfgTable.h | 70 + Vlv2TbltDevicePkg/Include/Platform.h | 138 ++ Vlv2TbltDevicePkg/Include/PlatformBootMode.h | 40 + Vlv2TbltDevicePkg/Include/PlatformDefinitions.h | 48 + Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h | 47 + Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h | 136 ++ Vlv2TbltDevicePkg/Include/Ppi/Speaker.h | 70 + Vlv2TbltDevicePkg/Include/Ppi/UsbController.h | 90 ++ .../Include/Protocol/CK505ClockPlatformInfo.h | 131 ++ .../Include/Protocol/EnhancedSpeedstep.h | 81 ++ Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h | 484 +++++++ .../Include/Protocol/HwWatchdogTimer.h | 240 ++++ Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h | 112 ++ Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h | 169 +++ Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h | 168 +++ Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h | 143 +++ Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h | 524 ++++++++ Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h | 199 +++ .../Include/Protocol/LpcWpc83627Policy.h | 97 ++ .../Include/Protocol/LpcWpce791Policy.h | 60 + Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h | 89 ++ Vlv2TbltDevicePkg/Include/Protocol/Observable.h | 191 +++ .../Include/Protocol/PlatformGopPolicy.h | 73 ++ .../Include/Protocol/PlatformIdeInit.h | 48 + Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h | 84 ++ .../Include/Protocol/SmbiosSlotPopulation.h | 52 + Vlv2TbltDevicePkg/Include/Protocol/Speaker.h | 70 + Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h | 72 ++ Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h | 141 ++ Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h | 131 ++ .../Include/Protocol/VlvPlatformPolicy.h | 108 ++ Vlv2TbltDevicePkg/Include/SetupMode.h | 90 ++ 68 files changed, 10273 insertions(+) create mode 100644 Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h create mode 100644 Vlv2TbltDevicePkg/Include/ChipsetAccess.h create mode 100644 Vlv2TbltDevicePkg/Include/CommonIncludes.h create mode 100644 Vlv2TbltDevicePkg/Include/CpuType.h create mode 100644 Vlv2TbltDevicePkg/Include/FileHandleLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/BiosId.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/IdccData.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/ItkData.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/OsSelection.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h create mode 100644 Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h create mode 100644 Vlv2TbltDevicePkg/Include/Hpet.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/CpuIA32.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/Esrt.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/Fd.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/SpiFlash.H create mode 100644 Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h create mode 100644 Vlv2TbltDevicePkg/Include/Mcfg.h create mode 100644 Vlv2TbltDevicePkg/Include/McfgTable.h create mode 100644 Vlv2TbltDevicePkg/Include/Platform.h create mode 100644 Vlv2TbltDevicePkg/Include/PlatformBootMode.h create mode 100644 Vlv2TbltDevicePkg/Include/PlatformDefinitions.h create mode 100644 Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h create mode 100644 Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h create mode 100644 Vlv2TbltDevicePkg/Include/Ppi/Speaker.h create mode 100644 Vlv2TbltDevicePkg/Include/Ppi/UsbController.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/Observable.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/Speaker.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h create mode 100644 Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h create mode 100644 Vlv2TbltDevicePkg/Include/SetupMode.h (limited to 'Vlv2TbltDevicePkg/Include') diff --git a/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h b/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h new file mode 100644 index 0000000000..c70b395956 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h @@ -0,0 +1,127 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + AlertStandardFormatTable.h + +Abstract: + + ACPI Alert Standard Format Description Table ASF! as described + in the ASF2.0 Specification + +--*/ + +#ifndef _ALERT_STANDARD_FORMAT_TABLE_H +#define _ALERT_STANDARD_FORMAT_TABLE_H + +#include + +// +// Ensure proper structure formats. +// +#pragma pack (1) + +// +// Information Record header that appears at the beginning of each record. +// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 RecordLength; +} EFI_ACPI_ASF_RECORD_HEADER; + +// +// This structure contains information that identifies the system type +// and configuration. +// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 MinWatchDogResetValue; + UINT8 MinPollingInterval; + UINT16 SystemID; + UINT32 IANAManufactureID; + UINT8 FeatureFlags; + UINT8 Reserved[3]; +} EFI_ACPI_ASF_INFO; + +// +// Alert sensors definition. +// +#define ASF_ALRT_SENSOR_ARRAY_LENGTH 36 + +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 AssertionEventBitMask; + UINT8 DeassertionEventBitMask; + UINT8 NumberOfAlerts; + UINT8 ArrayElementLength; + UINT8 DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH]; +} EFI_ACPI_ASF_ALRT; + +// +// Alert Remote Control System Actions. +// +#define ASF_RCTL_DEVICES_ARRAY_LENGTH 16 + +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 NumberOfControls; + UINT8 ArrayElementLength; + UINT16 RctlReserved; + UINT8 ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH]; +} EFI_ACPI_ASF_RCTL; + +// +// Remote Control Capabilities. +// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 RemoteControlCapabilities[7]; + UINT8 RMCPCompletionCode; + UINT32 RMCPIANA; + UINT8 RMCPSpecialCommand; + UINT8 RMCPSpecialCommandParameter[2]; + UINT8 RMCPBootOptions[2]; + UINT8 RMCPOEMParameters[2]; +} EFI_ACPI_ASF_RMCP; + +// +// SMBus Devices with fixed addresses. +// +#define ASF_ADDR_DEVICE_ARRAY_LENGTH 16 + +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 SEEPROMAddress; + UINT8 NumberOfDevices; + UINT8 FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH]; +} EFI_ACPI_ASF_ADDR; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_ASF_INFO AsfInfo; + EFI_ACPI_ASF_ALRT AsfAlert; + EFI_ACPI_ASF_RCTL AsfRctl; + EFI_ACPI_ASF_RMCP AsfRmcp; + EFI_ACPI_ASF_ADDR AsfAddr; +} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE; + +// +// "ASF!" ASF Description Table Signature. +// +#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE 0x21465341 + +#pragma pack () + +#endif // _ALERT_STANDARD_FORMAT_TABLE_H diff --git a/Vlv2TbltDevicePkg/Include/ChipsetAccess.h b/Vlv2TbltDevicePkg/Include/ChipsetAccess.h new file mode 100644 index 0000000000..baf9b2905a --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/ChipsetAccess.h @@ -0,0 +1,33 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + ChipsetAccess.h + +Abstract: + + Common Include file for Platform Drivers to access the Chipset registers. + +--*/ + +#ifndef _CHIPSET_ACCESS_H_ +#define _CHIPSET_ACCESS_H_ + +#include "PchAccess.h" +#include "Valleyview.h" +#include "VlvAccess.h" +#include "VlvCommonDefinitions.h" + +#endif diff --git a/Vlv2TbltDevicePkg/Include/CommonIncludes.h b/Vlv2TbltDevicePkg/Include/CommonIncludes.h new file mode 100644 index 0000000000..04b5405806 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/CommonIncludes.h @@ -0,0 +1,120 @@ +/** + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +@file + CommonIncludes.h + +@brief + This file defines common equates. + +**/ +#ifndef _COMMON_INCLUDES_H_ +#define _COMMON_INCLUDES_H_ + +#define V_INTEL_VID 0x8086 + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif +/// +/// Min Max +/// +#define V_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define V_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/// +/// Bit map macro +/// +#ifndef BIT0 + +#define BIT63 0x8000000000000000 +#define BIT62 0x4000000000000000 +#define BIT61 0x2000000000000000 +#define BIT60 0x1000000000000000 +#define BIT59 0x0800000000000000 +#define BIT58 0x0400000000000000 +#define BIT57 0x0200000000000000 +#define BIT56 0x0100000000000000 +#define BIT55 0x0080000000000000 +#define BIT54 0x0040000000000000 +#define BIT53 0x0020000000000000 +#define BIT52 0x0010000000000000 +#define BIT51 0x0008000000000000 +#define BIT50 0x0004000000000000 +#define BIT49 0x0002000000000000 +#define BIT48 0x0001000000000000 +#define BIT47 0x0000800000000000 +#define BIT46 0x0000400000000000 +#define BIT45 0x0000200000000000 +#define BIT44 0x0000100000000000 +#define BIT43 0x0000080000000000 +#define BIT42 0x0000040000000000 +#define BIT41 0x0000020000000000 +#define BIT40 0x0000010000000000 +#define BIT39 0x0000008000000000 +#define BIT38 0x0000004000000000 +#define BIT37 0x0000002000000000 +#define BIT36 0x0000001000000000 +#define BIT35 0x0000000800000000 +#define BIT34 0x0000000400000000 +#define BIT33 0x0000000200000000 +#define BIT32 0x0000000100000000 + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 +#endif + +#define BITS(x) (1 << (x)) + +// +// Notes : +// 1. Bit position always starts at 0. +// 2. Following macros are applicable only for Word alligned integers. +// +#define BIT(Pos, Value) (1 << (Pos) & (Value)) +#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1)) + +#endif diff --git a/Vlv2TbltDevicePkg/Include/CpuType.h b/Vlv2TbltDevicePkg/Include/CpuType.h new file mode 100644 index 0000000000..50562dc660 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/CpuType.h @@ -0,0 +1,64 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + CpuType.h + +Abstract: + +--*/ + +#ifndef _CPU_TYPE_H +#define _CPU_TYPE_H + +#pragma pack(1) + +typedef enum { + EnumCpuUarchUnknown = 0, + EnumNehalemUarch, +} EFI_CPU_UARCH; + +typedef enum { + EnumCpuPlatformUnknown = 0, + EnumDesktop, + EnumMobile, + EnumServer, + EnumNetTop +} EFI_CPU_PLATFORM; + +typedef enum { + EnumCpuTypeUnknown = 0, + EnumAtom, + EnumNehalemEx, + EnumBloomfield, + EnumGainestown, + EnumHavendale, + EnumLynnfield, + EnumAuburndale, + EnumClarksfield, + EnumPineview, + EnumCedarview, + EnumValleyview, + EnumClarkdale // Havendale 32nm +} EFI_CPU_TYPE; + +typedef enum { + EnumCpuFamilyUnknown = 0, + EnumFamilyField, + EnumFamilyDale +} EFI_CPU_FAMILY; + +#pragma pack() + +#endif diff --git a/Vlv2TbltDevicePkg/Include/FileHandleLib.h b/Vlv2TbltDevicePkg/Include/FileHandleLib.h new file mode 100644 index 0000000000..59d1b92355 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/FileHandleLib.h @@ -0,0 +1,504 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef _FILE_HANDLE_LIBRARY_HEADER_ +#define _FILE_HANDLE_LIBRARY_HEADER_ + +#include + +// +// The tag for use in identifying UNICODE files. +// If the file is UNICODE, the first 16 bits of the file will equal this value. +// +extern CONST UINT16 gUnicodeFileTag; + +/** + This function retrieves information about the file for the handle + specified and stores it in the allocated pool memory. + + This function allocates a buffer to store the file's information. It is the + caller's responsibility to free the buffer. + + @param[in] FileHandle The file handle of the file for which information is + being requested. + + @retval NULL Information could not be retrieved. + @retval !NULL The information about the file. +**/ +EFI_FILE_INFO* +EFIAPI +FileHandleGetInfo ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + This function sets the information about the file for the opened handle + specified. + + @param[in] FileHandle The file handle of the file for which information + is being set. + + @param[in] FileInfo The information to set. + + @retval EFI_SUCCESS The information was set. + @retval EFI_INVALID_PARAMETER A parameter was out of range or invalid. + @retval EFI_UNSUPPORTED The FileHandle does not support FileInfo. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write protected. + @retval EFI_ACCESS_DENIED The file was opened read only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +EFI_STATUS +EFIAPI +FileHandleSetInfo ( + IN EFI_FILE_HANDLE FileHandle, + IN CONST EFI_FILE_INFO *FileInfo + ); + +/** + This function reads information from an opened file. + + If FileHandle is not a directory, the function reads the requested number of + bytes from the file at the file's current position and returns them in Buffer. + If the read goes beyond the end of the file, the read length is truncated to the + end of the file. The file's current position is increased by the number of bytes + returned. If FileHandle is a directory, the function reads the directory entry + at the file's current position and returns the entry in Buffer. If the Buffer + is not large enough to hold the current directory entry, then + EFI_BUFFER_TOO_SMALL is returned and the current file position is not updated. + BufferSize is set to be the size of the buffer needed to read the entry. On + success, the current position is updated to the next directory entry. If there + are no more directory entries, the read returns a zero-length buffer. + EFI_FILE_INFO is the structure returned as the directory entry. + + @param[in] FileHandle The opened file handle. + @param[in, out] BufferSize On input, the size of buffer in bytes. On return, + the number of bytes written. + @param[out] Buffer The buffer to put read data into. + + @retval EFI_SUCCESS Data was read. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TO_SMALL Buffer is too small. ReadSize contains required + size. + +**/ +EFI_STATUS +EFIAPI +FileHandleRead( + IN EFI_FILE_HANDLE FileHandle, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Write data to a file. + + This function writes the specified number of bytes to the file at the current + file position. The current file position is advanced the actual number of bytes + written, which is returned in BufferSize. Partial writes only occur when there + has been a data error during the write attempt (such as "volume space full"). + The file is automatically grown to hold the data if required. Direct writes to + opened directories are not supported. + + @param[in] FileHandle The opened file for writing. + @param[in, out] BufferSize On input, the number of bytes in Buffer. On output, + the number of bytes written. + @param[in] Buffer The buffer containing data to write is stored. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to an open directory are not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write-protected. + @retval EFI_ACCESS_DENIED The file was opened for read only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +EFI_STATUS +EFIAPI +FileHandleWrite( + IN EFI_FILE_HANDLE FileHandle, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Close an open file handle. + + This function closes a specified file handle. All "dirty" cached file data is + flushed to the device, and the file is closed. In all cases the handle is + closed. + + @param[in] FileHandle The file handle to close. + + @retval EFI_SUCCESS The file handle was closed successfully. +**/ +EFI_STATUS +EFIAPI +FileHandleClose ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Delete a file and close the handle. + + This function closes and deletes a file. In all cases the file handle is closed. + If the file cannot be deleted, the warning code EFI_WARN_DELETE_FAILURE is + returned, but the handle is still closed. + + @param[in] FileHandle The file handle to delete. + + @retval EFI_SUCCESS The file was closed successfully. + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not + deleted. + @retval INVALID_PARAMETER One of the parameters has an invalid value. +**/ +EFI_STATUS +EFIAPI +FileHandleDelete ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Set the current position in a file. + + This function sets the current file position for the handle to the position + supplied. With the exception of moving to position 0xFFFFFFFFFFFFFFFF, only + absolute positioning is supported, and moving past the end of the file is + allowed (a subsequent write would grow the file). Moving to position + 0xFFFFFFFFFFFFFFFF causes the current position to be set to the end of the file. + If FileHandle is a directory, the only position that may be set is zero. This + has the effect of starting the read process of the directory entries over again. + + @param[in] FileHandle The file handle on which the position is being set. + @param[in] Position The byte position from the begining of the file. + + @retval EFI_SUCCESS The operation completed sucessfully. + @retval EFI_UNSUPPORTED The request for non-zero is not valid on + directories. + @retval INVALID_PARAMETER One of the parameters has an invalid value. +**/ +EFI_STATUS +EFIAPI +FileHandleSetPosition ( + IN EFI_FILE_HANDLE FileHandle, + IN UINT64 Position + ); + +/** + Gets a file's current position. + + This function retrieves the current file position for the file handle. For + directories, the current file position has no meaning outside of the file + system driver. As such, the operation is not supported. An error is returned + if FileHandle is a directory. + + @param[in] FileHandle The open file handle on which to get the position. + @param[out] Position The byte position from begining of file. + + @retval EFI_SUCCESS The operation completed successfully. + @retval INVALID_PARAMETER One of the parameters has an invalid value. + @retval EFI_UNSUPPORTED The request is not valid on directories. +**/ +EFI_STATUS +EFIAPI +FileHandleGetPosition ( + IN EFI_FILE_HANDLE FileHandle, + OUT UINT64 *Position + ); + +/** + Flushes data on a file. + + This function flushes all modified data associated with a file to a device. + + @param[in] FileHandle The file handle on which to flush data. + + @retval EFI_SUCCESS The data was flushed. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write protected. + @retval EFI_ACCESS_DENIED The file was opened for read only. +**/ +EFI_STATUS +EFIAPI +FileHandleFlush ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Function to determine if a given handle is a directory handle. + + If DirHandle is NULL, then ASSERT(). + + Open the file information on the DirHandle, and verify that the Attribute + includes EFI_FILE_DIRECTORY bit set. + + @param[in] DirHandle The handle to open the file. + + @retval EFI_SUCCESS DirHandle is a directory. + @retval EFI_INVALID_PARAMETER DirHandle did not have EFI_FILE_INFO available. + @retval EFI_NOT_FOUND DirHandle is not a directory. +**/ +EFI_STATUS +EFIAPI +FileHandleIsDirectory ( + IN EFI_FILE_HANDLE DirHandle + ); + +/** + Retrieve first entry from a directory. + + This function takes an open directory handle and gets information from the + first entry in the directory. A buffer is allocated to contain + the information and a pointer to the buffer is returned in *Buffer. The + caller can use FileHandleFindNextFile() to get subsequent directory entries. + + The buffer will be freed by FileHandleFindNextFile() when the last directory + entry is read. Otherwise, the caller must free the buffer, using FreePool, + when finished with it. + + @param[in] DirHandle The file handle of the directory to search. + @param[out] Buffer The pointer to pointer to buffer for file's information. + + @retval EFI_SUCCESS Found the first file. + @retval EFI_NOT_FOUND Cannot find the directory. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @return Others The status of FileHandleGetInfo, FileHandleSetPosition, + or FileHandleRead. +**/ +EFI_STATUS +EFIAPI +FileHandleFindFirstFile ( + IN EFI_FILE_HANDLE DirHandle, + OUT EFI_FILE_INFO **Buffer + ); + +/** + Retrieve next entries from a directory. + + To use this function, the caller must first call the FileHandleFindFirstFile() + function to get the first directory entry. Subsequent directory entries are + retrieved by using the FileHandleFindNextFile() function. This function can + be called several times to get each entry from the directory. If the call of + FileHandleFindNextFile() retrieved the last directory entry, the next call of + this function will set *NoFile to TRUE and free the buffer. + + @param[in] DirHandle The file handle of the directory. + @param[out] Buffer The pointer to buffer for file's information. + @param[out] NoFile The pointer to boolean when last file is found. + + @retval EFI_SUCCESS Found the next file, or reached last file. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. +**/ +EFI_STATUS +EFIAPI +FileHandleFindNextFile( + IN EFI_FILE_HANDLE DirHandle, + OUT EFI_FILE_INFO *Buffer, + OUT BOOLEAN *NoFile + ); + +/** + Retrieve the size of a file. + + If FileHandle is NULL then ASSERT(). + If Size is NULL then ASSERT(). + + This function extracts the file size info from the FileHandle's EFI_FILE_INFO + data. + + @param[in] FileHandle The file handle from which size is retrieved. + @param[out] Size The pointer to size. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Cannot access the file. +**/ +EFI_STATUS +EFIAPI +FileHandleGetSize ( + IN EFI_FILE_HANDLE FileHandle, + OUT UINT64 *Size + ); + +/** + Set the size of a file. + + If FileHandle is NULL then ASSERT(). + + This function changes the file size info from the FileHandle's EFI_FILE_INFO + data. + + @param[in] FileHandle The file handle whose size is to be changed. + @param[in] Size The new size. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Cannot access the file. +**/ +EFI_STATUS +EFIAPI +FileHandleSetSize ( + IN EFI_FILE_HANDLE FileHandle, + IN UINT64 Size + ); + +/** + Function to get a full filename given a EFI_FILE_HANDLE somewhere lower on the + directory 'stack'. + + @param[in] Handle Handle to the Directory or File to create path to. + @param[out] FullFileName Pointer to pointer to generated full file name. It + is the responsibility of the caller to free this memory + with a call to FreePool(). + @retval EFI_SUCCESS The operation was successful and FullFileName is valid. + @retval EFI_INVALID_PARAMETER Handle was NULL. + @retval EFI_INVALID_PARAMETER FullFileName was NULL. + @retval EFI_OUT_OF_MEMORY A memory allocation failed. +**/ +EFI_STATUS +EFIAPI +FileHandleGetFileName ( + IN CONST EFI_FILE_HANDLE Handle, + OUT CHAR16 **FullFileName + ); + +/** + Function to read a single line (up to but not including the \n) from a file. + + If the position upon start is 0, then the Ascii Boolean will be set. This should be + maintained and not changed for all operations with the same file. + + @param[in] Handle FileHandle to read from. + @param[in, out] Buffer The pointer to buffer to read into. + @param[in, out] Size The pointer to number of bytes in Buffer. + @param[in] Truncate If the buffer is large enough, this has no effect. + If the buffer is is too small and Truncate is TRUE, + the line will be truncated. + If the buffer is is too small and Truncate is FALSE, + then no read will occur. + + @param[in, out] Ascii Boolean value for indicating whether the file is + Ascii (TRUE) or UCS2 (FALSE). + + @retval EFI_SUCCESS The operation was successful. The line is stored in + Buffer. + @retval EFI_INVALID_PARAMETER Handle was NULL. + @retval EFI_INVALID_PARAMETER Size was NULL. + @retval EFI_BUFFER_TOO_SMALL Size was not large enough to store the line. + Size was updated to the minimum space required. + @sa FileHandleRead +**/ +EFI_STATUS +EFIAPI +FileHandleReadLine( + IN EFI_FILE_HANDLE Handle, + IN OUT CHAR16 *Buffer, + IN OUT UINTN *Size, + IN BOOLEAN Truncate, + IN OUT BOOLEAN *Ascii + ); + +/** + Function to read a single line from a file. The \n is not included in the returned + buffer. The returned buffer must be callee freed. + + If the position upon start is 0, then the Ascii Boolean will be set. This should be + maintained and not changed for all operations with the same file. + + @param[in] Handle FileHandle to read from. + @param[in, out] Ascii Boolean value for indicating whether the file is + Ascii (TRUE) or UCS2 (FALSE). + + @return The line of text from the file. + + @sa FileHandleReadLine +**/ +CHAR16* +EFIAPI +FileHandleReturnLine( + IN EFI_FILE_HANDLE Handle, + IN OUT BOOLEAN *Ascii + ); + +/** + Function to write a line of unicode text to a file. + + If Handle is NULL, ASSERT. + + @param[in] Handle FileHandle to write to. + @param[in] Buffer Buffer to write, if NULL the function will + take no action and return EFI_SUCCESS. + + @retval EFI_SUCCESS The data was written. + @retval other Failure. + + @sa FileHandleWrite +**/ +EFI_STATUS +EFIAPI +FileHandleWriteLine( + IN EFI_FILE_HANDLE Handle, + IN CHAR16 *Buffer + ); + +/** + Function to take a formatted argument and print it to a file. + + @param[in] Handle The file handle for the file to write to. + @param[in] Format The format argument (see printlib for the format specifier). + @param[in] ... The variable arguments for the format. + + @retval EFI_SUCCESS The operation was successful. + @retval other A return value from FileHandleWriteLine. + + @sa FileHandleWriteLine +**/ +EFI_STATUS +EFIAPI +FileHandlePrintLine( + IN EFI_FILE_HANDLE Handle, + IN CONST CHAR16 *Format, + ... + ); + +/** + Function to determine if a FILE_HANDLE is at the end of the file. + + This will NOT work on directories. + + If Handle is NULL, then ASSERT(). + + @param[in] Handle The file handle. + + @retval TRUE The position is at the end of the file. + @retval FALSE The position is not at the end of the file. +**/ +BOOLEAN +EFIAPI +FileHandleEof( + IN EFI_FILE_HANDLE Handle + ); + +#endif //_FILE_HANDLE_LIBRARY_HEADER_ + diff --git a/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h new file mode 100644 index 0000000000..663b26d4da --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h @@ -0,0 +1,35 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + AcpiTableStorage.h + +Abstract: + + GUID for the ACPI Table Storage filename. + + This GUID is defined in the Tiano ACPI Table Storage EPS. + +--*/ + +#ifndef _ACPI_TABLE_STORAGE_H_ +#define _ACPI_TABLE_STORAGE_H_ + +#define EFI_ACPI_TABLE_STORAGE_GUID \ + { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd} } + +extern EFI_GUID gEfiAcpiTableStorageGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h new file mode 100644 index 0000000000..54df0b5b31 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h @@ -0,0 +1,91 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Asf.h + +Abstract: + + Alert Standard Format address variable + +--*/ + +#ifndef AlertStandardFormat_h_included +#define AlertStandardFormat_h_included + + +#pragma pack(1) + +// +// ASF address +// +// +// {3D995FB4-4F05-4073-BE72-A19CFB5DE690} +// +#define ALERT_STANDARD_FORMAT_VARIABLE_GUID \ + {0x3d995fb4, 0x4f05, 0x4073, 0xbe, 0x72, 0xa1, 0x9c, 0xfb, 0x5d, 0xe6, 0x90} + +#define ALERT_STANDARD_FORMAT_VARIABLE_NAME (L"ASF") +#define ASCII_ALERT_STANDARD_FORMAT_VARIABLE_NAME ("ASF") + +extern EFI_GUID gAlertStandardFormatGuid; +extern CHAR16 gAlertStandardFormatName[]; + +typedef struct { + UINT8 SmbusAddr; + struct { + UINT32 VendorSpecificId; + UINT16 SubsystemDeviceId; + UINT16 SubsystemVendorId; + UINT16 Interface; + UINT16 DeviceId; + UINT16 VendorId; + UINT8 VendorRevision; + UINT8 DeviceCapabilities; + } Udid; + struct { + UINT8 SubCommand; + UINT8 Version; + UINT32 IanaId; + UINT8 SpecialCommand; + UINT16 SpecialCommandParam; + UINT16 BootOptionsBits; + UINT16 OemParam; + } AsfBootOptions; + struct { + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT16 VendorId; + UINT16 DeviceId; + UINT16 IderCmdBar; + UINT16 IderCtrlBar; + UINT8 IderIrq; + UINT16 SolBar; + UINT8 SolIrq; + } PciInfo; + struct { + UINT8 IamtProvisioningStatus; + BOOLEAN IamtIsProvisioned; + } IamtInfo; + struct { + BOOLEAN FlashUpdatingIsAllowed; + } MeInfoForEbu; + UINT32 EitBPFAddress; +} EFI_ASF_VARIABLE; + +#pragma pack() + +#endif + diff --git a/Vlv2TbltDevicePkg/Include/Guid/BiosId.h b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h new file mode 100644 index 0000000000..15914b883e --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h @@ -0,0 +1,35 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + BiosId.h + +Abstract: + + GUIDs used for Bios ID. + +--*/ + +#ifndef _BIOS_ID_H_ +#define _BIOS_ID_H_ + + +#define EFI_BIOS_ID_GUID \ +{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } + + +extern EFI_GUID gEfiBiosIdGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h new file mode 100644 index 0000000000..11bb98bb74 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h @@ -0,0 +1,219 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + BoardFeatures.h + +Abstract: + + EFI Platform Board Features + + + +--*/ + +#ifndef BoardFeatures_h_included +#define BoardFeatures_h_included + +#include + +#pragma pack(1) + +// +// Board Features +// +#if defined LEGACY_BOARD_FEATURES && LEGACY_BOARD_FEATURES +#define B_BOARD_FEATURES_CHIPSET_LAN BIT0 +#define B_BOARD_FEATURES_LAN_MARVELL BIT1 +#define B_BOARD_FEATURES_AA_NOT_FOUND BIT2 +#define B_BOARD_FEATURES_SIO_NO_COM1 BIT3 +#define B_BOARD_FEATURES_SIO_COM2 BIT4 +#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT5 +#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT6 +#define B_BOARD_FEATURES_CHIPSET_VIDEO_OPTION0 BIT7 +#define B_BOARD_FEATURES_VIDEO_SLOT BIT8 +#define B_BOARD_FEATURES_MINI_CARD BIT9 +#define B_BOARD_FEATURES_DISCRETE_1394 BIT10 +#define B_BOARD_FEATURES_LEGACY_FREE BIT11 +#define B_BOARD_FEATURES_USB_HUB BIT12 +#define B_BOARD_FEATURES_TPM BIT13 +#define B_BOARD_FEATURES_VIIV BIT14 +#define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19) +#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15 +#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16 +#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17 +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18 +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19 +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR1 BIT20 +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21 +#define B_BOARD_FEATURES_MEMORY_SLOT_MASK BIT23 | BIT22 +#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT22=0, BIT23=0 +#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT22 // BIT22=1, BIT23=0 +#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT23 // BIT22=0, BIT23=1 +#define V_BOARD_FEATURES_4_MEMORY_SLOT BIT23 | BIT22 // BIT22=1, BIT23=1 +#define B_BOARD_FEATURES_ALT_MEM_CLK_RT BIT24 +#define B_BOARD_FEATURES_SLEEP_MASK BIT25 +#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT25=0 +#define V_BOARD_FEATURES_SLEEP_S3 BIT25 // BIT25=1 +#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT26 // 0/1= 5/3 Rear Jacks +#define B_BOARD_FEATURES_DISCRETE_SATA BIT27 +#define B_BOARD_FEATURES_2_SATA BIT28 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8) +#define B_BOARD_FEATURES_RVP BIT29 // Board is an RVP board +#define B_BOARD_FEATURES_PORT80_LPC BIT30 // Port80 PCI(0) or LPC(1) +#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT31 // Limited CPU support +#define B_BOARD_FEATURES_PMP_SUPPORT BIT32 // Support for over-voltaging memory +#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT33 // Support for the HW-based 555 Watchdog Timer feature +#define B_BOARD_FEATURES_NO_QRT BIT34 // disable QRT +#define B_BOARD_FEATURES_VERB_TABLE1 BIT35 // Verb table 1 +#define B_BOARD_FEATURES_VERB_TABLE2 BIT36 // Verb table 2 +#define B_BOARD_FEATURES_VERB_TABLE3 BIT37 // Verb table 3 +#define B_BOARD_FEATURES_VERB_TABLE4 BIT38 // Verb table 4 +#define B_BOARD_FEATURES_VERB_TABLE5 BIT39 // Reserved for Verb table 5 +#define B_BOARD_FEATURES_VERB_TABLE_MASK BIT35 | BIT36 | BIT37 | BIT38 | BIT39 +#define B_BOARD_FEATURES_KENTSFIELD_BLOCK BIT40 // Kentsfield not supported +#define B_BOARD_FEATURES_KENTSFIELD_WARNING BIT41 // Kentsfield warning +#define B_BOARD_FEATURES_ESATA_PORT0 BIT42 // E-SATA on Port0 +#define B_BOARD_FEATURES_ESATA_PORT1 BIT43 // E-SATA on Port1 +#define B_BOARD_FEATURES_ESATA_PORT2 BIT44 // E-SATA on Port2 +#define B_BOARD_FEATURES_ESATA_PORT3 BIT45 // E-SATA on Port3 +#define B_BOARD_FEATURES_ESATA_PORT4 BIT46 // E-SATA on Port4 +#define B_BOARD_FEATURES_ESATA_PORT5 BIT47 // E-SATA on Port5 +#define B_BOARD_FEATURES_ECIR BIT48 // Enhanced Consumer IR +#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT49 // Wake from S5 via PS2 keyboard +#define B_BOARD_FEATURES_HDAUDIOLINK BIT50 // HD audio link support +#define B_BOARD_FEATURES_1_PATA BIT51 +#define B_BOARD_FEATURES_MOBILE BIT52 +#define B_BOARD_FEATURES_NO_FLOPPY BIT53 +#define B_BOARD_FEATURES_DISABLE_UNUSED_FSB BIT54 + +// +// Bit 55-58 reserved by PSID support. CPU power requirement below are preliminary. +// They might be changed. +// This is not same as 8.6.1 products so be careful. +// +#define B_BOARD_FEATURES_CPU_POWER_BITNUM 55 +#define B_BOARD_FEATURES_CPU_POWER_MASK (BIT55 | BIT56 | BIT57 | BIT58) +#define B_BOARD_FEATURES_CPU_POWER_35W 0 // Theoretically doesn't exist. +#define B_BOARD_FEATURES_CPU_POWER_40W BIT55 // 0001 +#define B_BOARD_FEATURES_CPU_POWER_45W BIT56 // 0010 +#define B_BOARD_FEATURES_CPU_POWER_50W (BIT55 | BIT56) // 0011 +#define B_BOARD_FEATURES_CPU_POWER_65W BIT57 // 0100 Wolfdale-H/-M +#define B_BOARD_FEATURES_CPU_POWER_70W (BIT55 | BIT57) // 0101 +#define B_BOARD_FEATURES_CPU_POWER_75W (BIT56 | BIT57) // 0110 +#define B_BOARD_FEATURES_CPU_POWER_80W (BIT55 | BIT56 | BIT57) // 0111 +#define B_BOARD_FEATURES_CPU_POWER_95W BIT58 // 1000 Yorkfield +#define B_BOARD_FEATURES_CPU_POWER_100W (BIT55 | BIT58) // 1001 +#define B_BOARD_FEATURES_CPU_POWER_105W (BIT56 | BIT58) // 1010 +#define B_BOARD_FEATURES_CPU_POWER_110W (BIT55 | BIT56 | BIT58) // 1011 +#define B_BOARD_FEATURES_CPU_POWER_130W (BIT57 | BIT58) // 1100 XE Yorkfield +#define B_BOARD_FEATURES_CPU_POWER_135W (BIT55 | BIT57 | BIT58) // 1101 +#define B_BOARD_FEATURES_CPU_POWER_Over135W (BIT56 | BIT57 | BIT58) // 1110 Reserved +#define B_BOARD_FEATURES_CPU_POWER_140W (BIT55 | BIT56 | BIT57 | BIT58) // 1111 Reserved +#define B_VV_BOARD_FEATURES BIT59 +#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT60 // Include IDCC2 support +#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT61 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag +#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT62 +#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT63 + +#else + +#define B_BOARD_FEATURES_CHIPSET_LAN BIT0 +#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT1 +#define B_BOARD_FEATURES_VIDEO_SLOT BIT2 +#define B_BOARD_FEATURES_AA_NOT_FOUND BIT3 +#define B_BOARD_FEATURES_SIO_NO_COM1 BIT4 +#define B_BOARD_FEATURES_SIO_COM2 BIT5 +#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT6 +#define B_BOARD_FEATURES_NO_FLOPPY BIT7 +#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT8 // Wake from S5 via PS2 keyboard +#define B_BOARD_FEATURES_ECIR BIT9 // Enhanced Consumer IR +#define B_BOARD_FEATURES_LEGACY_FREE BIT10 +#define B_BOARD_FEATURES_MINI_CARD BIT11 +#define B_BOARD_FEATURES_DISCRETE_1394 BIT12 +#define B_BOARD_FEATURES_USB_HUB BIT13 +#define B_BOARD_FEATURES_TPM BIT14 +#define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20) +#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15 +#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16 +#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17 +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18 +#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19 +#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20 +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21 +#define B_BOARD_FEATURES_MEMORY_TYPE_DDR3 BIT22 +#define B_BOARD_FEATURES_MEMORY_SLOT_MASK (BIT24 | BIT23) +#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT23=0, BIT24=0 +#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT23 // BIT23=1, BIT24=0 +#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT24 // BIT23=0, BIT24=1 +#define V_BOARD_FEATURES_4_MEMORY_SLOT (BIT24 | BIT23) // BIT23=1, BIT24=1 +#define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2 Channel 0 memory slot +#define B_BOARD_FEATURES_SLEEP_MASK BIT26 +#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT26=0 +#define V_BOARD_FEATURES_SLEEP_S3 BIT26 // BIT26=1 +#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT27 // 0/1= 5/3 Rear Jacks +#define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio link support +#define B_BOARD_FEATURES_DISCRETE_SATA BIT29 +#define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8) +#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT31 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag +#define B_BOARD_FEATURES_RVP BIT32 // Board is an RVP board +#define B_BOARD_FEATURES_ESATA_PORT0 BIT33 // E-SATA on Port0 +#define B_BOARD_FEATURES_ESATA_PORT1 BIT34 // E-SATA on Port1 +#define B_BOARD_FEATURES_ESATA_PORT2 BIT35 // E-SATA on Port2 +#define B_BOARD_FEATURES_ESATA_PORT3 BIT36 // E-SATA on Port3 +#define B_BOARD_FEATURES_ESATA_PORT4 BIT37 // E-SATA on Port4 +#define B_BOARD_FEATURES_ESATA_PORT5 BIT38 // E-SATA on Port5 +#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT39 // Include IDCC2 support +#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT40 +#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT41 // Limited CPU support +#define B_BOARD_FEATURES_PMP_SUPPORT BIT42 // Support for over-voltaging memory +#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT43 // Support for the HW-based 555 Watchdog Timer feature +#define B_BOARD_FEATURES_LVDS BIT44 // Support for LVDS +#define B_BOARD_FEATURES_VERB_TABLE_MASK (BIT45|BIT46|BIT47|BIT48) // Verb table +#define B_BOARD_FEATURES_VERB_TABLE1 BIT45 // Verb table 1 +#define B_BOARD_FEATURES_VERB_TABLE2 BIT46 // Verb table 2 +#define B_BOARD_FEATURES_VERB_TABLE3 BIT47 // Verb table 3 +#define B_BOARD_FEATURES_VERB_TABLE4 BIT48 // Verb table 4 +#define B_BOARD_FEATURES_NO_MINIPCIE BIT49 // Mini PCIe slot +#define B_BOARD_FEATURES_HDMI_SLOT BIT50 // HDMI slot +#define B_BOARD_FEATURES_PS2_HIDE BIT51 // PS2 hide +#define B_BOARD_FEATURES_DVID_SLOT BIT52 // DVID slot + +#define B_BOARD_FEATURES_SIO_COM3 BIT53 +#define B_BOARD_FEATURES_SIO_COM4 BIT54 + +#define B_BOARD_FEATURES_LAN2 BIT55 +#define B_BOARD_FEATURES_PCIe_SLOT BIT56 +#endif + +typedef UINT64 EFI_BOARD_FEATURES; + +#pragma pack() + +// +// Global ID for the Platform Boot Mode Protocol. +// +#define EFI_BOARD_FEATURES_GUID \ + { 0x94b9e8ae, 0x8877, 0x479a, 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 } + +extern EFI_GUID gEfiBoardFeaturesGuid; + +#define BOARD_FEATURES_NAME L"BoardFeatures" + +#define EFI_BOARD_ID_GUID \ + { 0x6b2dd245, 0x3f2, 0x414a, 0x8c, 0x2, 0x9f, 0xfc, 0x23, 0x52, 0xe3, 0x1e } +#define EFI_BOARD_ID_NAME (L"BoardId") + +#endif + diff --git a/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h new file mode 100644 index 0000000000..31fa3e0511 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h @@ -0,0 +1,161 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + EfiVpdData.h + +Abstract: + + Constants and declarations that are common accross PEI and DXE. +--*/ + +#ifndef _EFI_VPD_DATA_H_ +#define _EFI_VPD_DATA_H_ + + +#pragma pack(1) + +// +// DMI data +// +typedef struct { + + CHAR8 DmiGpnvHeader[4]; // $DMI + CHAR8 SystemInfoManufacturer[0x20]; // Structure Type 1 String 1 + CHAR8 SystemInfoProductName[0x20]; // Structure Type 1 String 2 + CHAR8 SystemInfoVersion[0x18]; // Structure Type 1 String 3 + CHAR8 SystemInfoSerialNumber[0x20]; // Structure Type 1 String 4 + CHAR8 BaseBoardManufacturer[0x20]; // Structure Type 2 String 1 + CHAR8 BaseBoardProductName[0x20]; // Structure Type 2 String 2 + CHAR8 BaseBoardVersion[0x18]; // Structure Type 2 String 3 + CHAR8 BaseBoardSerialNumber[0x20]; // Structure Type 2 String 4 + CHAR8 ChassisManufacturer[0x20]; // Structure Type 3 String 1 + UINT8 ChassisType; // Enumerated + CHAR8 ChassisVersion[0x18]; // Structure Type 3 String 2 + CHAR8 ChassisSerialNumber[0x20]; // Structure Type 3 String 3 + CHAR8 ChassisAssetTag[0x20]; // Structure Type 3 String 4 + UINT8 MfgAccessKeyWorkspace; + + UINT8 ChecksumFixupPool[0xd]; // Checksum Fix-ups + UINT8 SwitchboardData[4]; // 32 switch switchboard + UINT8 IntelReserved; // Reserved for Future Use +} DMI_DATA; + +#define DMI_DATA_GUID \ + { \ + 0x70e56c5e, 0x280c, 0x44b0, 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e \ + } + +#define DMI_DATA_NAME (L"DmiData") +#define ASCII_DMI_DATA_NAME ("DmiData") + +extern EFI_GUID gDmiDataGuid; +extern CHAR16 gDmiDataName[]; + +// +// UUID - universally unique system id. +// +#define UUID_VARIABLE_GUID \ + { \ + 0xd357c710, 0x0ada, 0x4717, 0x8d, 0xba, 0xc6, 0xad, 0xc7, 0xcd, 0x2b, 0x2a \ + } + +#define UUID_VARIABLE_NAME (L"UUID") +#define ASCII_UUID_VARIABLE_NAME ("UUID") + +// +// UUID data +// +typedef struct { + UINT32 UuidHigh; + UINT32 UuidLow; +} SYSTEM_1394_UUID; + +typedef struct { + EFI_GUID SystemUuid; // System Unique ID + SYSTEM_1394_UUID System1394Uuid; // Onboard 1394 UUID +} UUID_DATA; + +extern EFI_GUID gUuidVariableGuid; +extern CHAR16 gUuidVariableName[]; + +// +// MB32GUID for Computrace. +// + +#define MB32_GUID \ + { 0x539D62BA, 0xDE35, 0x453E, 0xBA, 0xB0, 0x85, 0xDB, 0x8D, 0xA2, 0x42, 0xF9 } + +#define MB32_VARIABLE_NAME (L"MB32") +#define ASCII_MB32_VARIABLE_NAME ("MB32") + +extern EFI_GUID gMb32Guid; +extern CHAR16 gMb32VariableName[]; + +// +// ACPI OSFR Manufacturer String. +// +// {72234213-0FD7-48a1-A59F-B41BC107FBCD} +// +#define ACPI_OSFR_MFG_STRING_VARIABLE_GUID \ + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd} +#define ACPI_OSFR_MFG_STRING_VARIABLE_NAME (L"OcurMfg") +#define ASCII_ACPI_OSFR_MF_STRING_VARIABLE_NAME ("OcurMfg") + +extern EFI_GUID gACPIOSFRMfgStringVariableGuid; + + +// +// ACPI OSFR Model String. +// +// {72234213-0FD7-48a1-A59F-B41BC107FBCD} +// +#define ACPI_OSFR_MODEL_STRING_VARIABLE_GUID \ + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd} +#define ACPI_OSFR_MODEL_STRING_VARIABLE_NAME (L"OcurModel") +#define ASCII_ACPI_OSFR_MODEL_STRING_VARIABLE_NAME ("OcurModel") + +extern EFI_GUID gACPIOSFRModelStringVariableGuid; + +// +// ACPI OSFR Reference Data Block. +// +// {72234213-0FD7-48a1-A59F-B41BC107FBCD} +// +#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_GUID \ + {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd} +#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME (L"OcurRef") +#define ASCII_ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME ("OcurRef") +extern EFI_GUID gACPIOSFRRefDataBlockVariableGuid; + +// +// Manufacturing mode GUID +// +#define MfgMode_GUID \ + { 0xEF14FD78, 0x0793, 0x4e2b, 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 } + +#define MFGMODE_VARIABLE_NAME (L"MfgMode") +#define ASCII_MFGMODE_VARIABLE_NAME ("MfgMode") + +typedef struct { + UINT8 MfgModeData; +} MFG_MODE_VAR; + +extern EFI_GUID gMfgModeVariableGuid; +extern CHAR16 gMfgModeVariableName[]; + +#pragma pack() + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h new file mode 100644 index 0000000000..061ded0f7a --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h @@ -0,0 +1,66 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + FirmwareId.h + +--*/ + +#ifndef _FirmwareId_h_GUID_included +#define _FirmwareId_h_GUID_included + + +#pragma pack(1) + +// +// Firmware ID +// + +#define FIRMWARE_ID_MAX_LENGTH 35 + +typedef struct { + CHAR8 BiosId[8]; + CHAR8 Separator1; + CHAR8 OemId[3]; + CHAR8 Separator2; + CHAR8 BuildId[4]; + CHAR8 Separator3; + CHAR8 Century[2]; + CHAR8 Year[2]; + CHAR8 Separator4; + CHAR8 Month[2]; + CHAR8 Date[2]; + CHAR8 Separator5; + CHAR8 Hour[2]; + CHAR8 Minute[2]; + CHAR8 Dummy[3]; +} FIRMWARE_ID_DATA; + +#define OLD_FIRMWARE_ID_GUID \ + {0xefc071ae, 0x41b8, 0x4018, 0xaf, 0xa7, 0x31, 0x4b, 0x18, 0x5e, 0x57, 0x8b} + +#define FIRMWARE_ID_GUID \ + {0x5e559c23, 0x1faa, 0x4ae1, 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f} + +#define FIRMWARE_ID_NAME L"FirmwareId" +#define FIRMWARE_ID_NAME_WITH_PASSWORD FIRMWARE_ID_NAME L"H#8,^-!t" + +extern EFI_GUID gFirmwareIdGuid; +extern CHAR16 gFirmwareIdName[]; + +#pragma pack() + +#endif + diff --git a/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h new file mode 100644 index 0000000000..cfb2228e2c --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h @@ -0,0 +1,139 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + HwWatchdogTimerHob.h + +Abstract: + + GUID used for Watchdog Timer status in the HOB list. + +--*/ + +#ifndef _EFI_WATCHDOG_TIMER_HOB_GUID_H_ +#define _EFI_WATCHDOG_TIMER_HOB_GUID_H_ + +#define EFI_WATCHDOG_TIMER_HOB_GUID \ + { 0x226cd3f, 0x69b5, 0x4150, 0xac, 0xbe, 0xbf, 0xbf, 0x18, 0xe3, 0x3, 0xd5 } + +#define EFI_WATCHDOG_TIMER_DEFINITION_HOB_GUID \ + { 0xd29302b0, 0x11ba, 0x4073, 0xa2, 0x27, 0x53, 0x8d, 0x25, 0x42, 0x70, 0x9f } + +typedef enum { + HWWD_NONE, + HWWD_TIMER_EXPIRED, + HWWD_SPONTANEOUS_REBOOT, + HWWD_FORCED_TIMEOUT +} HW_WATCHDOG_TIMEOUT; + +typedef struct { + HW_WATCHDOG_TIMEOUT TimeoutStatus; +} HW_WATCHDOG_INFO; + +// +// Watchdog timer action values. +// +#define WDT_ACTION_RESET 0x01 // reload/reset timer +#define WDT_ACTION_QUERY_CURRENT_VALUE 0x04 // get current value // DON'T NEED FOR OVERCLOCK UTILITY +#define WDT_ACTION_QUERY_COUNTDOWN_PERIOD 0x05 // get countdown period +#define WDT_ACTION_SET_COUNTDOWN_PERIOD 0x06 // set countdown period +#define WDT_ACTION_QUERY_RUNNING_STATE 0x08 // query if running +#define WDT_ACTION_SET_RUNNING_STATE 0x09 // start timer +#define WDT_ACTION_QUERY_STOPPED_STATE 0x0A // query if stopped +#define WDT_ACTION_SET_STOPPED_STATE 0x0B // stop timer +#define WDT_ACTION_QUERY_STATUS 0x20 // is current boot cause by wdt timeout? +#define WDT_ACTION_SET_STATUS 0x21 // resets wdt status bit + +// +// Watchdog timer instruction values. +// +#define WDT_INSTR_VALUE_MASK 0x03 // Mask for just the value +#define WDT_INSTR_READ_CMP_VALUE 0x00 // Read / compare value +#define WDT_INSTR_READ_COUNTDOWN 0x01 // read countdown value +#define WDT_INSTR_WRITE_VALUE 0x02 // Write value +#define WDT_INSTR_WRITE_COUNTDOWN 0x03 // write countdown value +#define WDT_INSTR_PRESERVE_REG 0x80 // preserve reg; used in Write Value / Write Countdown +#define WDT_INSTR_WRITE_VALUE_PRES (0x02 | WDT_INSTR_PRESERVE_REG) // Write value with preserve +#define WDT_INSTR_WRITE_COUNTDOWN_PRES (0x03 | WDT_INSTR_PRESERVE_REG) // write countdown value with preserve + +// +// The Generic Address Structure is defined in the ACPI Specification and should only be +// changed to match updated revisions of that specification. The GAS_ADDRESS_SPACE and +// GAS_ACCESS_SIZE enumerations are also defined by the ACPI Specification. +// +typedef enum { + GAS_SYSTEM_MEMORY, + GAS_SYSTEM_IO, + GAS_PCI_CONFIG_SPACE, + GAS_EMBEDDED_CONTROLLER, + GAS_SMBUS +} GAS_ADDRESS_SPACE; + +typedef enum { + GAS_UNDEFINED, + GAS_BYTE_ACCESS, + GAS_WORD_ACCESS, + GAS_DWORD_ACCESS, + GAS_QWORD_ACCESS +} GAS_ACCESS_SIZE; + +#pragma pack(1) + +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} GENERIC_ADDRESS_STRUCTURE; + +// +// GAS_SYSTEM_MEMORY - When used as the AddressSpaceId, the 64-bit physical memory address +// of the register. 32-bit platforms must have the high DWORD set to 0. +// GAS_SYSTEM_IO - The 64-bit I/O address of the register. 32-bit platforms must have +// the high DWORD set to 0. +// GAS_PCI_CONFIG_SPACE - PCI Configuration space addresses must be confined to devices on PCI +// Sepment Group 0, Bus 0. This restriction exists to accommodate access +// to fixed hardware prior to PCI bus enumeration. The format of addresses +// are defined as follows: +// Highest WORD: Reserved and must be -0- +// ... PCI Device number on bus 0 +// ... PCI Function number +// Lowest WORD: Offset in the configuration space header. +// + +typedef struct { + UINT8 WdAction; + UINT8 Flag; + UINT16 Res; + GENERIC_ADDRESS_STRUCTURE GenericAddressStructures; + UINT32 Value; + UINT32 Mask; +} WD_INSTRUCTION; + +typedef struct { + UINT32 TimerPeriod; + UINT32 MaxTimerCount; + UINT32 MinTimerCount; + UINT16 InstructionCount; + WD_INSTRUCTION ActionDefinitions[1]; +} WD_HOB_DEFINITION; + +#pragma pack() + +extern EFI_GUID gWatchdogTimerHobGuid; +extern EFI_GUID gWatchdogTimerDefinitionHobGuid; + +#endif // _EFI_WATCHDOG_TIMER_HOB_GUID_H_ diff --git a/Vlv2TbltDevicePkg/Include/Guid/IdccData.h b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h new file mode 100644 index 0000000000..fa8988b364 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h @@ -0,0 +1,109 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + IdccData.h + +Abstract: + +--*/ + +#ifndef _IDCCDATAHUB_GUID_H_ +#define _IDCCDATAHUB_GUID_H_ + +// +// This GUID is for the IDCC related data found in the Data Hub. +// +#define IDCC_DATA_HUB_GUID \ + { 0x788e1d9f, 0x1eab, 0x47d2, 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 } + +extern EFI_GUID gIdccDataHubGuid; + +#pragma pack(1) + +typedef struct { + UINT32 Type; + UINT32 RecordLength; +} EFI_IDCC_DATA_HEADER; + +typedef struct { + EFI_IDCC_DATA_HEADER IdccHeader; + UINT32 Tcontrol; +} EFI_IDCC_TCONTROL; + +typedef struct { + UINT32 EntryCount; +} EFI_IDCC_CLOCK_COMMON; + +typedef struct { + UINT8 Polarity; + UINT8 Percent; + UINT32 FpValue; +} EFI_IDCC_TYPE_2_DATA; + +typedef struct { + UINT8 SetupVal; + UINT32 FpValue; +} EFI_IDCC_TYPE_3_4_DATA; + +typedef struct { + EFI_IDCC_DATA_HEADER IdccHeader; + UINT32 ProcessorRatio; +} EFI_IDCC_PROCESSOR_RATIO; + +typedef struct { + EFI_IDCC_DATA_HEADER IdccHeader; + UINT32 BoardFormFactor; +} EFI_IDCC_BOARD_FORM_FACTOR; + +typedef struct { + EFI_IDCC_DATA_HEADER IdccHeader; + UINT32 ProcessorInfo; +} EFI_IDCC_PROCESSOR_INFO; + +#define EFI_IDCC_PROCESSOR_UNCON (1 << 0) // Bit 0: UnCon CPU +#define EFI_IDCC_PROCESSOR_UNLOCK (1 << 1) // Bit 1: UnLock CPU +#define EFI_IDCC_PROCESSOR_CNR (1 << 2) // Bit 2: CNR CPU +#define EFI_IDCC_PROCESSOR_KNF (1 << 3) // Bit 3: KNF CPU + +typedef struct { + EFI_IDCC_DATA_HEADER IdccHeader; + UINT32 MinFSB; + UINT32 MaxFSB; + UINT8 StepFSB; +} EFI_IDCC_FSB_DATA; + +#pragma pack() + +#define EFI_IDCC_POSITIVE 0 +#define EFI_IDCC_NEGATIVE 1 + +// +// Board Form Factor equates. +// +#define ATX_FORM_FACTOR 0x00 +#define BTX_FORM_FACTOR 0x01 + + +#define EFI_IDCC_TCONTROL_TYPE 1 +#define EFI_IDCC_FSB_TYPE 2 +#define EFI_IDCC_PCI_TYPE 3 +#define EFI_IDCC_PCIE_TYPE 4 +#define EFI_IDCC_PROC_RATIO_TYPE 5 +#define EFI_IDCC_BOARD_FORM_FACTOR_TYPE 6 +#define EFI_IDCC_PROC_INFO_TYPE 7 +#define EFI_IDCC_FSB_DATA_TYPE 8 + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/ItkData.h b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h new file mode 100644 index 0000000000..3e02fd49cc --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h @@ -0,0 +1,75 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + ItkData.h + +Abstract: + +--*/ + +#ifndef _ITKDATAHUB_GUID_H_ +#define _ITKDATAHUB_GUID_H_ + +// +// This GUID is for the ITK related data found in the Data Hub {E7060843-A336-4d5b-9598-13402F5D7375} +// +#define ITK_DATA_HUB_GUID \ + { 0xe7060843, 0xa336, 0x4d5b, 0x95, 0x98, 0x13, 0x40, 0x2f, 0x5d, 0x73, 0x75 } + +extern EFI_GUID gItkDataHubGuid; + +// +// This GUID is for the ITK related data found in a Variable {3812723D-7E48-4e29-BC27-F5A39AC94EF1} +// +#define ITK_DATA_VAR_GUID \ + { 0x3812723d, 0x7e48, 0x4e29, 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 } + +extern EFI_GUID gItkDataVarGuid; + +#define ITK_DATA_VAR_NAME L"ItkDataVar" + +extern CHAR16 gItkDataVarName[]; + +#define ITK_BIOS_MOD_VAR_NAME L"ItkBiosModVar" + +extern CHAR16 gItkBiosModVarName[]; + +#pragma pack(1) +typedef struct { + UINT32 Type; + UINT32 RecordLength; +} EFI_ITK_DATA_HEADER; + +typedef struct { + EFI_ITK_DATA_HEADER ItkHeader; + UINT32 HecetaAddress; +} EFI_ITK_HECETA_ADDRESS; + +typedef struct { + UINT16 VarEqName; + UINT16 VarEqValue; +} EFI_ITK_VAR_EQ_RECORD; + +typedef struct { + EFI_ITK_DATA_HEADER ItkHeader; + EFI_ITK_VAR_EQ_RECORD VarEqRecord[0x10000]; +} EFI_ITK_VAR_EQ; +#pragma pack() + +#define EFI_ITK_HECETA_ADDRESS_TYPE 1 +#define EFI_ITK_MOBILE_BIOS_TYPE 2 +#define EFI_ITK_VAR_EQ_TYPE 3 + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..6780b3f924 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,37 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + MemoryConfigData.h + +Abstract: + + GUID used for Memory Configuration Data entries in the HOB list. + +--*/ + +#ifndef _MEMORY_CONFIG_DATA_GUID_H_ +#define _MEMORY_CONFIG_DATA_GUID_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \ + } + +extern EFI_GUID gEfiMemoryConfigDataGuid; +extern CHAR16 EfiMemoryConfigVariable[]; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h new file mode 100644 index 0000000000..3e65ae659b --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h @@ -0,0 +1,90 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + OsSelection.h + +Abstract: + + GUID used for LPSS, SCC and LPE configuration data entries in the HOB list. + +--*/ + +#ifndef _OS_SELECTION_GUID_H_ +#define _OS_SELECTION_GUID_H_ + +#ifndef ECP_FLAG +#include + +#include +#include +#include +#endif + +#define ANDROID 1 + +#define EFI_OS_SELECTION_VARIABLE_GUID \ + { \ + 0x86843f56, 0x675d, 0x40a5, 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 \ + } + +extern EFI_GUID gOsSelectionVariableGuid; + +#pragma pack(1) + +typedef struct { + UINT8 LpssPciModeEnabled; + //SCC + UINT8 LpsseMMCEnabled; + UINT8 LpssSdioEnabled; + UINT8 LpssSdcardEnabled; + UINT8 LpssSdCardSDR25Enabled; + UINT8 LpssSdCardDDR50Enabled; + UINT8 LpssMipiHsi; + UINT8 LpsseMMC45Enabled; + UINT8 LpsseMMC45DDR50Enabled; + UINT8 LpsseMMC45HS200Enabled; + UINT8 LpsseMMC45RetuneTimerValue; + UINT8 eMMCBootMode; + //LPSS2 + UINT8 LpssDma1Enabled; + UINT8 LpssI2C0Enabled; + UINT8 LpssI2C1Enabled; + UINT8 LpssI2C2Enabled; + UINT8 LpssI2C3Enabled; + UINT8 LpssI2C4Enabled; + UINT8 LpssI2C5Enabled; + UINT8 LpssI2C6Enabled; + //LPSS1 + UINT8 LpssDma0Enabled; + UINT8 LpssPwm0Enabled; + UINT8 LpssPwm1Enabled; + UINT8 LpssHsuart0Enabled; + UINT8 LpssHsuart1Enabled; + UINT8 LpssSpiEnabled; + UINT8 I2CTouchAd; +} EFI_PLATFORM_LPSS_DATA; + +typedef struct _EFI_OS_SELECTION_HOB { + UINT8 OsSelection; + UINT8 OsSelectionChanged; + UINT8 Lpe; + UINT8 PchAzalia; + EFI_PLATFORM_LPSS_DATA LpssData; +} EFI_OS_SELECTION_HOB; + +#pragma pack() + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h new file mode 100644 index 0000000000..775f71081c --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h @@ -0,0 +1,44 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PciLanInfo.h + +Abstract: + +--*/ + +#ifndef _PCI_LAN_INFO_GUID_H_ +#define _PCI_LAN_INFO_GUID_H_ + +#pragma pack(1) + +// +// structure used for Pci Lan variable +// +typedef struct { + UINT8 PciBus; + UINT8 PciDevice; + UINT8 PciFunction; +} PCI_LAN_INFO; + +#pragma pack() + +#define EFI_PCI_LAN_INFO_GUID \ + {0xd9a1427, 0xe02a, 0x437d, 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba}; + +extern EFI_GUID gEfiPciLanInfoGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h new file mode 100644 index 0000000000..ec9db67199 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h @@ -0,0 +1,185 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformCpuInfo.h + +Abstract: + + GUID used for Platform CPU Info Data entries in the HOB list. + +--*/ + +#ifndef _PLATFORM_CPU_INFO_GUID_H_ +#define _PLATFORM_CPU_INFO_GUID_H_ + +#include "CpuType.h" +#include + +#define EFI_PLATFORM_CPU_INFO_GUID \ + {\ + 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \ + } + +extern EFI_GUID gEfiPlatformCpuInfoGuid; +extern CHAR16 EfiPlatformCpuInfoVariable[]; + +// +// Tri-state for feature capabilities and enable/disable. +// [0] clear=feature isn't capable +// [0] set =feature is capable +// [1] clear=feature is disabled +// [1] set =feature is enabled +// +#define CPU_FEATURES_CAPABLE BIT0 +#define CPU_FEATURES_ENABLE BIT1 + +#define MAX_CACHE_DESCRIPTORS 64 +#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48 + +#pragma pack(1) + +typedef struct { + UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF + UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0 + UINT8 ExtendedFamilyId; // [27:20] + UINT8 ExtendedModelId; // [19:16] + UINT8 ProcessorType; // [13:11] + UINT8 FamilyId; // [11:8] + UINT8 Model; // [7:4] + UINT8 SteppingId; // [3:0] +} EFI_CPU_VERSION_INFO; // CPUID.1.EAX + +typedef struct { + UINT32 L1InstructionCacheSize; + UINT32 L1DataCacheSize; + UINT32 L2CacheSize; + UINT32 L3CacheSize; + UINT32 TraceCacheSize; + UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS]; +} EFI_CPU_CACHE_INFO; // CPUID.2.EAX + +typedef struct { + UINT8 PhysicalPackages; + UINT8 LogicalProcessorsPerPhysicalPackage; + UINT8 CoresPerPhysicalPackage; + UINT8 ThreadsPerCore; +} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX + +typedef struct { + UINT32 RegEdx; // CPUID.5.EAX + UINT8 MaxCState; + UINT8 C0SubCStatesMwait; // EDX [3:0] + UINT8 C1SubCStatesMwait; // EDX [7:4] + UINT8 C2SubCStatesMwait; // EDX [11:8] + UINT8 C3SubCStatesMwait; // EDX [15:12] + UINT8 C4SubCStatesMwait; // EDX [19:16] + UINT8 C5SubCStatesMwait; // EDX [23:20] + UINT8 C6SubCStatesMwait; // EDX [27:24] + UINT8 C7SubCStatesMwait; // EDX [31:28] + UINT8 MonitorMwaitSupport; // ECX [0] + UINT8 InterruptsBreakMwait; // ECX [1] +} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX + +typedef struct { + UINT8 Turbo; // EAX [1] + UINT8 PECI; // EAX [0] + UINT8 NumIntThresholds; // EBX [3:0] + UINT8 HwCoordinationFeedback; // ECX [0] +} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX + +// +// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable. +// - Keep the respective feature entry variable as default value (0x00) +// if the CPU is not capable for the feature. +// - Use the specially defined programming convention to update the variable +// to indicate capable, enable or disable. +// ie. F_CAPABLE for feature available +// F_ENABLE for feature enable +// F_DISABLE for feature disable +// +typedef struct { + EFI_CPUID_REGISTER Regs; // CPUID.1.EAX + UINT8 Xapic; // ECX [21] + UINT8 SSE4_2; // ECX [20] + UINT8 SSE4_1; // ECX [19] + UINT8 Dca; // ECX [18] + UINT8 SupSSE3; // ECX [9] + UINT8 Tm2; // ECX [8] + UINT8 Eist; // ECX [7] + UINT8 Lt; // ECX [6] + UINT8 Vt; // ECX [5] + UINT8 Mwait; // ECX [3] + UINT8 SSE3; // ECX [0] + UINT8 Tcc; // EDX [29] + UINT8 Mt; // EDX [28] + UINT8 SSE2; // EDX [26] + UINT8 SSE; // EDX [25] + UINT8 MMX; // EDX [23] + EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX + UINT8 ExtLahfSahf64; // ECX [0] + UINT8 ExtIntel64; // EDX [29] + UINT8 ExtXd; // EDX [20] + UINT8 ExtSysCallRet64; // EDX [11] + UINT16 Ht; // CPUID.0B.EAX EBX [15:0] +} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX + +typedef struct { + UINT8 PhysicalBits; + UINT8 VirtualBits; +} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX + +typedef struct { + UINT8 PlatformID; // MSR 0x17 [52:50] + UINT32 MicrocodeRevision; // MSR 0x8B [63:32] + UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40] + UINT8 DdrRatioUnlockCap; // MSR 0xCE [30] + UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29] + UINT8 RatioLimitsTurbo; // MSR 0xCE [28] + UINT8 PreProduction; // MSR 0xCE [27] + UINT8 DcuModeSelect; // MSR 0xCE [26] + UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8] + UINT8 Emrr; // MSR 0xFE [12] + UINT8 Smrr; // MSR 0xFE [11] + UINT8 VariableMtrrCount; // MSR 0xFE [7:0] + UINT16 PState; // MSR 0x198 [15:0] + UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16] + UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8] + UINT32 PCIeBar; // MSR 0x300 [39:20] + UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1] +} EFI_MSR_FEATURES; + +typedef struct { + BOOLEAN IsIntelProcessor; + UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1]; + UINT32 CpuidMaxInputValue; + UINT32 CpuidMaxExtInputValue; + EFI_CPU_UARCH CpuUarch; + EFI_CPU_FAMILY CpuFamily; + EFI_CPU_PLATFORM CpuPlatform; + EFI_CPU_TYPE CpuType; + EFI_CPU_VERSION_INFO CpuVersion; + EFI_CPU_CACHE_INFO CpuCache; + EFI_CPU_FEATURES CpuFeatures; + EFI_CPU_CSTATE_INFO CpuCState; + EFI_CPU_PACKAGE_INFO CpuPackage; + EFI_CPU_POWER_MANAGEMENT CpuPowerManagement; + EFI_CPU_ADDRESS_BITS CpuAddress; + EFI_MSR_FEATURES Msr; +} EFI_PLATFORM_CPU_INFO; + +#pragma pack() + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h new file mode 100644 index 0000000000..0a73f0d748 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h @@ -0,0 +1,437 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + PlatformInfo.h + +Abstract: + + GUID used for Platform Info Data entries in the HOB list. + +--*/ + +#ifndef _PLATFORM_INFO_GUID_H_ +#define _PLATFORM_INFO_GUID_H_ + +#ifndef ECP_FLAG +#include + +#include +#include +#include +#include +#include +#endif + +#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct. + +// +// Start::BayLake Board Defines +// +#define BOARD_REVISION_DEFAULT = 0xff +#define UNKNOWN_FABID 0x0F +#define FAB_ID_MASK 0x0F +#define BOARD_ID_2 0x01 +#define BOARD_ID_1 0x40 +#define BOARD_ID_0 0x04 + +#define BOARD_ID_DT_CRB 0x0 +#define BOARD_ID_DT_VLVR 0x1 +#define BOARD_ID_SVP_VLV 0xC +#define BOARD_ID_SVP_EV_VLV 0xD +// +// End::BayLake Board Defines +// + +// +// Start::Alpine Valley Board Defines +// +#define DC_ID_DDR3L 0x00 +#define DC_ID_DDR3 0x04 +#define DC_ID_LPDDR3 0x02 +#define DC_ID_LPDDR2 0x06 +#define DC_ID_DDR4 0x01 +#define DC_ID_DDR3L_ECC 0x05 +#define DC_ID_NO_MEM 0x07 +// +// End::Alpine Valley Board Defines +// + +#define MAX_FAB_ID_RETRY_COUNT 100 +#define MAX_FAB_ID_CHECK_COUNT 3 + +#define PLATFORM_INFO_HOB_REVISION 0x1 + +#define EFI_PLATFORM_INFO_GUID \ + { \ + 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \ + } + +extern EFI_GUID gEfiPlatformInfoGuid; + +typedef enum { + FlavorUnknown = 0, + + // + // Mobile + // + FlavorMobile = 1, + + // + // Desktop + // + FlavorDesktop = 2, + + // + // Tablet + // + FlavorTablet = 3 +} PLATFORM_FLAVOR; + +#pragma pack(1) + +typedef struct { + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT8 PciHostAddressWidth; + UINT8 PciResourceMinSecBus; +} EFI_PLATFORM_PCI_DATA; + +typedef struct { + UINT8 CpuAddressWidth; + UINT32 CpuFamilyStepping; +} EFI_PLATFORM_CPU_DATA; + +typedef struct { + UINT8 SysIoApicEnable; + UINT8 SysSioExist; +} EFI_PLATFORM_SYS_DATA; + +typedef struct { + UINT32 MemTolm; + UINT32 MemMaxTolm; + UINT32 MemTsegSize; + UINT32 MemTsegBase; + UINT32 MemIedSize; + UINT32 MemIgdSize; + UINT32 MemIgdBase; + UINT32 MemIgdGttSize; + UINT32 MemIgdGttBase; + UINT64 MemMir0; + UINT64 MemMir1; + UINT32 MemConfigSize; + UINT16 MmioSize; + UINT8 DdrFreq; + UINT8 DdrType; + UINT32 MemSize; + BOOLEAN EccSupport; + UINT8 Reserved[3]; + UINT16 DimmSize[2]; +} EFI_PLATFORM_MEM_DATA; + + +typedef struct { + UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address + UINT8 IgdBootType; // IGD Boot Display Device + UINT8 IgdPanelType; // IGD Panel Type CMOs option + UINT8 IgdTvFormat; // IGD TV Format CMOS option + UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option + UINT8 IgdPanelScaling; // IGD Panel Scaling + UINT8 IgdBlcConfig; // IGD BLC Configuration + UINT8 IgdBiaConfig; // IGD BIA Configuration + UINT8 IgdSscConfig; // IGD SSC Configuration + UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size + UINT8 IgdFunc1Enable; // IGD Function 1 Enable + UINT8 IgdHpllVco; // HPLL VCO + UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI) + UINT8 IgdPAVP; // IGD PAVP data +} EFI_PLATFORM_IGD_DATA; + +typedef enum { + BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board + BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP) + BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011 + BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD) + BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L) + BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board + BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board + BOARD_ID_BS_RVP = 0x30, // Bakersport Board + BOARD_ID_CVH = 0x90, // Crestview Hills + BOARD_ID_MINNOW2 = 0xA0 // Minnow2 + +} BOARD_ID_LIST; + +typedef enum { + FAB1 = 0, + FAB2 = 1, + FAB3 = 2 +} FAB_ID_LIST; + +typedef enum { + PR0 = 0, // FFRD PR0 + PR05 = 1, // FFRD PR0.3 and PR 0.5 + PR1 = 2, // FFRD PR1 + PR11 = 3 // FFRD PR1.1 +} FFRD_ID_LIST; + + +// +// VLV2 GPIO GROUP OFFSET +// +#define GPIO_SCORE_OFFSET 0x0000 +#define GPIO_NCORE_OFFSET 0x1000 +#define GPIO_SSUS_OFFSET 0x2000 + +// +// GPIO Initialization Data Structure for BayLake. +// SC = SCORE, SS= SSUS +// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode. +// + +// +// IO space +// +typedef struct{ + UINT32 Use_Sel_SC0; + UINT32 Use_Sel_SC1; + UINT32 Use_Sel_SC2; + UINT32 Use_Sel_SS; + + UINT32 Io_Sel_SC0; + UINT32 Io_Sel_SC1; + UINT32 Io_Sel_SC2; + UINT32 Io_Sel_SS; + + UINT32 GP_Lvl_SC0; + UINT32 GP_Lvl_SC1; + UINT32 GP_Lvl_SC2; + UINT32 GP_Lvl_SS; + + UINT32 TPE_SC0; + UINT32 TPE_SS; + + UINT32 TNE_SC0; + UINT32 TNE_SS; + + UINT32 TS_SC0; + UINT32 TS_SS; + + UINT32 WE_SS; +} CFIO_INIT_STRUCT; + + + +// +// CFIO PAD configuration Registers +// +// +// Memory space +// +typedef union { + UINT32 dw; + struct { + UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection + UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width + UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate + UINT32 Pull_assign:2; // 7:8 Pull assignment + UINT32 Pull_strength:2; // 9:10 Pull strength + UINT32 Bypass_flop:1; // 11 Bypass flop + UINT32 Filter_en:1; // 12 Filter Enable + UINT32 Hist_ctrl:2; // 13:14 hysteresis control + UINT32 Hist_enb:1; // 15 Hysteresis enable, active low + UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output + UINT32 Reserved:3; // 22:24 Reserved + UINT32 TPE:1; // 25 Trigger Positive Edge Enable + UINT32 TNE:1; // 26 Trigger Negative Edge Enable + UINT32 Reserved2:3; // 27:29 Reserved + UINT32 i1p5sel:1; // 30 + UINT32 IODEN:1; // 31 : Open Drain enable. Active high + } r; +} PAD_CONF0; + +typedef union{ + UINT32 dw; + struct { + UINT32 instr:16; // 0:15 Pad (N) strength. + UINT32 ipstr:16; // 16:31 Pad (P) strength. + }r; +} PAD_CONF1; + +typedef union{ + UINT32 dw; + struct { + UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each. + UINT32 ioutenb:1; // 1 output enable + UINT32 iinenb:1; // 2 input enable + UINT32 Reserved:29; // 3:31 Reserved + }r; +} PAD_VAL; + +typedef union{ + UINT32 GPI; + struct { + UINT32 ihbpen:1; // 0 Pad high by pass enable + UINT32 ihbpinen:1; // 1 Pad high by pass input + UINT32 instaticen:1; // 2 TBD + UINT32 ipstaticen:1; // 3 TBD + UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists. + UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used. + UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing + }r; +} PAD_DFT; + +// +// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits. +// +typedef enum { + Native = 0xFF, // Native, no need to set PAD_VALUE + GPI = 2, // GPI, input only in PAD_VALUE + GPO = 4, // GPO, output only in PAD_VALUE + GPIO = 0, // GPIO, input & output + TRISTS = 6, // Tri-State + GPIO_NONE +} GPIO_USAGE; + +typedef enum { + LO = 0, + HI = 1, + NA = 0xFF +} GPO_D4; + +typedef enum { + F0 = 0, + F1 = 1, + F2 = 2, + F3 = 3, + F4 = 4, + F5 = 5, + F6 = 6, + F7 = 7 +} GPIO_FUNC_NUM; + +// +// Mapping to CONF0 bit 27:24 +// Note: Assume "Direct Irq En" is not set, unless specially notified. +// +typedef enum { + TRIG_ = 0, + TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing) + TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling) + TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge + TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High + TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low +} INT_TYPE; + +typedef enum { + P_20K_H, // Pull Up 20K + P_20K_L, // Pull Down 20K + P_10K_H, // Pull Up 10K + P_10K_L, // Pull Down 10K + P_2K_H, // Pull Up 2K + P_2K_L, // Pull Down 2K + P_NONE // Pull None +} PULL_TYPE; + +#ifdef EFI_DEBUG + #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset} +#else + #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset} +#endif + +// +// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits. +// NC = NCORE, SC = SCORE, SS= SSUS +// +typedef struct { + +#ifdef EFI_DEBUG + char pad_name[32];// GPIO Pin Name for debug purpose +#endif + + GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode + GPO_D4 gpod4; // GPO default value + GPIO_FUNC_NUM func; // Function Number (F0~F7) + INT_TYPE int_type; // Edge or Level trigger, low or high active + PULL_TYPE pull; // Pull Up or Down + UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits) +} GPIO_CONF_PAD_INIT; + +// +//typedef UINT64 BOARD_FEATURES +// +typedef struct _EFI_PLATFORM_INFO_HOB { + UINT16 PlatformType; // Platform Type + UINT8 BoardId; // Board ID + UINT8 BoardRev; // Board Revision + PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor + UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id + UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id + UINT8 ECOId; // ECO applied on platform + UINT16 IohSku; + UINT8 IohRevision; + UINT16 IchSku; + UINT8 IchRevision; + EFI_PLATFORM_PCI_DATA PciData; + EFI_PLATFORM_CPU_DATA CpuData; + EFI_PLATFORM_MEM_DATA MemData; + EFI_PLATFORM_SYS_DATA SysData; + EFI_PLATFORM_IGD_DATA IgdData; + UINT8 RevisonId; // Structure Revision ID + EFI_PHYSICAL_ADDRESS PlatformCfioData; + EFI_PHYSICAL_ADDRESS PlatformGpioData_NC; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS; + EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1; + EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1; + + UINT8 CfioEnabled; + UINT32 SsidSvid; + UINT16 AudioSubsystemDeviceId; + UINT64 AcpiOemId; + UINT64 AcpiOemTableId; + UINT16 MemCfgID; +} EFI_PLATFORM_INFO_HOB; + +#pragma pack() + +EFI_STATUS +GetPlatformInfoHob ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob + ); + + +EFI_STATUS +InstallPlatformClocksNotify ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +InstallPlatformSysCtrlGPIONotify ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h new file mode 100644 index 0000000000..b058e3ceb5 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h @@ -0,0 +1,284 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + SensorInfoVariable.h + +Abstract: + + GUID used for Sensor Info variable. + +--*/ + + +// +// Module: SensorInfoVariable.h +// +// Description: Provides structure and literal definitions for the +// Sensor Information Variable. The BIOS will provide +// this variable to runtime applications via the EFI +// GetVariable function. +// +// Notes: 1. When defining and initializing the variable within the +// BIOS, the module will define the structure using the +// typedef macros in a block. For an ATX board using a +// single Heceta 6P, which has 4 temperature sensors, 6 +// voltage sensors, 4 fan speed sensors and 3 fan speed +// controllers, this block would be declared as follows: +// +// TYPEDEF_TEMP_SENSOR_SECTION(4); +// TYPEDEF_VOLT_SENSOR_SECTION(6); +// TYPEDEF_FAN_SENSOR_SECTION(4); +// TYPEDEF_FAN_CONTROLLER_SENSOR(3); +// TYPEDEF_SENSOR_INFO_VAR; +// +// 2. When crafting code to access the variable, the module +// will also need to invoke the typedef macros in a +// block but, since it cannot declare a structure for the +// overall variable (because array lengths will vary), it +// cannot use TYPEDEF_SENSOR_INFO_VAR. The block will +// typically be used as follows: +// +// TYPEDEF_TEMP_SENSOR_SECTION(1); +// TYPEDEF_VOLT_SENSOR_SECTION(1); +// TYPEDEF_FAN_SENSOR_SECTION(1); +// TYPEDEF_FAN_CONTROLLER_SENSOR(1); +// +// The structure buffer should instead be declared as a +// BYTE array. Pointers to the various sections can then +// be built using the XXXX_SECTION_LEN macros... +// + + +#ifndef _SENSOR_INFO_VAR_GUID_H_ +#define _SENSOR_INFO_VAR_GUID_H_ + +#define SENSOR_INFO_VAR_GUID \ + { \ + 0xE59E7B4D, 0x06DC, 0x44AB, 0xB3, 0x6D, 0x5E, 0xD7, 0x78, 0x9C, 0x53, 0x0A \ + } + +extern EFI_GUID gEfiSensorInfoVarGuid; +extern CHAR16 gEfiSensorInfoVarName[]; +extern CHAR16 gEfiSensorInfoVarNameWithPassword[]; + +#define SENSOR_INFO_VAR_NAME L"SensorInfoVar" +#define SENSOR_INFO_VAR_NAME_WITH_PASSWORD SENSOR_INFO_VAR_NAME L"S4k?A^7!" + +// +// Sensor/Controller usage definitions +// + +#define UNKNOWN_OTHER 0 + +// +// Temperature Sensors +// +#define CPU_CORE_TEMPERATURE 1 +#define CPU_DIE_TEMPERATURE 2 +#define ICH_TEMPERATURE 3 +#define MCH_TEMPERATURE 4 +#define VR_TEMPERATURE 5 +#define MEMORY_TEMPERATURE 6 +#define MOTHERBOARD_AMBIENT_TEMPERATURE 7 +#define SYSTEM_AMBIENT_AIR_TEMPERATURE 8 +#define CPU_INLET_AIR_TEMPERATURE 9 +#define SYSTEM_INLET_AIR_TEMPERATURE 10 +#define SYSTEM_OUTLET_AIR_TEMPERATURE 11 +#define PSU_HOTSPOT_TEMPERATURE 12 +#define PSU_INLET_AIR_TEMPERATURE 13 +#define PSU_OUTLET_AIR_TEMPERATURE 14 +#define DRIVE_TEMPERATURE 15 +#define GPU_TEMPERATURE 16 +#define IOH_TEMPERATURE 17 + +#define LAST_TEMPERATURE 17 + +// +// Voltage Sensors +// +#define PLUS_12_VOLTS 1 +#define NEG_12_VOLTS 2 +#define PLUS_5_VOLTS 3 +#define PLUS_5_VOLT_BACKUP 4 +#define NEG_5_VOLTS 5 +#define PLUS_3P3_VOLTS 6 +#define PLUS_2P5_VOLTS 7 +#define PLUS_1P5_VOLTS 8 +#define CPU_1_VCCP_VOLTAGE 9 +#define CPU_2_VCCP_VOLTAGE 10 +#define CPU_3_VCCP_VOLTAGE 11 +#define CPU_4_VCCP_VOLTAGE 12 +#define PSU_INPUT_VOLTAGE 13 +#define MCH_VCC_VOLTAGE 14 +#define PLUS_3P3_VOLT_STANDBY 15 +#define CPU_VTT_VOLTAGE 16 +#define PLUS_1P8_VOLTS 17 + +#define LAST_VOLTAGE 17 + +// +// Fan Speed Sensors and Controllers. +// +#define CPU_COOLING_FAN 1 +#define SYSTEM_COOLING_FAN 2 +#define MCH_COOLING_FAN 3 +#define VR_COOLING_FAN 4 +#define CHASSIS_COOLING_FAN 5 +#define CHASSIS_INLET_FAN 6 +#define CHASSIS_OUTLET_FAN 7 +#define PSU_COOLING_FAN 8 +#define PSU_INLET_FAN 9 +#define PSU_OUTLET_FAN 10 +#define DRIVE_COOLING_FAN 11 +#define GPU_COOLING_FAN 12 +#define AUX_COOLING_FAN 13 +#define IOH_COOLING_FAN 14 + +#define LAST_FAN 14 + +// +// Fan Type Definitions +// +#define FAN_TYPE_UNKNOWN 0 +#define FAN_3WIRE_PULSE 1 +#define FAN_3WIRE_VOLTAGE 2 +#define FAN_4WIRE 3 + +#pragma pack(1) + +// +// TEMP_SENSOR_INFO - Structure providing info for a temperature sensor. +// +typedef struct _TEMP_SENSOR_INFO +{ + UINT8 byDevice; // Device index + UINT8 byIndex; // Physical sensor index + UINT8 byUsage; // Usage indicator + UINT8 bRelative; // Relative vs. Absolute readings + +} TEMP_SENSOR_INFO, *P_TEMP_SENSOR_INFO; + +// +// TYPEDEF_TEMP_SENSOR_SECTION - Macro that can be used to typedef the +// TEMP_SENSOR_SECTION structure, which provides information about all +// temperature sensors. +// +#define TYPEDEF_TEMP_SENSOR_SECTION(count) \ +typedef struct _TEMP_SENSOR_SECTION \ +{ \ + UINT8 byCount; \ + TEMP_SENSOR_INFO stSensor[count]; \ + \ +} TEMP_SENSOR_SECTION, *P_TEMP_SENSOR_SECTION + +// +// VOLT_SENSOR_INFO - Structure providing info for a voltage sensor. +// +typedef struct _VOLT_SENSOR_INFO +{ + UINT8 byDevice; // Device index + UINT8 byIndex; // Physical sensor index + UINT8 byUsage; // Usage indicator + +} VOLT_SENSOR_INFO, *P_VOLT_SENSOR_INFO; + +// +// TYPEDEF_VOLT_SENSOR_SECTION - Macro that can be used to typedef the +// VOLT_SENSOR_SECTION structure, which provides information about all +// voltage sensors. +// +#define TYPEDEF_VOLT_SENSOR_SECTION(count) \ +typedef struct _VOLT_SENSOR_SECTION \ +{ \ + UINT8 byCount; \ + VOLT_SENSOR_INFO stSensor[count]; \ + \ +} VOLT_SENSOR_SECTION, *P_VOLT_SENSOR_SECTION + +// +// FAN_SENSOR_INFO - Structure providing info for a fan speed sensor. +// +typedef struct _FAN_SENSOR_INFO +{ + UINT8 byDevice; // Device index + UINT8 byIndex; // Physical sensor index + UINT8 byUsage; // Usage indicator + UINT8 byType; // Fan type + UINT8 byController; // Associated Fan Controller + +} FAN_SENSOR_INFO, *P_FAN_SENSOR_INFO; + +// +// TYPEDEF_FAN_SENSOR_SECTION - Macro that can be used to typedef the +// FAN_SENSOR_SECTION structure, which provides information about all fan +// speed sensors. +// +#define TYPEDEF_FAN_SENSOR_SECTION(count) \ +typedef struct _FAN_SENSOR_SECTION \ +{ \ + UINT8 byCount; \ + FAN_SENSOR_INFO stSensor[count]; \ + \ +} FAN_SENSOR_SECTION, *P_FAN_SENSOR_SECTION + +// +// FAN_CONTROLLER_INFO - Structure providing info for a fan speed controller. +// +#define MAX_ASSOC_FANS 4 +#define ASSOC_UNUSED 0xFF + +typedef struct _FAN_CONTROLLER_INFO +{ + UINT8 byDevice; // Device index + UINT8 byIndex; // Physical Controller Index + UINT8 byUsage; // Usage Indicator + UINT8 byFan[MAX_ASSOC_FANS]; // Associated Fan Sensors + +} FAN_CONTROLLER_INFO, *P_FAN_CONTROLLER_INFO; + +// +// TYPEDEF_FAN_CONTROLLER_SECTION - Macro that can be used to typedef the +// FAN_CONTROLLER_SECTION structure, which provides information about all +// fan speed controllers. +// +#define TYPEDEF_FAN_CONTROLLER_SECTION(count) \ +typedef struct _FAN_CONTROLLER_SECTION \ +{ \ + UINT8 byCount; \ + FAN_CONTROLLER_INFO stController[count]; \ + \ +} FAN_CONTROLLER_SECTION, *P_FAN_CONTROLLER_SECTION + +// +// TYPEDEF_SENSOR_INFO_VAR - Macro that can be used to typedef the +// SENSOR_INFO_VAR structure, which provides information about all sensors +// and fan speed controllers. The other TYPEDEF macros must be invoked +// before using this one... +// +#define TYPEDEF_SENSOR_INFO_VAR \ +typedef struct _SENSOR_INFO_VAR \ +{ \ + TEMP_SENSOR_SECTION stTemps; \ + VOLT_SENSOR_SECTION stVolts; \ + FAN_SENSOR_SECTION stFans; \ + FAN_CONTROLLER_SECTION stCtrls; \ + \ +} SENSOR_INFO_VAR, *P_SENSOR_INFO_VAR + +#pragma pack() + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..eb0a1760b0 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h @@ -0,0 +1,1351 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + + This program and the accompanying materials are licensed and made available under + + the terms and conditions of the BSD License that accompanies this distribution. + + The full text of the license may be found at + + http://opensource.org/licenses/bsd-license.php. + + + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + SetupVariable.h + +Abstract: + + Driver configuration include file + + +--*/ + +#ifndef _SETUP_VARIABLE_H +#define _SETUP_VARIABLE_H + +// +// --------------------------------------------------------------------------- +// +// Driver Configuration +// +// --------------------------------------------------------------------------- +// + +// +// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9} +// +#define SYSTEM_CONFIGURATION_GUID\ + { \ + 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 \ + } + +#define ROOT_SECURITY_GUID\ + { \ + 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 \ + } + +// +// {6936B3BD-4350-46d9-8940-1FA20961AEB1} +// +#define SYSTEM_ROOT_MAIN_GUID\ + { \ + 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 \ + } + +// +// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C} +// +#define ADDITIONAL_SYSTEM_INFO_GUID\ + { \ + 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c \ + } + +#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 } + +// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0} +#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead, 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 } + +#define PASSWORD_MAX_SIZE 20 + +#define MAX_CUSTOM_VID_TABLE_STATES 6 +// +// Overclocking Source Defines +// +#define OVERCLOCK_SOURCE_BIOS 0 +#define OVERCLOCK_SOURCE_OS 1 + +#define PCH_PCIE_MAX_ROOT_PORTS 4 + +#pragma pack(1) + +// NOTE: When you add anything to this structure, +// you MUST add it to the very bottom!!!! +// You must make sure the structure size is able to divide by 32! +typedef struct { + + // + // Floppy + // + UINT8 Floppy; + UINT8 FloppyLockHide; + + UINT8 FloppyWriteProtect; + UINT8 FloppyWriteProtectLockHide; + + // + // System ports + // + UINT8 Serial; + UINT8 SerialLockHide; + + UINT8 Serial2; + UINT8 Serial2LockHide; + + UINT8 Parallel; + UINT8 ParallelLockHide; + + UINT8 ParallelMode; + UINT8 ParallelModeLockHide; + + UINT8 AllUsb; + UINT8 UsbPortsLockHide; + + UINT8 Usb2; + UINT8 Usb2LockHide; + + UINT8 UsbLegacy; + UINT8 UsbLegacyLockHide; + + UINT8 Audio; + UINT8 AudioLockHide; + + UINT8 Lan; + UINT8 LanLockHide; + + // + // Keyboard + // + UINT8 Numlock; + UINT8 NumlockLockHide; + + // + // ECIR + // + UINT8 ECIR; + UINT8 ECIRLockHide; + + // + // Power State + // + UINT8 PowerState; + UINT8 PowerStateLockHide; + + // + // Wake on RTC variables + // + UINT8 WakeOnRtcS5; + UINT8 WakeOnRtcS5LockHide; + UINT8 RTCWakeupDate; + UINT8 RTCWakeupDateLockHide; + UINT8 RTCWakeupTimeHour; + UINT8 RTCWakeupHourLockHide; + UINT8 RTCWakeupTimeMinute; + UINT8 RTCWakeupMinuteLockHide; + UINT8 RTCWakeupTimeSecond; + UINT8 RTCWakeupSecondLockHide; + + // + // Wake On Lan + // + UINT8 WakeOnLanS5; + UINT8 WakeOnLanS5LockHide; + + //Spread spectrum + UINT8 SpreadSpectrum; + + // + // Boot Order + // + UINT8 BootOrder[8]; + UINT8 BootOrderLockHide; + + // + // Hard Drive Boot Order + // + UINT8 HardDriveBootOrder[8]; + UINT8 HardDriveBootOrderLockHide; + + // + // CD Drive Boot Order + // + UINT8 CdDriveBootOrder[4]; + UINT8 CdDriveBootOrderLockHide; + + // + // FDD Drive Boot Order + // + UINT8 FddDriveBootOrder[4]; + UINT8 FddDriveBootOrderLockHide; + + // + // Drive Boot Order + // + UINT8 DriveBootOrder[16]; + UINT8 DriveBootOrderLockHide; + + // + // Boot Menu Type + // + UINT8 BootMenuType; + UINT8 BootMenuTypeLockHide; + + // + // Boot from Removable Devices + // + UINT8 BootFloppy; + UINT8 BootFloppyLockHide; + + // + // Boot from Optical Devices + // + UINT8 BootCd; + UINT8 BootCdLockHide; + + // + // Boot from Network + // + UINT8 BootNetwork; + UINT8 BootNetworkLockHide; + + // + // Boot USB + // + UINT8 BootUsb; + UINT8 BootUsbLockHide; + + // + // USB Zip Emulation Type + // + UINT8 UsbZipEmulation; + UINT8 UsbZipEmulationLockHide; + + // + // USB Devices Boot First in Boot Order + // + UINT8 UsbDevicesBootFirst; + UINT8 UsbDevicesBootFirstLockHide; + + // + // USB Boot Device SETUP Emulation + // + UINT8 UsbSetupDeviceEmulation; + UINT8 UsbSetupDeviceEmulationLockHide; + + // + // BIOS INT13 Emulation for USB Mass Devices + // + UINT8 UsbBIOSINT13DeviceEmulation; + UINT8 UsbBIOSINT13DeviceEmulationLockHide; + + // + // BIOS INT13 Emulation Size for USB Mass Devices + // + UINT16 UsbBIOSINT13DeviceEmulationSize; + UINT8 UsbBIOSINT13DeviceEmulationSizeLockHide; + + // + // Dummy place holder to prevent VFR compiler problem. + // + UINT16 DummyDataForVfrBug; // Don't change or use. + + // + // Language Select + // + UINT8 LanguageSelect; + + // + // SATA Type (Ide, Ahci, Raid) + // + UINT8 SataType; + UINT8 SataTypeLockHide; + UINT8 SataTestMode; + + // + // Fixed Disk Boot Sector (Fdbs) + // + UINT8 Fdbs; + UINT8 FdbsLockHide; + + // + // DisplaySetupPrompt + // + UINT8 DisplaySetupPrompt; + UINT8 DisplaySetupPromptLockHide; + + // + // ASF + // + UINT8 Asf; + UINT8 AsfLockHide; + + // + // Event Logging + // + UINT8 EventLogging; + UINT8 EventLoggingLockHide; + + // + // Clear Event Log + // + UINT8 ClearEvents; + UINT8 ClearEventsLockHide; + + // + // Expansion Card Text + // + UINT8 ExpansionCardText; + UINT8 ExpansionCardTextLockHide; + + // + // Video Adaptor + // + UINT8 PrimaryVideoAdaptor; + UINT8 PrimaryVideoAdaptorLockHide; + + // + // Chassis intrusion + // + UINT8 IntruderDetection; + UINT8 IntruderDetectionLockHide; + + // + // User Access Level + // + UINT8 UserPasswordLevel; + UINT8 UserPasswordLevelLockHide; + + // + // Maximum FSB Automatic/Disable + // + UINT8 MaxFsb; + UINT8 MaxFsbLockHide; + + // + // Hard Disk Pre-delay + // + UINT8 HddPredelay; + UINT8 HddPredelayLockHide; + + // + // S.M.A.R.T. Mode + // + UINT8 SmartMode; + UINT8 SmartModeLockHide; + + // + // ACPI Suspend State + // + UINT8 AcpiSuspendState; + UINT8 AcpiSuspendStateLockHide; + + // + // PCI Latency Timer + // + UINT8 PciLatency; + UINT8 PciLatencyLockHide; + + // + // Fan Control + // + UINT8 FanControl; + UINT8 FanControlLockHide; + + // + // CPU Fan Control + // + UINT8 CpuFanControl; + UINT8 CpuFanControlLockHide; + + // + // Lowest Fan Speed + // + UINT8 LowestFanSpeed; + UINT8 LowestFanSpeedLockHide; + + // + // Processor (CPU) + // + UINT8 CpuFlavor; + + UINT8 CpuidMaxValue; + UINT8 CpuidMaxValueLockHide; + + UINT8 ExecuteDisableBit; + UINT8 ExecuteDisableBitLockHide; + + // + // EIST or GV3 setup option + // + UINT8 ProcessorEistEnable; + UINT8 ProcessorEistEnableLockHide; + + // + // C1E Enable + // + UINT8 ProcessorC1eEnable; + UINT8 ProcessorC1eEnableLockHide; + + // + // Enabling CPU C-States of processor + // + UINT8 ProcessorCcxEnable; + UINT8 ProcessorCcxEnableLockHide; + + // + // Package C-State Limit + // + UINT8 PackageCState; + UINT8 PackageCStateLockHide; + + // + // Enable/Disable NHM C3(ACPI C2) report to OS + // + UINT8 OSC2Report; + UINT8 OSC2ReportLockHide; + + // + // Enable/Disable NHM C6(ACPI C3) report to OS + // + UINT8 C6Enable; + UINT8 C6EnableLockHide; + + // + // Enable/Disable NHM C7(ACPI C3) report to OS + // + UINT8 C7Enable; + UINT8 C7EnableLockHide; + + // + // EIST/PSD Function select option + // + UINT8 ProcessorEistPsdFunc; + UINT8 ProcessorEistPsdFuncLockHide; + + // + // + // + UINT8 CPU00; + UINT8 CPU01; + + // + // + // + UINT8 CPU02; + UINT8 CPU03; + + // + // + // + UINT8 CPU04; + UINT8 CPU05; + + // + // + // + UINT8 CPU06; + UINT8 CPU07; + + // + // + // + UINT8 CPU08; + UINT8 CPU09; + + // + // + // + UINT8 CPU10; + UINT8 CPU11; + + // + // + // + UINT8 CPU12; + UINT8 CPU13; + + // + // + // + UINT8 CPU14; + UINT8 CPU15; + + // + // + // + UINT8 CPU16; + UINT8 CPU17; + + // + // + // + UINT8 CPU18; + UINT8 CPU19; + + // + // + // + UINT8 CPU20; + UINT8 CPU21; + + // + // + // + UINT8 CPU22; + UINT8 CPU23; + + // + // + // + UINT8 CPU24; + UINT8 CPU25; + + // + // + // + UINT8 CPU26; + UINT8 CPU27; + + // + // + // + UINT8 CPU28; + UINT8 CPU29; + + // + // + // + UINT8 CPU30; + UINT8 CPU31; + + // + // + // + UINT8 CPU32; + UINT8 CPU33; + + // + // + // + UINT8 CPU34; + UINT8 CPU35; + + // + // + // + UINT8 CPU36; + UINT8 CPU37; + + // + // + // + UINT8 CPU38; + UINT8 CPU39; + + // + // + // + UINT16 CPU40; + UINT8 CPU41; + + // + // + // + UINT8 CPU42; + UINT8 CPU43; + + // + // + // + UINT16 CPU44; + UINT8 CPU45; + + // + // + // + UINT8 CPU46; + UINT8 CPU47; + + // + // + // + UINT8 CPU48; + UINT8 CPU49; + + // + // + // + UINT8 CPU50; + UINT8 CPU51; + + // + // + // + UINT8 CPU52; + UINT8 CPU53; + + // + // + // + UINT8 CPU54; + UINT8 CPU55; + + // + // + // + UINT8 CPU56; + UINT8 CPU57; + + // + // + // + UINT8 CPU58; + UINT8 CPU59; + + // + // + // + UINT8 CPU60; + UINT8 CPU61; + + // + // + // + UINT8 CPU62; + UINT8 CPU63; + + // + // + // + UINT8 CPU64; + UINT8 CPU65; + + // + // + // + UINT8 CPU66; + UINT8 CPU67; + + // + // + // + UINT16 CPU68; + UINT8 CPU69; + + // + // + // + UINT16 CPU70; + + // + // + // + UINT8 CPU71; + + // + // + // + UINT8 MEM00; + UINT8 MEM01; + + // + // + // + UINT8 MEM02; + UINT8 MEM03; + + UINT16 MEM04; + UINT8 MEM05; + + UINT8 MEM06; + UINT8 MEM07; + + UINT8 MEM08; + UINT8 MEM09; + + UINT8 MEM10; + UINT8 MEM11; + + UINT8 MEM12; + UINT8 MEM13; + + UINT8 MEM14; + UINT8 MEM15; + + UINT8 MEM16; + UINT8 MEM17; + + UINT16 MEM18; + UINT8 MEM19; + + UINT8 MEM20; + UINT8 MEM21; + + UINT8 MEM22; + UINT8 MEM23; + + UINT8 MEM24; + UINT8 MEM25; + + UINT8 MEM26; + UINT8 MEM27; + + UINT8 MEM28; + UINT8 MEM29; + + UINT8 MEM30; + UINT8 MEM31; + + UINT8 MEM32; + UINT8 MEM33; + + UINT8 MEM34; + UINT8 MEM35; + + // + // + // + UINT8 MEM36; + UINT8 MEM37; + UINT8 MEM38; + UINT8 MEM39; + + // + // + // + UINT8 MEM40; + UINT8 MEM41; + UINT8 MEM42; + UINT8 MEM43; + UINT8 MEM44; + UINT8 MEM45; + UINT8 MEM46; + UINT8 MEM47; + + + // + // Port 80 decode 0/1 - PCI/LPC + UINT8 Port80Route; + UINT8 Port80RouteLockHide; + + // + // ECC Event Logging + // + UINT8 EccEventLogging; + UINT8 EccEventLoggingLockHide; + + // + // TPM Enable/Disable + // + UINT8 ETpm; + + // + // TPM question 0 = Disabled, 1 = Enabled + // + UINT8 ETpmClear; + + // + // Secondary SATA Controller question 0 = Disabled, 1 = Enabled + // + UINT8 ExtSata; + UINT8 ExtSataLockHide; + + // + // Mode selection for Secondary SATA Controller (0=IDE, 1=RAID) + // + UINT8 ExtSataMode; + UINT8 ExtSataModeLockHide; + + // + // LT Technology 0/1 -> Disable/Enable + // + UINT8 LtTechnology; + UINT8 LtTechnologyLockHide; + + // + // HPET Support 0/1 -> Disable/Enable + // + UINT8 Hpet; + UINT8 HpetLockHide; + + // + // ICH Function Level Reset enable/disable + // + UINT8 FlrCapability; + UINT8 FlrCapabilityLockHide; + + // VT-d Option + UINT8 VTdSupport; + UINT8 VTdSupportLockHide; + + UINT8 InterruptRemap; + UINT8 InterruptRemapLockHide; + + UINT8 Isoc; + UINT8 IsocLockHide; + + UINT8 CoherencySupport; + UINT8 CoherencySupportLockHide; + + UINT8 ATS; + UINT8 ATSLockHide; + + UINT8 PassThroughDma; + UINT8 PassThroughDmaLockHide; + + // + // IGD option + // + UINT8 GraphicsDriverMemorySize; + UINT8 GraphicsDriverMemorySizeLockHide; + + + // + // Discrete SATA Type (Ide, Raid, Ahci) + // + UINT8 ExtSataMode2; + UINT8 ExtSataMode2LockHide; + + UINT8 ProcessorReserve00; + UINT8 ProcessorReserve01; + + // + // IGD Aperture Size question + // + UINT8 IgdApertureSize; + UINT8 IgdApertureSizeLockHide; + + // + // Boot Display Device + // + UINT8 BootDisplayDevice; + UINT8 BootDisplayDeviceLockHide; + + + // + // System fan speed duty cycle + // + UINT8 SystemFanDuty; + UINT8 SystemFanDutyLockHide; + + + // + // S3 state LED indicator + // + UINT8 S3StateIndicator; + UINT8 S3StateIndicatorLockHide; + + // + // S1 state LED indicator + // + UINT8 S1StateIndicator; + UINT8 S1StateIndicatorLockHide; + + // + // PS/2 Wake from S5 + // + UINT8 WakeOnS5Keyboard; + UINT8 WakeOnS5KeyboardLockHide; + + + // + // SATA Controller question 0 = Disabled, 1 = Enabled + // + UINT8 Sata; + UINT8 SataLockHide; + + // + // PS2 port + // + UINT8 PS2; + + // + // No VideoBeep + // + UINT8 NoVideoBeepEnable; + + // + // Integrated Graphics Device + // + UINT8 Igd; + + // + // Video Device select order + // + UINT8 VideoSelectOrder[8]; + + // Flash update sleep delay + UINT8 FlashSleepDelay; + UINT8 FlashSleepDelayLockHide; + + // + // Boot Display Device2 + // + UINT8 BootDisplayDevice2; + UINT8 BootDisplayDevice2LockHide; + + // + // Flat Panel + // + UINT8 EdpInterfaceType; + UINT8 EdpInterfaceTypeLockHide; + + UINT8 LvdsInterfaceType; + UINT8 LvdsInterfaceTypeLockHide; + + UINT8 ColorDepth; + UINT8 ColorDepthLockHide; + + UINT8 EdidConfiguration; + UINT8 EdidConfigurationLockHide; + + UINT8 PwmReserved; + UINT8 MaxInverterPWMLockHide; + + UINT8 PreDefinedEdidConfiguration; + UINT8 PreDefinedEdidConfigurationLockHide; + + UINT16 ScreenBrightnessResponseTime; + UINT8 ScreenBrightnessResponseTimeLockHide; + + UINT8 Serial3; + UINT8 Serial3LockHide; + + UINT8 Serial4; + UINT8 Serial4LockHide; + + UINT8 CurrentSetupProfile; + UINT8 CurrentSetupProfileLockHide; + + // + // FSC system Variable + // + UINT8 CPUFanUsage; + UINT8 CPUFanUsageLockHide; + UINT16 CPUUnderSpeedthreshold; + UINT8 CPUUnderSpeedthresholdLockHide; + UINT8 CPUFanControlMode; + UINT8 CPUFanControlModeLockHide; + UINT16 Voltage12UnderVolts; + UINT8 Voltage12UnderVoltsLockHide; + UINT16 Voltage12OverVolts; + UINT8 Voltage12OverVoltsLockHide; + UINT16 Voltage5UnderVolts; + UINT8 Voltage5UnderVoltsLockHide; + UINT16 Voltage5OverVolts; + UINT8 Voltage5OverVoltsLockHide; + UINT16 Voltage3p3UnderVolts; + UINT8 Voltage3p3UnderVoltsLockHide; + UINT16 Voltage3p3OverVolts; + UINT8 Voltage3p3OverVoltsLockHide; + UINT16 Voltage2p5UnderVolts; + UINT8 Voltage2p5UnderVoltsLockHide; + UINT16 Voltage2p5OverVolts; + UINT8 Voltage2p5OverVoltsLockHide; + UINT16 VoltageVccpUnderVolts; + UINT8 VoltageVccpUnderVoltsLockHide; + UINT16 VoltageVccpOverVolts; + UINT8 VoltageVccpOverVoltsLockHide; + UINT16 Voltage5BackupUnderVolts; + UINT8 Voltage5BackupUnderVoltsLockHide; + UINT16 Voltage5BackupOverVolts; + UINT8 Voltage5BackupOverVoltsLockHide; + UINT16 VS3p3StbyUnderVolt; + UINT8 VS3p3StbyUnderVoltLockHide; + UINT16 VS3p3StbyOverVolt; + UINT8 VS3p3StbyOverVoltLockHide; + UINT8 CPUFanMinDutyCycle; + UINT8 CPUFanMinDutyCycleLockHide; + UINT8 CPUFanMaxDutyCycle; + UINT8 CPUFanMaxDutyCycleLockHide; + UINT8 CPUFanOnDutyCycle; + UINT8 CPUFanOnDutyCycleLockHide; + UINT16 CpuOverTemp; + UINT8 CpuOverTempLockHide; + UINT16 CpuControlTemp; + UINT8 CpuControlTempLockHide; + UINT16 CpuAllOnTemp; + UINT8 CpuAllOnTempLockHide; + UINT8 CpuResponsiveness; + UINT8 CpuResponsivenessLockHide; + UINT8 CpuDamping; + UINT8 CpuDampingLockHide; + UINT16 PchOverTemp; + UINT8 PchOverTempLockHide; + UINT16 PchControlTemp; + UINT8 PchControlTempLockHide; + UINT16 PchAllOnTemp; + UINT8 PchAllOnTempLockHide; + UINT8 PchResponsiveness; + UINT8 PchResponsivenessLockHide; + UINT8 PchDamping; + UINT8 PchDampingLockHide; + UINT16 MemoryOverTemp; + UINT8 MemoryOverTempLockHide; + UINT16 MemoryControlTemp; + UINT8 MemoryControlTempLockHide; + UINT16 MemoryAllOnTemp; + UINT8 MemoryAllOnTempLockHide; + UINT8 MemoryResponsiveness; + UINT8 MemoryResponsivenessLockHide; + UINT8 MemoryDamping; + UINT8 MemoryDampingLockHide; + UINT16 VROverTemp; + UINT8 VROverTempLockHide; + UINT16 VRControlTemp; + UINT8 VRControlTempLockHide; + UINT16 VRAllOnTemp; + UINT8 VRAllOnTempLockHide; + UINT8 VRResponsiveness; + UINT8 VRResponsivenessLockHide; + UINT8 VRDamping; + UINT8 VRDampingLockHide; + + UINT8 LvdsBrightnessSteps; + UINT8 LvdsBrightnessStepsLockHide; + UINT8 EdpDataRate; + UINT8 EdpDataRateLockHide; + UINT16 LvdsPowerOnToBacklightEnableDelayTime; + UINT8 LvdsPowerOnToBacklightEnableDelayTimeLockHide; + UINT16 LvdsPowerOnDelayTime; + UINT8 LvdsPowerOnDelayTimeLockHide; + UINT16 LvdsBacklightOffToPowerDownDelayTime; + UINT8 LvdsBacklightOffToPowerDownDelayTimeLockHide; + UINT16 LvdsPowerDownDelayTime; + UINT8 LvdsPowerDownDelayTimeLockHide; + UINT16 LvdsPowerCycleDelayTime; + UINT8 LvdsPowerCycleDelayTimeLockHide; + + UINT8 IgdFlatPanel; + UINT8 IgdFlatPanelLockHide; + UINT8 Lan2; + UINT8 Lan2LockHide; + + UINT8 SwapMode; + UINT8 SwapModeLockHide; + + UINT8 Sata0HotPlugCap; + UINT8 Sata0HotPlugCapLockHide; + UINT8 Sata1HotPlugCap; + UINT8 Sata1HotPlugCapLockHide; + + UINT8 UsbCharging; + UINT8 UsbChargingLockHide; + + UINT8 Cstates; + UINT8 EnableC4; + UINT8 EnableC6; + + UINT8 FastBoot; + UINT8 EfiNetworkSupport; + UINT8 PxeRom; + + //Add for PpmPlatformPlicy + UINT8 PPM00; + UINT8 PPM01; + UINT8 PPM02; + UINT8 PPM03; + UINT8 PPM04; + UINT8 PPM05; + UINT8 PPM06; + UINT8 PPM07; + UINT8 PPM08; + UINT8 PPM09; + UINT8 PPM10; + UINT8 QuietBoot; + UINT8 LegacyUSBBooting; + + UINT8 PwmReserved02; + // + // Thermal Policy Values + // + UINT8 EnableDigitalThermalSensor; + UINT8 PassiveThermalTripPoint; + UINT8 PassiveTc1Value; + UINT8 PassiveTc2Value; + UINT8 PassiveTspValue; + UINT8 DisableActiveTripPoints; + UINT8 CriticalThermalTripPoint; + UINT8 IchPciExp[4]; + UINT8 DeepStandby; + UINT8 AlsEnable; + UINT8 IgdLcdIBia; + UINT8 LogBootTime; + + + UINT8 PcieRootPortIOApic[4]; + UINT8 IffsEnable; + UINT8 IffsOnS3RtcWake; + UINT8 IffsS3WakeTimerMin; + UINT8 IffsOnS3CritBattWake; + UINT8 IffsCritBattWakeThreshold; + UINT8 ScramblerSupport; + UINT8 SecureBoot; + UINT8 SecureBootCustomMode; + UINT8 SecureBootUserPhysicalPresent; + UINT8 CoreFreMultipSelect; + UINT8 MaxCState; + UINT8 PanelScaling; + UINT8 IgdLcdIGmchBlc; + UINT8 GfxBoost; + UINT8 IgdThermal; + UINT8 SEC00; + UINT8 SEC01; + UINT8 SEC02; + UINT8 SEC03; + UINT8 MeasuredBootEnable; + UINT8 UseProductKey; + //Image Signal Processor PCI Device Configuration + // + UINT8 ISPDevSel; + UINT8 ISPEn; + // Passwords + UINT16 UserPassword[PASSWORD_MAX_SIZE]; + UINT16 AdminPassword[PASSWORD_MAX_SIZE]; + UINT8 Tdt; + UINT8 Recovery; + UINT8 Suspend; + UINT8 TdtState; + UINT8 TdtEnrolled; + UINT8 PBAEnable; + + UINT8 HpetBootTime; + UINT8 UsbDebug; + UINT8 Lpe; + // + // LPSS Configuration + // + UINT8 LpssPciModeEnabled; + //Scc + UINT8 LpsseMMCEnabled; + UINT8 LpssSdioEnabled; + UINT8 LpssSdcardEnabled; + UINT8 LpssSdCardSDR25Enabled; + UINT8 LpssSdCardDDR50Enabled; + UINT8 LpssMipiHsi; + UINT8 LpsseMMC45Enabled; + UINT8 LpsseMMC45DDR50Enabled; + UINT8 LpsseMMC45HS200Enabled; + UINT8 LpsseMMC45RetuneTimerValue; + UINT8 eMMCBootMode; + + //LPSS2 + UINT8 LpssDma1Enabled; + UINT8 LpssI2C0Enabled; + UINT8 LpssI2C1Enabled; + UINT8 LpssI2C2Enabled; + UINT8 LpssI2C3Enabled; + UINT8 LpssI2C4Enabled; + UINT8 LpssI2C5Enabled; + UINT8 LpssI2C6Enabled; + //LPSS1 + UINT8 LpssDma0Enabled; + UINT8 LpssPwm0Enabled; + UINT8 LpssPwm1Enabled; + UINT8 LpssHsuart0Enabled; + UINT8 LpssHsuart1Enabled; + UINT8 LpssSpiEnabled; + UINT8 I2CTouchAd; + + UINT8 GTTSize; + // + // DVMT5.0 Graphic memory setting + // + UINT8 IgdDvmt50PreAlloc; + UINT8 IgdDvmt50TotalAlloc; + UINT8 IgdTurboEnabled; + + // + // Usb Config + // + UINT8 UsbAutoMode; // PCH controller Auto mode + UINT8 UsbXhciSupport; + UINT8 Hsic0; + UINT8 PchUsb30Mode; + UINT8 PchUsb30Streams; + UINT8 PchUsb20; + UINT8 PchUsbPerPortCtl; + UINT8 PchUsbPort[8]; + UINT8 PchUsbRmh; + UINT8 PchUsbOtg; + UINT8 PchUsbVbusOn; //OTG VBUS control + UINT8 PchFSAOn; //FSA control + UINT8 EhciPllCfgEnable; + + + //Gbe + UINT8 PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS]; + UINT8 SlpLanLowDc; + + UINT8 ISCT00; + UINT8 ISCT01; + UINT8 ISCT02; + UINT8 ISCT03; + UINT8 ISCT04; + UINT8 ISCT05; + UINT8 ISCT06; + UINT8 ISCT07; + // + // Azalia Configuration + // + UINT8 PchAzalia; + UINT8 AzaliaVCiEnable; + UINT8 AzaliaDs; + UINT8 AzaliaPme; + UINT8 HdmiCodec; + + UINT8 UartInterface; + UINT8 PcuUart1; + //UINT8 PcuUart2;//for A0 + UINT8 StateAfterG3; + UINT8 EnableClockSpreadSpec; + UINT8 GraphicReserve00; + UINT8 GOPEnable; + UINT8 GOPBrightnessLevel; //Gop Brightness level + UINT8 PavpMode; + UINT8 SEC04; + UINT8 SEC05; + UINT8 SEC06; + UINT8 SEC07; + + UINT8 HdmiCodecPortB; + UINT8 HdmiCodecPortC; + UINT8 HdmiCodecPortD; + UINT8 LidStatus; + UINT8 Reserved00; + UINT8 Reserved01; + UINT16 Reserved02; + UINT16 Reserved03; + UINT16 Reserved04; + UINT16 Reserved05; + UINT16 Reserved06; + UINT16 Reserved07; + UINT16 Reserved08; + UINT16 Reserved09; + UINT16 Reserved0A; + UINT16 Reserved0B; + UINT16 Reserved0C; + UINT16 Reserved0D; + UINT8 Reserved0E; + UINT8 Reserved0F; + UINT32 Reserved10; + UINT32 Reserved11; + UINT32 Reserved12; + UINT32 Reserved13; + UINT32 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; + UINT8 Reserved17; + UINT8 Reserved18; + UINT8 Reserved19; + UINT8 Reserved1A; + UINT8 Reserved1B; + UINT8 Reserved1C; + UINT8 Reserved1D; + UINT8 Reserved1E; + UINT8 Reserved1F; + UINT8 Reserved20; + UINT8 PmicEnable; + UINT8 IdleReserve; + UINT8 TSEGSizeSel; + UINT8 ACPIMemDbg; + UINT8 ExISupport; + UINT8 BatteryChargingSolution; //0-non ULPMC 1-ULPMC + UINT8 PnpSettings; + UINT8 CfioPnpSettings; + UINT8 PchEhciDebug; + UINT8 CRIDSettings; + UINT8 ULPMCFWLock; + UINT8 SpiRwProtect; + UINT8 GraphicReserve02; + UINT8 PDMConfig; + UINT16 LmMemSize; + UINT8 PunitBIOSConfig; + UINT8 LpssSdioMode; + UINT8 ENDBG2; + UINT8 WittEnable; + UINT8 UtsEnable; + UINT8 TristateLpc; + UINT8 GraphicReserve05; + UINT8 UsbXhciLpmSupport; + UINT8 EnableAESNI; + UINT8 SecureErase; + + UINT8 MmioSize; + + + UINT8 SAR1; + + UINT8 DisableCodec262; + UINT8 ReservedO; + UINT8 PcieDynamicGating; // Need PMC enable it first from PMC 0x3_12 MCU 318. + + UINT8 MipiDsi; + + //Added flow control item for UART1 and UART2 + UINT8 LpssHsuart0FlowControlEnabled; + UINT8 LpssHsuart1FlowControlEnabled; + + UINT8 SdCardRemovable; // ACPI reporting MMC/SD media as: removable/non-removable + + UINT8 GpioWakeCapability; + +} SYSTEM_CONFIGURATION; +#pragma pack() + +#ifndef PLATFORM_SETUP_VARIABLE_NAME +#define PLATFORM_SETUP_VARIABLE_NAME L"Setup" +#endif + +#pragma pack(1) +typedef struct{ + // Passwords + UINT16 UserPassword[PASSWORD_MAX_SIZE]; + UINT16 AdminPassword[PASSWORD_MAX_SIZE]; + UINT16 DummyDataForVfrBug; // Don't change or use + +} SYSTEM_PASSWORDS; +#pragma pack() + +// +// #defines for Drive Presence +// +#define EFI_HDD_PRESENT 0x01 +#define EFI_HDD_NOT_PRESENT 0x00 +#define EFI_CD_PRESENT 0x02 +#define EFI_CD_NOT_PRESENT 0x00 + +#define EFI_HDD_WARNING_ON 0x01 +#define EFI_CD_WARNING_ON 0x02 +#define EFI_SMART_WARNING_ON 0x04 +#define EFI_HDD_WARNING_OFF 0x00 +#define EFI_CD_WARNING_OFF 0x00 +#define EFI_SMART_WARNING_OFF 0x00 + +#ifndef VFRCOMPILE +extern EFI_GUID gEfiSetupVariableGuid; +#endif + +#define SETUP_DATA SYSTEM_CONFIGURATION + +#endif // #ifndef _SETUP_VARIABLE diff --git a/Vlv2TbltDevicePkg/Include/Hpet.h b/Vlv2TbltDevicePkg/Include/Hpet.h new file mode 100644 index 0000000000..10ada915b1 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Hpet.h @@ -0,0 +1,45 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Mseg.h + +Abstract: + + This file describes the contents of the ACPI HEPT Table. + +--*/ + +#ifndef _HPET_H +#define _HPET_H + +// +// Statements that include other files +// +#include +#include +#include +#include + +// +// HPET Definitions +// +#define EFI_ACPI_HPET_TABLE_REVISION 0x1 +#define MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS 0x80 //approx 1ms + +#define HPET_BASE_ADDRESS 0xFED00000 +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A001 + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h b/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h new file mode 100644 index 0000000000..aa20539570 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h @@ -0,0 +1,109 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + BiosIdLib.h + +Abstract: + + BIOS ID library definitions. + + This library provides functions to get BIOS ID, VERSION, DATE and TIME + +--*/ + +#ifndef _BIOS_ID_LIB_H_ +#define _BIOS_ID_LIB_H_ + +// +// BIOS ID string format: +// +// $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM +// +// Example: "TRFTCRB1.86C.0008.D03.0506081529" +// +#pragma pack(1) + +typedef struct { + CHAR16 BoardId[7]; // "TRFTCRB" + CHAR16 BoardRev; // "1" + CHAR16 Dot1; // "." + CHAR16 OemId[3]; // "86C" + CHAR16 Dot2; // "." + CHAR16 VersionMajor[4]; // "0008" + CHAR16 Dot3; // "." + CHAR16 BuildType; // "D" + CHAR16 VersionMinor[2]; // "03" + CHAR16 Dot4; // "." + CHAR16 TimeStamp[10]; // "YYMMDDHHMM" + CHAR16 NullTerminator; // 0x0000 +} BIOS_ID_STRING; + +#define MEM_IFWIVER_START 0x7E0000 +#define MEM_IFWIVER_LENGTH 0x1000 + +typedef struct _MANIFEST_OEM_DATA{ + UINT32 Signature; + unsigned char FillNull[0x39]; + UINT32 IFWIVersionLen; + unsigned char IFWIVersion[32]; +}MANIFEST_OEM_DATA; + +// +// A signature precedes the BIOS ID string in the FV to enable search by external tools. +// +typedef struct { + UINT8 Signature[8]; // "$IBIOSI$" + BIOS_ID_STRING BiosIdString; // "TRFTCRB1.86C.0008.D03.0506081529" +} BIOS_ID_IMAGE; + +#pragma pack() + +/** + This function returns BIOS ID by searching HOB or FV. + + @param[in] BiosIdImage The BIOS ID got from HOB or FV + + @retval EFI_SUCCESS All parameters were valid and BIOS ID has been got. + @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified. + @retval EFI_INVALID_PARAMETER The parameter is NULL. + +**/ +EFI_STATUS +GetBiosId ( + OUT BIOS_ID_IMAGE *BiosIdImage + ); + +/** + This function returns the Version & Release Date and Time by getting and converting + BIOS ID. + + @param[in] BiosVersion The Bios Version out of the conversion. + @param[in] BiosReleaseDate The Bios Release Date out of the conversion. + @param[in] BiosReleaseTime The Bios Release Time out of the conversion. + + @retval EFI_SUCCESS BIOS Version & Release Date and Time have been got successfully. + @retval EFI_NOT_FOUND BiosId image is not found, and no parameter will be modified. + @retval EFI_INVALID_PARAMETER All the parameters are NULL. + +**/ +EFI_STATUS +GetBiosVersionDateTime ( + OUT CHAR16 *BiosVersion, OPTIONAL + OUT CHAR16 *BiosReleaseDate, OPTIONAL + OUT CHAR16 *BiosReleaseTime OPTIONAL + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h b/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h new file mode 100644 index 0000000000..b8c53c94b3 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h @@ -0,0 +1,350 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + CpuIA32.h + +Abstract: + +--*/ + +#ifndef _CPU_IA32_H +#define _CPU_IA32_H + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +typedef struct { + UINT32 HeaderVersion; + UINT32 UpdateRevision; + UINT32 Date; + UINT32 ProcessorId; + UINT32 Checksum; + UINT32 LoaderRevision; + UINT32 ProcessorFlags; + UINT32 DataSize; + UINT32 TotalSize; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_HEADER; + +typedef struct { + UINT32 ExtendedSignatureCount; + UINT32 ExtendedTableChecksum; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +typedef struct { + UINT32 ProcessorSignature; + UINT32 ProcessorFlag; + UINT32 ProcessorChecksum; +} EFI_CPU_MICROCODE_EXTENDED_TABLE; + +typedef struct { + UINT32 Stepping : 4; + UINT32 Model : 4; + UINT32 Family : 4; + UINT32 Type : 2; + UINT32 Reserved1 : 2; + UINT32 ExtendedModel : 4; + UINT32 ExtendedFamily : 8; + UINT32 Reserved2 : 4; +} EFI_CPU_VERSION; + +#define EFI_CPUID_SIGNATURE 0x0 +#define EFI_CPUID_VERSION_INFO 0x1 +#define EFI_CPUID_CACHE_INFO 0x2 +#define EFI_CPUID_SERIAL_NUMBER 0x3 +#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000 +#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001 +#define EFI_CPUID_BRAND_STRING1 0x80000002 +#define EFI_CPUID_BRAND_STRING2 0x80000003 +#define EFI_CPUID_BRAND_STRING3 0x80000004 + +#define EFI_MSR_IA32_PLATFORM_ID 0x17 +#define EFI_MSR_IA32_APIC_BASE 0x1B +#define EFI_MSR_EBC_HARD_POWERON 0x2A +#define EFI_MSR_EBC_SOFT_POWERON 0x2B +#define BINIT_DRIVER_DISABLE 0x40 +#define INTERNAL_MCERR_DISABLE 0x20 +#define INITIATOR_MCERR_DISABLE 0x10 +#define EFI_MSR_EBC_FREQUENCY_ID 0x2C +#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79 +#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B +#define EFI_MSR_PSB_CLOCK_STATUS 0xCD +#define EFI_APIC_GLOBAL_ENABLE 0x800 +#define EFI_MSR_IA32_MISC_ENABLE 0x1A0 +#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000 +#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008 +#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004 +#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002 +#define FAST_STRING_ENABLE_BIT 0x00000001 + +#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200 +#define EFI_CACHE_VARIABLE_MTRR_END 0x20F +#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF +#define EFI_CACHE_MTRR_VALID 0x800 +#define EFI_CACHE_FIXED_MTRR_VALID 0x400 +#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 +#define EFI_MSR_VALID_MASK 0xFFFFFFFFF +#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000 +#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF + +#define EFI_IA32_MTRR_FIX64K_00000 0x250 +#define EFI_IA32_MTRR_FIX16K_80000 0x258 +#define EFI_IA32_MTRR_FIX16K_A0000 0x259 +#define EFI_IA32_MTRR_FIX4K_C0000 0x268 +#define EFI_IA32_MTRR_FIX4K_C8000 0x269 +#define EFI_IA32_MTRR_FIX4K_D0000 0x26A +#define EFI_IA32_MTRR_FIX4K_D8000 0x26B +#define EFI_IA32_MTRR_FIX4K_E0000 0x26C +#define EFI_IA32_MTRR_FIX4K_E8000 0x26D +#define EFI_IA32_MTRR_FIX4K_F0000 0x26E +#define EFI_IA32_MTRR_FIX4K_F8000 0x26F + +#define EFI_IA32_MCG_CAP 0x179 +#define EFI_IA32_MCG_CTL 0x17B +#define EFI_IA32_MC0_CTL 0x400 +#define EFI_IA32_MC0_STATUS 0x401 + +#define EFI_IA32_PERF_STATUS 0x198 +#define EFI_IA32_PERF_CTL 0x199 + +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITECOMBINING 1 +#define EFI_CACHE_WRITETHROUGH 4 +#define EFI_CACHE_WRITEPROTECTED 5 +#define EFI_CACHE_WRITEBACK 6 + +// +// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number +// +#define EfiMakeCpuVersion(f, m, s) \ + (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s))) + +/** + Halt the Cpu + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiHalt ( + VOID + ); + +/** + Write back and invalidate the Cpu cache + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiWbinvd ( + VOID + ); + +/** + Invalidate the Cpu cache + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiInvd ( + VOID + ); + +/** + Get the Cpu info by excute the CPUID instruction + + @param[in] RegisterInEax The input value to put into register EAX + @param[in] Regs The Output value + + @retval None + +**/ +VOID +EFIAPI +EfiCpuid ( + IN UINT32 RegisterInEax, + OUT EFI_CPUID_REGISTER *Regs + ); + +/** + When RegisterInEax != 4, the functionality is the same as EfiCpuid. + When RegisterInEax == 4, the function return the deterministic cache + parameters by excuting the CPUID instruction. + + @param[in] RegisterInEax The input value to put into register EAX. + @param[in] CacheLevel The deterministic cache level. + @param[in] Regs The Output value. + + @retval None + +**/ +VOID +EFIAPI +EfiCpuidExt ( + IN UINT32 RegisterInEax, + IN UINT32 CacheLevel, + OUT EFI_CPUID_REGISTER *Regs + ); + +/** + Read Cpu MSR + + @param[in] Index The index value to select the register + + @retval Return the read data + +**/ +UINT64 +EFIAPI +EfiReadMsr ( + IN UINT32 Index + ); + +/** + Write Cpu MSR + + @param[in] Index The index value to select the register + @param[in] Value The value to write to the selected register + + @retval None + +**/ +VOID +EFIAPI +EfiWriteMsr ( + IN UINT32 Index, + IN UINT64 Value + ); + +/** + Read Time stamp + + @param[in] None + + @retval Return the read data + +**/ +UINT64 +EFIAPI +EfiReadTsc ( + VOID + ); + +/** + Writing back and invalidate the cache,then diable it + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiDisableCache ( + VOID + ); + +/** + Invalidate the cache,then Enable it + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiEnableCache ( + VOID + ); + +/** + Get Eflags + + @param[in] None + + @retval Return the Eflags value + +**/ +UINT32 +EFIAPI +EfiGetEflags ( + VOID + ); + +/** + Disable Interrupts + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiDisableInterrupts ( + VOID + ); + +/** + Enable Interrupts + + @param[in] None + + @retval None + +**/ +VOID +EFIAPI +EfiEnableInterrupts ( + VOID + ); + +/** + Extract CPU detail version infomation + + @param[in] FamilyId FamilyId, including ExtendedFamilyId + @param[in] Model Model, including ExtendedModel + @param[in] SteppingId SteppingId + @param[in] Processor Processor + +**/ +VOID +EFIAPI +EfiCpuVersion ( + IN UINT16 *FamilyId, OPTIONAL + IN UINT8 *Model, OPTIONAL + IN UINT8 *SteppingId, OPTIONAL + IN UINT8 *Processor OPTIONAL + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h b/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h new file mode 100644 index 0000000000..796c64c9a1 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h @@ -0,0 +1,201 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + EfiRegTableLib.h + +Abstract: + + Definitions and macros for building register tables for chipset + initialization.. + + Components linking this lib must include CpuIo, PciRootBridgeIo, and + BootScriptSave protocols in their DPX. + + + +--*/ + +#ifndef EFI_REG_TABLE_H +#define EFI_REG_TABLE_H + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define OPCODE_BASE(OpCode) ((UINT8)((OpCode) & 0xFF)) +#define OPCODE_FLAGS(OpCode) ((UINT8)(((OpCode) >> 8) & 0xFF)) +#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16)) + +// +// RegTable Base OpCodes +// +#define OP_TERMINATE_TABLE 0 +#define OP_MEM_WRITE 1 +#define OP_MEM_READ_MODIFY_WRITE 2 +#define OP_IO_WRITE 3 +#define OP_IO_READ_MODIFY_WRITE 4 +#define OP_PCI_WRITE 5 +#define OP_PCI_READ_MODIFY_WRITE 6 +#define OP_STALL 7 + +// +// RegTable OpCode Flags +// +#define OPCODE_FLAG_S3SAVE 1 + + +#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 } + + +// +// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode +// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values +// +typedef struct { + UINT32 OpCode; + UINT32 PciAddress; + UINT32 Data; +} EFI_REG_TABLE_PCI_WRITE; + +#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag) \ + { \ + (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \ + (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \ + (UINT32) (Data), \ + (UINT32) (0) \ + } + +typedef struct { + UINT32 OpCode; + UINT32 MemAddress; + UINT32 Data; +} EFI_REG_TABLE_MEM_WRITE; + +typedef struct { + UINT32 OpCode; + UINT32 PciAddress; + UINT32 OrMask; + UINT32 AndMask; +} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE; + +#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag) \ + { \ + (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \ + (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))), \ + (UINT32) (OrMask), \ + (UINT32) (AndMask) \ + } + +typedef struct { + UINT32 OpCode; + UINT32 MemAddress; + UINT32 OrMask; + UINT32 AndMask; +} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE; + +#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag) \ + { \ + (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)), \ + (UINT32) (Address), \ + (UINT32) (OrMask), \ + (UINT32) (AndMask) \ + } + +typedef struct { + UINT32 OpCode; + UINT32 Field2; + UINT32 Field3; + UINT32 Field4; +} EFI_REG_TABLE_GENERIC; + +typedef union { + EFI_REG_TABLE_GENERIC Generic; + EFI_REG_TABLE_PCI_WRITE PciWrite; + EFI_REG_TABLE_PCI_READ_MODIFY_WRITE PciReadModifyWrite; + EFI_REG_TABLE_MEM_READ_MODIFY_WRITE MemReadModifyWrite; +} EFI_REG_TABLE; + +/** + Processes register table assuming which may contain PCI, IO, MEM, and STALL + entries. + + No parameter checking is done so the caller must be careful about omitting + values for PciRootBridgeIo or CpuIo parameters. If the regtable does + not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply + NULL). If the regtable does not contain any IO or Mem entries, it is safe to + omit the CpuIo (supply NULL). + + The RegTableEntry parameter is not checked, but is required. + + gBS is assumed to have been defined and is used when processing stalls. + + The function processes each entry sequentially until an OP_TERMINATE_TABLE + entry is encountered. + + @param[in] RegTableEntry A pointer to the register table to process + + @param[in] PciRootBridgeIo A pointer to the instance of PciRootBridgeIo that is used + when processing PCI table entries + + @param[in] CpuIo A pointer to the instance of CpuIo that is used when processing IO and + MEM table entries + + @retval Nothing. + +**/ +VOID +ProcessRegTablePci ( + EFI_REG_TABLE * RegTableEntry, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo, + EFI_CPU_IO_PROTOCOL * CpuIo + ); + +/** + Processes register table assuming which may contain IO, MEM, and STALL + entries, but must NOT contain any PCI entries. Any PCI entries cause an + ASSERT in a DEBUG build and are skipped in a free build. + + No parameter checking is done. Both RegTableEntry and CpuIo parameters are + required. + + gBS is assumed to have been defined and is used when processing stalls. + + The function processes each entry sequentially until an OP_TERMINATE_TABLE + entry is encountered. + + @param[in] RegTableEntry - A pointer to the register table to process + + @param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and + MEM table entries + + @retval Nothing. + +**/ +VOID +ProcessRegTableCpu ( + EFI_REG_TABLE * RegTableEntry, + EFI_CPU_IO_PROTOCOL * CpuIo + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/Esrt.h b/Vlv2TbltDevicePkg/Include/Library/Esrt.h new file mode 100644 index 0000000000..06977b640a --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/Esrt.h @@ -0,0 +1,79 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Esrt.h + +Abstract: + +--*/ + +#ifndef _DFU_ESRT_H_ +#define _DFU_ESRT_H_ + +typedef struct { + EFI_GUID FwClass; + UINT32 FwType; + UINT32 FwVersion; + UINT32 FwLstCompatVersion; + UINT32 CapsuleFlags; + UINT32 LastAttemptVersion; + UINT32 LastAttemptStatus; +} FW_RES_ENTRY; + +typedef struct { + UINT32 NumEntries; + FW_RES_ENTRY FwEntries[256]; +} FW_RES_ENTRY_LIST; + + +typedef struct { + UINT32 FwResourceCount; + UINT32 FwResourceMax; + UINT64 FwResourceVersion; +} EFI_SYSTEM_RESOURCE_TABLE; + + +typedef +EFI_STATUS +(EFIAPI *ESRT_POPULATE_TABLE) ( +); + +typedef +EFI_STATUS +(EFIAPI *ESRT_UPDATE_TABLE_ENTRY_BY_GUID) ( + IN EFI_GUID FwEntryGuid, + IN FW_RES_ENTRY *FwEntry +); + +typedef +EFI_STATUS +(EFIAPI *ESRT_GET_FW_ENTRY_BY_GUID) ( + IN EFI_GUID FwEntryGuid, + OUT FW_RES_ENTRY *FwEntry +); + + +#pragma pack() + +typedef struct _ESRT_OPERATION_PROTOCOL { + ESRT_POPULATE_TABLE EsrtPopulateTable; + ESRT_UPDATE_TABLE_ENTRY_BY_GUID EsrtUpdateTableEntryByGuid; + ESRT_GET_FW_ENTRY_BY_GUID EsrtGetFwEntryByGuid; +} ESRT_OPERATION_PROTOCOL; + +extern EFI_GUID gEfiEsrtOperationProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/Fd.h b/Vlv2TbltDevicePkg/Include/Library/Fd.h new file mode 100644 index 0000000000..20c70527d8 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/Fd.h @@ -0,0 +1,269 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + Fd.h + +Abstract: + + EFI Intel82802AB/82802AC Firmware Hub. + + +--*/ + + +// +// Supported SPI devices +// + +// +// MFG and Device code +// +#define SST_25LF040A 0x0044BF +#define SST_25LF040 0x0040BF +#define SST_25LF080A 0x0080BF +#define SST_25VF080B 0x008EBF +#define SST_25VF016B 0x0041BF +#define SST_25VF032B 0x004ABF + +#define PMC_25LV040 0x007E9D + +#define ATMEL_26DF041 0x00441F +#define Atmel_AT26F004 0x00041F +#define Atmel_AT26DF081A 0x01451F +#define Atmel_AT25DF161 0x02461F +#define Atmel_AT26DF161 0x00461F +#define Atmel_AT25DF641 0x00481F +#define Atmel_AT26DF321 0x00471F + +#define Macronix_MX25L8005 0x1420C2 +#define Macronix_MX25L1605A 0x1520C2 +#define Macronix_MX25L3205D 0x1620C2 + +#define STMicro_M25PE80 0x148020 + +#define Winbond_W25X40 0x1330EF +#define Winbond_W25X80 0x1430EF +#define Winbond_W25Q80 0x1440EF + +#define Winbond_W25X16 0x1540EF // W25Q16 +#define Winbond_W25X32 0x1630EF + +// +// NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary. +// Treating 4Mbit and 8Mbit devices the same. +// + +// +// BIOS Base Address +// +#define BIOS_BASE_ADDRESS_4M 0xFFF80000 +#define BIOS_BASE_ADDRESS_8M 0xFFF00000 +#define BIOS_BASE_ADDRESS_16M 0xFFE00000 + +// +// block and sector sizes +// +#define SECTOR_SIZE_256BYTE 0x100 // 256byte page size +#define SECTOR_SIZE_4KB 0x1000 // 4kBytes sector size +#define BLOCK_SIZE_32KB 0x00008000 // 32Kbytes block size +#define MAX_FLASH_SIZE 0x00400000 // 32Mbit (Note that this can also be used for the 4Mbit & 8Mbit) + +// +// Flash commands +// +#define SPI_SST25LF_COMMAND_WRITE 0x02 +#define SPI_SST25LF_COMMAND_READ 0x03 +#define SPI_SST25LF_COMMAND_ERASE 0x20 +#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04 +#define SPI_SST25LF_COMMAND_READ_STATUS 0x05 +#define SPI_SST25LF_COMMAND_WRITE_ENABLE 0x06 +#define SPI_SST25LF_COMMAND_READ_ID 0xAB +#define SPI_SST25LF_COMMAND_WRITE_S_EN 0x50 +#define SPI_SST25LF_COMMAND_WRITE_S 0x01 + +#define SPI_PMC25LV_COMMAND_WRITE 0x02 +#define SPI_PMC25LV_COMMAND_READ 0x03 +#define SPI_PMC25LV_COMMAND_ERASE 0xD7 +#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04 +#define SPI_PMC25LV_COMMAND_READ_STATUS 0x05 +#define SPI_PMC25LV_COMMAND_WRITE_ENABLE 0x06 +#define SPI_PMC25LV_COMMAND_READ_ID 0xAB +#define SPI_PMC25LV_COMMAND_WRITE_S_EN 0x06 +#define SPI_PMC25LV_COMMAND_WRITE_S 0x01 + +#define SPI_AT26DF_COMMAND_WRITE 0x02 +#define SPI_AT26DF_COMMAND_READ 0x03 +#define SPI_AT26DF_COMMAND_ERASE 0x20 +#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00 +#define SPI_AT26DF_COMMAND_READ_STATUS 0x05 +#define SPI_AT26DF_COMMAND_WRITE_ENABLE 0x00 +#define SPI_AT26DF_COMMAND_READ_ID 0x9F +#define SPI_AT26DF_COMMAND_WRITE_S_EN 0x00 +#define SPI_AT26DF_COMMAND_WRITE_S 0x00 + +#define SPI_AT26F_COMMAND_WRITE 0x02 +#define SPI_AT26F_COMMAND_READ 0x03 +#define SPI_AT26F_COMMAND_ERASE 0x20 +#define SPI_AT26F_COMMAND_WRITE_DISABLE 0x04 +#define SPI_AT26F_COMMAND_READ_STATUS 0x05 +#define SPI_AT26F_COMMAND_WRITE_ENABLE 0x06 +#define SPI_AT26F_COMMAND_JEDEC_ID 0x9F +#define SPI_AT26F_COMMAND_WRITE_S_EN 0x00 +#define SPI_AT26F_COMMAND_WRITE_S 0x01 +#define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39 + +#define SPI_SST25VF_COMMAND_WRITE 0x02 +#define SPI_SST25VF_COMMAND_READ 0x03 +#define SPI_SST25VF_COMMAND_ERASE 0x20 +#define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04 +#define SPI_SST25VF_COMMAND_READ_STATUS 0x05 +#define SPI_SST25VF_COMMAND_WRITE_ENABLE 0x06 +#define SPI_SST25VF_COMMAND_READ_ID 0xAB +#define SPI_SST25VF_COMMAND_JEDEC_ID 0x9F +#define SPI_SST25VF_COMMAND_WRITE_S_EN 0x50 +#define SPI_SST25VF_COMMAND_WRITE_S 0x01 + +#define SPI_STM25PE_COMMAND_WRITE 0x02 +#define SPI_STM25PE_COMMAND_READ 0x03 +#define SPI_STM25PE_COMMAND_ERASE 0xDB +#define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04 +#define SPI_STM25PE_COMMAND_READ_STATUS 0x05 +#define SPI_STM25PE_COMMAND_WRITE_ENABLE 0x06 +#define SPI_STM25PE_COMMAND_JEDEC_ID 0x9F + +#define SPI_WinbondW25X_COMMAND_WRITE_S 0x01 +#define SPI_WinbondW25X_COMMAND_WRITE 0x02 +#define SPI_WinbondW25X_COMMAND_READ 0x03 +#define SPI_WinbondW25X_COMMAND_READ_STATUS 0x05 +#define SPI_WinbondW25X_COMMAND_ERASE_S 0x20 +#define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06 +#define SPI_WinbondW25X_COMMAND_JEDEC_ID 0x9F + +// +// SPI default opcode slots +// +#define SPI_OPCODE_WRITE_INDEX 0 +#define SPI_OPCODE_READ_INDEX 1 +#define SPI_OPCODE_ERASE_INDEX 2 +#define SPI_OPCODE_READ_S_INDEX 3 +#define SPI_OPCODE_READ_ID_INDEX 4 +#define SPI_OPCODE_WRITE_S_INDEX 6 +#define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7 + +#define SPI_PREFIX_WRITE_S_EN 1 +#define SPI_PREFIX_WRITE_EN 0 + +// +// Atmel AT26F00x +// +#define B_AT26F_STS_REG_SPRL 0x80 +#define B_AT26F_STS_REG_SWP 0x0C + +// +// Block lock bit definitions: +// +#define READ_LOCK 0x04 +#define LOCK_DOWN 0x02 +#define WRITE_LOCK 0x01 +#define FULL_ACCESS 0x00 + +// +// Function Prototypes +// +EFI_STATUS +FlashGetNextBlock ( + IN UINTN* Key, + OUT EFI_PHYSICAL_ADDRESS* BlockAddress, + OUT UINTN* BlockSize + ); + +EFI_STATUS +FlashGetSize ( + OUT UINTN* Size + ); + +EFI_STATUS +FlashGetUniformBlockSize ( + OUT UINTN* Size + ); + +EFI_STATUS +FlashEraseWithNoTopSwapping ( + IN UINT8 *BaseAddress, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashErase ( + IN UINT8 *BaseAddress, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashWriteWithNoTopSwapping ( + IN UINT8* DstBufferPtr, + IN UINT8* SrcBufferPtr, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashWrite ( + IN UINT8 *DstBufferPtr, + IN UINT8 *SrcBufferPtr, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashReadWithNoTopSwapping ( + IN UINT8 *BaseAddress, + IN UINT8 *DstBufferPtr, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashRead ( + IN UINT8 *BaseAddress, + IN UINT8 *DstBufferPtr, + IN UINTN NumBytes + ); + +EFI_STATUS +FlashLockWithNoTopSwapping ( + IN UINT8* BaseAddress, + IN UINTN NumBytes, + IN UINT8 LockState + ); + +EFI_STATUS +FlashLock( + IN UINT8 *BaseAddress, + IN UINTN NumBytes, + IN UINT8 LockState + ); + +EFI_STATUS +CheckIfErased( + IN UINT8 *DstBufferPtr, + IN UINTN NumBytes + ); + +EFI_STATUS +CheckIfFlashIsReadyForWrite ( + IN UINT8 *DstBufferPtr, + IN UINT8 *SrcBufferPtr, + IN UINTN NumBytes + ); diff --git a/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h b/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h new file mode 100644 index 0000000000..bddc1f89b3 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h @@ -0,0 +1,127 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + Flash device library class header file. + + Flash Device Library common type, MACRO and API definition. The basic idea for + this library is to provide API to abstract the different between flash + technology (SPI, FWH etc..), flash controller (SPI host controller on + ICH, MMIO type access for FWH), flash chip (programming command, method + of status checking). This library class can be consumed by drivers or applications + such as Firmware Volume Block driver, Flash Update application. These driver + can be written in a generic manner so that they are more easy to be + ported to other platforms. + + This library can be build on a set of APIs which can touch flash controller, flash + chip directly for a platform with simple flash device configuration. + + For a platform with complex flash device configuration, this library can be built + on the Flash Device Operate Library. Please see the header file for that library + class for detailed usage. + +**/ + +#ifndef __FLASHDEVICE_LIB_H__ +#define __FLASHDEVICE_LIB_H__ + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] PAddress The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +LibFvbFlashDeviceRead ( + IN UINTN PAddress, + IN OUT UINTN *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] PAddress The starting physical address of the write. + @param[in,out] NumBytes On input, the number of bytes to write. On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +LibFvbFlashDeviceWrite ( + IN UINTN PAddress, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block staring at PAddress. + + @param[in] PAddress The starting physical address of the region to be erased. + @param[in] LbaLength The length of the region to be erased. This parameter is necessary + as the physical block size on a flash device could be different than + the logical block size of Firmware Volume Block protocol. Erase on + flash chip is always performed block by block. Therefore, the ERASE + operation to a logical block is converted a number of ERASE operation + (or a partial erase) on the hardware. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +LibFvbFlashDeviceBlockErase ( + IN UINTN PAddress, + IN UINTN LbaLength +); + +/** + Lock or unlock the block staring at PAddress. + + @param[in] PAddress The starting physical address of region to be (un)locked. + @param[in] LbaLength The length of the region to be (un)locked. This parameter is necessary + as the physical block size on a flash device could be different than + the logical block size of Firmware Volume Block protocol. (Un)Lock on + flash chip is always performed block by block. Therefore, the (Un)Lock + operation to a logical block is converted a number of (Un)Lock operation + (or a partial erase) on the hardware. + @param[in] Lock TRUE to lock. FALSE to unlock. + + @retval EFI_SUCCESS. Opertion is successful. + +**/ +EFI_STATUS +EFIAPI +LibFvbFlashDeviceBlockLock ( + IN UINTN PAddress, + IN UINTN LbaLength, + IN BOOLEAN Lock +); + +#endif + + diff --git a/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h b/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h new file mode 100644 index 0000000000..b1f91471f0 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h @@ -0,0 +1,28 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __MMIO_CONFIG_LIB_H__ +#define __MMIO_CONFIG_LIB_H__ + +#include + +/// +/// Declare the memory mapped I/O devices assocaited with the +/// board. +/// +extern CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList [ ]; +extern CONST UINTN gMmioDeviceCount; + +#endif // __MMIO_CONFIG_LIB_H__ diff --git a/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h b/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h new file mode 100644 index 0000000000..f52352f812 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h @@ -0,0 +1,31 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef _I2C_PORT_H +#define _I2C_PORT_H + +// +// Types +// + +// +// Context passed from platform (board) layer to the I2C port driver. +// +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 InputFrequencyHertz; +} I2C_PIO_PLATFORM_CONTEXT; + +#endif // _I2C_PORT_A0_H diff --git a/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h b/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h new file mode 100644 index 0000000000..3ff3fb1852 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h @@ -0,0 +1,55 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +#ifndef _FSA_LIB_H +#define _FSA_LIB_H +#include +#include + +#define FSA_REG_DEVID 0x1 +#define FSA_REG_CTRL 0x2 +#define FSA_REG_INTR 0x3 +#define FSA_REG_INTR_MSK 0x5 +#define FSA_REG_RESISTOR_CODE 0x7 +#define FSA_REG_TIMING_SET 0x8 +#define FSA_REG_STATUS 0x9 +#define FSA_REG_DEV_TYPE 0xA +#define FSA_REG_DAC_SAR 0xB +#define FSA_REG_MANUAL_SW 0x13 +#define FSA_REG_MANUAL_CHG_CTRL 0x14 + +extern +EFI_STATUS +EFIAPI +FsaUsbDeviceMode ( + VOID +); + + +extern +EFI_STATUS +EFIAPI +DisableFsaTimerHandler ( + VOID +); + +extern +EFI_STATUS +EFIAPI +FSAInit ( + IN UINT32 FFRDVer +); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h b/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h new file mode 100644 index 0000000000..2352514090 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h @@ -0,0 +1,28 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +#ifndef _PLATFORM_FSP_LIB_H +#define _PLATFORM_FSP_LIB_H +#include +#include + +extern +EFI_STATUS +PlatformHobCreateFromFsp ( + IN CONST EFI_PEI_SERVICES **PeiServices, + VOID *HobList + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H b/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H new file mode 100644 index 0000000000..9d1e898fed --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H @@ -0,0 +1,244 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SPIFlash_H_ +#define _SPIFlash_H_ + +#include + +//EFI_STATUS SpiFlashLock(BOOLEAN Lock); +//EFI_STATUS SpiFlashInit(void); + +typedef enum { + EnumSpiFlashW25Q64, + EnumSpiFlashAT25DF321A, + EnumSpiFlashAT26DF321, + EnumSpiFlashAT25DF641, + EnumSpiFlashW25Q16, + EnumSpiFlashW25Q32, + EnumSpiFlashW25X32, + EnumSpiFlashW25X64, + EnumSpiFlashW25Q128, + EnumSpiFlashMX25L16, + EnumSpiFlashMX25L32, + EnumSpiFlashMX25L64, + EnumSpiFlashMX25L128, + EnumSpiFlashMX25U6435F, + EnumSpiFlashSST25VF016B, + EnumSpiFlashSST25VF064C, + EnumSpiFlashN25Q064, + EnumSpiFlashM25PX16, + EnumSpiFlashN25Q032, + EnumSpiFlashM25PX32, + EnumSpiFlashM25PX64, + EnumSpiFlashN25Q128, + EnumSpiFlashEN25Q16, + EnumSpiFlashEN25Q32, + EnumSpiFlashEN25Q64, + EnumSpiFlashEN25Q128, + EnumSpiFlashA25L016, + EnumSpiFlashMax +} SPI_FLASH_TYPES_SUPPORTED; + +// +// Serial Flash VendorId and DeviceId +// +#define SF_VENDOR_ID_ATMEL 0x1F +#define SF_DEVICE_ID0_AT26DF321 0x47 +#define SF_DEVICE_ID1_AT26DF321 0x00 +#define SF_DEVICE_ID0_AT25DF321A 0x47 +#define SF_DEVICE_ID1_AT25DF321A 0x01 +#define SF_DEVICE_ID0_AT25DF641 0x48 +#define SF_DEVICE_ID1_AT25DF641 0x00 + +#define SF_VENDOR_ID_WINBOND 0xEF +#define SF_DEVICE_ID0_W25XXX 0x30 +#define SF_DEVICE_ID1_W25X32 0x16 +#define SF_DEVICE_ID1_W25X64 0x17 +#define SF_DEVICE_ID0_W25QXX 0x60 +#define SF_DEVICE_ID1_W25Q16 0x15 +#define SF_DEVICE_ID1_W25Q32 0x16 +#define SF_DEVICE_ID1_W25Q64 0x17 +#define SF_DEVICE_ID1_W25Q128 0x18 + +#define SF_VENDOR_ID_MACRONIX 0xC2 +#define SF_DEVICE_ID0_MX25LXX 0x20 +#define SF_DEVICE_ID1_MX25L16 0x15 +#define SF_DEVICE_ID1_MX25L32 0x16 +#define SF_DEVICE_ID1_MX25L64 0x17 +#define SF_DEVICE_ID1_MX25L128 0x18 +#define SF_DEVICE_ID0_MX25UXX 0x25 +#define SF_DEVICE_ID1_MX25U6435F 0x37 + +#define SF_VENDOR_ID_NUMONYX 0x20 +#define SF_DEVICE_ID0_N25Q064 0xBB +#define SF_DEVICE_ID1_N25Q064 0x17 +#define SF_DEVICE_ID0_M25PXXX 0x71 +#define SF_DEVICE_ID0_N25QXXX 0xBA +#define SF_DEVICE_ID1_M25PX16 0x15 +#define SF_DEVICE_ID1_N25Q032 0x16 +#define SF_DEVICE_ID1_M25PX32 0x16 +#define SF_DEVICE_ID1_M25PX64 0x17 +#define SF_DEVICE_ID1_N25Q128 0x18 + +#define SF_VENDOR_ID_SST 0xBF +#define SF_DEVICE_ID0_SST25VF0XXX 0x25 +#define SF_DEVICE_ID1_SST25VF016B 0x41 +#define SF_DEVICE_ID1_SST25VF064C 0x4B + +#define SF_VENDOR_ID_EON 0x1C +#define SF_DEVICE_ID0_EN25QXX 0x30 +#define SF_DEVICE_ID1_EN25Q16 0x15 +#define SF_DEVICE_ID1_EN25Q32 0x16 +#define SF_DEVICE_ID1_EN25Q64 0x17 +#define SF_DEVICE_ID1_EN25Q128 0x18 + +#define SF_VENDOR_ID_AMIC 0x37 +#define SF_DEVICE_ID0_A25L016 0x30 +#define SF_DEVICE_ID1_A25L016 0x15 + +#define ATMEL_AT26DF321_SIZE 0x00400000 +#define ATMEL_AT25DF321A_SIZE 0x00400000 +#define ATMEL_AT25DF641_SIZE 0x00800000 +#define WINBOND_W25X32_SIZE 0x00400000 +#define WINBOND_W25X64_SIZE 0x00800000 +#define WINBOND_W25Q16_SIZE 0x00200000 +#define WINBOND_W25Q32_SIZE 0x00400000 +#define WINBOND_W25Q64_SIZE 0x00800000 +#define WINBOND_W25Q128_SIZE 0x01000000 +#define SST_SST25VF016B_SIZE 0x00200000 +#define SST_SST25VF064C_SIZE 0x00800000 +#define MACRONIX_MX25L16_SIZE 0x00200000 +#define MACRONIX_MX25L32_SIZE 0x00400000 +#define MACRONIX_MX25L64_SIZE 0x00800000 +#define MACRONIX_MX25U64_SIZE 0x00800000 +#define MACRONIX_MX25L128_SIZE 0x01000000 +#define NUMONYX_M25PX16_SIZE 0x00400000 +#define NUMONYX_N25Q032_SIZE 0x00400000 +#define NUMONYX_M25PX32_SIZE 0x00400000 +#define NUMONYX_M25PX64_SIZE 0x00800000 +#define NUMONYX_N25Q064_SIZE 0x00800000 +#define NUMONYX_N25Q128_SIZE 0x01000000 +#define EON_EN25Q16_SIZE 0x00200000 +#define EON_EN25Q32_SIZE 0x00400000 +#define EON_EN25Q64_SIZE 0x00800000 +#define EON_EN25Q128_SIZE 0x01000000 +#define AMIC_A25L16_SIZE 0x00200000 + +#define SF_VENDOR_ID_SST 0xBF +#define SF_DEVICE_ID0_25LF080A 0x25 +#define SF_DEVICE_ID1_25LF080A 0x8E +#define SF_DEVICE_ID0_25VF016B 0x25 +#define SF_DEVICE_ID1_25VF016B 0x41 + +#define SF_VENDOR_ID_ATMEL 0x1F +#define SF_DEVICE_ID0_AT26DF321 0x47 +#define SF_DEVICE_ID1_AT26DF321 0x00 + +#define SF_VENDOR_ID_STM 0x20 +#define SF_DEVICE_ID0_M25P32 0x20 +#define SF_DEVICE_ID1_M25P32 0x16 + +#define SF_VENDOR_ID_WINBOND 0xEF +#define SF_DEVICE_ID0_W25XXX 0x30 +#define SF_DEVICE_ID0_W25QXX 0x60 +#define SF_DEVICE_ID1_W25X80 0x14 +#define SF_DEVICE_ID1_W25X16 0x15 +#define SF_DEVICE_ID1_W25X32 0x16 +#define SF_DEVICE_ID1_W25X64 0x17 + +#define SF_VENDOR_ID_MX 0xC2 +#define SF_DEVICE_ID0_25L1605A 0x20 +#define SF_DEVICE_ID1_25L1605A 0x15 + +#define SF_VENDOR_ID_NUMONYX 0x20 +#define SF_DEVICE_ID0_M25PX16 0x71 +#define SF_DEVICE_ID1_M25PX16 0x15 + +#define SST_25LF080A_SIZE 0x00100000 +#define SST_25LF016B_SIZE 0x00200000 +#define ATMEL_AT26DF321_SIZE 0x00400000 +#define STM_M25P32_SIZE 0x00400000 +#define WINBOND_W25X80_SIZE 0x00100000 +#define WINBOND_W25X16_SIZE 0x00200000 +#define WINBOND_W25X32_SIZE 0x00400000 +#define WINBOND_W25X64_SIZE 0x00800000 +#define MX_25L1605A_SIZE 0x00200000 + +// +// Physical Sector Size on the Serial Flash device +// +#define SF_SECTOR_SIZE 0x1000 +#define SF_BLOCK_SIZE 0x8000 + +// +// Serial Flash Status Register definitions +// +#define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress +#define SF_SR_WEL 0x02 // Indicates if device is memory write enabled +#define SF_SR_BP0 0x04 // Block protection bit 0 +#define SF_SR_BP1 0x08 // Block protection bit 1 +#define SF_SR_BP2 0x10 // Block protection bit 2 +#define SF_SR_BP3 0x20 // Block protection bit 3 +#define SF_SR_WPE 0x3C // Enable write protection on all blocks +#define SF_SR_AAI 0x40 // Auto Address Increment Programming status +#define SF_SR_BPL 0x80 // Block protection lock-down + +// +// Operation Instruction definitions for the Serial Flash Device +// +#define SF_INST_WRSR 0x01 // Write Status Register +#define SF_INST_PROG 0x02 // Byte Program +#define SF_INST_READ 0x03 // Read +#define SF_INST_WRDI 0x04 // Write Disable +#define SF_INST_RDSR 0x05 // Read Status Register +#define SF_INST_WREN 0x06 // Write Enable +#define SF_INST_HS_READ 0x0B // High-speed Read +#define SF_INST_SERASE 0x20 // Sector Erase (4KB) +#define SF_INST_BERASE 0x52 // Block Erase (32KB) +#define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB) +#define SF_INST_EWSR 0x50 // Enable Write Status Register +#define SF_INST_READ_ID 0xAB // Read ID +#define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID +#define SF_INST_DOFR 0x3B // Dual Output Fast Read +#define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size +#define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size +#define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit ) + +// +// Prefix Opcode Index on the host SPI controller +// +typedef enum { + SPI_WREN, // Prefix Opcode 0: Write Enable + SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register +} PREFIX_OPCODE_INDEX; + +// +// Opcode Menu Index on the host SPI controller +// +typedef enum { + SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address + SPI_READ, // Opcode 1: READ, Read cycle with address + SPI_RDSR, // Opcode 2: Read Status Register, No address + SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address + SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address + SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address + SPI_PROG, // Opcode 6: Byte Program, Write cycle with address + SPI_WRSR, // Opcode 7: Write Status Register, No address +} SPI_OPCODE_INDEX; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h b/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h new file mode 100644 index 0000000000..364dc87679 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h @@ -0,0 +1,45 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + SmmStallLib.h + +Abstract: + + This library provides SMM functions for Stall. + These can be used to save size and simplify code. + All contents must be runtime and SMM safe. + +--*/ + +#ifndef _SMM_STALL_LIB_H_ +#define _SMM_STALL_LIB_H_ +#include "PiDxe.h" +#include "Pi/PiSmmCis.h" +extern EFI_SMM_SYSTEM_TABLE2 *mSmst; + +/** + Delay for at least the request number of microseconds + + @param[in] Microseconds Number of microseconds to delay. + + @retval None + +**/ +VOID +SmmStall ( + IN UINTN Microseconds + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h b/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h new file mode 100644 index 0000000000..4af713e4f9 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h @@ -0,0 +1,186 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __BASE_USBDEVICEMODE_LIB_H__ +#define __BASE_USBDEVICEMODE_LIB_H__ + +#pragma pack(1) +typedef struct { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bMaxBurst; + UINT8 bmAttributes; + UINT16 wBytesPerInterval; +} endpointCompanionDescriptor; +#pragma pack() + +#pragma pack(1) +typedef struct { + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bEndpointAddress; + UINT8 bmAttributes; + UINT16 wMaxPacketSize; + UINT8 bInterval; +} endpointDescriptor; +#pragma pack() + +typedef struct { + endpointDescriptor *pEpDesc; + endpointCompanionDescriptor *pEpCompDesc; +} USB_DEV_EP_INFO; //usbdEpInfo; + +typedef struct { + VOID *pBuf; + UINT32 dataLen; +} USBD_IO_INFO; + +typedef struct { + USBD_IO_INFO ioInfo; + USB_DEV_EP_INFO epInfo; +} USBD_IO_REQ; + +UINTN +EFIAPI +usbdInitDCI ( + VOID + ); + +BOOLEAN +EFIAPI +fbInit ( + OUT VOID *pParams + ); + +BOOLEAN +EFIAPI +fbDeinit ( + VOID + ); + +BOOLEAN +EFIAPI +fbStart ( + VOID + ); + +BOOLEAN +EFIAPI +fbStop ( + VOID + ); + +BOOLEAN +EFIAPI +usbdSetMmioBar ( + UINT32 mmioBar + ); + +BOOLEAN +EFIAPI +udciDeinit ( + VOID *pUdciHndl, + UINT32 flags + ); + +BOOLEAN +EFIAPI +udciIsr ( + VOID *pUdciHndl + ); + +BOOLEAN +EFIAPI +udciConnect ( + VOID *pUdciHndl + ); + +BOOLEAN +EFIAPI +udciDisconnect ( + VOID *pUdciHndl + ); + +BOOLEAN +EFIAPI +udciSetAddress ( + VOID *pUdciHndl, + UINT8 address + ); + +BOOLEAN +EFIAPI +udciInitEp ( + VOID *pUdciHndl, + USB_DEV_EP_INFO *pEpInfo + ); + +BOOLEAN +EFIAPI +udciEnableEp ( + VOID *pUdciHndl, + USB_DEV_EP_INFO *pEpInfo + ); + +BOOLEAN +EFIAPI +udciDisableEp ( + VOID *pUdciHndl, + USB_DEV_EP_INFO *pEpInfo + ); + +BOOLEAN +EFIAPI +udciStallEp ( + VOID *pUdciHndl, + USB_DEV_EP_INFO *pEpInfo + ); + +BOOLEAN +EFIAPI +udciClearStallEp ( + VOID *pUdciHndl, + USB_DEV_EP_INFO *pEpInfo + ); + + +BOOLEAN +EFIAPI +udciEp0TxStatus ( + VOID *pUdciHndl + ); + + +BOOLEAN +EFIAPI +udciEpTxData ( + VOID *pUdciHndl, + USBD_IO_REQ *pIoReq + ); + +BOOLEAN +EFIAPI +udciEpRxData ( + VOID *pUdciHndl, + USBD_IO_REQ *pIoReq + ); + +BOOLEAN +EFIAPI +udciRegisterCallbacks ( + VOID *pUdciHndl + ); + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Mcfg.h b/Vlv2TbltDevicePkg/Include/Mcfg.h new file mode 100644 index 0000000000..50dfc7003c --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Mcfg.h @@ -0,0 +1,74 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Mcfg.h + +Abstract: + + ACPI Memory mapped configuration space base address Description Table + implementation, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// +#include +#include "McfgTable.h" +#include "Platform.h" + +// +// "MCFG" Static Resource Affinity Table +// +#define EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D + +// +// MCFG Definitions, see specification for details. +// +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT 1 + +// +// MCFG Table definition. The table must be defined in a platform +// specific manner. +// +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + +#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE Segment[ + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT]; +#endif + +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE; + +#pragma pack() + +#endif // _MCFG_H_ diff --git a/Vlv2TbltDevicePkg/Include/McfgTable.h b/Vlv2TbltDevicePkg/Include/McfgTable.h new file mode 100644 index 0000000000..39461a2cc4 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/McfgTable.h @@ -0,0 +1,70 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + McfgTable.h + +Abstract: + + ACPI Memory mapped configuration space base address Description Table + definition, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + +**/ + +#ifndef _MCFG_TABLE_H_ +#define _MCFG_TABLE_H_ + +// +// Include files +// +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// MCFG Revision (defined in spec) +// +#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION 0x01 + +// +// MCFG Structure Definitions +// +// +// Memory Mapped Enhanced Configuration Base Address Allocation +// Structure Definition +// +typedef struct { + UINT64 BaseAddress; + UINT16 PciSegmentGroupNumber; + UINT8 StartBusNumber; + UINT8 EndBusNumber; + UINT32 Reserved; +} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE; + +// +// MCFG Table header definition. The rest of the table +// must be defined in a platform specific manner. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER; + +#pragma pack() + +#endif // _MCFG_TABLE_H diff --git a/Vlv2TbltDevicePkg/Include/Platform.h b/Vlv2TbltDevicePkg/Include/Platform.h new file mode 100644 index 0000000000..fa651f595b --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Platform.h @@ -0,0 +1,138 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Platform.h + +Abstract: + + Pinetrail platform specific information. + +**/ + +#ifndef _PLATFORM_H +#define _PLATFORM_H + +#include "ChipsetAccess.h" +#include "PlatformBaseAddresses.h" + + +// +// Number of P & T states supported. +// +#define NPTM_P_STATES_SUPPORTED 16 +#define NPTM_T_STATES_SUPPORTED 8 + +// +// I/O APIC IDs, the code uses math to generate the numbers +// instead of using these defines. +// +#define ICH_IOAPIC (1 << 0) +#define ICH_IOAPIC_ID 0x08 + +// +// Possible SMBus addresses that will be present. +// +#define SMBUS_ADDR_CH_A_1 0xA0 +#define SMBUS_ADDR_CH_A_2 0xA2 +#define SMBUS_ADDR_CH_B_1 0xA4 +#define SMBUS_ADDR_CH_B_2 0xA6 +#define SMBUS_ADDR_CH_C_1 0xA8 +#define SMBUS_ADDR_CH_C_2 0xAA +#define SMBUS_ADDR_CH_D_1 0xAC +#define SMBUS_ADDR_CH_D_2 0xAE +#define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC +#define SMBUS_ADDR_ICH_SLAVE 0x44 +#define SMBUS_ADDR_HECETA 0x5C +#define SMBUS_ADDR_SMBARP 0xC2 +#define SMBUS_ADDR_82573E 0xC6 +#define SMBUS_ADDR_CLKCHIP 0xD2 +#define SMBUS_ADDR_BRD_REV 0x4E +#define SMBUS_ADDR_DB803 0x82 + +// +// SMBus addresses that used on this platform. +// +#define PLATFORM_SMBUS_RSVD_ADDRESSES { \ + SMBUS_ADDR_CH_A_1, \ + SMBUS_ADDR_CH_A_2, \ + SMBUS_ADDR_HOST_CLK_BUFFER, \ + SMBUS_ADDR_ICH_SLAVE, \ + SMBUS_ADDR_SMBARP, \ + SMBUS_ADDR_CLKCHIP, \ + SMBUS_ADDR_BRD_REV, \ + SMBUS_ADDR_DB803 \ + } + +// +// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES. +// +#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8 + +// +// CMOS usage +// +#define CMOS_CPU_BSP_SELECT 0x10 +#define CMOS_CPU_UP_MODE 0x11 +#define CMOS_CPU_RATIO_OFFSET 0x12 +#define CMOS_CPU_CORE_HT_OFFSET 0x13 +#define CMOS_EFI_DEBUG 0x14 +#define CMOS_CPU_BIST_OFFSET 0x15 +#define CMOS_CPU_VMX_OFFSET 0x16 +#define CMOS_ICH_PORT80_OFFSET 0x17 +#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID. +#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP. +#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600 +#define CMOS_DCU_MODE_OFFSET 0x1B +#define CMOS_VR11_SET_OFFSET 0x1C +#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!! +#define CMOS_RESET_TYPE_BY_OS 0x52 +#define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c & +#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E +#define ACPI_TPM_REQUEST 0x75 +#define ACPI_TPM_LAST_REQUEST 0x76 +#define CMOS_BOOT_FLAG_ADDRESS 0x7E + +// +// GPIO Index Data Structure. +// +typedef struct { + UINT8 Register; + UINT32 Value; +} ICH_GPIO_DEV; + +// +// CPU Equates +// +#define MAX_THREAD 2 +#define MAX_CORE 1 +#define MAX_DIE 2 +#define MAX_CPU_SOCKET 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET) + +#define MEM64_LEN 0x00100000000 +#define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36 +#define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36 +#define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39 +#define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39 +#define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40 +#define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40 + +#define PLATFORM_MAX_BUS_NUM 0x3f +#define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d +#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b +#define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086 + +#endif diff --git a/Vlv2TbltDevicePkg/Include/PlatformBootMode.h b/Vlv2TbltDevicePkg/Include/PlatformBootMode.h new file mode 100644 index 0000000000..5335ab95be --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/PlatformBootMode.h @@ -0,0 +1,40 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformBootMode.h + +Abstract: + + EFI Platform Boot Mode + +Revision History + +--*/ + +#ifndef _EFI_PLATFORM_BOOT_MODE_H_ +#define _EFI_PLATFORM_BOOT_MODE_H_ + +// +// Global ID for the Platform Boot Mode Protocol. +// +#define MANUFACTURE_SETUP_NAME L"MfgDefault" +#define SAFE_SETUP_NAME L"SetupDefault" +#define OEM_DEFAULTS_SETUP_NAME L"OemDefault" +#define CUSTOM_DEFAULTS_SETUP_NAME L"CustomDefault" + +#endif + + diff --git a/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h b/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h new file mode 100644 index 0000000000..edff69d194 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h @@ -0,0 +1,48 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformDefinitions.h + +Abstract: + + This header file provides platform specific definitions used by other modules + for platform specific initialization. + + THIS FILE SHOULD ONLY CONTAIN #defines BECAUSE IT IS CONSUMED BY NON-C MODULES + (ASL and VFR) + + This file should not contain addition or other operations that an ASL compiler or + VFR compiler does not understand. + +--*/ + +#ifndef _PLATFORM_DEFINITIONS_H_ +#define _PLATFORM_DEFINITIONS_H_ + + +// +// Platform Base Address definitions +// +#define PCIEX_BASE_ADDRESS EDKII_GLUE_PciExpressBaseAddress // Pci Express Configuration Space Base Address + +#define PCIEX_LENGTH PLATFORM_PCIEXPRESS_LENGTH + +#define THERMAL_BASE_ADDRESS 0xFED08000 + +#ifndef MCH_BASE_ADDRESS +#define MCH_BASE_ADDRESS 0xFED10000 // MCH Register Base Address +#endif +#endif diff --git a/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h b/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h new file mode 100644 index 0000000000..fc4744822f --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h @@ -0,0 +1,47 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + BaseMemoryTest.h + +Abstract: + + Pei memory test PPI as defined in Tiano + + Used to Pei memory test in PEI + +--*/ + +#ifndef _BASE_MEMORY_TEST_H_ +#define _BASE_MEMORY_TEST_H_ + +typedef struct _PEI_MFG_MEMORY_TEST_PPI PEI_MFG_MEMORY_TEST_PPI; + +typedef +EFI_STATUS +(EFIAPI *PEI_MFG_MEMORY_TEST) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_MFG_MEMORY_TEST_PPI * This, + IN UINT32 BeginAddress, + IN UINT32 MemoryLength + ); + +typedef struct _PEI_MFG_MEMORY_TEST_PPI { + PEI_MFG_MEMORY_TEST MfgMemoryTest; +}PEI_MFG_MEMORY_TEST_PPI; + + +extern EFI_GUID gPeiMfgMemoryTestPpiGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h b/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h new file mode 100644 index 0000000000..8511b4c935 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h @@ -0,0 +1,136 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Speaker.h + +Abstract: + + EFI Speaker Interface Protocol + + + +--*/ + +#ifndef _PEI_SHA256_HASH_H +#define _PEI_SHA256_HASH_H + +// +// Global ID Speaker Interface +// +#define PEI_SHA256_HASH_PPI_GUID \ + { \ + 0x950e191b, 0x8524, 0x4f51, 0x80, 0xa1, 0x5c, 0x4f, 0x1b, 0x3, 0xf3, 0x5c \ + } + +typedef struct _PEI_SHA256_HASH_PPI PEI_SHA256_HASH_PPI; + +/** + @return The size, in bytes, of the context buffer required for hash operations. + +**/ +typedef +UINTN +(EFIAPI *HASH_GET_CONTEXT_SIZE)( + VOID + ); + +/** + Initializes user-supplied memory pointed by HashContext as hash context for + subsequent use. + + If HashContext is NULL, then ASSERT(). + + @param[in, out] HashContext Pointer to Context being initialized. + + @retval TRUE HASH context initialization succeeded. + @retval FALSE HASH context initialization failed. + +**/ +typedef +BOOLEAN +(EFIAPI *HASH_INIT)( + IN OUT VOID *HashContext + ); + +/** + Performs digest on a data buffer of the specified length. This function can + be called multiple times to compute the digest of long or discontinuous data streams. + + If HashContext is NULL, then ASSERT(). + + @param[in, out] HashContext Pointer to the MD5 context. + @param[in] Data Pointer to the buffer containing the data to be hashed. + @param[in] DataLength Length of Data buffer in bytes. + + @retval TRUE HASH data digest succeeded. + @retval FALSE Invalid HASH context. After HashFinal function has been called, the + HASH context cannot be reused. + +**/ +typedef +BOOLEAN +(EFIAPI *HASH_UPDATE)( + IN OUT VOID *HashContext, + IN CONST VOID *Data, + IN UINTN DataLength + ); + +/** + Completes hash computation and retrieves the digest value into the specified + memory. After this function has been called, the context cannot be used again. + + If HashContext is NULL, then ASSERT(). + If HashValue is NULL, then ASSERT(). + + @param[in, out] HashContext Pointer to the MD5 context + @param[out] HashValue Pointer to a buffer that receives the HASH digest + value. + + @retval TRUE HASH digest computation succeeded. + @retval FALSE HASH digest computation failed. + +**/ +typedef +BOOLEAN +(EFIAPI *HASH_FINAL)( + IN OUT VOID *HashContext, + OUT UINT8 *HashValue + ); + +// +// Ppi definition +// +typedef struct _PEI_SHA256_HASH_PPI { + // + // Pointer to Hash GetContentSize function + // + HASH_GET_CONTEXT_SIZE GetContextSize; + // + // Pointer to Hash Init function + // + HASH_INIT HashInit; + // + // Pointer to Hash Update function + // + HASH_UPDATE HashUpdate; + // + // Pointer to Hash Final function + // + HASH_FINAL HashFinal; + +} PEI_SHA256_HASH_PPI; + +extern EFI_GUID gPeiSha256HashPpiGuid; +#endif diff --git a/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h b/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h new file mode 100644 index 0000000000..2dfdafbd6f --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h @@ -0,0 +1,70 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Speaker.h + +Abstract: + + EFI Speaker Interface Protocol + + + +--*/ + +#ifndef _PEI_SPEAKER_IF_H +#define _PEI_SPEAKER_IF_H + +// +// Global ID Speaker Interface +// +#define PEI_SPEAKER_INTERFACE_PPI_GUID \ + { \ + 0x30ac275e, 0xbb30, 0x4b84, 0xa1, 0xcd, 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0 \ + } + +typedef struct _PEI_SPEAKER_IF_PPI PEI_SPEAKER_IF_PPI; + +// +// Beep Code +// +typedef +EFI_STATUS +(EFIAPI *EFI_SPEAKER_GENERATE_BEEP) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN NumberOfBeep, + IN UINTN BeepDuration, + IN UINTN TimeInterval + ); + +// +// Set Frequency +// +typedef +EFI_STATUS +(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 Frequency + ); + +// +// Protocol definition +// +typedef struct _PEI_SPEAKER_IF_PPI { + EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency; + EFI_SPEAKER_GENERATE_BEEP GenerateBeep; +} PEI_SPEAKER_IF_PPI; + +extern EFI_GUID gPeiSpeakerInterfacePpiGuid; +#endif diff --git a/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h b/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h new file mode 100644 index 0000000000..dc6468a045 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h @@ -0,0 +1,90 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Define APIs to retrieve USB Host Controller Info such as controller type and + I/O Port Base Address. + + +**/ + +#ifndef _PEI_USB_CONTROLLER_PPI_H_ +#define _PEI_USB_CONTROLLER_PPI_H_ + +// +// Global ID for the PEI_USB_CONTROLLER_PPI. +// +#define PEI_USB_CONTROLLER_PPI_GUID \ + { \ + 0x3bc1f6de, 0x693e, 0x4547,{ 0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2} \ + } + +// +// Forward declaration for the PEI_USB_CONTROLLER_PPI. +// +typedef struct _PEI_USB_CONTROLLER_PPI PEI_USB_CONTROLLER_PPI; + +// +// This bit is used in the ControllerType return parameter of GetUsbController() +// to identify the USB Host Controller type as UHCI +// +#define PEI_UHCI_CONTROLLER 0x01 + +// +// This bit is used in the ControllerType return parameter of GetUsbController() +// to identify the USB Host Controller type as OHCI +// +#define PEI_OHCI_CONTROLLER 0x02 + +// +// This bit is used in the ControllerType return parameter of GetUsbController() +// to identify the USB Host Controller type as EHCI +// +#define PEI_EHCI_CONTROLLER 0x03 + +/** + Retrieve USB Host Controller Info such as controller type and I/O Base Address. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_USB_CONTROLLER_PPI. + @param[in] ControllerId The ID of the USB controller. + @param[out] ControllerType On output, returns the type of the USB controller. + @param[out] BaseAddress On output, returns the base address of UHCI's I/O ports + if UHCI is enabled or the base address of EHCI's MMIO + if EHCI is enabled. + + @retval EFI_SUCCESS USB controller attributes were returned successfully. + @retval EFI_INVALID_PARAMETER ControllerId is greater than the maximum number + of USB controller supported by this platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_GET_USB_CONTROLLER)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_USB_CONTROLLER_PPI *This, + IN UINT8 UsbControllerId, + OUT UINTN *ControllerType, + OUT UINTN *BaseAddress + ); + +// +// This PPI contains a single service to retrieve the USB Host Controller type +// and the base address of the I/O ports used to access the USB Host Controller. +// +struct _PEI_USB_CONTROLLER_PPI { + PEI_GET_USB_CONTROLLER GetUsbController; +}; + +extern EFI_GUID gPeiUsbControllerPpiGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h b/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h new file mode 100644 index 0000000000..87c1c37686 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h @@ -0,0 +1,131 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + CK505ClockPlatformInfo.h + +Abstract: + + Protocol to communicate product clock routing information. + +GUID Info: + {3C485EA4-449A-46ce-BB08-2A336EA96B4E} + 0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e); + +**/ + +#ifndef _CLOCK_PLATFORM_INFO_H_ +#define _CLOCK_PLATFORM_INFO_H_ + + +#define EFI_CK505_CLOCK_PLATFORM_INFO_GUID \ + {0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e} + +// +// Structure to hold register modifications +// +typedef enum { + None = 0x00000000, + nICS9LP505_1 = 0x00000001, + nICS9LP505_2 = 0x00000002, + nIDTCV163 = 0x00000004, + nIDTCV174 = 0x00000008, + nSLG505YC56 = 0x00000010, + nSLG505YC64 = 0x00000020, + nCY28505 = 0x00000040, + nCY28505_2 = 0x00000080, + nCY28505LF = 0x00000100, + nPI6C505_OLD = 0x00000200, + nPI6C505_RevD = 0x00000400, + nGENERIC_505 = 0x00000800, + nSLG505YC264 = 0x00001000, + nIDTCV183 = 0x00002000, + nSLG505YC256 = 0x00004000, + nIDTCV184 = 0x00008000, + nIDTCV190 = 0x00010000, + All = 0xFFFFFFFF +} EFI_CLOCKS_SUPPORTED; + +typedef enum { + Disabled, + Enabled, + EnabledWithoutSwitch, + EnabledWithSwitch +} EFI_SIGNAL_STATE; + +typedef enum { + SrcClk11, + SrcClk10, + SrcClk9, + SrcClk8, + SrcClk7, + SrcClk6, + SrcClk5, + SrcClk4, + SrcClk3, + SrcClk2, + SrcClk1, + SrcClk0, + CpuClk1, + CpuClk0, + Ref0, + Dot96, + Usb48, + PciClkF5, + PciClk4, + PciClk3, + PciClk2, + PciClk1, + PciClk0, + SaveClockConfiguration, + MePresent, + Cr_A, + Cr_B, + Cr_C, + Cr_D, + Cr_E, + Cr_F, + Cr_G, + Cr_H, + Clk_None // Dummy entry for dynamic detection +} EFI_CLOCK_SIGNAL_NAME; + +typedef struct { + EFI_CLOCK_SIGNAL_NAME Signal; + EFI_SIGNAL_STATE State; + EFI_CLOCKS_SUPPORTED Supported; +} EFI_STATIC_SIGNALS; + +typedef struct { + BOOLEAN BehindBridge; + UINT16 BridgeBus; + UINT16 BridgeDev; + UINT16 BridgeFunction; + UINT16 TargetDevice; + EFI_CLOCK_SIGNAL_NAME Signal; +} EFI_DYNAMIC_SIGNALS; + + +typedef struct { + EFI_STATIC_SIGNALS *StaticClockTable; + UINTN StaticClockTableCount; + EFI_STATIC_SIGNALS *SxClockTable; + UINTN SxClockTableCount; + EFI_STATIC_SIGNALS *DynamicDisabledClocksTable; + UINTN DynamicDisabledClocksTableCount; +} EFI_CLOCK_PLATFORM_INFO; + +extern EFI_GUID gEfiCk505ClockPlatformInfoGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h b/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h new file mode 100644 index 0000000000..e71778f833 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h @@ -0,0 +1,81 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + EnhancedSpeedstep.h + +Abstract: + + Enhanced Speedstep protocol + + The Enhanced Speedstep Protocol support. + +**/ + +#ifndef _ENHANCED_SPEEDSTEP_H_ +#define _ENHANCED_SPEEDSTEP_H_ + +#define ENHANCED_SPEEDSTEP_PROTOCOL_GUID \ + { \ + 0x91a1ddcf, 0x5374, 0x4939, 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f \ + } + +typedef struct _ENHANCED_SPEEDSTEP_PROTOCOL ENHANCED_SPEEDSTEP_PROTOCOL; + +typedef struct { + UINT8 Version; // EIST State format + UINT8 Size; // Size of element + UINT32 RatioStep; // Step + UINT32 MinRatio; // Calculated min ratio + UINT32 MaxRatio; // Calculated max ratio + UINT32 MinCoreFreq; // Calculated min freq + UINT32 MaxCoreFreq; // Calculated max freq + UINT32 MinPower; // Calculated min power + UINT32 MaxPower; // Calculated max power + UINT32 NumStates; // Number of states +} EIST_INFORMATION; + +typedef struct { + UINT32 CoreFrequency; + UINT32 Power; + UINT32 TransitionLatency; + UINT32 BusMasterLatency; + UINT32 Control; + UINT32 Status; +} EFI_ACPI_CPU_PSS_STATE; + +typedef +EFI_STATUS +(EFIAPI *GET_EIST_TABLE) ( + IN ENHANCED_SPEEDSTEP_PROTOCOL *This, + OUT EIST_INFORMATION **EistInformation, + OUT VOID **PssStates + ); + +struct _ENHANCED_SPEEDSTEP_PROTOCOL { + UINT32 ProcApicId; + GET_EIST_TABLE GetEistTable; +}; + +// +// There will be an instance of this protocol for every processor +// in the system. ProcNumber is used to manage all the different +// processors in the system and passed into the MP protocol +// to run code streams on application processors +// +extern EFI_GUID gEnhancedSpeedstepProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h new file mode 100644 index 0000000000..231c8c018d --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h @@ -0,0 +1,484 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + + This program and the accompanying materials are licensed and made available under + + the terms and conditions of the BSD License that accompanies this distribution. + + The full text of the license may be found at + + http://opensource.org/licenses/bsd-license.php. + + + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + + +Module Name: + + GlobalNvsArea.h + +Abstract: + + Definition of the global NVS area protocol. This protocol + publishes the address and format of a global ACPI NVS buffer used as a communications + buffer between SMM code and ASL code. + The format is derived from the ACPI reference code, version 0.95. + + Note: Data structures defined in this protocol are not naturally aligned. + +**/ + + +#ifndef _GLOBAL_NVS_AREA_H_ +#define _GLOBAL_NVS_AREA_H_ + +// +// Includes +// +#define GLOBAL_NVS_DEVICE_ENABLE 1 +#define GLOBAL_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// + +//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL); + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ +{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc } + +// +// Revision id - Added TPM related fields +// +#define GLOBAL_NVS_AREA_RIVISION_1 1 + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +// +// Global NVS Area definition +// +#pragma pack (1) +typedef struct { + // + // Miscellaneous Dynamic Values, the definitions below need to be matched + // GNVS definitions in Platform.ASL + // + UINT16 OperatingSystem; // 00 + UINT8 SmiFunction; // 02 SMI function call via IO Trap + UINT8 SmiParameter0; // 03 + UINT8 SmiParameter1; // 04 + UINT8 SciFunction; // 05 SCI function call via _L00 + UINT8 SciParameter0; // 06 + UINT8 SciParameter1; // 07 + UINT8 GlobalLock; // 08 Global lock function call + UINT8 LockParameter0; // 09 + UINT8 LockParameter1; // 10 + UINT32 Port80DebugValue; // 11 + UINT8 LidState; // 15 Open = 1 + UINT8 PowerState; // 16 AC = 1 + UINT8 DebugState; // 17 + + + // + // Thermal Policy Values + // + UINT8 EnableThermalOffset; // 18 ThermalOffset for KSC + UINT8 Reserved1; // 19 + UINT8 Reserved2; // 20 + UINT8 PassiveThermalTripPoint; // 21 + UINT8 PassiveTc1Value; // 22 + UINT8 PassiveTc2Value; // 23 + UINT8 PassiveTspValue; // 24 + UINT8 CriticalThermalTripPoint; // 25 + UINT8 ReserveD; + UINT8 BspDigitalThermalSensorTemperature; // 27 Temperature of BSP + UINT8 ApDigitalThermalSensorTemperature; // 28 Temperature of AP + UINT8 DigitalThermalSensorSmiFunction; // 29 SMI function call via DTS IO Trap + + // + // Battery Support Values + // + UINT8 NumberOfBatteries; // 30 + UINT8 BatteryCapacity0; // 31 Battery 0 Stored Capacity + UINT8 BatteryCapacity1; // 32 Battery 1 Stored Capacity + UINT8 BatteryCapacity2; // 33 Battery 2 Stored Capacity + UINT8 BatteryStatus0; // 34 Battery 0 Stored Status + UINT8 BatteryStatus1; // 35 Battery 1 Stored Status + UINT8 BatteryStatus2; // 36 Battery 2 Stored Status + + // NOTE: Do NOT Change the Offset of Revision Field + UINT8 Revision; // 37 Revision of the structure EFI_GLOBAL_NVS_AREA + UINT8 Reserved3[2]; // 38:39 + + // + // Processor Configuration Values + // + UINT8 ApicEnable; // 40 APIC Enabled by SBIOS (APIC Enabled = 1) + UINT8 LogicalProcessorCount; // 41 Processor Count Enabled (MP Enabled != 0) + UINT8 CurentPdcState0; // 42 PDC settings, Processor 0 + UINT8 CurentPdcState1; // 43 PDC settings, Processor 1 + UINT8 MaximumPpcState; // 44 Maximum PPC state + UINT32 PpmFlags; // 45:48 PPM configuration flags, same as CFGD + UINT8 Reserved4[1]; // 49 + + // + // SIO Configuration Values + // + UINT8 DockedSioPresent; // 50 Dock SIO Present + UINT8 DockComA; // 51 COM A Port + UINT8 DockComB; // 52 COM B Port + UINT8 LptP; // 53 LPT Port + UINT8 DockFdc; // 54 FDC Port + UINT8 OnboardCom; // 55 Onboard COM Port + UINT8 OnboardComCir; // 56 Onboard COM CIR Port + + UINT8 WPCN381U; // 57 + UINT8 NPCE791x; // 58 + UINT8 Reserved5[1]; // 59 + + // + // Internal Graphics Device Values + // + UINT8 IgdState; // 60 IGD State (Primary Display = 1) + UINT8 DisplayToggleList; // 61 Display Toggle List Selection + UINT8 CurrentDeviceList; // 62 Current Attached Device List + UINT8 PreviousDeviceList; // 63 Previous Attached Device List + UINT16 CurrentDisplayState; // 64 Current Display State + UINT16 NextDisplayState; // 66 Next Display State + UINT16 SetDisplayState; // 68 Set Display State + UINT8 NumberOfValidDeviceId; // 70 Number of Valid Device IDs + UINT32 DeviceId1; // 71 Device ID 1 + UINT32 DeviceId2; // 75 Device ID 2 + UINT32 DeviceId3; // 79 Device ID 3 + UINT32 DeviceId4; // 83 Device ID 4 + UINT32 DeviceId5; // 87 Device ID 5 + + UINT32 AKsv0; // 91:94 First four bytes of AKSV (manufacturing mode) + UINT8 AKsv1; // 95 Fifth byte of AKSV (manufacturing mode + + UINT8 Reserved6[7]; // 96:102 + + // + // Backlight Control Values + // + UINT8 BacklightControlSupport; // 103 Backlight Control Support + UINT8 BrightnessPercentage; // 104 Brightness Level Percentage + + // + // Ambient Light Sensor Values + // + UINT8 AlsEnable; // 105 Ambient Light Sensor Enable + UINT8 AlsAdjustmentFactor; // 106 Ambient Light Adjusment Factor + UINT8 LuxLowValue; // 107 LUX Low Value + UINT8 LuxHighValue; // 108 LUX High Value + + UINT8 Reserved7[1]; // 109 + + // + // Extended Mobile Access Values + // + UINT8 EmaEnable; // 110 EMA Enable + UINT16 EmaPointer; // 111 EMA Pointer + UINT16 EmaLength; // 113 EMA Length + + UINT8 Reserved8[1]; // 115 + + // + // Mobile East Fork Values + // + UINT8 MefEnable; // 116 Mobile East Fork Enable + + // + // PCIe Dock Status + // + UINT8 PcieDockStatus; // 117 PCIe Dock Status + + UINT8 Reserved9[2]; // 118:119 + + // + // TPM Registers + // + UINT8 TpmPresent; // 120 TPM Present + UINT8 TpmEnable; // 121 TPM Enable + + UINT8 MorData; // 122 Memory Overwrite Request Data + UINT8 TcgParamter; // 123 Used for save the Mor and/or physical presence paramter + UINT32 PPResponse; // 124 Physical Presence request operation response + UINT8 PPRequest; // 128 Physical Presence request operation + UINT8 LastPPRequest; // 129 Last Physical Presence request operation + + // + // SATA Values + // + UINT8 GtfTaskFileBufferPort0[7]; // 130 GTF Task File Buffer for Port 0 + UINT8 GtfTaskFileBufferPort2[7]; // 137 GTF Task File Buffer for Port 2 + UINT8 IdeMode; // 144 IDE Mode (Compatible\Enhanced) + UINT8 GtfTaskFileBufferPort1[7]; // 145:151 GTF Task File Buffer for Port 1 + + UINT8 Reserved111[10]; // 152:161 + UINT64 BootTimeLogAddress; // 162:169 Boot Time Log Table Address + + UINT32 IgdOpRegionAddress; // 170 IGD OpRegion Starting Address + UINT8 IgdBootType; // 174 IGD Boot Type CMOS option + UINT8 IgdPanelType; // 175 IGD Panel Type CMOs option + UINT8 IgdTvFormat; // 176 IGD TV Format CMOS option + UINT8 IgdTvMinor; // 177 IGD TV Minor Format CMOS option + UINT8 IgdPanelScaling; // 178 IGD Panel Scaling + UINT8 IgdBlcConfig; // 179 IGD BLC Configuration + UINT8 IgdBiaConfig; // 180 IGD BIA Configuration + UINT8 IgdSscConfig; // 181 IGD SSC Configuration + UINT8 Igd409; // 182 IGD 0409 Modified Settings Flag + UINT8 Igd509; // 183 IGD 0509 Modified Settings Flag + UINT8 Igd609; // 184 IGD 0609 Modified Settings Flag + UINT8 Igd709; // 185 IGD 0709 Modified Settings Flag + UINT8 IgdPowerConservation; // 186 IGD Power Conservation Feature Flag + UINT8 IgdDvmtMemSize; // 187 IGD DVMT Memory Size + UINT8 IgdFunc1Enable; // 188 IGD Function 1 Enable + UINT8 IgdHpllVco; // 189 HPLL VCO + UINT32 NextStateDid1; // 190 Next state DID1 for _DGS + UINT32 NextStateDid2; // 194 Next state DID2 for _DGS + UINT32 NextStateDid3; // 198 Next state DID3 for _DGS + UINT32 NextStateDid4; // 202 Next state DID4 for _DGS + UINT32 NextStateDid5; // 206 Next state DID5 for _DGS + UINT32 NextStateDid6; // 210 Next state DID6 for _DGS + UINT32 NextStateDid7; // 214 Next state DID7 for _DGS + UINT32 NextStateDid8; // 218 Next state DID8 for _DGS + UINT8 IgdSciSmiMode; // 222 GMCH SMI/SCI mode (0=SCI) + UINT8 IgdPAVP; // 223 IGD PAVP data + UINT8 IgdSelfRefresh; // 224 IGD Self Refresh + UINT8 PcieOSCControl; // 225 PCIE OSC Control + UINT8 NativePCIESupport; // 226 Native PCI Express Support + + // + // USB Sideband Deferring Support + // + UINT8 HostAlertVector; // 227 GPE vector used for HOST_ALERT + UINT8 HostAlertPio; // 228 PIO of USB device used for HOST_ALERT + + UINT8 Reserved112[27]; // 229 + UINT32 NvIgOpRegionAddress; // 256 NVIG support + UINT32 NvHmOpRegionAddress; // 260 NVHM support + UINT32 ApXmOpRegionAddress; // 264 AMDA support + UINT32 DeviceId6; // 268 Device ID 6 + UINT32 DeviceId7; // 272 Device ID 7 + UINT32 DeviceId8; // 276 Device ID 8 + UINT32 EndpointBaseAddress; // 280 PEG Endpoint PCIe Base Address + UINT32 CapStrPresence; // 284 PEG Endpoint Capability Structure Presence + UINT32 EndpointPcieCapBaseAddress; // 288 PEG Endpoint PCIe Capability Structure Base Address + UINT32 EndpointVcCapBaseAddress; // 292 PEG Endpoint Virtual Channel Capability Structure Base Address + UINT32 XPcieCfgBaseAddress; // 296 Any Device's PCIe Config Space Base Address + UINT32 OccupiedBuses1; // 300 Occupied Buses from 0 to 31 + UINT32 OccupiedBuses2; // 304 Occupied Buses from 32 to 63 + UINT32 OccupiedBuses3; // 308 Occupied Buses from 64 to 95 + UINT32 OccupiedBuses4; // 312 Occupied Buses from 96 to 127 + UINT32 OccupiedBuses5; // 316 Occupied Buses from 128 to 159 + UINT32 OccupiedBuses6; // 320 Occupied Buses from 160 to 191 + UINT32 OccupiedBuses7; // 324 Occupied Buses from 192 to 223 + UINT32 OccupiedBuses8; // 328 Occupied Buses from 224 to 255 + UINT8 UartSelection; // 332 UART Interface Selection 0: Internal; 1: SIO + UINT8 PcuUart1Enable; // 333 PCU UART 1 Enabled + UINT8 PcuUart2Enable; // 334 PCU UART 2 Enabled + + UINT32 LPEBar0; // 335~338 LPE Bar0 + UINT32 LPEBar1; // 339~342 LPE Bar1 + + UINT32 LPEBar2; // 343~346 LPE Bar2 + UINT8 AcSetup; // 347 For Ac Powered Config option - IST applet + UINT8 BatterySetup; // 348 For Battery Powered Config option - IST applet + UINT8 PlatformFlavor; // 349 0:unknown 1: Mobile; 2: desktop + UINT8 Reserved113[1]; // 350 + + UINT8 IsctReserve; // 351 ISCT / AOAC Configuration + UINT8 XhciMode; // 352 xHCI mode + UINT8 PmicEnable; // 353 PMIC enable + + UINT8 LpeEnable; // 354 LPE enable + UINT32 ISPAddr; // 355 ISP Base address + UINT8 ISPDevSel; // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3 + + // + // Lpss controllers + // + UINT32 PCIBottomAddress; //360 ((4+8+6)*4+2)*4=296 + UINT32 PCITopAddress; //364 + + UINT32 LDMA1Addr; // 368 + UINT32 LDMA1Len; // 372 + UINT32 LDMA11Addr; // 376 + UINT32 LDMA11Len; // 380 + UINT32 PWM1Addr; // 384 PWM1 + UINT32 PWM1Len; // 388 + UINT32 PWM11Addr; // 392 + UINT32 PWM11Len; // 396 + UINT32 PWM2Addr; // 400 PWM2 + UINT32 PWM2Len; // 404 + UINT32 PWM21Addr; // 408 + UINT32 PWM21Len; // 412 + UINT32 UART1Addr; // 416 UART1 + UINT32 UART1Len; // 420 + UINT32 UART11Addr; // 424 UART1 + UINT32 UART11Len; // 428 + UINT32 UART2Addr; // 432 UART2 + UINT32 UART2Len; // 436 + UINT32 UART21Addr; // 440 UART2 + UINT32 UART21Len; // 444 + UINT32 SPIAddr; // 448 SPI + UINT32 SPILen; // 452 + UINT32 SPI1Addr; // 456 + UINT32 SPI1Len; // 460 + + UINT32 LDMA2Addr; // 464 + UINT32 LDMA2Len; // 468 + UINT32 LDMA21Addr; // 472 + UINT32 LDMA21Len; // 476 + UINT32 I2C1Addr; // 480 I2C1 + UINT32 I2C1Len; // 484 + UINT32 I2C11Addr; // 488 I2C1 + UINT32 I2C11Len; // 492 + UINT32 I2C2Addr; // 496 I2C2 + UINT32 I2C2Len; // 500 + UINT32 I2C21Addr; // 504 I2C2 + UINT32 I2C21Len; // 508 + UINT32 I2C3Addr; // 512 I2C3 + UINT32 I2C3Len; // 516 + UINT32 I2C31Addr; // 520 I2C3 + UINT32 I2C31Len; // 524 + UINT32 I2C4Addr; // 528 I2C4 + UINT32 I2C4Len; // 532 + UINT32 I2C41Addr; // 536 I2C4 + UINT32 I2C41Len; // 540 + UINT32 I2C5Addr; // 544 I2C5 + UINT32 I2C5Len; // 548 + UINT32 I2C51Addr; // 552 I2C5 + UINT32 I2C51Len; // 556 + UINT32 I2C6Addr; // 560 I2C6 + UINT32 I2C6Len; // 564 + UINT32 I2C61Addr; // 566 I2C6 + UINT32 I2C61Len; // 570 + UINT32 I2C7Addr; // 574 I2C7 + UINT32 I2C7Len; // 578 + UINT32 I2C71Addr; // 582 I2C7 + UINT32 I2C71Len; // 586 + + // + // Scc controllers + // + UINT32 eMMCAddr; // 590 EMMC + UINT32 eMMCLen; // 594 + UINT32 eMMC1Addr; // 598 + UINT32 eMMC1Len; // 602 + UINT32 SDIOAddr; // 606 SDIO + UINT32 SDIOLen; // 610 + UINT32 SDIO1Addr; // 614 + UINT32 SDIO1Len; // 618 + UINT32 SDCardAddr; // 622 SDCard + UINT32 SDCardLen; // 626 + UINT32 SDCard1Addr; // 630 + UINT32 SDCard1Len; // 636 + UINT32 MipiHsiAddr; // 640 MIPI-HSI + UINT32 MipiHsiLen; // 644 + UINT32 MipiHsi1Addr; // 648 + UINT32 MipiHsi1Len; // 652 + + UINT8 SdCardRemovable; // 656 reserve offset upto 658 + UINT8 HideLPSSDevices; // 657 Hide unsupported LPSS devices when in ACPI mode + UINT8 ReservedO; // 658 OS Selection + UINT8 Reserved00; // 659 + UINT8 Reserved01; // 660 + UINT8 Reserved02; // 661 + UINT8 Reserved03; // 662 + UINT8 Reserved04; // 663 + UINT8 Reserved05; // 664 + UINT8 Reserved06; // 665 + UINT8 Reserved07; // 666 + UINT8 Reserved08; // 667 + UINT8 Reserved09; // 668 + UINT8 Reserved0A; // 669 + UINT32 Reserved0B; // 670 + UINT32 Reserved0C; // 674 + UINT32 Reserved0D; // 678 + UINT32 Reserved0E; // 682 + UINT32 Reserved0F; // 686 + UINT32 Reserved10; // 690 + UINT32 Reserved11; // 694 + UINT32 Reserved12; // 698 + UINT32 Reserved13; // 702 + UINT32 Reserved14; // 706 + UINT32 Reserved15; // 710 + UINT32 Reserved16; // 714 + UINT8 Reserved17; + UINT32 Reserved18; + UINT32 Reserved19; + UINT32 Reserved1A; + UINT32 Reserved1B; + UINT32 Reserved1C; + UINT8 Reserved1D; + UINT32 Reserved1E; + UINT32 Reserved1F; + UINT32 Reserved20; + UINT32 Reserved21; + UINT32 Reserved22; + UINT8 Reserved23; + UINT8 BatteryChargingSolution; // 761 0-non ULPMC 1-ULPMC + + // + //101 bytes + // + UINT8 NFCnSelect; // 762 NFCx Select 1: NFC1 2:NFC2 + UINT8 LpssSccMode; // 763 EMMC device 0-ACPI mode, 1-PCI mode + + UINT32 TPMAddress; // 764 + UINT32 TPMLength; // 768 + + UINT8 I2CTouchAddress; // 772 I2C touch address, 0x4B:RVP 0x4A:FFRD + UINT8 IdleReserve; // 773 0 - disabled 1 - enabled + UINT8 SDIOMode; // 774 3 - Default 2 - DDR50 + UINT8 emmcVersion; // 775 0 - 4.41 1 - 4.5 + UINT32 BmBound; // 776 BM Bound + UINT8 FsaStatus; // 780 0 - Fsa is off, 1- Fsa is on + + // + // Board Id + // This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc + // + UINT8 BoardID; // 781 + UINT8 FabID; // 782 + UINT8 OtgMode; // 783 0- OTG disable 1- OTG PCI mode + UINT8 Stepping; // 784 Stepping + UINT8 WittEnable; // 785 WITT eanble 0 - disable 1 - enable + + UINT8 SocStepping; // 786 Soc Stepping infomation + UINT8 AmbientTripPointChange; // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled) + UINT8 UtsEnable; // 788 Uart Test eanble 0 - disable 1 - enable + UINT8 DptfReserve; // 789 + + UINT8 SarEnable; // 790 + UINT8 PssDeveice; // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K + UINT8 EDPV; // 792 Check for eDP display device + UINT32 DIDX; // 793 Device ID for eDP device + UINT8 MicrosoftIoT; // (794)JP1 pins are for Microsoft IoT project. +} EFI_GLOBAL_NVS_AREA; +#pragma pack () + +// +// Global NVS Area Protocol +// +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + EFI_GLOBAL_NVS_AREA *Area; +} EFI_GLOBAL_NVS_AREA_PROTOCOL; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h b/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h new file mode 100644 index 0000000000..75c707162f --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h @@ -0,0 +1,240 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + HwWatchdogTimer.h + +Abstract: + + +--*/ + +#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ +#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ + +#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \ + { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } + +#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \ + { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf } + + +#include + +// +// General Purpose Constants +// +#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48. +#define B_INSTAFLUSH BIT4 + +// +// Other Watchdog timer values +// +#define WDT_COUNTDOWN_VALUE 0x14 +#define BDS_WDT_COUNTDOWN_VALUE 0x35 + +// +// Prototypes for the Watchdog Timer Driver Protocol +// + +/** + This service begins the Watchdog Timer countdown. If the countdown completes prior to + Stop Timer or Restart Timer the system will reset. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_START_TIMER) ( + VOID + ); + +/** + This service resets the Watchdog Timer countdown and should only be called after the + Start Timer function. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_RESET_TIMER) ( + VOID + ); + +/** + This service restarts the Watchdog Timer countdown and should only be called after the + Start Timer function. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) ( + VOID + ); + +/** + This service disables the Watchdog Timer countdown. + + @param[in] None + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_STOP_TIMER) ( + VOID + ); + +/** + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) ( + OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout + ); + + + +/** + This service forces a reboot of the system due to a reset of the POWERGOOD_PS, + POWERGOOD_CLK, and the BSEL Override + + Arguments: + None + + Returns: + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) ( + IN BOOLEAN ForceTimeout, + IN UINT8 ResetType + ); + +/** + This service notifies the Watchdog Timer of the fact that a known reset is occuring. + + @param[in] AllowReset TRUE if a Reset is currently expected + FALSE if a Reset is not currently expected + + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) ( + IN BOOLEAN AllowReset + ); + +/** + This service reads the current Watchdog Timer countdown reload value. + + @param[in] CountdownValue pointer to UINT32 to return the value of the reload register. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 *CountdownValue + ); + +/** + This service reads the current Watchdog Timer countdown reload value. + + @param[in] CountdownValue Value to set the reload register. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 CountdownValue + ); + +/** + This service clears the state that indicates the Watchdog Timer fired. + + @retval EFI_SUCCESS - Operation completed successfully + @retval EFI_DEVICE_ERROR - The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) ( + ); + +/** + This service disables the Watchdog Timer countdown. It also closes the recurring restart event + if the event exists. + + @param[in] Stall TRUE = Stop the timer countdown + FALSE = Start the timer countdown + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) ( + IN BOOLEAN Stall + ); + + +typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL { + EFI_WATCHDOG_START_TIMER StartWatchdogTimer; + PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout; + EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer; + EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer; + EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout; + EFI_WATCHDOG_FORCE_REBOOT ForceReboot; + EFI_WATCHDOG_KNOWN_RESET AllowKnownReset; + EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod; + EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod; + PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState; + EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown; +} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL; + +extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid; +extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h new file mode 100644 index 0000000000..14a0b7079e --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h @@ -0,0 +1,112 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +**/ + +#ifndef __I2C_ACPI_H__ +#define __I2C_ACPI_H__ + +#include + +// +// I2C ACPI protocol +// +typedef struct _EFI_I2C_ACPI_PROTOCOL EFI_I2C_ACPI_PROTOCOL; + +// +// I2C device description +// +// This structure provides the platform specific information which +// describes an I2C device. +// +typedef struct { + // + // Hardware revision - ACPI _HRV value + // + UINT32 HardwareRevision; + + // + // Device path node for the I2C device. + // + CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + // + // I2C bus configuration for the I2C device. + // + UINT32 I2cBusConfiguration; + + // + // Number of slave addresses for the I2C device. + // + UINT32 SlaveAddressCount; + + // + // Address of the array of slave addresses for the I2C device. + // + CONST UINT32 *SlaveAddressArray; +}EFI_I2C_DEVICE; + + +/** + Enumerate the I2C devices + + This routine must be called at or below TPL_NOTIFY. + + This function walks the platform specific data to enumerates the + I2C devices on an I2C bus. + + @param[in] This Address of an EFI_I2C_ENUM_PROTOCOL + structure. + @param[in, out] Device Buffer containing the address of an + EFI_I2C_DEVICE structure. Enumeration + is started by setting the initial + EFI_I2C_DEVICE structure address to NULL. + The buffer receives an EFI_I2C_DEVICE + structure address for the next I2C device. + + @retval EFI_SUCCESS The platform data for the next device + on the I2C bus was returned successfully. + @retval EFI_INVALID_PARAMETER NextDevice was NULL + @retval EFI_NO_MAPPING PreviousDevice does not point to a valid + EFI_I2C_DEVICE structure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_ACPI_ENUMERATE) ( + IN CONST EFI_I2C_ACPI_PROTOCOL *This, + IN OUT CONST EFI_I2C_DEVICE **Device + ); + +// +// I2C device description +// +// This structure provides the platform specific information which +// describes an I2C device. +// +struct _EFI_I2C_ACPI_PROTOCOL { + // + // Walk the platform's list of I2C devices on the bus. This + // routine returns the next I2C device in the platform's list + // for this I2C bus. + // + EFI_I2C_ACPI_ENUMERATE Enumerate; +}; + +// +// Variable containing the GUID for the I2C device enumeration protocol +// +extern EFI_GUID gEfiI2cAcpiProtocolGuid; + +#endif // __I2C_ACPI_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h new file mode 100644 index 0000000000..d32837a921 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h @@ -0,0 +1,169 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __I2C_BUS_H__ +#define __I2C_BUS_H__ + +#include + +// +// I2C bus protocol +// +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL; + + +/** + Perform an I2C operation on the device + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + N.B. The typical consumers of this API are the third party I2C + drivers. Extreme care must be taken by other consumers of this + API to prevent confusing the third party I2C drivers due to a + state change at the I2C device which the third party I2C drivers + did not initiate. I2C platform drivers may use this API within + these guidelines. + + This routine queues an operation to the I2C controller for execution + on the I2C bus. + + As an upper layer driver writer, the following need to be provided + to the platform vendor: + + 1. ACPI CID value or string - this is used to connect the upper layer + driver to the device. + 2. Slave address array guidance when the I2C device uses more than one + slave address. This is used to access the blocks of hardware within + the I2C device. + + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL + structure + @param[in] SlaveAddressIndex Index into an array of slave addresses for + the I2C device. The values in the array are + specified by the board designer, with the + I2C device driver writer providing the slave + address order. + + For devices that have a single slave address, + this value must be zero. If the I2C device + uses more than one slave address then the third + party (upper level) I2C driver writer needs to + specify the order of entries in the slave address + array. + + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers" + section in I2cMaster.h. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller can not distinguish + when the NACK occurred. + @retval EFI_NOT_FOUND I2C slave address exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_BUS_START_REQUEST) ( + IN CONST EFI_I2C_BUS_PROTOCOL *This, + IN UINTN SlaveAddressIndex, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +// +// The I2C bus protocol enables access to a specific device on the I2C bus. +// +// Each I2C device is described as an ACPI node (HID, UID and CID) within the +// platform layer. The I2C bus protocol enumerates the I2C devices in the +// platform and creates a unique handle and device path for each I2C device. +// +// I2C slave addressing is abstracted to validate addresses and limit operation +// to the specified I2C device. The third party providing the I2C device support +// provides an ordered list of slave addresses for the I2C device to the team +// building the platform layer. The platform team must preserve the order of the +// supplied list. SlaveAddressCount is the number of entries in this list or +// array within the platform layer. The third party device support references +// a slave address using an index into the list or array in the range of zero +// to SlaveAddressCount - 1. +// +struct _EFI_I2C_BUS_PROTOCOL { + // + // Start an I2C operation on the bus + // + EFI_I2C_BUS_START_REQUEST StartRequest; + + // + // The maximum number of slave addresses for the I2C device. The caller may + // validate this value as a check on the platform layer's configuration. Slave + // address selection uses an index value in the range of zero to SlaveAddressCount - 1. + // + UINTN SlaveAddressCount; + + // + // Hardware revision - Matches the ACPI _HRV value + // + // The HardwareRevision value allows a single driver to support multiple hardware + // revisions and implement the necessary workarounds for limitations within the + // hardware. + // + UINT32 HardwareRevision; + + // + // The maximum number of bytes the I2C host controller + // is able to receive from the I2C bus. + // + UINT32 MaximumReceiveBytes; + + // + // The maximum number of bytes the I2C host controller + // is able to send on the I2C bus. + // + UINT32 MaximumTransmitBytes; + + // + // The maximum number of bytes in the I2C bus transaction. + // + UINT32 MaximumTotalBytes; +}; + +// +// GUID for the I2C bus protocol +// +extern EFI_GUID gEfiI2cBusProtocolGuid; + +#endif // __I2C_BUS_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h new file mode 100644 index 0000000000..0fcadd5d2e --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h @@ -0,0 +1,168 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __I2C_BUS_H__ +#define __I2C_BUS_H__ + +#include + +// +// I2C bus protocol +// +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL; + +/** + Perform an I2C operation on the device + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + N.B. The typical consumers of this API are the third party I2C + drivers. Extreme care must be taken by other consumers of this + API to prevent confusing the third party I2C drivers due to a + state change at the I2C device which the third party I2C drivers + did not initiate. I2C platform drivers may use this API within + these guidelines. + + This routine queues an operation to the I2C controller for execution + on the I2C bus. + + As an upper layer driver writer, the following need to be provided + to the platform vendor: + + 1. ACPI CID value or string - this is used to connect the upper layer + driver to the device. + 2. Slave address array guidance when the I2C device uses more than one + slave address. This is used to access the blocks of hardware within + the I2C device. + + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL + structure + @param[in] SlaveAddressIndex Index into an array of slave addresses for + the I2C device. The values in the array are + specified by the board designer, with the + I2C device driver writer providing the slave + address order. + + For devices that have a single slave address, + this value must be zero. If the I2C device + uses more than one slave address then the third + party (upper level) I2C driver writer needs to + specify the order of entries in the slave address + array. + + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers" + section in I2cMaster.h. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller can not distinguish + when the NACK occurred. + @retval EFI_NOT_FOUND I2C slave address exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_BUS_START_REQUEST) ( + IN CONST EFI_I2C_BUS_PROTOCOL *This, + IN UINTN SlaveAddressIndex, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +// +// The I2C bus protocol enables access to a specific device on the I2C bus. +// +// Each I2C device is described as an ACPI node (HID, UID and CID) within the +// platform layer. The I2C bus protocol enumerates the I2C devices in the +// platform and creates a unique handle and device path for each I2C device. +// +// I2C slave addressing is abstracted to validate addresses and limit operation +// to the specified I2C device. The third party providing the I2C device support +// provides an ordered list of slave addresses for the I2C device to the team +// building the platform layer. The platform team must preserve the order of the +// supplied list. SlaveAddressCount is the number of entries in this list or +// array within the platform layer. The third party device support references +// a slave address using an index into the list or array in the range of zero +// to SlaveAddressCount - 1. +// +struct _EFI_I2C_BUS_PROTOCOL { + // + // Start an I2C operation on the bus + // + EFI_I2C_BUS_START_REQUEST StartRequest; + + // + // The maximum number of slave addresses for the I2C device. The caller may + // validate this value as a check on the platform layer's configuration. Slave + // address selection uses an index value in the range of zero to SlaveAddressCount - 1. + // + UINTN SlaveAddressCount; + + // + // Hardware revision - Matches the ACPI _HRV value + // + // The HardwareRevision value allows a single driver to support multiple hardware + // revisions and implement the necessary workarounds for limitations within the + // hardware. + // + UINT32 HardwareRevision; + + // + // The maximum number of bytes the I2C host controller + // is able to receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + // + // The maximum number of bytes the I2C host controller + // is able to send on the I2C bus. + // + UINT32 MaximumTransmitBytes; + + // + // The maximum number of bytes in the I2C bus transaction. + // + UINT32 MaximumTotalBytes; +}; + +// +// GUID for the I2C bus protocol +// +extern EFI_GUID gEfiI2cBusProtocolGuid; + +#endif // __I2C_BUS_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h new file mode 100644 index 0000000000..3395043d3e --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h @@ -0,0 +1,143 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __I2C_HOST_H__ +#define __I2C_HOST_H__ + +#include + +/** + Declare the forward references + +**/ +typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL; +typedef struct _EFI_I2C_HOST_CALLBACKS EFI_I2C_HOST_CALLBACKS; + + +/** + Queue an I2C operation for execution on the I2C controller. + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + N.B. The typical consumers of this API are the I2C bus driver and + on rare occasions the I2C test application. Extreme care must be + taken by other consumers of this API to prevent confusing the + third party I2C drivers due to a state change at the I2C device + which the third party I2C drivers did not initiate. I2C platform + drivers may use this API within these guidelines. + + This layer uses the concept of I2C bus configurations to describe + the I2C bus. An I2C bus configuration is defined as a unique + setting of the multiplexers and switches in the I2C bus which + enable access to one or more I2C devices. When using a switch + to divide a bus, due to speed differences, the I2C platform layer + would define an I2C bus configuration for the I2C devices on each + side of the switch. When using a multiplexer, the I2C platform + layer defines an I2C bus configuration for each of the selector + values required to control the multiplexer. See Figure 1 in the + I2C + Specification for a complex I2C bus configuration. + + The I2C host driver processes all operations in FIFO order. Prior to + performing the operation, the I2C host driver calls the I2C platform + driver to reconfigure the switches and multiplexers in the I2C bus + enabling access to the specified I2C device. The I2C platform driver + also selects the maximum bus speed for the device. After the I2C bus + is configured, the I2C host driver calls the I2C port driver to + initialize the I2C controller and start the I2C operation. + + @param[in] This Address of an EFI_I2C_HOST_PROTOCOL instance. + @param[in] I2cBusConfiguration I2C bus configuration to access the I2C + device. + @param[in] SlaveAddress Address of the device on the I2C bus. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller cannot distinguish + when the NACK occurred. + @retval EFI_NOT_FOUND I2C slave address exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_HOST_QUEUE_REQUEST) ( + IN CONST EFI_I2C_HOST_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + IN UINTN SlaveAddress, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// Host access to the I2C bus. +/// +struct _EFI_I2C_HOST_PROTOCOL { + /// + /// Queue an operation for execution on the I2C bus + /// + EFI_I2C_HOST_QUEUE_REQUEST QueueRequest; + + /// + /// The maximum number of I2C bus configurations + /// + UINTN I2cBusConfigurationCount; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to send on the I2C bus. + /// + UINT32 MaximumTransmitBytes; + + /// + /// The maximum number of bytes in the I2C bus transaction. + /// + UINT32 MaximumTotalBytes; +}; + +/// +/// GUID for the EFI_I2C_HOST_PROTOCOL +/// +extern EFI_GUID gEfiI2cHostProtocolGuid; + +#endif // __I2C_HOST_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h new file mode 100644 index 0000000000..f239b5ec2f --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h @@ -0,0 +1,524 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + \section I2cDriverStack I2C Driver Stack + + The following is a representation of the I2C (I2C) + driver stack and an I2C bus layout. + + 
+              +-----------------+
+              |   Application   |
+              +-----------------+
+                       |
+                       | Third Party or UEFI
+                       |
+                       V
+ +--------+   +-----------------+
+ | Slave  |   |   Third Party   |
+ | Driver |   |   I2C Device    |
+ |        |   |     Driver      |
+ +--------+   +-----------------+
+      |                |
+      |          BUS   |
+      |                |
+      |                V
+      |       +-----------------+
+      |       | I2C Bus Driver  |------------------.
+      |       +-----------------+                  |
+      |                |                           |
+      |         HOST   |          BUS              |
+      |                |          CONFIGURATION    |
+SLAVE |                V          MANAGEMENT       | ACPI
+      |       +-----------------+                  |
+      |       | I2C Host Driver |----------.       |
+      |       +-----------------+          |       |
+      |                |                   |       |
+      |        MASTER  |                   V       V
+      |                |               +-------=-------------+
+      |                V               | I2C Platform Driver |
+      |       +-----------------+      +---------------------+
+      `------>| I2C Port Driver |               |      |
+              +-----------------+               |      |
+                       |                        |      |
+            Software   |                        |      |
+            --------------------------------------------------
+            Hardware   |                        |      |
+                       |                        |      |
+                       V                        |      |
+              +-----------------+               |      |
+              | I2C Controller  |               |      |
+              +-----------------+               |      |
+                       |                        |      |
+            -----------------------             |      |
+            I2C Bus    |                        |      |
+                       |    +------------+      |      |
+                       +----| High speed |      |      |
+                       |    | I2C device |      |      |
+                       |    |    0x01    |      |      |
+                       |    +------------+      |      |
+                       |                        |      |
+                  +---------+  0                |      |
+                  | Switch  |<------------------`      |
+                  +---------+  1                       |
+                       |                               |
+                       |    +------------+             |
+                       +----| Fast speed |             |
+                       |    | I2C device |             |
+                       |    |    0x02    |             |
+                       |    +------------+             |
+                       |                               |
+                +-------------+                        |
+                | Multiplexer |<-----------------------`
+                +-------------+
+                 0 |       | 1
+                   |       |
+                   |       |
+                   |       |    +-------------+
+                   |       +----| Third Party |
+                   |       |    | I2C Device  |
+                   |       |    |  0x03, 0x04 |
+                   |       |    +-------------+
+                   |       |
+                   |
+                   |            +-------------+
+                   +------------| Third Party |
+                   |            | I2C Device  |
+                   |            |  0x03, 0x04 |
+                   |            +-------------+
+                   |
+
+ + The platform hardware designer chooses the bus layout based upon + the platform, I2C chip and software requirements. The design uses + switches to truncate the bus to enable higher speed operation for a + subset of devices which are placed closer to the controller. When the + switch is on, the extended bus must operate at a lower speed. The + design uses multiplexer to create separate address spaces enabling + the use of multiple devices which would otherwise have conflicting + addresses. See the + I2C + Specification for more details. + + N.B. Some operating systems may prohibit the changing of switches + and multiplexers in the I2C bus. In this case the platform hardware + and software designers must select a single I2C bus configuration + consisting of constant input values for the switches and multiplexers. + The platform software designer must then ensure that this I2C bus + configuration is enabled prior to passing control to the operating + system. + + The platform hardware designer needs to provide the platform software + designer the following data for each I2C bus: + + 1. Which controller controls this bus + + 2. A list of logic blocks contained in one or more I2C devices: + + a. I2C device which contains this logic block + + b. Logic block slave address + + c. Logic block name + + 3. For each configuration of the switches and multiplexer + + a. What is the maximum speed of operation + + b. What devices are accessible + + 4. The settings for the switches and multiplexers when control is + given to the operating system. + + \section ThirdPartyI2cDrivers Third Party I2C Drivers + + This layer is I2C chip specific but platform and host controller + independent. + + Third party I2C driver writers, typically silicon vendors, need + to provide: + + 1. The device path node data that is used to select their + driver. + + 2. The order for the blocks of logic that get referenced + by the entries in the slave address array. + + 3. The hardware version of the I2C device, this value is passed + to the third party I2C driver to enable it to perform work + arounds for the specific hardware version. This value should + match the value in the ACPI _HRV tag. + + The third party I2C driver uses relative addressing to abstract + the platform specific details of the I2C device. Using an + example I2C device containing an accelerometer and a magnetometer + which consumes two slave addresses, one for each logic block. The + third party I2C driver writer may choose to write two drivers, one + for each block of logic, in which case each driver refers to the + single I2C slave address using the relative value of zero (0). + However if the third party I2C driver writer chooses to write a + single driver which consumes multiple slave addresses then the + third party I2C driver writer needs to convey the order of the + I2C slave address entries in the slave address array to the + platform software designer. For the example: + + 0: Accelerometer + + 1: Magnetometer + + The platform hardware designer picks the actual slave addresses + from the I2C device's data sheet and provides this information + to the platform software designer. The platform software designer + then places the slave addresses into the slave address array in the + order specified by the third party I2C driver writer. The third + party driver I2C writer then indirectly references this array by + specifying the index value as the relative slave address. The + relative value always starts at zero (0) and its maximum value is + the number of entries in slave address array minus one. + + The slave address is specified as a 32-bit integer to allow room + for future slave address expansion. Only the port driver knows + the maximum slave address value. All other drivers and + applications must look for the EFI_NOT_FOUND status for the + indication that the maximum slave address was exceeded. + + \section I2cBusDriver I2C Bus Driver + + This layer is platform, host controller, and I2C chip independent. + + The I2C bus driver creates a handle for each of the I2C devices + described within the platform driver. The I2C controller's device + path is extended with the device path node provided by the platform + driver and attached to the handle. The third party I2C device driver + uses the device path to determine if it may connect. For ACPI nodes, + the third party I2C driver should use the CID or CidString value. + + The I2C bus driver validates the relative address for the I2C device + and then converts the relative value to an actual I2C slave address. + The request is then passed to the I2C host driver. + + \section I2cHostDriver I2C Host Driver + + This layer is platform, host controller, and I2C chip independent. + + N.B. For proper operation of the I2C bus, only the I2C bus driver + and the I2C test application should connect to the I2C host driver + via the EFI_I2C_HOST_DRIVER_PROTOCOL. + + The I2C host driver may access any device on the I2C bus. The I2C + host driver has the following responsibilities: + + 1. Limits the number of requests to the I2C port driver to one. + The I2C host driver holds on to additional requests until the + I2C port driver is available to process the request. The I2C + requests are issued in FIFO order to the I2C port driver. + + 2. Enable the proper I2C bus configuration before starting the + I2C request on the I2C port driver + + I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress. + I2C bus configuration zero (0) is the portion of the I2C bus that + connects to the host controller. The bus configuration specifies + the control values for the switches and multiplexers in the I2C bus. + After the switches and multiplexers are properly configured, the I2C + controller uses the slave address to access the requested I2C device. + + Since the I2C driver stack supports asynchronous operations this + layer maintains a queue of I2C requests until the I2C controller + is available them. When a request reaches the head of the queue + the necessary bus configuration is enabled and then the request + is sent to the I2C port driver. + + \section I2cPortDriver I2C Port Driver + + This layer is I2C controller specific but platform independent. + + This layer manipulates the I2C controller to perform an operation + on the I2C bus. This layer does not configure the I2C bus so it + is up to the caller to ensure that the I2C bus is in the proper + configuration before issuing the I2C request. + + This layer typically needs the following information: + + 1. Host controller address + 2. Controller's input clock frequency + + Depending upon the I2C controller, more data may be necessary. + This layer may use any method to get these values: hard coded + values, PCD values, or may choose to communicate with the platform + layer using an undefined mechanism to get these values. + + If the I2C port driver requires data from the platform driver then + the I2C port driver writer needs to provide the platform interface + details to the platform software designer. + + \section I2cPlatformDriver I2C Platform Driver + + When enabling access to I2C devices within UEFI, this driver + installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device + descriptions to the I2C bus driver using the EFI_I2C_DEVICE + structure. These descriptions include the bus configuration + number required for the I2C device, the slave address array + and the device path. + + The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional. + This protocol needs to be specified under the following conditions: + + 1. The I2C bus must operate at a frequency greater than 100 KHz + 2. The I2C bus contains switches or multiplexers. + + The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the + I2C host driver to call into the I2C platform driver to enable + a specific I2C bus configuration and set its maximum clock speed. + + The platform software designer collects the data requirements + from third party I2C driver writers, the I2C controller + driver writer, the EFI_I2C_ACPI_PROTOCOL and + EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform + software designer gets the necessary data from the platform + hardware designer. The platform software designer then builds + the data structures and implements the necessary routines to + construct the I2C platform driver. + + \section I2cSwitches Switches and Multiplexers + + There are some I2C switches and I2C multiplexers where the control + is done via I2C commands. When the control inputs come via the + same I2C bus that is being configured then the platform driver must + use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform + driver. While the I2C host driver makes the call to the I2C + platform driver to configure the bus, the host driver keeps the + I2C port driver idle, to allow the I2C platform driver preform + the necessary configuration operations. + + If however the configuration control is done via and I2C device + connected to a different I2C bus (host controller), then it is + possible for the platform software designer may choose between + the following: + + 1. Call into a third party I2C driver to manipulate the I2C + bus control device. + 2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C + driver exists for the I2C bus control device + 3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does + not expose the I2C bus control device. + +**/ + +#ifndef __I2C_MASTER_H__ +#define __I2C_MASTER_H__ + +/** + Declare the forward references + +**/ +typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL; ///< I2C master protocol + +/// +/// I2C device operation +/// +/// This structure provides the information necessary for an operation +/// on an I2C device +/// +typedef struct { + /// + /// Number of bytes to send to the I2C device + /// + UINT32 WriteBytes; + + /// + /// Number of bytes to read, set to zero for write only operations + /// + UINT32 ReadBytes; + + /// + /// Address of the buffer containing the data to send to the I2C device. + /// The WriteBuffer must be at least WriteBytes in length. + /// + UINT8 *WriteBuffer; + + /// + /// Address of the buffer to receive data from the I2C device. Use NULL + /// for write only operations. The ReadBuffer must be at least ReadBytes + /// in length. + /// + UINT8 *ReadBuffer; + + /// + /// Timeout for the I2C operation in 100 ns units + /// + UINT32 Timeout; +} EFI_I2C_REQUEST_PACKET; + + +/** + Set the I2C controller bus clock frequency. + + This routine must be called at or below TPL_NOTIFY. + + The software and controller do a best case effort of using the specified + frequency for the I2C bus. If the frequency does not match exactly then + the controller will use a slightly lower frequency to avoid + exceeding the operating conditions for any of the I2C devices on the bus. + For example if 400 KHz was specified and the controller's divide network + only supports 402 KHz or 398 KHz then the controller would be set to 398 + KHz. However if the desired frequency is 400 KHz and the controller only + supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED. + + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL + structure + @param[in] BusClockHertz New I2C bus clock frequency in Hertz + + @retval EFI_SUCCESS The bus frequency was set successfully. + @retval EFI_UNSUPPORTED The controller does not support this frequency. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN BusClockHertz + ); + +/** + Reset the I2C controller and configure it for use + + This routine must be called at or below TPL_NOTIFY. + + The I2C controller is reset and the I2C bus frequency is set to 100 KHz. + + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL + structure + +**/ +typedef +VOID +(EFIAPI *EFI_I2C_MASTER_RESET) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ); + +/** + Start an I2C operation on the host controller + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + This function initiates an I2C operation on the controller. + + The operation is performed by selecting the I2C device with its slave + address and then sending all write data to the I2C device. If read data + is requested, a restart is sent followed by the slave address and then + the read data is clocked into the I2C controller and placed in the read + buffer. When the operation completes, the status value is returned and + then the event is set. + + N.B. The typical consumer of this API is the I2C host driver. + Extreme care must be taken by other consumers of this API to + prevent confusing the third party I2C drivers due to a state + change at the I2C device which the third party I2C drivers did + not initiate. I2C platform drivers may use this API within + these guidelines. + + N.B. This API supports only one operation, no queuing support + exists at this layer. This API assumes that the I2C bus is in + the correct configuration for the I2C request. + + @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL + structure + @param[in] SlaveAddress Address of the device on the I2C bus. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NOT_FOUND SlaveAddress exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller cannot distinguish + when the NACK occurred. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_MASTER_START_REQUEST) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// I2C master mode protocol +/// +/// This protocol manipulates the I2C host controller to perform transactions as a +/// master on the I2C bus using the current state of any switches or multiplexers +/// in the I2C bus. +/// +struct _EFI_I2C_MASTER_PROTOCOL { + /// + /// Set the clock frequency for the I2C bus + /// + EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet; + + /// + /// Reset the I2C host controller + /// + EFI_I2C_MASTER_RESET Reset; + + /// + /// Start an I2C transaction in master mode on the host controller + /// + EFI_I2C_MASTER_START_REQUEST StartRequest; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to send on the I2C bus. + /// + UINT32 MaximumTransmitBytes; + + /// + /// The maximum number of bytes in the I2C bus transaction. + /// + UINT32 MaximumTotalBytes; +}; + +/// +/// GUID for the EFI_I2C_MASTER_PROTOCOL +/// +extern EFI_GUID gEfiI2cMasterProtocolGuid; + +#endif // __I2C_MASTER_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h new file mode 100644 index 0000000000..ba094ff807 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h @@ -0,0 +1,199 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +**/ + +#ifndef __I2C_SLAVE_H__ +#define __I2C_SLAVE_H__ + +#include + +/** + Declare the forward references + +**/ +typedef struct _EFI_I2C_SLAVE_PROTOCOL EFI_I2C_SLAVE_PROTOCOL; ///< I2C slave protocol + +/** + The I2C controller received a data byte from the + I2C msster. + + @param[in] Context The value passed to the slave enable routine. + @param[in] NumberOfBytes Number of data bytes received + @param[in] Data Buffer containing the received data bytes + + @retval EFI_SUCCESS ACK the data byte + @retval EFI_UNSUPPORTED NACK the data byte + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_DATA) ( + IN VOID *Context, + IN UINTN NumberOfBytes, + IN CONST UINT8 *Data + ); + +/** + The I2C controller received the start bit from the + I2C master. + + @param[in] Context The value passed to the slave enable routine. + +**/ +typedef +VOID +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_START) ( + IN VOID *Context, + IN UINTN BytesSent, + IN EFI_STATUS Status + ); + +/** + The I2C controller received the stop bit from the + I2C master. + + @param[in] Context The value passed to the slave enable routine. + @param[in] BytesSent Number of bytes successfully ACKed by the + I2C master. This is a hint, not all I2C + controllers support the ability to return + the number of bytes sent. When it is not + possible, the port driver returns zero. + @param[in] Status
    +
  • EFI_SUCCESS - All of the data was successfully sent
    • +
  • EFI_ABORTED - The controller was reset
    • +
  • EFI_DEVICE_ERROR - A NACK was received when sending the data.
    • +
  • EFI_END_OF_FILE - The stop bit was received before all of + the data was sent.
    • +
+ +**/ +typedef +VOID +(EFIAPI *EFI_I2C_SLAVE_RECEIVE_STOP) ( + IN VOID *Context, + IN UINTN BytesSent, + IN EFI_STATUS Status + ); + +/** + Enable or disable I2C slave operation. + + The ReceiveData callback allows the port driver to return data + to the driver or application handling slave mode operations. This + is data that a remote master has sent to the local I2C controller. + The data may be returned one byte at a time if the controller supports + the ability to ACK/NACK on each receive byte. If not, a block of + data may be returned by the I2C port driver and the ACK/NACK status + is used only as a hint for the port driver. + + The slave mode driver or application should buffer the data until + either ReceiveStart or ReceiveStop is called. At that time all of + the data is received and the command may be processed. + + ReceiveStart is called when the I2C master is expecting a response. + After processing the command, but before sending the response the + slave driver or application should mark the command as processed to + avoid processing it a second time when ReceiveStop is called. The + slave driver or application then calls SendData to send to queue the + response data for transmission. The data must remain valid in the + WriteBuffer until ReceiveStop is called. + + ReceiveStop is called when the stop bit is received on the I2C bus. + The slave driver or application starts processing the command if an + command data is pending in the slave driver's or application's buffer. + The BytesSent value is a hint to the slave driver or application as + to how much data was returned to the I2C master. If the controller + does not provide this level of support then this value is set to zero. + + @param[in] This Address of an EFI_I2C_SLAVE_PROTOCOL + structure + @param[in] SlaveAddress Slave address for the I2C controller + @param[in] Context Address of a context structure for use when + calling ReceiveData or ReceiveStop + @param[in] ReceiveData Called by the I2C port driver as data bytes + are received from the master. Response status + indicates if the byte is ACKed or NACKed. When + data is passed back a byte at a time, the port + driver must hold the clock until this callback + returns. + @param[in] ReceiveStart Called when the I2C controller receives a start bit. + @param[in] ReceiveStop Called after all of the data bytes are + received. + + @retval EFI_SUCCESS Slave operation is enabled on the controller. + @retval EFI_UNSUPPORTED The controller does not support this frequency. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_SLAVE_ENABLE) ( + IN CONST EFI_I2C_SLAVE_PROTOCOL *This, + IN UINT32 SlaveAddress, + IN VOID *Context, + IN EFI_I2C_SLAVE_RECEIVE_DATA ReceiveData, + IN EFI_I2C_SLAVE_RECEIVE_START ReceiveStart, + IN EFI_I2C_SLAVE_RECEIVE_STOP ReceiveStop + ); + +/** + Send data to the I2C master. + + Port drivers may implement this as a blocking or non-blocking call. + The data in the write buffer must remain valid until ReceiveStop or + ReceiveStart is called indicating that the I2C master has terminated + the transfer. + + @param[in] This Address of an EFI_I2C_SLAVE_PROTOCOL + structure + @param[in] WriteBytes Number of bytes to write + @param[in] WriteBuffer Buffer containing the data to send + + @retval EFI_SUCCESS Data waiting for master access. + @retval EFI_INVALID_PARAMETER WriteBuffer is NULL or WriteBytes + is zero. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_SLAVE_SEND) ( + IN CONST EFI_I2C_SLAVE_PROTOCOL *This, + IN UINTN WriteBytes, + IN CONST UINT8 *WriteBuffer + ); + +/// +/// I2C slave protocol +/// +/// The port driver publishes this protocol when slave mode is +/// supported by the controller. +/// +struct _EFI_I2C_SLAVE_PROTOCOL { + /// + /// Enable or disable I2C slave operation + /// + EFI_I2C_SLAVE_ENABLE SlaveEnable; + + /// + /// Send data to the I2C master + /// + EFI_I2C_SLAVE_SEND SendData; +}; + +/// +/// GUID for the EFI_I2C_SLAVE_PROTOCOL +/// +extern EFI_GUID gEfiI2cSlaveProtocolGuid; + +#endif // __I2C_SLAVE_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h new file mode 100644 index 0000000000..d7b54bedf9 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h @@ -0,0 +1,97 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + LpcWpc83667Policy.h + +Abstract: + + Protocol used for WPC83627 Policy definition. +------------------------------------------------------------------------------- + Rev Date Name Description + ------------------------------------------------------------------------------- + R01 < 4/22/2011> LB Update driver for Sio83627UGH support. + ------------------------------------------------------------------------------- +**/ + +#ifndef _WPC83627_POLICY_PROTOCOL_H_ +#define _WPC83627_POLICY_PROTOCOL_H_ + +EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL); + +#define EFI_WPC83627_POLICY_PROTOCOL_GUID \ + { \ + 0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d \ + } + +#define EFI_WPC83627_COM1_ENABLE 0x01 +#define EFI_WPC83627_COM2_ENABLE 0x01 + +#define EFI_WPC83627_COM3_ENABLE 0x01 +#define EFI_WPC83627_COM4_ENABLE 0x01 + +#define EFI_WPC83627_LPT1_ENABLE 0x01 +#define EFI_WPC83627_LPT1_ENABLE 0x01 +#define EFI_WPC83627_FDD_ENABLE 0x01 +#define EFI_WPC83627_FDD_WRITE_ENABLE 0x01 +#define EFI_WPC83627_PS2_KBC_ENABLE 0x01 +#define EFI_WPC83627_ECIR_ENABLE 0x01 + +#define EFI_WPC83627_COM1_DISABLE 0x00 +#define EFI_WPC83627_COM2_DISABLE 0x00 + +#define EFI_WPC83627_COM3_DISABLE 0x00 +#define EFI_WPC83627_COM4_DISABLE 0x00 + +#define EFI_WPC83627_LPT1_DISABLE 0x00 +#define EFI_WPC83627_FDD_DISABLE 0x00 +#define EFI_WPC83627_FDD_WRITE_PROTECT 0x00 +#define EFI_WPC83627_PS2_KBC_DISABLE 0x00 +#define EFI_WPC83627_ECIR_DISABLE 0x00 +#define EFI_WPC83627_RESERVED_DEFAULT 0x00 + +typedef struct { + UINT16 Com1 :1; // 0 = Disable, 1 = Enable + UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable + UINT16 Floppy :1; // 0 = Disable, 1 = Enable + UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable + UINT16 Port80 :1; // 0 = Disable, 1 = Enable + UINT16 CIR :1; // CIR enable or disable + UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable + UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable + UINT16 Com2 :1; // 0 = Disable, 1 = Enable + + UINT16 Com3 :1; // 0 = Disable, 1 = Enable + UINT16 Com4 :1; // 0 = Disable, 1 = Enable + + UINT16 Dac :1; // 0 = Disable, 1 = Enable + UINT16 Rsvd :6; +} EFI_WPC83627_DEVICE_ENABLES; + +typedef enum { + LptModeOutput, + LptModeBiDirectional, + LptModeEpp, + LptModeEcp +} EFI_LPT_MODE; + +typedef struct _EFI_WPC83627_POLICY_PROTOCOL { + EFI_WPC83627_DEVICE_ENABLES DeviceEnables; + EFI_LPT_MODE LptMode; +} EFI_WPC83627_POLICY_PROTOCOL; + +extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h new file mode 100644 index 0000000000..4c897da382 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h @@ -0,0 +1,60 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + LpcWpce791Policy.h + +Abstract: + + Protocol used for WPCE791 Policy definition. + +**/ + +#ifndef _WPCE791_POLICY_PROTOCOL_H_ +#define _WPCE791_POLICY_PROTOCOL_H_ + + +#define EFI_WPCE791_POLICY_PROTOCOL_GUID \ + { \ + 0xab2bee2f, 0xc1a6, 0x4399, 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0xd \ + } + +#define EFI_WPCE791_PS2_KEYBOARD_ENABLE 0x01 +#define EFI_WPCE791_PS2_KEYBOARD_DISABLE 0x00 + +#define EFI_WPCE791_PS2_MOUSE_ENABLE 0x01 +#define EFI_WPCE791_PS2_MOUSE_DISABLE 0x00 + +typedef struct { + UINT16 Com1 :1; // 0 = Disable, 1 = Enable + UINT16 Lpt1 :1; // 0 = Disable, 1 = Enable + UINT16 Floppy :1; // 0 = Disable, 1 = Enable + UINT16 FloppyWriteProtect :1; // 0 = Write Protect, 1 = Write Enable + UINT16 Port80 :1; // 0 = Disable, 1 = Enable + UINT16 CIR :1; // CIR enable or disable + UINT16 Ps2Keyboard :1; // 0 = Disable, 1 = Enable + UINT16 Ps2Mouse :1; // 0 = Disable, 1 = Enable + UINT16 Com2 :1; // 0 = Disable, 1 = Enable + UINT16 Dac :1; // 0 = Disable, 1 = Enable + UINT16 Rsvd :6; +} EFI_WPCE791_DEVICE_ENABLES; + +typedef struct _EFI_WPCE791_POLICY_PROTOCOL { + EFI_WPCE791_DEVICE_ENABLES DeviceEnables; +} EFI_WPCE791_POLICY_PROTOCOL; + +extern EFI_GUID gEfiLpcWpce791PolicyProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h b/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h new file mode 100644 index 0000000000..6848f52f06 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h @@ -0,0 +1,89 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#ifndef __MMIO_DEVICE_H__ +#define __MMIO_DEVICE_H__ + +// +// Protocol to define for the MMIO device +// +typedef struct { + // + // Address of a GUID + // + EFI_GUID *Guid; + + // + // Context for the protocol + // + VOID *Context; +} EFI_MMIO_DEVICE_PROTOCOL_ITEM; + + +typedef struct _EFI_MMIO_DEVICE_PROTOCOL EFI_MMIO_DEVICE_PROTOCOL; + +// +// The MMIO device protocol defines a memory mapped I/O device +// for use by the system. +// +struct _EFI_MMIO_DEVICE_PROTOCOL { + // + // Pointer to an ACPI_EXTENDED_HID_DEVICE_PATH structure + // containing HID/HidStr and CID/CidStr values. + // + // See the note below associated with the UnitIdentification + // field. + // + CONST ACPI_EXTENDED_HID_DEVICE_PATH *AcpiPath; + + // + // Allow the use of a shared template for the AcpiPath. + // + // If this value is non-zero UID value then the AcpiPath must + // be a template which contains only the HID/HidStr and CID/CidStr + // values. The UID/UidStr values in the AcpiPath must be zero! + // + // If this value is zero then the AcpiPath is not shared and + // must contain either a non-zero UID value or a UidStr value. + // + UINT32 UnitIdentification; + + // + // Hardware revision - ACPI _HRV value + // + UINT32 HardwareRevision; + + // + // Pointer to a data structure containing the controller + // resources and configuration. At a minimum this points + // to an EFI_PHYSICAL_ADDRESS for the base address of the + // MMIO device. + // + CONST VOID *DriverResources; + + // + // Number of protocols in the array + // + UINTN ProtocolCount; + + // + // List of protocols to define + // + CONST EFI_MMIO_DEVICE_PROTOCOL_ITEM *ProtocolArray; +}; + +extern EFI_GUID gEfiMmioDeviceProtocolGuid; + +#endif // __MMIO_DEVICE_H__ diff --git a/Vlv2TbltDevicePkg/Include/Protocol/Observable.h b/Vlv2TbltDevicePkg/Include/Protocol/Observable.h new file mode 100644 index 0000000000..31af6dd4ca --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/Observable.h @@ -0,0 +1,191 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Observable.h + +Abstract: + + Interface and GUID definitions for Observable protocol. + +**/ + +#ifndef _OBSERVABLE_PROTOCOL_H_ +#define _OBSERVABLE_PROTOCOL_H_ + +// +// GUID Definitions +// +#define OBSERVABLE_PROTOCOL_GUID \ + { \ + 0xe227c522, 0xd5fe, 0x4a53, 0x87, 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9 \ + } + +extern EFI_GUID gObservableProtocolGuid; + +typedef struct _OBS_OBSERVABLE_PROTOCOL OBS_OBSERVABLE_PROTOCOL; + +// +// Interface Definitions +// + +/** + Remove all observables. + + Remove all observable guids and all interfaces subscribed to them. + + @param VOID No Parameters. + + @return EFI_SUCCESS Successfully removed all observables and subscribed interfaces. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_REMOVE_ALL_OBSERVABLES) ( + VOID + ); + +/** + Interface for notification functions. + + Functions that are to be used as callbacks must inherit this interface in order to be used properly. + + @param VOID* Data Parameter context to be passed to the notification function. + + @return EFI_STATUS Varies depending on implementation. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_CALLBACK) ( + IN OUT VOID* Data + ); + +/** + Subscribe an interface with an observable guid. + + Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed + whenever the appropriate observable instance specified by ReferenceGuid calls Publish. + + @param EFI_GUID ReferenceGuid The observable guid that the callback interface will subscribe to. + OBS_NOTIFY_INTERFACE CallbackInterface A pointer to the function that is subscribing to the observable. + + @return EFI_SUCCESS Successfully subscribed the interface to the observable guid. + EFI_NOT_FOUND No match could be found between the provided guid and existing observables. + EFI_OUT_OF_RESOURCES Could not subscribe to this observer due to resource limitations. + EFI_INVALID_PARAMETER Interface is already subscribed to this observer. +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_SUBSCRIBE) ( + IN EFI_GUID ReferenceGuid, + IN OBS_CALLBACK CallbackInterface + ); + +/** + Unsubscribe an interface with an observable guid. + + Use this to remove an interface from the callback list associated with an observable guid. + + @param EFI_GUID ReferenceGuid The observable guid to unsubscribe the interface from. + OBS_NOTIFY_INTERFACE NotifyCallback A pointer to the interface that is being unsubscribed. + + @return EFI_SUCCESS Successfully unsubscribed the interface from the observable guid. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_UNSUBSCRIBE) ( + IN EFI_GUID ReferenceGuid, + IN OBS_CALLBACK CallbackInterface + ); + +/** + Notify observing functions. + + Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid. + + @param EFI_GUID ReferenceGuid The observable guid that contains the the list of interfaces to be notified. + VOID* Data Parameter context to be passed to the notification function. + + @return EFI_SUCCESS Successfully notified all observers listening to this guid. + EFI_NOT_FOUND No match could be found between the provided guid and existing observables. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_PUBLISH) ( + IN EFI_GUID ReferenceGuid, + IN OUT VOID* Data + ); + +/** + Creates a new observable. + + Create a new observable that can be observed with the use of Subscribe function. + + @param EFI_GUID ReferenceGuid The observable guid to add. + + @return EFI_SUCCESS Successfully added observable. + EFI_INVALID_PARAMETER Observable already exists. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_ADD_OBSERVABLE) ( + IN EFI_GUID ReferenceGuid + ); + +/** + Remove an observable. + + Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions + that are subscribed to this guid. + + @param EFI_GUID ReferenceGuid The observable guid to remove. + + @return EFI_SUCCESS Successfully removed observable. + +**/ +typedef +EFI_STATUS +(EFIAPI *OBS_REMOVE_OBSERVABLE) ( + IN EFI_GUID ReferenceGuid + ); + +// +// Protocol Definitions +// +typedef struct _OBS_LEAF { + OBS_CALLBACK Observer; + struct _OBS_LEAF* Next; +} OBS_LEAF; + +typedef struct _OBS_TREE { + EFI_GUID ObservableGuid; + OBS_LEAF* Leaf; + struct _OBS_TREE* Next; +} OBS_TREE; + +struct _OBS_OBSERVABLE_PROTOCOL { + OBS_ADD_OBSERVABLE AddObservable; + OBS_REMOVE_OBSERVABLE RemoveObservable; + OBS_SUBSCRIBE Subscribe; + OBS_UNSUBSCRIBE Unsubscribe; + OBS_PUBLISH Publish; + OBS_REMOVE_ALL_OBSERVABLES RemoveAllObservables; +} ; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h new file mode 100644 index 0000000000..f0d021bd70 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h @@ -0,0 +1,73 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +/** @file +**/ + +#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_ +#define _PLATFORM_GOP_POLICY_PROTOCOL_H_ + +#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \ + { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } + +#define EFI_BMP_IMAGE_GUID \ + { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } + +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01 +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222 + +#pragma pack(1) + +typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +typedef enum { + Docked, + UnDocked, + DockStatusMax +} DOCK_STATUS; + +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS *CurrentLidStatus +); + +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize +); + +#pragma pack() + +typedef struct _PLATFORM_GOP_POLICY_PROTOCOL { + UINT32 Revision; + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; + GET_VBT_DATA GetVbtData; +} PLATFORM_GOP_POLICY_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPlatformGOPPolicyGuid; + +extern EFI_GUID gBmpImageGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h b/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h new file mode 100644 index 0000000000..45add2b421 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h @@ -0,0 +1,48 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformIdeInit.h + +Abstract: + + EFI Platform Ide Init Protocol + +Revision History + +**/ + +#ifndef _EFI_PLATFORM_IDE_INIT_H_ +#define _EFI_PLATFORM_IDE_INIT_H_ + +// +// Global ID for the IDE Platform Protocol +// +#define EFI_PLATFORM_IDE_INIT_PROTOCOL_GUID \ + { 0x377c66a3, 0x8fe7, 0x4ee8, 0x85, 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e, 0x3b }; + +EFI_FORWARD_DECLARATION (EFI_PLATFORM_IDE_INIT_PROTOCOL); + + +// +// Interface structure for the Platform IDE Init Protocol +// +typedef struct _EFI_PLATFORM_IDE_INIT_PROTOCOL { + BOOLEAN SmartMode; +} EFI_PLATFORM_IDE_INIT_PROTOCOL; + +extern EFI_GUID gEfiPlatformIdeInitProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h b/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h new file mode 100644 index 0000000000..87fb5237a8 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h @@ -0,0 +1,84 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SetupMode.h + +Abstract: + + EFI Setup Mode + +Revision History + +**/ + +#ifndef _EFI_SETUP_MODE_H_ +#define _EFI_SETUP_MODE_H_ + +// +// Global ID for the Setup Mode +// +#define EFI_PLATFORM_BOOT_MODE_GUID \ + { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 } + +#define EFI_NORMAL_SETUP_GUID \ + { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } + +#define EFI_NORMAL_SETUP_RESET_NAME L"Reset" + +enum { + // + // This means: "whatever reset defaults in setup does" + // + SetupDataResetNormal = 0, + + // + // This means: "the defaults built into the BIOS" + // + SetupDataResetStandard = 1, + + // + // This means: "the manufacturing mode defaults" + // + SetupDataResetManufacturing = 2, + + // + // This means: "the oem defaults" + // + SetupDataResetOem = 3, +}; + +// +// PlatformBootMode types +// +#define PLATFORM_NORMAL_MODE 0x01 +#define PLATFORM_SAFE_MODE 0x02 +#define PLATFORM_RECOVERY_MODE 0x04 +#define PLATFORM_MANUFACTURING_MODE 0x08 +#define PLATFORM_BACK_TO_BIOS_MODE 0x10 + +extern EFI_GUID gEfiPlatformBootModeGuid; +extern EFI_GUID gEfiNormalSetupGuid; +extern CHAR16 gEfiNormalSetupName[]; +extern CHAR16 gEfiInSetupName[]; +extern CHAR16 gEfiSystemPasswordName[]; + +typedef struct { + EFI_GUID SetupGuid; + CHAR16 SetupName[0x20]; // Maximum "Setup" Name + UINT32 PlatformBootMode; +} EFI_PLATFORM_SETUP_ID; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h b/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h new file mode 100644 index 0000000000..e677be3756 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h @@ -0,0 +1,52 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + SmbiosSlotPopulation.h + +Abstract: + + EFI SMBIOS slot structure control code. + +GUID: + {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0} + 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 + +Revision History + +**/ + +#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_ +#define _EFI_SMBIOS_SLOT_POPULATION_H_ + +// +// Slot Population Protocol GUID +// +#define EFI_SMBIOS_SLOT_POPULATION_GUID \ + { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } + +typedef struct { + UINT16 SmbiosSlotId; // SMBIOS Slot ID + BOOLEAN InUse; // Does the slot have a card in it + BOOLEAN Disabled; // Should the slot information be in SMBIOS +} EFI_SMBIOS_SLOT_ENTRY; + +typedef struct { + UINT32 NumberOfEntries; + EFI_SMBIOS_SLOT_ENTRY *SlotEntries; +} EFI_SMBIOS_SLOT_POPULATION_INFO; + +extern EFI_GUID gEfiSmbiosSlotPopulationGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h b/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h new file mode 100644 index 0000000000..f76d63286f --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h @@ -0,0 +1,70 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Speaker.h + +Abstract: + + EFI Speaker Interface Protocol + +Revision History + +**/ + +#ifndef _EFI_SPEAKER_H +#define _EFI_SPEAKER_H + +// +// Global Id for Speaker Interface +// +#define EFI_SPEAKER_INTERFACE_PROTOCOL_GUID \ + { \ + 0x400b4476, 0x3081, 0x11d6, 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3, 0xb9 \ + } + +typedef struct _EFI_SPEAKER_IF_PROTOCOL EFI_SPEAKER_IF_PROTOCOL; + +// +// Beep Code +// +typedef +EFI_STATUS +(EFIAPI *EFI_GENERATE_BEEP) ( + IN EFI_SPEAKER_IF_PROTOCOL * This, + IN UINTN NumberOfBeep, + IN UINTN BeepDuration, + IN UINTN TimeInterval + ); + +// +// Set Frequency +// +typedef +EFI_STATUS +(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) ( + IN EFI_SPEAKER_IF_PROTOCOL * This, + IN UINT16 Frequency + ); + +// +// Protocol definition +// +struct _EFI_SPEAKER_IF_PROTOCOL { + EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency; + EFI_GENERATE_BEEP GenerateBeep; +} ; + +extern EFI_GUID gEfiSpeakerInterfaceProtocolGuid; +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h b/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h new file mode 100644 index 0000000000..d8047d408b --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h @@ -0,0 +1,72 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + TcoReset.h + +Abstract: + + Protocol to communicate with ICH TCO. + +GUID Info: + {A6A79162-E325-4c30-BCC3-59373064EFB3} + 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3); + + +--*/ + +#ifndef _TCO_RESET_H_ +#define _TCO_RESET_H_ + + +#define EFI_TCO_RESET_PROTOCOL_GUID \ + {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3} + +typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL; + +/** + Enables the TCO timer to reset the system in case of a system hang. This is + used when writing the clock registers. + + @param[in] RcrbGcsSaveValue This is the value of the RCRB GCS register before it is + changed by this procedure. This will be used to restore + the settings of this register in PpiDisableTcoReset. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) ( + IN UINT32 *RcrbGcsSaveValue + ); + +/** + Disables the TCO timer. This is used after writing the clock registers. + + @param[in] RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that it can + restored. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) ( + OUT UINT32 RcrbGcsRestoreValue + ); + +typedef struct _EFI_TCO_RESET_PROTOCOL { + EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset; + EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset; +} EFI_TCO_RESET_PROTOCOL; + +extern EFI_GUID gEfiTcoResetProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h b/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h new file mode 100644 index 0000000000..8ce084867d --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h @@ -0,0 +1,141 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Tpm.h + +Abstract: + + +--*/ + +#ifndef __EFI_TPM_MP_DRIVER_PROTOCOL_H__ +#define __EFI_TPM_MP_DRIVER_PROTOCOL_H__ + + +#define EFI_TPM_MP_DRIVER_PROTOCOL_GUID \ + { 0xde161cfe, 0x1e60, 0x42a1, 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 } + + +EFI_FORWARD_DECLARATION (EFI_TPM_MP_DRIVER_PROTOCOL); + +#define TPM_DRIVER_STATUS 0 +#define TPM_DEVICE_STATUS 1 + +#define TPM_DRIVER_OK 0 +#define TPM_DRIVER_FAILED 1 +#define TPM_DRIVER_NOT_OPENED 2 +#define TPM_DEVICE_OK 0 +#define TPM_DEVICE_UNRECOVERABLE 1 +#define TPM_DEVICE_RECOVERABLE 2 +#define TPM_DEVICE_NOT_FOUND 3 + +// +// Prototypes for the TPM MP Driver Protocol +// + +/** + This service Open the TPM interface + + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + @retval EFI_NOT_FOUND The component was not running + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TPM_MP_INIT) ( + IN EFI_TPM_MP_DRIVER_PROTOCOL *This + ); + +/** + This service close the TPM interface and deactivate TPM + + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + @retval EFI_NOT_FOUND The component was not running + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TPM_MP_CLOSE) ( + IN EFI_TPM_MP_DRIVER_PROTOCOL *This + ); + +/** + This service get the current status infomation of TPM + + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL. + @param[in] ReqStatusType Requested type of status information, driver or device. + @param[in] Status Pointer to the returned status. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect + @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small + @retval EFI_NOT_FOUND The component was not running + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TPM_MP_GET_STATUS_INFO) ( + IN EFI_TPM_MP_DRIVER_PROTOCOL *This, + IN UINT32 ReqStatusType, + OUT UINT32 *Status + ); + +/** + This service transmit data to the TPM and get response from TPM + + @param[in] This A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL. + @param[in] TransmitBuf Pointer to a buffer containing TPM transmit data. + @param[in] TransmitBufLen Sizeof TPM input buffer in bytes. + @param[in] ReceiveBuf Pointer to a buffer containing TPM receive data. + @param[in] ReceiveBufLen On input, size of TPM receive buffer in bytes. + On output, number of bytes written. + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_DEVICE_ERROR The command was unsuccessful + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect + @retval EFI_BUFFER_TOO_SMALL The receive buffer is too small + @retval EFI_NOT_FOUND The component was not running + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TPM_MP_TRANSMIT) ( + IN EFI_TPM_MP_DRIVER_PROTOCOL *This, + IN UINT8 *TransmitBuffer, + IN UINT32 TransmitBufferLen, + OUT UINT8 *ReceiveBuf, + IN OUT UINT32 *ReceiveBufLen + ); + + + +typedef struct _EFI_TPM_MP_DRIVER_PROTOCOL { + EFI_TPM_MP_INIT Init; + EFI_TPM_MP_CLOSE Close; + EFI_TPM_MP_GET_STATUS_INFO GetStatusInfo; + EFI_TPM_MP_TRANSMIT Transmit; +} EFI_TPM_MP_DRIVER_PROTOCOL; + +extern EFI_GUID gEfiTpmMpDriverProtocolGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h new file mode 100644 index 0000000000..31ac22ea50 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h @@ -0,0 +1,131 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + UsbPolicy.h + +Abstract: + +--*/ + +#ifndef _USB_POLICY_H_ +#define _USB_POLICY_H_ + +EFI_FORWARD_DECLARATION (EFI_USB_POLICY_PROTOCOL); + +#define USB_POLICY_GUID \ + {\ + 0xf617b358, 0x12cf, 0x414a, 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4\ + } + +#define TIANO_CODE_BASE 0x00 +#define ICBD_CODE_BASE 0x01 + +#define ATUO_TYPE 0x00 +#define USB_FDD_TYPE 0x01 +#define HDD_TYPE 0x02 +#define ZIP_TYPE 0x03 +#define CDROM_TYPE 0x04 +#define SIZE_TYPE 0x05 + +#define ZIP_FDD 0x80 + +#define FDD_EMULATION 0x00 +#define HDD_EMULATION 0x01 + +#define HIGH_SPEED 0x00 +#define FULL_SPEED 0x01 +#define SUPER_SPEED 0x02 + +#define LEGACY_KB_EN 0x01 +#define LEGACY_KB_DIS 0x00 +#define LEGACY_MS_EN 0x01 +#define LEGACY_MS_DIS 0x00 +#define LEGACY_USB_EN 0x00 +#define LEGACY_USB_DIS 0x01 +#define LEGACY_FREE_SUPP 0x01 +#define LEGACY_FREE_UN_SUPP 0x00 +#define LEGACY_PERIOD_SUPP 0x01 +#define LEGACY_PERIOD_UN_SUPP 0x00 + +#define LEGACY_USB_TIME_TUE_ENABLE 0x01 +#define LEGACY_USB_TIME_TUE_DISABLE 0x00 +#define USB_HAVE_HUB_INTERNEL 0x01 +#define USB_NOT_HAVE_HUB_INTERNEL 0x00 + +#define USB_POLICY_PROTOCOL_REVISION_1 1 +#define USB_POLICY_PROTOCOL_REVISION_2 2 + +#ifndef __GNUC__ +#pragma warning ( disable : 4306 ) +#pragma warning ( disable : 4054 ) +#endif + +#define GET_USB_CFG (UsbCfg);\ + do{\ + UINT16 *pSegOfEbda;\ + UINT32 mToEbda;\ + pSegOfEbda = (UINT16 *)(UINTN)0x40E;\ + mToEbda = (UINT32)(((UINTN)(*pSegOfEbda) << 4) + 0x80);\ + UsbCfg = (USB_CFG *)(UINTN)mToEbda;\ + }while(0); + +#pragma pack(1) +typedef struct { + UINT8 HasUSBKeyboard:1; + UINT8 HasUSBMouse:1; + UINT8 LegacyFreeSupport:1; + UINT8 UsbOperationMode:1; + UINT8 LegacyKBEnable:1; + UINT8 LegacyMSEnable:1; + UINT8 USBPeriodSupport:1; + UINT8 Reserved:1; +} USB_DEVICE_INFOR; + +typedef struct { + UINT8 Codebase; + UINT8 USBHDDForceType; + UINT8 Configurated; + UINT8 LpcAcpiBase; + UINT8 AcpiTimerReg; + UINT8 Reserved1[0x01]; + UINT8 LegacyUsbEnable; + USB_DEVICE_INFOR UsbDeviceInfor; + UINT16 UsbEmulationSize; + UINT8 Reserved2[0x06]; +} USB_CFG; +#pragma pack() + +typedef struct _EFI_USB_POLICY_PROTOCOL{ + UINT8 Version; + UINT8 UsbMassStorageEmulationType; // 1: FDD_Type; 2: HDD_Type; other:Auto_Type* + UINT8 UsbOperationMode; // 0: High_Speed; 1: Full_Speed; + UINT8 LegacyKBEnable; // 0: Disabled; 1: Enabled* + UINT8 LegacyMSEnable; // 0: Disabled; 1: Enabled* + UINT8 USBPeriodSupport; // 0; Unsupport; 1: Support + UINT8 LegacyUsbEnable; // 1: Disabled; 0: Enabled* + UINT8 LegacyFreeSupport; // 0: Unsupport; 1: Support + UINT8 CodeBase; + UINT8 LpcAcpiBase; // 40h(default) + UINT8 AcpiTimerReg; + UINT8 UsbTimeTue; + UINT8 InternelHubExist; // 1: Host have internel hub on board; 0: No internel hub on board + UINT8 EnumWaitPortStableStall; // Value for wait port stable when enum a new dev. + UINT16 UsbEmulationSize; // Mbytes. + UINT8 UsbZipEmulationType; + UINT8 Reserved[3]; // Reserved fields for future expansion w/o protocol change +} EFI_USB_POLICY_PROTOCOL; + +extern EFI_GUID gUsbPolicyGuid; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h new file mode 100644 index 0000000000..8e500935d0 --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h @@ -0,0 +1,108 @@ +/** + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvPlatformPolicy.h + +Abstract: + + Interface definition details between MCH and platform drivers during DXE phase. + +--*/ + +#ifndef _VLV_PLATFORM_POLICY_H_ +#define _VLV_PLATFORM_POLICY_H_ + +// +// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-B6AD-B812F6881CD6} +// +#define DXE_VLV_PLATFORM_POLICY_GUID \ + {0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6} + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gDxeVlvPlatformPolicyGuid; + +// +// Protocol revision number +// Any backwards compatible changes to this protocol will result in an update in the revision number +// Major changes will require publication of a new protocol +// +#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0 + + +typedef struct { + UINT8 PFITStatus; + UINT8 IgdTheramlSupport; + UINT8 ALSEnabled; + UINT8 LidStatus; +} IGD_PANEL_FEATURES; + +typedef struct { + UINT8 Reserved00; + UINT8 Reserved01; + UINT16 Reserved02; + UINT16 Reserved03; + UINT16 Reserved04; + UINT16 Reserved05; + UINT16 Reserved06; + UINT16 Reserved07; + UINT16 Reserved08; + UINT16 Reserved09; + UINT16 Reserved0A; + UINT16 Reserved0B; + UINT16 Reserved0C; + UINT16 Reserved0D; + UINT8 Reserved0E; + UINT8 Reserved0F; + UINT32 Reserved10; + UINT32 Reserved11; + UINT32 Reserved12; + UINT32 Reserved13; + UINT32 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; +} DPTF_SETTINGS; + +// +// MCH DXE Platform Policiy ================================================== +// + +#define NO_AUDIO 0 +#define HD_AUDIO 1 +#define LPE_AUDIO 2 + +typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + IGD_PANEL_FEATURES IgdPanelFeatures; + DPTF_SETTINGS Reserved; + UINT8 GraphicReserve00; + UINT8 GraphicsPerfAnalyzers; + UINT8 PwmReserved00; + UINT8 PwmReserved01; + UINT8 PmSupport; + UINT8 GraphicReserve01; + UINT8 GfxPause; + UINT8 GraphicsFreqReq; + UINT8 GraphicReserve03; + UINT8 GraphicReserve02; + UINT8 GraphicReserve04; + UINT8 PavpMode; + UINT8 GraphicReserve05; + UINT8 UlClockGating; + UINT8 IdleReserve; + UINT8 AudioTypeSupport; + UINT8 GraphicReserve06; +} DXE_VLV_PLATFORM_POLICY_PROTOCOL; + +#endif diff --git a/Vlv2TbltDevicePkg/Include/SetupMode.h b/Vlv2TbltDevicePkg/Include/SetupMode.h new file mode 100644 index 0000000000..f0ec67c08e --- /dev/null +++ b/Vlv2TbltDevicePkg/Include/SetupMode.h @@ -0,0 +1,90 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SetupMode.h + +Abstract: + + EFI Setup Mode + + + +--*/ + +#ifndef _EFI_SETUP_MODE_H_ +#define _EFI_SETUP_MODE_H_ + +// +// Global ID for the Setup Mode +// +#define EFI_PLATFORM_BOOT_MODE_GUID \ + { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 } + +#define EFI_NORMAL_SETUP_GUID \ + { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } + +#define EFI_NORMAL_SETUP_RESET_NAME L"Reset" + +enum { + // + // This means: "whatever reset defaults in setup does" + // + SetupDataResetNormal = 0, + + // + // This means: "the defaults built into the BIOS" + // + SetupDataResetStandard = 1, + + // + // This means: "the manufacturing mode defaults" + // + SetupDataResetManufacturing = 2, + + // + // This means: "the oem defaults" + // + SetupDataResetOem = 3, +}; + +// +// PlatformBootMode types +// +#define PLATFORM_NORMAL_MODE 0x01 +#define PLATFORM_SAFE_MODE 0x02 +#define PLATFORM_RECOVERY_MODE 0x04 +#define PLATFORM_MANUFACTURING_MODE 0x08 +#define PLATFORM_BACK_TO_BIOS_MODE 0x10 + +extern EFI_GUID gEfiPlatformBootModeGuid; + +#define NORMAL_SETUP_NAME L"Setup" +#define IN_SETUP_NAME L"InSetup" +#define SYSTEM_PASSWORD_NAME L"SystemPassword" +#define BOOT_TIME_NAME L"BootTime" + +extern EFI_GUID gEfiNormalSetupGuid; +extern CHAR16 gEfiNormalSetupName[]; +extern CHAR16 gEfiInSetupName[]; +extern CHAR16 gEfiSystemPasswordName[]; + +typedef struct { + EFI_GUID SetupGuid; + CHAR16 SetupName[0x20]; // Maximum "Setup" Name + UINT32 PlatformBootMode; +} EFI_PLATFORM_SETUP_ID; + +#endif -- cgit v1.2.3