From 3cbfba02fef9dae07a041fdbf2e89611d72d6f90 Mon Sep 17 00:00:00 2001 From: David Wei Date: Mon, 12 Jan 2015 09:37:20 +0000 Subject: Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei Reviewed-by: Mike Wu Reviewed-by: Hot Tian git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524 --- Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c | 426 ++++++ Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c | 49 + Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c | 324 +++++ Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c | 148 ++ Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c | 173 +++ Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h | 76 + Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c | 77 + Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c | 345 +++++ Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c | 369 +++++ Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c | 813 +++++++++++ .../PlatformInitPei/PlatformEarlyInit.c | 1034 ++++++++++++++ .../PlatformInitPei/PlatformEarlyInit.h | 1502 ++++++++++++++++++++ .../PlatformInitPei/PlatformInfoInit.c | 186 +++ .../PlatformInitPei/PlatformInitPei.inf | 122 ++ .../PlatformInitPei/PlatformSsaInitPeim.c | 63 + Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c | 366 +++++ Vlv2TbltDevicePkg/PlatformInitPei/Stall.c | 96 ++ 17 files changed, 6169 insertions(+) create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c create mode 100644 Vlv2TbltDevicePkg/PlatformInitPei/Stall.c (limited to 'Vlv2TbltDevicePkg/PlatformInitPei') diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c b/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c new file mode 100644 index 0000000000..174d8e974e --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c @@ -0,0 +1,426 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + BootMode.c + +Abstract: + + EFI PEIM to provide the platform support functionality on the Thurley. + + +--*/ + +#include "PlatformEarlyInit.h" + + +#define NORMALMODE 0 +#define RECOVERYMODE 1 +#define SAFEMODE 2 +#define MANUFACTURINGMODE 3 + +#define GPIO_SSUS_OFFSET 0x2000 +#define PMU_PWRBTN_B_OFFSET 0x88 + +EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiBootInRecoveryModePpiGuid, + NULL +}; + +/** + Return the setting of the Bios configuration jumper + + @param VOID + + @retval RECOVERYMODE jumper set to recovery mode + @retval SAFEMODE jumper set to config mode + @retval NORMALMODE jumper in normal mode + +**/ +UINTN +GetConfigJumper( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + // + // Do the Forced recovery detection based on logic chart above + // + if (IsRecoveryJumper(PeiServices, PlatformInfoHob)) { + return RECOVERYMODE; + } else { + return NORMALMODE; + } +} + +BOOLEAN +CheckIfRecoveryMode( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + if (GetConfigJumper(PeiServices, PlatformInfoHob) == RECOVERYMODE) { + return TRUE; + } + return FALSE; +} + +BOOLEAN +CheckIfSafeMode( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + if (GetConfigJumper(PeiServices, PlatformInfoHob) == SAFEMODE) { + return TRUE; + } + return FALSE; +} + +BOOLEAN +CheckIfManufacturingMode ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINT32 Attributes; + UINTN DataSize; + CHAR16 VarName[] = MFGMODE_VARIABLE_NAME; + UINT8 MfgMode; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + ASSERT_EFI_ERROR (Status); + + // + // Check if SW MMJ mode + // + Attributes = (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS); + DataSize = sizeof (MFG_MODE_VAR); + + Status = Variable->GetVariable ( + Variable, + VarName, + &gMfgModeVariableGuid, + &Attributes, + &DataSize, + &MfgMode + ); + if (!(EFI_ERROR (Status))) { + return TRUE; + } + return FALSE; +} + +EFI_STATUS +UpdateBootMode ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT16 SleepType; + CHAR16 *strBootMode; + PEI_CAPSULE_PPI *Capsule; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + SYSTEM_CONFIGURATION SystemConfiguration; + UINTN VarSize; + volatile UINT32 GpioValue; + BOOLEAN IsFirstBoot; + UINT32 Data32; + + Status = (*PeiServices)->GetBootMode( + PeiServices, + &BootMode + ); + ASSERT_EFI_ERROR (Status); + if (BootMode == BOOT_IN_RECOVERY_MODE){ + return Status; + } + GetWakeupEventAndSaveToHob (PeiServices); + + // + // Let's assume things are OK if not told otherwise + // + BootMode = BOOT_WITH_FULL_CONFIGURATION; + + // + // When this boot is WDT reset, the system needs booting with CrashDump function eanbled. + // + Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS); + + // + // Check Power Button, click the power button, the system will boot in fast boot mode, + // if it is pressed and hold for a second, it will boot in FullConfiguration/setup mode. + // + GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + PMU_PWRBTN_B_OFFSET); // The value of GPIOS_16 (PMU_PWRBTN_B) + if (((GpioValue & BIT0) != 0)&&((Data32 & B_PCH_TCO_STS_SECOND_TO) != B_PCH_TCO_STS_SECOND_TO)){ + IsFirstBoot = PcdGetBool(PcdBootState); + if (!IsFirstBoot){ + VarSize = sizeof (SYSTEM_CONFIGURATION); + ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION)); + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + ASSERT_EFI_ERROR (Status); + + // + // Use normal setup default from NVRAM variable, + // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable. + // + VarSize = sizeof(SYSTEM_CONFIGURATION); + Status = Variable->GetVariable ( + Variable, + L"Setup", + &gEfiSetupVariableGuid, + NULL, + &VarSize, + &SystemConfiguration + ); + + if (SystemConfiguration.FastBoot == 1) { + BootMode = BOOT_WITH_MINIMAL_CONFIGURATION; + } + } + } + + // + // Check if we need to boot in forced recovery mode + // + if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) { + BootMode = BOOT_IN_RECOVERY_MODE; + } + + if (BootMode == BOOT_IN_RECOVERY_MODE) { + Status = (*PeiServices)->InstallPpi ( + PeiServices, + &mPpiListRecoveryBootMode + ); + ASSERT_EFI_ERROR (Status); + } else { + if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode = BOOT_ON_S3_RESUME; + + // + // Determine if we're in capsule update mode + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gPeiCapsulePpiGuid, + 0, + NULL, + (void **)&Capsule + ); + + if (Status == EFI_SUCCESS) { + if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices) == EFI_SUCCESS) { + BootMode = BOOT_ON_FLASH_UPDATE; + } + } + + break; + + case V_PCH_ACPI_PM1_CNT_S4: + BootMode = BOOT_ON_S4_RESUME; + break; + + case V_PCH_ACPI_PM1_CNT_S5: + BootMode = BOOT_ON_S5_RESUME; + break; + } // switch (SleepType) + } + + // + // Check for Safe Mode + // + } + + switch (BootMode) { + case BOOT_WITH_FULL_CONFIGURATION: + strBootMode = L"BOOT_WITH_FULL_CONFIGURATION"; + break; + case BOOT_WITH_MINIMAL_CONFIGURATION: + strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION"; + break; + case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES: + strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES"; + break; + case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS: + strBootMode = L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS"; + break; + case BOOT_WITH_DEFAULT_SETTINGS: + strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS"; + break; + case BOOT_ON_S4_RESUME: + strBootMode = L"BOOT_ON_S4_RESUME"; + break; + case BOOT_ON_S5_RESUME: + strBootMode = L"BOOT_ON_S5_RESUME"; + break; + case BOOT_ON_S2_RESUME: + strBootMode = L"BOOT_ON_S2_RESUME"; + break; + case BOOT_ON_S3_RESUME: + strBootMode = L"BOOT_ON_S3_RESUME"; + break; + case BOOT_ON_FLASH_UPDATE: + strBootMode = L"BOOT_ON_FLASH_UPDATE"; + break; + case BOOT_IN_RECOVERY_MODE: + strBootMode = L"BOOT_IN_RECOVERY_MODE"; + break; + default: + strBootMode = L"Unknown boot mode"; + } // switch (BootMode) + + DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode)); + Status = (*PeiServices)->SetBootMode( + PeiServices, + BootMode + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Get sleep type after wakeup + + @param PeiServices Pointer to the PEI Service Table. + @param SleepType Sleep type to be returned. + + @retval TRUE A wake event occured without power failure. + @retval FALSE Power failure occured or not a wakeup. + +**/ +BOOLEAN +GetSleepTypeAfterWakeup ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT16 *SleepType + ) +{ + UINT16 Pm1Sts; + UINT16 Pm1Cnt; + UINT16 GenPmCon1; + GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1); + + // + // Read the ACPI registers + // + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS); + Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT); + + if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) || + (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) { + // + // If power failure indicator, then don't attempt s3 resume. + // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has + // lost already. This is to make sure no one will use PM1_CNT to check for S3 after + // power failure. + // + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) { + Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5); + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + // + // Clear Wake Status (WAK_STS) + // + IoWrite16 ((ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS), B_PCH_ACPI_PM1_STS_WAK); + } + // + // Get sleep type if a wake event occurred and there is no power failure + // + if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) { + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP; + return TRUE; + } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4){ + *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP; + return TRUE; + } + return FALSE; +} + +VOID +SetPlatformBootMode ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + EFI_PLATFORM_SETUP_ID PlatformSetupId; + + ZeroMem(&PlatformSetupId, sizeof (EFI_PLATFORM_SETUP_ID)); + + CopyMem (&PlatformSetupId.SetupGuid, + &gEfiNormalSetupGuid, + sizeof (EFI_GUID)); + + if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) { + // + // Recovery mode + // + CopyMem (&PlatformSetupId.SetupName, + SAFE_SETUP_NAME, + StrSize (SAFE_SETUP_NAME)); + PlatformSetupId.PlatformBootMode = PLATFORM_RECOVERY_MODE; + } else if (CheckIfSafeMode(PeiServices, PlatformInfoHob)) { + // + // Safe mode also called config mode or maintenace mode. + // + CopyMem (&PlatformSetupId.SetupName, + SAFE_SETUP_NAME, + StrSize (SAFE_SETUP_NAME)); + PlatformSetupId.PlatformBootMode = PLATFORM_SAFE_MODE; + + } else if(0) { // else if (CheckIfManufacturingMode(PeiServices)) { + // + // Manufacturing mode + // + CopyMem (&PlatformSetupId.SetupName, + MANUFACTURE_SETUP_NAME, + StrSize (MANUFACTURE_SETUP_NAME)); + PlatformSetupId.PlatformBootMode = PLATFORM_MANUFACTURING_MODE; + + } else { + // + // Default to normal mode. + // + CopyMem (&PlatformSetupId.SetupName, + &NORMAL_SETUP_NAME, + StrSize (NORMAL_SETUP_NAME)); + PlatformSetupId.PlatformBootMode = PLATFORM_NORMAL_MODE; + } + + BuildGuidDataHob ( + &gEfiPlatformBootModeGuid, + &PlatformSetupId, + sizeof (EFI_PLATFORM_SETUP_ID) + ); + return; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c new file mode 100644 index 0000000000..f75bacef48 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c @@ -0,0 +1,49 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + CpuInitPeim.c + +Abstract: + + Functions for LpcSio initilization + It is needed for early onboard LAN controller disable/enable in platform setup. + +--*/ + +#include "PlatformEarlyInit.h" + + +EFI_STATUS +PlatformCpuInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN EFI_PLATFORM_CPU_INFO *PlatformCpuInfo + ) +{ + BOOLEAN ResetRequired; + + // + // Variable initialization + // + ResetRequired = FALSE; + + + if (ResetRequired) { + CpuOnlyReset(PeiServices); + } + + return EFI_SUCCESS; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c b/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c new file mode 100644 index 0000000000..e4dd2d68f0 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c @@ -0,0 +1,324 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + Dimm.c + +Abstract: + + PPI for reading SPD modules on DIMMs. + +--*/ + + +// +// Header Files +// +#include "Platformearlyinit.h" + +#define DIMM_SOCKETS 4 // Total number of DIMM sockets allowed on + // the platform +#define DIMM_SEGMENTS 1 // Total number of Segments Per DIMM. +#define MEMORY_CHANNELS 2 // Total number of memory channels + // populated on the system board +// +// Prototypes +// + +EFI_STATUS +EFIAPI +GetDimmState ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + OUT PEI_PLATFORM_DIMM_STATE *State + ); + +EFI_STATUS +EFIAPI +SetDimmState ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + IN PEI_PLATFORM_DIMM_STATE *State + ); + +EFI_STATUS +EFIAPI +ReadSpd ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + IN UINT8 Offset, + IN UINTN Count, + IN OUT UINT8 *Buffer + ); + +static PEI_PLATFORM_DIMM_PPI mGchDimmPpi = { + DIMM_SOCKETS, + DIMM_SEGMENTS, + MEMORY_CHANNELS, + GetDimmState, + SetDimmState, + ReadSpd +}; + +static EFI_PEI_PPI_DESCRIPTOR mPpiPlatformDimm = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiPlatformDimmPpiGuid, + &mGchDimmPpi +}; + + +// +// Functions +// + +/** + This function returns the current state of a single DIMM. Present indicates + that the DIMM slot is physically populated. Disabled indicates that the DIMM + should not be used. + + @param PeiServices PEI services table pointer + @param This PPI pointer + @param Dimm DIMM to read from + @param State Pointer to a return buffer to be updated with the current state + of the DIMM + + @retval EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +GetDimmState ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + OUT PEI_PLATFORM_DIMM_STATE *State + ) +{ + EFI_STATUS Status; + UINT8 Buffer; + + PEI_ASSERT (PeiServices, (Dimm < This->DimmSockets)); + + // + // A failure here does not necessarily mean that no DIMM is present. + // Read a single byte. All we care about is the return status. + // + Status = ReadSpd ( + PeiServices, + This, + Dimm, + 0, + 1, + &Buffer + ); + + if (EFI_ERROR (Status)) { + State->Present = 0; + } else { + State->Present = 1; + } + + // + // BUGBUG: Update to check platform variable when it is available + // + State->Disabled = 0; + State->Reserved = 0; + + return EFI_SUCCESS; +} + +/** + + This function updates the state of a single DIMM. + + @param PeiServices PEI services table pointer + @param This PPI pointer + @param Dimm DIMM to set state for + @param State Pointer to the state information to set. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_UNSUPPORTED The function is not supported. + +**/ +EFI_STATUS +EFIAPI +SetDimmState ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + IN PEI_PLATFORM_DIMM_STATE *State + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function reads SPD information from a DIMM. + + PeiServices PEI services table pointer + This PPI pointer + Dimm DIMM to read from + Offset Offset in DIMM + Count Number of bytes + Buffer Return buffer + + @param EFI_SUCCESS The function completed successfully. + @param EFI_DEVICE_ERROR The DIMM being accessed reported a device error, + does not have an SPD module, or is not installed in + the system. + @retval EFI_TIMEOUT Time out trying to read the SPD module. + @retval EFI_INVALID_PARAMETER A parameter was outside the legal limits. + +**/ +EFI_STATUS +EFIAPI +ReadSpd ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_DIMM_PPI *This, + IN UINT8 Dimm, + IN UINT8 Offset, + IN UINTN Count, + IN OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + PEI_SMBUS_PPI *Smbus; + UINTN Index; + UINTN Index1; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_SMBUS_DEVICE_COMMAND Command; + UINTN Length; + + Status = (**PeiServices).LocatePpi ( + PeiServices, + &gPeiSmbusPpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + &Smbus // PPI + ); + ASSERT_PEI_ERROR (PeiServices, Status); + + switch (Dimm) { + case 0: + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_1 >> 1; + break; + case 1: + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_2 >> 1; + break; + case 2: + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_1 >> 1; + break; + case 3: + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_2 >> 1; + break; + default: + return EFI_INVALID_PARAMETER; + } + + Index = Count % 4; + if (Index != 0) { + // + // read the first serveral bytes to speed up following reading + // + for (Index1 = 0; Index1 < Index; Index1++) { + Length = 1; + Command = Offset + Index1; + Status = Smbus->Execute ( + PeiServices, + Smbus, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + &Buffer[Index1] + ); + if (EFI_ERROR(Status)) { + return Status; + } + } + } + + // + // Now collect all the remaining bytes on 4 bytes block + // + for (; Index < Count; Index += 2) { + Command = Index + Offset; + Length = 2; + Status = Smbus->Execute ( + PeiServices, + Smbus, + SlaveAddress, + Command, + EfiSmbusReadWord, + FALSE, + &Length, + &Buffer[Index] + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Index += 2; + Command = Index + Offset; + Length = 2; + Status = Smbus->Execute ( + PeiServices, + Smbus, + SlaveAddress, + Command, + EfiSmbusReadWord, + FALSE, + &Length, + &Buffer[Index] + ); + if (EFI_ERROR(Status)) { + return Status; + } + } + return EFI_SUCCESS; +} + +/** + This function initializes the PEIM. It simply installs the DIMM PPI. + + @param FfsHeader Not used by this function + @param PeiServices Pointer to PEI services table + + @retval EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +PeimInitializeDimm ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi + ) +{ + EFI_STATUS Status; + + Status = (**PeiServices).InstallPpi ( + PeiServices, + &mPpiPlatformDimm + ); + ASSERT_PEI_ERROR (PeiServices, Status); + + return EFI_SUCCESS; +} + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c b/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c new file mode 100644 index 0000000000..282faa85ff --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c @@ -0,0 +1,148 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + FlashMap.c + +Abstract: + + Build GUIDed HOBs for platform specific flash map. + +--*/ + +#include "Efi.h" +#include "Pei.h" +#include "PeiLib.h" +#include "PeiLib.h" +#include "EfiFlashMap.h" +#include EFI_PROTOCOL_CONSUMER (FirmwareVolumeBlock) +#include EFI_GUID_DEFINITION (FlashMapHob) +#include EFI_GUID_DEFINITION (SystemNvDataGuid) +#include EFI_GUID_DEFINITION (FirmwareFileSystem) + +EFI_GUID mFvBlockGuid = EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID; +EFI_GUID mFfsGuid = EFI_FIRMWARE_FILE_SYSTEM_GUID; +EFI_GUID mSystemDataGuid = EFI_SYSTEM_NV_DATA_HOB_GUID; + +static EFI_FLASH_AREA_DATA mFlashAreaData[] = { + // + // Variable area + // + { FixedPcdGet32 (PcdFlashNvStorageVariableBase), + FixedPcdGet32 (PcdFlashNvStorageVariableSize), + EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV, + EFI_FLASH_AREA_EFI_VARIABLES }, + + // + // Boot block 2nd part + // + { FixedPcdGet32 (PcdFlashFvRecovery2Base), + FixedPcdGet32 (PcdFlashFvRecovery2Size), + EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV, + EFI_FLASH_AREA_FTW_BACKUP }, + + // + // Recovery FV + // + { FixedPcdGet32 (PcdFlashFvRecoveryBase), + FixedPcdGet32 (PcdFlashFvRecoverySize), + EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV, + EFI_FLASH_AREA_RECOVERY_BIOS }, + + // + // Main FV + // + { FixedPcdGet32 (PcdFlashFvMainBase), + FixedPcdGet32 (PcdFlashFvMainSize), + EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV, + EFI_FLASH_AREA_MAIN_BIOS } + +}; + +#define NUM_FLASH_AREA_DATA (sizeof (mFlashAreaData) / sizeof (mFlashAreaData[0])) + +/** + Build GUID HOBs for platform specific flash map. + + @param FfsHeader Pointer this FFS file header. + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS Guid HOBs for platform flash map is built. + @retval Otherwise Failed to build the Guid HOB data. + +**/ +EFI_STATUS +PeimInitializeFlashMap ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + UINTN Index; + EFI_FLASH_AREA_HOB_DATA FlashHobData; + + // + // Build flash area entries as GUIDed HOBs. + // + for (Index = 0; Index < NUM_FLASH_AREA_DATA; Index++) { + ZeroMem(&FlashHobData, sizeof (EFI_FLASH_AREA_HOB_DATA)); + + FlashHobData.AreaType = mFlashAreaData[Index].AreaType; + FlashHobData.NumberOfEntries = 1; + FlashHobData.SubAreaData.Attributes = mFlashAreaData[Index].Attributes; + FlashHobData.SubAreaData.Base = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Base; + FlashHobData.SubAreaData.Length = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Length; + + switch (FlashHobData.AreaType) { + case EFI_FLASH_AREA_RECOVERY_BIOS: + case EFI_FLASH_AREA_MAIN_BIOS: + CopyMem ( + &FlashHobData.AreaTypeGuid, + &mFfsGuid, + sizeof (EFI_GUID) + ); + CopyMem ( + &FlashHobData.SubAreaData.FileSystem, + &mFvBlockGuid, + sizeof (EFI_GUID) + ); + break; + + case EFI_FLASH_AREA_GUID_DEFINED: + CopyMem ( + &FlashHobData.AreaTypeGuid, + &mSystemDataGuid, + sizeof (EFI_GUID) + ); + CopyMem ( + &FlashHobData.SubAreaData.FileSystem, + &mFvBlockGuid, + sizeof (EFI_GUID) + ); + break; + + default: + break; + } + + PeiBuildHobGuidData(PeiServices, + &gEfiFlashMapHobGuid, + &FlashHobData, + sizeof (EFI_FLASH_AREA_HOB_DATA) + ); + } + return EFI_SUCCESS; +} + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c new file mode 100644 index 0000000000..7ec276b089 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c @@ -0,0 +1,173 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + LegacySpeaker.c + +Abstract: + + This file implements PEIM for Legacy Speaker. This file is valid for platforms both + on IA32 and Itanium Product Family + +--*/ + +#include "PlatformEarlyInit.h" + +EFI_STATUS +OutputBeep ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN NumberOfBeep, + IN UINTN BeepDuration, + IN UINTN TimerInterval + ); + +/** + This function will enable the speaker to generate beep + + @param PeiServices PeiServices to locate PPI + + @retval EFI_STATUS + +**/ +EFI_STATUS +TurnOnSpeaker ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + UINT8 Data; + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT); + Data |= 0x03; + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data); + return EFI_SUCCESS; +} + +/** + This function will stop beep from speaker. + + @param PeiServices PeiServices to locate PPI + + @retval Status + +**/ +EFI_STATUS +TurnOffSpeaker ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + UINT8 Data; + + Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT); + Data &= 0xFC; + IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data); + return EFI_SUCCESS; +} + + +EFI_STATUS +OutputBeep ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN NumberOfBeep, + IN UINTN BeepDuration, + IN UINTN TimeInterval + ) +{ + UINTN Num; + EFI_PEI_STALL_PPI* StallPpi; + + (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, (void **)&StallPpi); + + for (Num=0; Num < NumberOfBeep; Num++) { + TurnOnSpeaker (PeiServices); + StallPpi->Stall(PeiServices, StallPpi, BeepDuration); + TurnOffSpeaker(PeiServices); + StallPpi->Stall(PeiServices, StallPpi, TimeInterval); + } + + return EFI_SUCCESS; +} + +/** + This function will program the speaker tone frequency. The value should be with 64k + boundary since it takes only 16 bit value which gets programmed in two step IO opearattion + + Frequency - A value which should be 16 bit only. + + EFI_SUCESS + +**/ +EFI_STATUS +EFIAPI +ProgramToneFrequency ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 Frequency + ) +{ + UINT8 Data; + + Data = 0xB6; + IoWrite8(EFI_TIMER_CONTROL_PORT, Data); + + Data = (UINT8)(Frequency & 0x00FF); + IoWrite8(EFI_TIMER_2_PORT, Data); + Data = (UINT8)((Frequency & 0xFF00) >> 8); + IoWrite8(EFI_TIMER_2_PORT, Data); + return EFI_SUCCESS; +} + +/** + This function will generate the beep for specified duration. + + @param PeiServices PeiServices to locate various PPIs + @param NumberOfBeeps Number of beeps which user want to produce + @param BeepDuration Duration for speaker gate need to be enabled + @param TimeInterval Interval between each beep + + @retval EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +GenerateBeepTone ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN NumberOfBeeps, + IN UINTN BeepDuration, + IN UINTN TimeInterval + ) +{ + + if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0)) { + TurnOnSpeaker (PeiServices); + return EFI_SUCCESS; + } + + if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0)) { + TurnOffSpeaker (PeiServices); + return EFI_SUCCESS; + } + + if (BeepDuration == 0) { + BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION; + } + + if (TimeInterval == 0) { + TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL; + } + + OutputBeep (PeiServices, NumberOfBeeps, BeepDuration, TimeInterval); + return EFI_SUCCESS; + + +} + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h new file mode 100644 index 0000000000..7f806a7a29 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h @@ -0,0 +1,76 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + LegacySpeaker.h + +Abstract: + + Speaker enabling related data + +--*/ + +#ifndef _PEI_LEGACY_SPEAKER_H +#define _PEI_LEGACY_SPEAKER_H + + +// +// Speaker Related Port Information +// +#define EFI_TIMER_COUNTER_PORT 0x40 +#define EFI_TIMER_CONTROL_PORT 0x43 +#define EFI_TIMER_2_PORT 0x42 +#define EFI_SPEAKER_CONTROL_PORT 0x61 + +#define EFI_SPEAKER_OFF_MASK 0xFC + +#define EFI_DEFAULT_BEEP_FREQUENCY 0x500 + +// +// Default Intervals/Beep Duration +// +#define EFI_DEFAULT_LONG_BEEP_DURATION 0x70000 +#define EFI_DEFAULT_SHORT_BEEP_DURATION 0x50000 +#define EFI_DEFAULT_BEEP_TIME_INTERVAL 0x20000 + + +EFI_STATUS +EFIAPI +ProgramToneFrequency ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 Frequency + ); + + +EFI_STATUS +EFIAPI +GenerateBeepTone ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN NumberOfBeeps, + IN UINTN BeepDuration, + IN UINTN TimeInterval + ); + +EFI_STATUS +TurnOnSpeaker ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +TurnOffSpeaker ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +#endif diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c new file mode 100644 index 0000000000..4cad67c541 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c @@ -0,0 +1,77 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + MchInit.c + +Abstract: + + +--*/ + + +#include "PlatformEarlyInit.h" + +#define PSE_PAGE_SIZE 0x400000 // 4MB + +extern BOOLEAN ImageInMemory; + + +VOID +EfiCommonLibEnablePsePaging ( + IN UINT32 PDBR + ); + +VOID +EfiCommonLibDisablePsePaging ( + ); + +/** + + Initialize the MCH Thermal Sensor + +**/ +VOID +InitMchThermalSensor() +{ +} + +/** + + Programs and enables the CRID for MCH and ICH + +**/ +VOID +ProgramMchCRID( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ +} + +/** + + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers + +**/ +VOID +MchInit ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + + return; +} + + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c new file mode 100644 index 0000000000..31cc88a576 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c @@ -0,0 +1,345 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + MemoryCallback.c + +Abstract: + + EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport. + +--*/ + +#include "PlatformEarlyInit.h" + + +VOID +UpdateDefaultSetupValue ( + IN EFI_PLATFORM_INFO_HOB *PlatformInfo + ) +{ +return; +} + +/** + PEI termination callback. + + @param PeiServices General purpose services available to every PEIM. + @param NotifyDescriptor Not uesed. + @param Ppi Not uesed. + + @retval EFI_SUCCESS If the interface could be successfully + installed. + +**/ +EFI_STATUS +EFIAPI +EndOfPeiPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + UINT64 MemoryTop; + UINT64 LowUncableBase; + EFI_PLATFORM_INFO_HOB *PlatformInfo; + UINT32 HecBaseHigh; + EFI_BOOT_MODE BootMode; + EFI_PEI_HOB_POINTERS Hob; + + Status = (*PeiServices)->GetBootMode( + PeiServices, + &BootMode + ); + + ASSERT_EFI_ERROR (Status); + + // + // Set the some PCI and chipset range as UC + // And align to 1M at leaset + // + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw != NULL); + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw); + + UpdateDefaultSetupValue (PlatformInfo); + + DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm)); + DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase)); + DEBUG ( + (EFI_D_ERROR, + "PCIE BASE: %lX Size : %X\n", + PlatformInfo->PciData.PciExpressBase, + PlatformInfo->PciData.PciExpressSize) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI32 BASE: %X Limit: %X\n", + PlatformInfo->PciData.PciResourceMem32Base, + PlatformInfo->PciData.PciResourceMem32Limit) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI64 BASE: %lX Limit: %lX\n", + PlatformInfo->PciData.PciResourceMem64Base, + PlatformInfo->PciData.PciResourceMem64Limit) + ); + DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1)); + + LowUncableBase = PlatformInfo->MemData.MemMaxTolm; + LowUncableBase &= (0x0FFF00000); + MemoryTop = (0x100000000); + + if (BootMode != BOOT_ON_S3_RESUME) { + // + // In BIOS, HECBASE will be always below 4GB + // + HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28); + ASSERT (HecBaseHigh < 16); + } + + return Status; +} + +/** + Install Firmware Volume Hob's once there is main memory + + @param PeiServices General purpose services available to every PEIM. + @param NotifyDescriptor Notify that this module published. + @param Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_CPUID_REGISTER FeatureInfo; + UINT8 CpuAddressWidth; + UINT16 Pm1Cnt; + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_INFO_HOB *PlatformInfo; + UINT32 RootComplexBar; + UINT32 PmcBase; + UINT32 IoBase; + UINT32 IlbBase; + UINT32 SpiBase; + UINT32 MphyBase; + + // + // Get Platform Info HOB + // + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw != NULL); + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + // + // Check if user wants to turn off in PEI phase + // + if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) { + CheckPowerOffNow(); + } else { + Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT); + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP; + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + #ifndef MINNOW2_FSP_BUILD + // + // Set PEI cache mode here + // + SetPeiCacheMode (PeiServices); + #endif + + // + // Pulish memory tyoe info + // + PublishMemoryTypeInfo (); + + // + // Work done if on a S3 resume + // + if (BootMode == BOOT_ON_S3_RESUME) { + // + //Program the side band packet register to send a sideband message to Punit + //To indicate that DRAM has been initialized and PUNIT FW base address in memory. + // + return EFI_SUCCESS; + } + + RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + RootComplexBar, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar)); + + PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + PmcBase, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase)); + + IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + IoBase, + 0x4000 + ); + DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase)); + + IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + IlbBase, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase)); + + SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + SpiBase, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase)); + + MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR; + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + MphyBase, + 0x100000 + ); + DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase)); + + // + // Local APIC + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + LOCAL_APIC_ADDRESS, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS)); + + // + // IO APIC + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + IO_APIC_ADDRESS, + 0x1000 + ); + DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS)); + + // + // Adding the PCIE Express area to the E820 memory table as type 2 memory. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + PlatformInfo->PciData.PciExpressBase, + PlatformInfo->PciData.PciExpressSize + ); + DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase)); + + // + // Adding the Flashpart to the E820 memory table as type 2 memory. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_FIRMWARE_DEVICE, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + FixedPcdGet32 (PcdFlashAreaBaseAddress), + FixedPcdGet32 (PcdFlashAreaSize) + ); + DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress))); + + // + // Create a CPU hand-off information + // + CpuAddressWidth = 32; + AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); + if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) { + AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx); + CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF); + } + + BuildCpuHob(CpuAddressWidth, 16); + ASSERT_EFI_ERROR (Status); + + return Status; + +} + + +EFI_STATUS +ValidateFvHeader ( + IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ) +{ + UINT16 *Ptr; + UINT16 HeaderLength; + UINT16 Checksum; + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ((FwVolHeader->Revision != EFI_FVH_REVISION) || + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength == ((UINT64) -1)) || + ((FwVolHeader->HeaderLength & 0x01) != 0) + ) { + return EFI_NOT_FOUND; + } + + // + // Verify the header checksum + // + HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2); + Ptr = (UINT16 *) FwVolHeader; + Checksum = 0; + while (HeaderLength > 0) { + Checksum = *Ptr++; + HeaderLength--; + } + + if (Checksum != 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c new file mode 100644 index 0000000000..9592b07705 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c @@ -0,0 +1,369 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + MemoryPeim.c + +Abstract: + + Tiano PEIM to provide the platform support functionality. + This file implements the Platform Memory Range PPI + +--*/ + +#include "PlatformEarlyInit.h" + +// +// Need min. of 48MB PEI phase +// +#define PEI_MIN_MEMORY_SIZE (6 * 0x800000) +#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000) + +// +// This is the memory needed for PEI to start up DXE. +// +// Over-estimating this size will lead to higher fragmentation +// of main memory. Under-estimation of this will cause catastrophic +// failure of PEI to load DXE. Generally, the failure may only be +// realized during capsule updates. +// +#define PRERESERVED_PEI_MEMORY ( \ + EFI_SIZE_TO_PAGES (3 * 0x800000) /* PEI Core memory based stack */ \ + ) + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = { + { EfiACPIReclaimMemory, 0x40 }, // 0x40 pages = 256k for ASL + { EfiACPIMemoryNVS, 0x100 }, // 0x100 pages = 1 MB for S3, SMM, HII, etc + { EfiReservedMemoryType, 0x600 }, // 48k for BIOS Reserved + { EfiMemoryMappedIO, 0 }, + { EfiMemoryMappedIOPortSpace, 0 }, + { EfiPalCode, 0 }, + { EfiRuntimeServicesCode, 0x200 }, + { EfiRuntimeServicesData, 0x100 }, + { EfiLoaderCode, 0x100 }, + { EfiLoaderData, 0x100 }, + { EfiBootServicesCode, 0x800 }, + { EfiBootServicesData, 0x2500}, + { EfiConventionalMemory, 0 }, + { EfiUnusableMemory, 0 }, + { EfiMaxMemoryType, 0 } +}; + +STATIC +EFI_STATUS +GetMemorySize ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT64 *LowMemoryLength, + OUT UINT64 *HighMemoryLength + ); + + + +EFI_STATUS +EFIAPI +SetPeiCacheMode ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + PEI_CACHE_PPI *CachePpi; + + EFI_BOOT_MODE BootMode; + UINT64 MemoryLength; + UINT64 MemOverflow; + UINT64 MemoryLengthUc; + UINT64 MaxMemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + UINT8 Index; + MTRR_SETTINGS MtrrSetting; + + // + // Load Cache PPI + // + Status = (**PeiServices).LocatePpi ( + PeiServices, + &gPeiCachePpiGuid, // GUID + 0, // Instance + NULL, // EFI_PEI_PPI_DESCRIPTOR + (void **)&CachePpi // PPI + ); + if (!EFI_ERROR(Status)) { + // + // Clear the CAR Settings (Default Cache Type => UC) + // + DEBUG ((EFI_D_INFO, "Reset cache attribute and disable CAR. \n")); + CachePpi->ResetCache( + (EFI_PEI_SERVICES**)PeiServices, + CachePpi + ); + } + + + // + // Variable initialization + // + LowMemoryLength = 0; + HighMemoryLength = 0; + MemoryLengthUc = 0; + + Status = (*PeiServices)->GetBootMode ( + PeiServices, + &BootMode + ); + + // + // Determine memory usage + // + GetMemorySize ( + PeiServices, + &LowMemoryLength, + &HighMemoryLength + ); + + LowMemoryLength = (EFI_PHYSICAL_ADDRESS)MmPci32( 0, 0, 2, 0, 0x70); + LowMemoryLength &= 0xFFF00000ULL; + + MaxMemoryLength = LowMemoryLength; + + // + // Round up to nearest 256MB with high memory and 64MB w/o high memory + // + if (HighMemoryLength != 0 ) { + MemOverflow = (LowMemoryLength & 0x0fffffff); + if (MemOverflow != 0) { + MaxMemoryLength = LowMemoryLength + (0x10000000 - MemOverflow); + } + } else { + MemOverflow = (LowMemoryLength & 0x03ffffff); + if (MemOverflow != 0) { + MaxMemoryLength = LowMemoryLength + (0x4000000 - MemOverflow); + } + } + + ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS)); + for (Index = 0; Index < 2; Index++) { + MtrrSetting.Fixed.Mtrr[Index]=0x0606060606060606; + } + for (Index = 2; Index < 11; Index++) { + MtrrSetting.Fixed.Mtrr[Index]=0x0505050505050505; + } + + // + // Cache the flash area to improve the boot performance in PEI phase + // + Index = 0; + MtrrSetting.Variables.Mtrr[0].Base = (FixedPcdGet32 (PcdFlashAreaBaseAddress) | CacheWriteProtected); + MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + Index ++; + + MemOverflow =0; + while (MaxMemoryLength > MemOverflow){ + MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; + MemoryLength = MaxMemoryLength - MemOverflow; + MemoryLength = GetPowerOfTwo64 (MemoryLength); + MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + + MemOverflow += MemoryLength; + Index++; + } + + MemoryLength = LowMemoryLength; + + while (MaxMemoryLength != MemoryLength) { + MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength); + + MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable; + MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + MaxMemoryLength -= MemoryLengthUc; + Index++; + } + + MemOverflow =0x100000000; + while (HighMemoryLength > 0) { + MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; + MemoryLength = HighMemoryLength; + MemoryLength = GetPowerOfTwo64 (MemoryLength); + + if (MemoryLength > MemOverflow){ + MemoryLength = MemOverflow; + } + + MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + + MemOverflow += MemoryLength; + HighMemoryLength -= MemoryLength; + Index++; + } + + + for (Index = 0; Index < MTRR_NUMBER_OF_VARIABLE_MTRR; Index++) { + if (MtrrSetting.Variables.Mtrr[Index].Base == 0){ + break; + } + DEBUG ((EFI_D_INFO, "Base=%lx, Mask=%lx\n",MtrrSetting.Variables.Mtrr[Index].Base ,MtrrSetting.Variables.Mtrr[Index].Mask)); + } + + // + // set FE/E bits for IA32_MTRR_DEF_TYPE + // + MtrrSetting.MtrrDefType |= 3 <<10; + + MtrrSetAllMtrrs(&MtrrSetting); + + + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SetDxeCacheMode ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + // + // This is not needed for now. + // + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetMemorySize ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT64 *LowMemoryLength, + OUT UINT64 *HighMemoryLength + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + + *HighMemoryLength = 0; + *LowMemoryLength = 0x100000; + + // + // Get the HOB list for processing + // + Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Collect memory ranges + // + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + // + // Need memory above 1MB to be collected here + // + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { + *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength); + } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { + *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return EFI_SUCCESS; +} + + +/** + Publish Memory Type Information. + + @param NULL + + @retval EFI_SUCCESS Success. + @retval Others Errors have occurred. +**/ + +EFI_STATUS +EFIAPI +PublishMemoryTypeInfo ( + void + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + + Status = PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "WARNING: Locating Pei variable failed 0x%x \n", Status)); + DEBUG((EFI_D_ERROR, "Build Hob from default\n")); + // + // Build the default GUID'd HOB for DXE + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof (mDefaultMemoryTypeInformation) + ); + + return Status; + } + + + DataSize = sizeof (MemoryData); + + // + // This variable is saved in BDS stage. Now read it back + // + Status = Variable->GetVariable ( + Variable, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + if (EFI_ERROR (Status)) { + // + //build default + // + DEBUG((EFI_D_ERROR, "Build Hob from default\n")); + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof (mDefaultMemoryTypeInformation) + ); + + } else { + // + // Build the GUID'd HOB for DXE from variable + // + DEBUG((EFI_D_ERROR, "Build Hob from variable \n")); + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); + } + + return Status; +} + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c new file mode 100644 index 0000000000..30f87c1906 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c @@ -0,0 +1,813 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchInitPeim.c + +Abstract: + + Do Early PCH platform initialization. + + +--*/ + +#include "PlatformEarlyInit.h" +#include "Ppi/PchPlatformPolicy.h" +#include "PchRegs.h" +#include +#include "Ppi/PchInit.h" +#include + +EFI_GUID gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID; + +#define MC_PMSTS_OFFSET 0xC + +#define DEFAULT_BUS_INFO 0x2020 + + +#define PCI_LPC_BASE (0x8000F800) +#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x)) +#define PCIEX_BASE_ADDRESS 0xE0000000 +#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15) + +VOID +PchPolicySetupInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ); + +VOID +PchInitInterrupt ( + IN SYSTEM_CONFIGURATION *SystemConfiguration + ); + +#ifndef __GNUC__ +#pragma warning (push) +#pragma warning (disable : 4245) +#pragma warning (pop) +#endif + +UINT8 +ReadCmosBank1Byte ( + IN UINT8 Address + ) +{ + UINT8 Data; + + IoWrite8(R_PCH_RTC_EXT_INDEX, Address); + Data = IoRead8 (R_PCH_RTC_EXT_TARGET); + return Data; +} + +VOID +WriteCmosBank1Byte ( + IN UINT8 Address, + IN UINT8 Data + ) +{ + IoWrite8(R_PCH_RTC_EXT_INDEX, Address); + IoWrite8(R_PCH_RTC_EXT_TARGET, Data); +} + +/** + Turn off system if needed. + + @param PeiServices Pointer to PEI Services + @param CpuIo Pointer to CPU I/O Protocol + + @retval None. + +**/ +VOID +CheckPowerOffNow ( + VOID + ) +{ + UINT16 Pm1Sts; + + // + // Read and check the ACPI registers + // + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS); + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) { + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN); + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5); + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN); + + // + // Should not return + // + CpuDeadLoop(); + } +} + +VOID +ClearPowerState ( + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + UINT8 Data8; + UINT16 Data16; + UINT32 Data32; + + // + // Check for PowerState option for AC power loss and program the chipset + // + + // + // Clear PWROK (Set to Clear) + // + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR); + + // + // Clear Power Failure Bit (Set to Clear) + // + // TODO: Check if it is OK to clear here + // + + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR); + + // + // Clear the GPE and PM enable + // + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00); + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32) 0x00); + + // + // Halt the TCO timer + // + Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT); + Data16 |= B_PCH_TCO_CNT_TMR_HLT; + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16); + + // + // if NMI_NOW_STS is set + // NMI NOW bit is "Write '1' to clear" + // + Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI); + if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) { + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI, B_PCH_ILB_GNMI_NMIN); + } + + // + // Before we clear the TO status bit here we need to save the results in a CMOS bit for later use. + // + Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS); + if ((Data32 & B_PCH_TCO_STS_SECOND_TO) == B_PCH_TCO_STS_SECOND_TO) + { +#if (defined(HW_WATCHDOG_TIMER_SUPPORT) && (HW_WATCHDOG_TIMER_SUPPORT != 0)) + WriteCmosBank1Byte ( + EFI_CMOS_PERFORMANCE_FLAGS, + ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) | B_CMOS_TCO_WDT_RESET + ); +#endif + } +} + +/*++ + + Clear any SMI status or wake status left over from boot. + +**/ +VOID +ClearSmiAndWake ( + VOID + ) +{ + UINT16 Pm1Sts; + UINT32 Gpe0Sts; + UINT32 SmiSts; + + // + // Read the ACPI registers + // + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS); + Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS); + SmiSts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS); + + // + // Register Wake up reason for S4. This information is used to notify + // WinXp of wake up reason because S4 wake up path doesn't keep SCI. + // This is important for Viiv(Quick resume) platform. + // + + // + // First Clear CMOS S4 Wake up flag. + // + WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 0); + + // + // Check wake up reason and set CMOS accordingly. Currently checks + // Power button, USB, PS/2. + // Note : PS/2 wake up is using GPI13 (IO_PME). This must be changed depending + // on board design. + // + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) || (Gpe0Sts & (B_PCH_ACPI_GPE0a_STS_CORE_GPIO | B_PCH_ACPI_GPE0a_STS_SUS_GPIO))) { + WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 1); + } + + // + // Clear any SMI or wake state from the boot + // + Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR | B_PCH_ACPI_PM1_STS_PWRBTN); + + Gpe0Sts |= + ( + B_PCH_ACPI_GPE0a_STS_CORE_GPIO | + B_PCH_ACPI_GPE0a_STS_SUS_GPIO | + B_PCH_ACPI_GPE0a_STS_PME_B0 | + B_PCH_ACPI_GPE0a_STS_BATLOW | + B_PCH_ACPI_GPE0a_STS_PCI_EXP | + B_PCH_ACPI_GPE0a_STS_GUNIT_SCI | + B_PCH_ACPI_GPE0a_STS_PUNIT_SCI | + B_PCH_ACPI_GPE0a_STS_SWGPE | + B_PCH_ACPI_GPE0a_STS_HOT_PLUG + ); + + SmiSts |= + ( + B_PCH_SMI_STS_SMBUS | + B_PCH_SMI_STS_PERIODIC | + B_PCH_SMI_STS_TCO | + B_PCH_SMI_STS_SWSMI_TMR | + B_PCH_SMI_STS_APM | + B_PCH_SMI_STS_ON_SLP_EN | + B_PCH_SMI_STS_BIOS + ); + + // + // Write them back + // + IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts); + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts); + IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts); +} + +/** + Issue PCI-E Secondary Bus Reset + + @param Bus Bus number of the bridge + @param Dev Devices number of the bridge + @param Fun Function number of the bridge + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +PcieSecondaryBusReset ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun + ) +{ + EFI_PEI_STALL_PPI *PeiStall; + EFI_STATUS Status; + + Status = (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiStallPpiGuid, + 0, + NULL, + (void **)&PeiStall + ); + ASSERT_EFI_ERROR (Status); + + // + // Issue secondary bus reset + // + MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS); + + // + // Wait 1ms + // + PeiStall->Stall (PeiServices, PeiStall, 1000); + + + // + // Clear the reset bit + // Note: The PCIe spec suggests 100ms delay between clearing this bit and accessing + // the device's config space. Since we will not access the config space until we enter DXE + // we don't put delay expressly here. + // + MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS)); + + return EFI_SUCCESS; +} + +/** + Provide hard reset PPI service. + To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT (0xCF9). + + @param PeiServices General purpose services available to every PEIM. + + @retval Not return System reset occured. + @retval EFI_DEVICE_ERROR Device error, could not reset the system. + +**/ +EFI_STATUS +EFIAPI +IchReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + IoWrite8 ( + R_PCH_RST_CNT, + V_PCH_RST_CNT_HARDSTARTSTATE + ); + + IoWrite8 ( + R_PCH_RST_CNT, + V_PCH_RST_CNT_HARDRESET + ); + + // + // System reset occured, should never reach at this line. + // + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR); + CpuDeadLoop(); + + return EFI_DEVICE_ERROR; +} + +VOID +PchPlatformLpcInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + EFI_BOOT_MODE BootMode; + UINT8 Data8; + UINT16 Data16; + + (*PeiServices)->GetBootMode(PeiServices, &BootMode); + + if ((BootMode != BOOT_ON_S3_RESUME)) { + + // + // Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI + // + ClearSmiAndWake (); + } + + ClearPowerState (SystemConfiguration); + + // + // Need to set and clear SET bit (RTC_REGB Bit 7) as requested by the ICH EDS + // early in POST after each power up directly after coin-cell battery insertion. + // This is to avoid the UIP bit (RTC_REGA Bit 7) from stuck at "1". + // The UIP bit status may be polled by software (i.e ME FW) during POST. + // + if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) { + // + // Set and clear SET bit in RTC_REGB + // + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB); + Data8 = IoRead8(R_PCH_RTC_TARGET); + Data8 |= B_PCH_RTC_REGISTERB_SET; + IoWrite8(R_PCH_RTC_TARGET, Data8); + + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB); + Data8 &= (~B_PCH_RTC_REGISTERB_SET); + IoWrite8(R_PCH_RTC_TARGET, Data8); + + // + // Clear the UIP bit in RTC_REGA + // + IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERA); + IoWrite8(R_PCH_RTC_TARGET, 0x00); + } + + // + // Disable SERR NMI and IOCHK# NMI in port 61 + // + Data8 = IoRead8 (R_PCH_NMI_SC); + IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 | B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN)); + + // + // Enable Bus Master, I/O, Mem, and SERR on LPC bridge + // + Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND); + MmioWrite16 ( + MmPciAddress (0, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + R_PCH_LPC_COMMAND + ), + (Data16 | + B_PCH_LPC_COMMAND_IOSE | + B_PCH_LPC_COMMAND_MSE | + B_PCH_LPC_COMMAND_BME | + B_PCH_LPC_COMMAND_SERR_EN) + ); + + // + // Set Stretch S4 to 1-2s per marketing request. + // Note: This register is powered by RTC well. + // + MmioAndThenOr8 ( + PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 , + (UINT8) (~B_PCH_PMC_GEN_PMCON_SLP_S4_MAW), + (UINT8) (B_PCH_PMC_GEN_PMCON_SLP_S4_ASE | V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S) + ); + +} + +#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable + +VOID +UARTInit ( + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + if (0) { // for fix cr4 issue + // + // Program and enable PMC Base. + // + IoWrite32 (0xCF8, PCI_LPC_REG(R_PCH_LPC_PMC_BASE)); + IoWrite32 (0xCFC, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN)); + + if( (SystemConfiguration->PcuUart1 == 1) && + (SystemConfiguration->LpssHsuart0Enabled == 0)){ + // + // Enable COM1 for debug message output. + // + MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24); + + // + //Enable internal UART3 port(COM1) + // + MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3); + MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L + MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0 + MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN); + } else { + // + //Disable UART3(COM1) + // + MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3); + MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07); + MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07); + MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN); + + + if (SystemConfiguration->LpssHsuart0Enabled == 1){ + // + //Valleyview BIOS Specification Vol2,17.2 + //LPSS_UART1 ¨C set each pad PAD_CONF0.Func_Pin_Mux to function 1: + // + MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07); + MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01); + MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07); + MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01); + + } + } + + + DEBUG ((EFI_D_ERROR, "EnableInternalUart\n")); + } else { + // + // If SIO UART interface selected + //Disable internal UART port(COM1) + // + if (0) {; // For fix CR4 issue + MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3); + MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07); + MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07); + MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN); + + } + } +} + +VOID +IchRcrbInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + UINT8 LpcRevisionID; + EFI_PLATFORM_CPU_INFO *PlatformCpuInfo; + EFI_PEI_HOB_POINTERS Hob; + EFI_BOOT_MODE BootMode; + + // + // Get Platform Info HOB + // + Hob.Raw = GetFirstGuidHob (&gEfiPlatformCpuInfoGuid); + ASSERT (Hob.Raw != NULL); + PlatformCpuInfo = GET_GUID_HOB_DATA(Hob.Raw); + + (*PeiServices)->GetBootMode(PeiServices, &BootMode); + + // + // If not recovery or flash update boot path. set the BIOS interface lock down bit. + // It locks the top swap bit and BIOS boot strap bits from being changed. + // + if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) { + MmioOr8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_BILD); + } + + // + // Disable the Watchdog timer expiration from causing a system reset + // + MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, B_PCH_PMC_PM_CFG_NO_REBOOT); + + // + // Initial RCBA according to the PeiRCBA table + // + LpcRevisionID = PchLpcPciCfg8 (R_PCH_LPC_RID_CC); + + if ((BootMode == BOOT_ON_S3_RESUME)) { + // + // We are resuming from S3 + // Enable HPET if enabled in Setup + // ICH Config register Offset 0x3404 bit 7 (Enable) = 1, + // Bit 1:0 (Mem I/O address) = 0 (0xFED00000) + // + MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, B_PCH_PCH_HPET_GCFG_EN); + + } + +} + + +EFI_STATUS +PlatformPchInit ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 PlatformType + ) +{ + IchRcrbInit (PeiServices, SystemConfiguration); + + // + // PCH Policy Initialization based on Setup variable. + // + PchPolicySetupInit (PeiServices, SystemConfiguration); + + UARTInit(SystemConfiguration); + + PchPlatformLpcInit (PeiServices, SystemConfiguration); + + return EFI_SUCCESS; +} + +/** + + Returns the state of A16 inversion + + @retval TRUE A16 is inverted + @retval FALSE A16 is not inverted + +**/ +BOOLEAN +IsA16Inverted ( + ) +{ + UINT8 Data; + Data = MmioRead8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS); + return (Data & B_PCH_RCRB_GCS_TS) ? TRUE : FALSE; +} + +VOID +PchPolicySetupInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc; + PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi; + PCH_HPET_CONFIG *HpetConfig; + PCH_PCIE_CONFIG *PcieConfig; + UINT8 Index; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_LPSS_CONFIG *LpssConfig; + UINT32 SpiHsfsReg; + UINT32 SpiFdodReg; + +// +// Disable codec ALC-262 +// + UINT32 IoBase; + + // + // Install Pch Platform Policy PPI. As we depend on Pch Init PPI so we are executed after + // PchInit PEIM. Thus we can insure PCH Initialization is performed when we install the Pch Platform Policy PPI, + // as PchInit PEIM registered a notification function on our policy PPI. + // + // --cr-- For better code structure / modularity, we should use a notification function on Pch Init PPI to perform + // actions that depend on PchInit PEIM's initialization. + // + //Todo: confirm if we need update to PCH_PLATFORM_POLICY_PPI_REVISION_5 + // + DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - Start\n")); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PchPlatformPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PLATFORM_POLICY_PPI), (void **)&PchPlatformPolicyPpi); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_HPET_CONFIG), (void **)&HpetConfig); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PCIE_CONFIG), (void **)&PcieConfig); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_IOAPIC_CONFIG), (void **)&IoApicConfig); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_LPSS_CONFIG), (void **)&LpssConfig); + ASSERT_EFI_ERROR (Status); + + PchPlatformPolicyPpi->Revision = PCH_PLATFORM_POLICY_PPI_REVISION_1; + PchPlatformPolicyPpi->BusNumber = DEFAULT_PCI_BUS_NUMBER_PCH; + PchPlatformPolicyPpi->SpiBase = SPI_BASE_ADDRESS; + PchPlatformPolicyPpi->PmcBase = PMC_BASE_ADDRESS; + PchPlatformPolicyPpi->IoBase = IO_BASE_ADDRESS; + PchPlatformPolicyPpi->IlbBase = ILB_BASE_ADDRESS; + PchPlatformPolicyPpi->PUnitBase = PUNIT_BASE_ADDRESS; + PchPlatformPolicyPpi->MphyBase = MPHY_BASE_ADDRESS; + PchPlatformPolicyPpi->Rcba = RCBA_BASE_ADDRESS; + PchPlatformPolicyPpi->AcpiBase = ACPI_BASE_ADDRESS; + PchPlatformPolicyPpi->GpioBase = GPIO_BASE_ADDRESS; + PchPlatformPolicyPpi->SataMode = SystemConfiguration->SataType; + PchPlatformPolicyPpi->EnableRmh = SystemConfiguration->PchUsbRmh; + + PchPlatformPolicyPpi->EhciPllCfgEnable = SystemConfiguration->EhciPllCfgEnable; + + + PchPlatformPolicyPpi->HpetConfig = HpetConfig; + PchPlatformPolicyPpi->PcieConfig = PcieConfig; + PchPlatformPolicyPpi->IoApicConfig = IoApicConfig; + + PchPlatformPolicyPpi->HpetConfig->Enable = SystemConfiguration->Hpet; + PchPlatformPolicyPpi->HpetConfig->Base = HPET_BASE_ADDRESS; + PchPlatformPolicyPpi->IoApicConfig->IoApicId = 0x01; + + // + // Set LPSS configuration according to setup value. + // + PchPlatformPolicyPpi->LpssConfig->LpssPciModeEnabled = SystemConfiguration->LpssPciModeEnabled; + + PchPlatformPolicyPpi->LpssConfig->Dma1Enabled = SystemConfiguration->LpssDma1Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C0Enabled = SystemConfiguration->LpssI2C0Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C1Enabled = SystemConfiguration->LpssI2C1Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C2Enabled = SystemConfiguration->LpssI2C2Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C3Enabled = SystemConfiguration->LpssI2C3Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C4Enabled = SystemConfiguration->LpssI2C4Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C5Enabled = SystemConfiguration->LpssI2C5Enabled; + PchPlatformPolicyPpi->LpssConfig->I2C6Enabled = SystemConfiguration->LpssI2C6Enabled; + + PchPlatformPolicyPpi->LpssConfig->Dma0Enabled = SystemConfiguration->LpssDma0Enabled;; + PchPlatformPolicyPpi->LpssConfig->Pwm0Enabled = SystemConfiguration->LpssPwm0Enabled; + PchPlatformPolicyPpi->LpssConfig->Pwm1Enabled = SystemConfiguration->LpssPwm1Enabled; + PchPlatformPolicyPpi->LpssConfig->Hsuart0Enabled = SystemConfiguration->LpssHsuart0Enabled; + PchPlatformPolicyPpi->LpssConfig->Hsuart1Enabled = SystemConfiguration->LpssHsuart1Enabled; + PchPlatformPolicyPpi->LpssConfig->SpiEnabled = SystemConfiguration->LpssSpiEnabled; + + + for (Index = 0; Index < PCH_PCIE_MAX_ROOT_PORTS; Index++) { + PchPlatformPolicyPpi->PcieConfig->PcieSpeed[Index] = SystemConfiguration->PcieRootPortSpeed[Index]; + } + + SpiHsfsReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_HSFS); + if ((SpiHsfsReg & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) { + MmioWrite32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOC, V_PCH_SPI_FDOC_FDSS_FSDM); + SpiFdodReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOD); + if (SpiFdodReg == V_PCH_SPI_FDBAR_FLVALSIG) { + } + // + // Disable codec ALC-262 + // + if (SystemConfiguration->DisableCodec262 == 1) { + IoBase = MmioRead32 (MmPciAddress (0, + PchPlatformPolicyPpi->BusNumber, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ) + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR; + MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07)); + } + } + + PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi; + + // + // Install PCH Platform Policy PPI + // + Status = (**PeiServices).InstallPpi ( + PeiServices, + PchPlatformPolicyPpiDesc + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - End\n")); +} + +EFI_STATUS +InstallPeiPchUsbPolicy ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + EFI_PEI_PPI_DESCRIPTOR *PeiPchUsbPolicyPpiDesc; + PCH_USB_POLICY_PPI *PeiPchUsbPolicyPpi; + PCH_USB_CONFIG *UsbConfig; + EFI_PLATFORM_INFO_HOB PlatformInfo; + + // + // Allocate descriptor and PPI structures. Since these are dynamically updated + // we cannot do a global variable PPI. + // + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PeiPchUsbPolicyPpiDesc); + + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_POLICY_PPI), (void **)&PeiPchUsbPolicyPpi); + + + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_CONFIG), (void **)&UsbConfig); + + + // + // Initiate PCH USB policy. + // + PeiPchUsbPolicyPpi->Revision = PCH_USB_POLICY_PPI_REVISION_1; + UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE; + UsbConfig->UsbPerPortCtl = PCH_DEVICE_DISABLE; + UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + + // + // Initialize PlatformInfo HOB + // + ZeroMem (&PlatformInfo, sizeof(PlatformInfo)); + MultiPlatformInfoInit(PeiServices, &PlatformInfo); + + UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0; + + UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0; + + UsbConfig->Usb20OverCurrentPins[2] = PchUsbOverCurrentPin1; + + UsbConfig->Usb20OverCurrentPins[3] = PchUsbOverCurrentPin1; + + + // + // Enable USB Topology control and program the topology setting for every USB port + // See Platform Design Guide for description of topologies + // + // + // Port 0: ~10.9", Port 1: ~10.1", Port 2: ~11.2", Port 3: ~11.5", Port 4: ~3.7", Port 5: ~2.7", Port 6: ~4.1" + // Port 7: ~4.5", Port 8: ~10.7", Port 9: ~10.5", Port 10: ~4.2", Port 11: ~4.3", Port 12: ~3.1", Port 13: ~2.9" + // + + // + // Port 0: ~3.5", Port 1: ~4.1", Port 2: ~4.6", Port 3: ~4.6", Port 4: ~12.5", Port 5: ~12", Port 6: ~5.1" + // Port 7: ~5.1", Port 8: ~4.1", Port 9: ~4.1", Port 10: ~14.5", Port 11: ~12.8", Port 12: ~12.9", Port 13: ~14.6" + // + UsbConfig->Usb20PortLength[0] = 0x53; + UsbConfig->Usb20PortLength[1] = 0x49; + UsbConfig->Usb20PortLength[2] = 0x47; + UsbConfig->Usb20PortLength[3] = 0x80; + + PeiPchUsbPolicyPpi->Mode = EHCI_MODE; + + PeiPchUsbPolicyPpi->EhciMemBaseAddr = PcdGet32(PcdPeiIchEhciControllerMemoryBaseAddress); + + PeiPchUsbPolicyPpi->EhciMemLength = (UINT32) 0x400 * PchEhciControllerMax; + + PeiPchUsbPolicyPpi->UsbConfig = UsbConfig; + + PeiPchUsbPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + + PeiPchUsbPolicyPpiDesc->Guid = &gPchUsbPolicyPpiGuid; + + PeiPchUsbPolicyPpiDesc->Ppi = PeiPchUsbPolicyPpi; + + // + // Install PCH USB Policy PPI + // + Status = (**PeiServices).InstallPpi (PeiServices, PeiPchUsbPolicyPpiDesc); + + return Status; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c new file mode 100644 index 0000000000..1a12c53e96 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c @@ -0,0 +1,1034 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformEarlyInit.c + +Abstract: + + Do platform specific PEI stage initializations. + +--*/ + + +#include "PlatformEarlyInit.h" + +#ifdef __GNUC__ +#pragma GCC push_options +#pragma GCC optimize ("O0") +#else +#pragma optimize ("", off) +#endif + + + +static EFI_PEI_STALL_PPI mStallPpi = { + PEI_STALL_RESOLUTION, + Stall +}; + +static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiStallPpiGuid, + &mStallPpi +}; + +// +// The reserved SMBus addresses are defined in PlatformDxe.h file. +// +static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES; +static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = { + SMBUS_BASE_ADDRESS, + SMBUS_BUS_DEV_FUNC, + PLATFORM_NUM_SMBUS_RSVD_ADDRESSES, + mSmbusRsvdAddresses +}; + +static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiSmbusPolicyPpiGuid, + &mSmbusPolicyPpi +}; +static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = { + ProgramToneFrequency, + GenerateBeepTone +}; + +static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiSpeakerInterfacePpiGuid, + &mSpeakerInterfacePpi +}; + +static EFI_PEI_RESET_PPI mResetPpi = { IchReset }; + + +static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = { + (EFI_PEI_FIND_FV_FINDFV)FindFv +}; + +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiPeiMasterBootModePpiGuid, + NULL + }, + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiPeiResetPpiGuid, + &mResetPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiFindFvPpiGuid, + &mEfiFindFvPpi + } +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = { + { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, + &gEfiEndOfPeiSignalPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback + }, + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback + } + +}; + + +/** + + Parse the status registers for figuring out the wake-up event and save it into + an GUID HOB which will be referenced later. However, modification is required + to meet the chipset register definition and the practical hardware design. Thus, + this is just an example. + + + @param PeiServices pointer to the PEI Service Table + @param EFI_SUCCESS Always return Success + + @retval None + + +**/ +EFI_STATUS +EFIAPI +GetWakeupEventAndSaveToHob ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + UINT16 Pm1Sts; + UINTN Gpe0Sts; + UINTN WakeEventData; + + // + // Read the ACPI registers + // + Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS); + Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS); + + // + // Figure out the wake-up event + // + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) { + WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH; + } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) { + WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME; + } else if (Gpe0Sts != 0) { + WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS; + } else { + WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN; + } + + DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts)); + + return EFI_SUCCESS; +} + +EFI_STATUS +GetSetupVariable ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + UINTN VariableSize; + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + + VariableSize = sizeof (SYSTEM_CONFIGURATION); + ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION)); + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + ASSERT_EFI_ERROR (Status); + + // + // Use normal setup default from NVRAM variable, + // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable. + // + VariableSize = sizeof(SYSTEM_CONFIGURATION); + Status = Variable->GetVariable ( + Variable, + L"Setup", + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + SystemConfiguration + ); + ASSERT_EFI_ERROR(Status); + return Status; +} + +EFI_STATUS +VlvPolicyInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc; + VLV_POLICY_PPI *mVlvPolicyPpi; + + Status = (*PeiServices)->AllocatePool( + PeiServices, + sizeof (EFI_PEI_PPI_DESCRIPTOR), + (void **)&mVlvPolicyPpiDesc + ); + ASSERT_EFI_ERROR (Status); + + Status = (*PeiServices)->AllocatePool( + PeiServices, + sizeof (VLV_POLICY_PPI), + (void **)&mVlvPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Initialize PPI + // + (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0); + mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid; + mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi; + mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor; + mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc; + mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize; + mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize; + if (SystemConfiguration->PrimaryVideoAdaptor != 2) { + mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd; + } else { + mVlvPolicyPpi->GtConfig.InternalGraphics = 0; + } + + + mVlvPolicyPpi->GtConfig.IgdTurboEn = 1; + + + mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot; + mVlvPolicyPpi->PlatformData.DynSR = 1; + DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn)); + mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn; + DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel)); + mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel; + if (SystemConfiguration->ISPEn == 0) { + mVlvPolicyPpi->ISPPciDevConfig = 0; + DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig)); + } + Status = (*PeiServices)->InstallPpi( + PeiServices, + mVlvPolicyPpiDesc + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +EFI_STATUS +ConfigureSoCGpio ( + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + + DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n")); + if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode + DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n")); + + // + //Silicon Steppings + // + switch (PchStepping()) { + case PchA0: // SOC A0 and A1 + case PchA1: + DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n")); + SystemConfiguration->LpsseMMCEnabled = 1; + SystemConfiguration->LpsseMMC45Enabled = 0; + break; + case PchB0: // SOC B0 and later + default: + DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n")); + SystemConfiguration->LpsseMMCEnabled = 0; + SystemConfiguration->LpsseMMC45Enabled = 1; + break; + } + } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41 + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n")); + SystemConfiguration->LpsseMMCEnabled = 1; + SystemConfiguration->LpsseMMC45Enabled = 0; + } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5 + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n")); + SystemConfiguration->LpsseMMCEnabled = 0; + SystemConfiguration->LpsseMMC45Enabled = 1; + + } else { // Disable eMMC controllers + DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n")); + SystemConfiguration->LpsseMMCEnabled = 0; + SystemConfiguration->LpsseMMC45Enabled = 0; + } + + /* + 20.1.1 EMMC + SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0 + SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390 + SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0 + SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400 + SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0 + SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360 + MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380 + MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0 + MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370 + MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0 + MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330 + */ + if (SystemConfiguration->LpsseMMCEnabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41 + MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01); + } + + /* + eMMC 4.5 controller + SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0 + SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390 + SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0 + SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400 + SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0 + SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360 + MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380 + MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0 + MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370 + MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0 + MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330 + */ + if (SystemConfiguration->LpsseMMC45Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5 + MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83); + MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03); + + } + +// +// Change GPIOC_0 setting to allow MMIO access under Android. +// + IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, + (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0)); + DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n")); + return EFI_SUCCESS; +} + +EFI_STATUS +MeasuredBootInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + if (SystemConfiguration->MeasuredBootEnable) { + PcdSetBool (PcdMeasuredBootEnable, TRUE); + } else { + PcdSetBool (PcdMeasuredBootEnable, FALSE); + } + + return EFI_SUCCESS; +} + + +EFI_STATUS +ConfigureLpssAndSccGpio ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN EFI_PLATFORM_INFO_HOB *PlatformInfo + ) +{ + /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration: + GPIO SCORE - write 0x01001002 to IOBASE + 0x0700 + GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00 + GPIO SSUS - write 0x01001002 to IOBASE + 0x1700 + */ + DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n")); + + /* + 19.1.1 PWM0 + PWM0 - write 0x2003CD01 to IOBASE + 0x00A0 + 19.1.2 PWM1 + PWM0 - write 0x2003CD01 to IOBASE + 0x00B0 + */ + if (SystemConfiguration->LpssPwm0Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01); + } else if (SystemConfiguration->LpssPwm0Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00); + } + + if (SystemConfiguration->LpssPwm1Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01); + } else if (SystemConfiguration->LpssPwm1Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00); + } + + /* + 19.1.3 UART1 + UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020 + UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010 + UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000 + UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040 + */ + if (SystemConfiguration->LpssHsuart0Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1 + MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81); + if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) { + DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n")); + MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80); + MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80); + } else { + DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n")); + MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81 + } + } else if (SystemConfiguration->LpssHsuart0Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1 + MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80); + } + + + /* + 19.1.4 UART2 + UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090 + UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080 + UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060 + UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070 + */ + if (SystemConfiguration->LpssHsuart1Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81); + + if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) { + DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n")); + MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B + MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B + } else { + DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n")); + MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2 + MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81 + } + } else if (SystemConfiguration->LpssHsuart1Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80); + MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80); + } + + /* + 19.1.5 SPI + SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110 + SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100 + SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130 + SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120 + */ + if (SystemConfiguration->LpssSpiEnabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI + MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01); + MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81); + } else if (SystemConfiguration->LpssSpiEnabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80); + MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80); + MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80); + MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80); + } + + /* + 19.1.6 I2C0 + I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210 + I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200 + */ + if (SystemConfiguration->LpssI2C0Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881); + } + /* + 19.1.7 I2C1 + I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0 + I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0 + */ + + if (SystemConfiguration->LpssI2C1Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881); + } + /* + 19.1.8 I2C2 + I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0 + I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0 + */ + if (SystemConfiguration->LpssI2C2Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881); + } + /* + 19.1.9 I2C3 + I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190 + I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0 + */ + if (SystemConfiguration->LpssI2C3Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881); + } + /* + 19.1.10 I2C4 + I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0 + I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170 + */ + if (SystemConfiguration->LpssI2C4Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881); + } + /* + 19.1.11 I2C5 + I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150 + I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140 + */ + //touch 1.7M support on i2c5(from 0) need 2k PULL-UP. + if (SystemConfiguration->LpssI2C5Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881); + } else if(SystemConfiguration->LpssI2C5Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880); + MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880); + } + /* + 19.1.12 I2C6 + I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180 + I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160 + */ + if (SystemConfiguration->LpssI2C6Enabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881); + MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881); + } else if (SystemConfiguration->LpssI2C6Enabled== 0) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880); + MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880); + } + + + /* + 20.1.2 SDIO + SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320 + SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300 + SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350 + SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0 + SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340 + SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310 + */ + if (SystemConfiguration->LpssSdioEnabled== 1) { + MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO + MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81); + } + + /* + 20.1.3 SD Card + SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0 + SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0 + SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0 + SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0 + SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0 + SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290 + SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0 + SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0 + SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690 + SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160 + */ + if (SystemConfiguration->LpssSdcardEnabled == 1) { + if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) { + MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD + MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01); + MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81); + MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin + } + } + + + DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n")); + return EFI_SUCCESS; +} + +EFI_STATUS +ConfigureLpeGpio ( + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n")); + + if (SystemConfiguration->PchAzalia == 0) { + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01)); + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01)); + } + + DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n")); + + return EFI_SUCCESS; +} + +EFI_STATUS +ConfigureSciSmiGpioRout ( + IN EFI_PLATFORM_INFO_HOB *PlatformInfo) +{ + UINT32 GPI_Routing; + + GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT); + + // + // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI + // + if(PlatformInfo->BoardRev == 3) { + GPI_Routing = GPI_Routing & 0xfffc3ffc; + GPI_Routing = GPI_Routing | 0x00024002; + } + + // + // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI + // + else { + GPI_Routing = GPI_Routing & 0x3fff3ffc; + GPI_Routing = GPI_Routing | 0x80004002; + } + MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing); + + return EFI_SUCCESS; +} + +EFI_STATUS +ConfigureMipiCsi ( + VOID) +{ + // + //Configure the platform clock for MIPI-CSI usage + //PLT_CLK0 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01)); + + // + //PLT_CLK1 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01)); + + // + //PLT_CLK2 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01)); + + return EFI_SUCCESS; +} + +EFI_STATUS +ConfigureUSBULPI ( + VOID) +{ + // + //Configure USB ULPI + //USB_ULPI_0_CLK + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA0 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA1 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA2 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA3 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA4 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA5 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA6 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DATA7 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_DIR + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81)); + + // + //USB_ULPI_0_NXT + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101)); + + // + //USB_ULPI_0_STP + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81)); + + // + //USB_ULPI_0_REFCLK + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101)); + + return EFI_SUCCESS; +} + +EFI_STATUS +DisableRTD3 ( + VOID) +{ + // + //Disable RTD3 + // + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00)); + MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00)); + + return EFI_SUCCESS; +} + +/** + Platform specific initializations in stage1. + + @param FfsHeader Pointer to the PEIM FFS file header. + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS Operation completed successfully. + @retval Otherwise Platform initialization failed. +**/ +EFI_STATUS +EFIAPI +PlatformEarlyInitEntry ( + + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + SYSTEM_CONFIGURATION SystemConfiguration; + EFI_PLATFORM_INFO_HOB *PlatformInfo; + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_CPU_INFO PlatformCpuInfo; + + // + // Initialize SmbusPolicy PPI + // + Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Stall PPIs + // + Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi); + ASSERT_EFI_ERROR (Status); + + // + // Initialize platform PPIs + // + Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi); + ASSERT_EFI_ERROR (Status); + + // + // Variable initialization + // + ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO)); + + // + // Set the some PCI and chipset range as UC + // And align to 1M at leaset + // + Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw != NULL); + PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw); + + // + // Initialize PlatformInfo HOB + // + MultiPlatformInfoInit(PeiServices, PlatformInfo); + + // + // Do basic MCH init + // + MchInit (PeiServices); + + // + // Set the new boot mode + // + Status = UpdateBootMode (PeiServices, PlatformInfo); + ASSERT_EFI_ERROR (Status); + + SetPlatformBootMode (PeiServices, PlatformInfo); + + // + // Get setup variable. This can only be done after BootMode is updated + // + GetSetupVariable (PeiServices, &SystemConfiguration); + + CheckOsSelection(PeiServices, &SystemConfiguration); + + // + // Update PlatformInfo HOB according to setup variable + // + PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration); + + InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration); + + // + // Initialize VlvPolicy PPI + // + Status = VlvPolicyInit (PeiServices, &SystemConfiguration); + ASSERT_EFI_ERROR (Status); + + // + // Soc specific GPIO setting + // + ConfigureSoCGpio(&SystemConfiguration); + + // + // Baylake Board specific. + // + if (PlatformInfo->BoardId == BOARD_ID_BL_RVP || + PlatformInfo->BoardId == BOARD_ID_BL_FFRD || + PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 || + PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L || + PlatformInfo->BoardId == BOARD_ID_BL_STHI || + PlatformInfo->BoardId == BOARD_ID_BB_RVP || + PlatformInfo->BoardId == BOARD_ID_BS_RVP || + PlatformInfo->BoardId == BOARD_ID_MINNOW2 || + PlatformInfo->BoardId == BOARD_ID_CVH) { + ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo); + + } + + + // + // Configure LPE + // Alpine Valley and Bayley Bay board specific + // + ConfigureLpeGpio(&SystemConfiguration); + + // + // Bayley Bay Board specific. + // + ConfigureSciSmiGpioRout(PlatformInfo); + if (SystemConfiguration.LpssI2C3Enabled == 1) { + ConfigureMipiCsi(); + } + + + // + // Do basic CPU init + // + Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo); + + // + // Perform basic SSA related platform initialization + // + PlatformSsaInit (&SystemConfiguration,PeiServices); + + + // + // Do basic PCH init + // + Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType); + ASSERT_EFI_ERROR (Status); + + // + // Initialize platform PPIs + // + Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]); + ASSERT_EFI_ERROR (Status); + + if (PlatformInfo->BoardId != BOARD_ID_CVH) { + InstallPlatformClocksNotify (PeiServices); + InstallPlatformSysCtrlGPIONotify(PeiServices); + } + + // + // Initialize platform PPIs + // + Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Measured Boot + // + Status = MeasuredBootInit (PeiServices, &SystemConfiguration); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + + Return the mainblockcompact Fv. + + @param FvNumber Our enumeration of the firmware volumes we care about. + + @param FvAddress Base Address of the memory containing the firmware volume + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND + +**/ +EFI_STATUS +EFIAPI +FindFv ( + IN EFI_PEI_FIND_FV_PPI *This, + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT8 *FvNumber, + OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress + ) +{ + // + // At present, we only have one Fv to search + // + if (*FvNumber == 0) { + *FvNumber = 1; + *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase); + return EFI_SUCCESS; + } + else if (*FvNumber == 1) { + *FvNumber = 2; + *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base); + return EFI_SUCCESS; + } + else { // Not the one Fv we care about + return EFI_NOT_FOUND; + } +} + +EFI_STATUS +EFIAPI +CpuOnlyReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ +// MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01) +#ifdef __GNUC__ + __asm__ + ( + "xorl %ecx, %ecx\n" + "1:hlt; hlt; hlt\n" + "jmp 1b\n" + ); +#else + _asm { + xor ecx, ecx + HltLoop: + hlt + hlt + hlt + loop HltLoop + } +#endif + // + // If we get here we need to mark it as a failure. + // + return EFI_UNSUPPORTED; +} + + +#ifdef __GNUC__ +#pragma GCC pop_options +#else +#pragma optimize ("", on) +#endif diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h new file mode 100644 index 0000000000..c2cdfa3900 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h @@ -0,0 +1,1502 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + PlatformEarlyInit.h + +Abstract: + + Platform Early Stage header file + + + +--*/ + +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +#ifndef _EFI_PLATFORM_EARLY_INIT_H_ +#define _EFI_PLATFORM_EARLY_INIT_H_ + +#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x +#include +#include "PlatformBaseAddresses.h" +#include "PchAccess.h" +#include "VlvAccess.h" +#include "SetupMode.h" +#include "PlatformBootMode.h" +#include "Platform.h" +#include "LegacySpeaker.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMC_LAN_ON 0x46 +#define SMC_LAN_OFF 0x47 +#define SMC_DEEP_S3_STS 0xB2 + + + + +// +// Wake Event Types +// +#define SMBIOS_WAKEUP_TYPE_RESERVED 0x00 +#define SMBIOS_WAKEUP_TYPE_OTHERS 0x01 +#define SMBIOS_WAKEUP_TYPE_UNKNOWN 0x02 +#define SMBIOS_WAKEUP_TYPE_APM_TIMER 0x03 +#define SMBIOS_WAKEUP_TYPE_MODEM_RING 0x04 +#define SMBIOS_WAKEUP_TYPE_LAN_REMOTE 0x05 +#define SMBIOS_WAKEUP_TYPE_POWER_SWITCH 0x06 +#define SMBIOS_WAKEUP_TYPE_PCI_PME 0x07 +#define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED 0x08 + +#define EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE 0x80000008 + +// +// Defines for stall ppi +// +#define PEI_STALL_RESOLUTION 1 + +// +// Used in PEI memory test routines +// +#define MEMORY_TEST_COVER_SPAN 0x40000 +#define MEMORY_TEST_PATTERN 0x5A5A5A5A + +#define EFI_LOW_BEEP_FREQUENCY 0x31B +#define EFI_HIGH_BEEP_FREQUENCY 0x254 + +// +// General Purpose Constants +// +#define ICH_ACPI_TIMER_MAX_VALUE 0x1000000 //The timer is 24 bit overflow + + + +// +// +// GPIO Register Settings for ValleyFalls (Tablet) +// +// +// IO Space configyuration registers +// Field Descriptions: +// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode. +// I/O: Defines whether GPIOs are inputs (I) or outputs (O). +// (Note: Only meaningful for pins used as GPIOs.) +// LVL: This field gives you the initial value for "output" GPIO's. +// (Note: The output level is dependent upon whether the pin is inverted.) +// TPE: Defines whether Trigger Positive Edge Enable. +// TNE: Defines whether Trigger Negative Edge Enable. +// WAKE_EN: only support in SUS community +// (Note: Only affects the level sent to the GPE logic and does not +// affect the level read through the GPIO registers.) +// +// +// Memory spcae configuration registers +// +// Field Descriptions: +// PAD releated: +// PAD_CONF0 +// PAD_CONF1 +// PAD_VAL +// PAD_DFT +// +// Notes: +// 1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE +// +// Signal UsedAs USE I/O LVL TPE TNE PCONF0 PCONF1 PVAL PDFT +// ------------------------------------------------------------------------------------------------------------------------- +// GPIO0 UART1_RXD-L N I - - - cd29h - - - +// GPIO1 UART1_TXD-0 N O - - - cd29h - - - +// *GPIO2 UART1_RTS_B-1 N I - - - cca9h - - - +// *GPIO3 UART1_CTS_B-H N O - - - cca9h - - - + +// GPIO4 I2C1_SDA-OD-O N - - - - cca9h - - - +// GPIO5 I2C1_SCL-OD-O N - - - - cca9h - - - +// GPIO6 I2S_SYSCLK-0 N O - - - 8d51h - - - +// GPIO7 I2S_L_R-0 (SP) N O - - - 8cd1h - - - +// GPIO8 I2S_DATA_OUT-0 N O - - - 8cd1h - - - +// GPIO9 I2S_SDATA_IN-L N I - - - 8cd1h - - - + +// GPIO10 PCM_CLK-0 N O - - - 8d51h - - - +// GPIO11 PCM_FSYNC-0 (SP) N O - - - 8cd1h - - - +// GPIO12 PCM_DATA_OUT-0 (SP) N O - - - 8cd1h - - - +// GPIO13 PCM_DATA_IN-L N I - - - 8d51h - - - + +// GPIO14 SATA_GP0 N - - - - - - - - +// GPIO15 I2C2_SDA-OD-O/I N - - - - ccaah - - - + +// GPIO16 SATA_LEDN N O - - - - - - - +// GPIO17 UART2_RTS_B-1 N I - - - cd2ah - - - +// GPIO18 UART2_CTS_B-H N O - - - ccaah - - - +// GPIO19 UART2_RXD-H N I - - - ccaah - - - + +// GPIO20 I2C2_SCL-OD-O/I N - - - - ccaah - - - +// GPIO21 **PCIE_CLKREQ4B N - - - - - - - - +// GPIO22 UART2_TXD-0 N O - - - ccaah - - - +// GPIO23 FLEX_CLK_SE1 N - - - - - - - - + +// GPIO24 SPI0_SCK-0 N O - - - 8d02h - - - +// GPIO25 SPI0_CS-1 N O - - - 8d02h - - - +// GPIO26 SPI0_MOSI-0 N O - - - 8d02h - - - +// GPIO27 SPI0_MISO-L N I - - - 8d02h - - - + +// GPIO28 UART3_RXD-L N I - - - - - - - +// GPIO29 UART3_TXD-0 N O - - - - - - - +// GPIO30 UART4_RXD-L N I - - - - - - - +// GPIO31 UART4_TXD-0 N O - - - - - - - + +// GPIO32 SDMMC1_CLK N - - - - 208d51h - - - +// GPIO33 SDMMC1_D0 N - - - - 8cd1h - - - +// GPIO34 SDMMC1_D1 N - - - - 8cd1h - - - +// GPIO35 SDMMC1_D2 N - - - - 8cd1h - - - +// GPIO36 SDMMC1_D3_CD_B N - - - - 8cd1h - - - +// GPIO37 MMC1_D4_SD_WE N - - - - 8cd1h - - - +// GPIO38 MMC1_D5 N - - - - 8cd1h - - - +// GPIO39 MMC1_D6 N - - - - 8cd1h - - - +// GPIO40 MMC1_D7 N - - - - 8cd1h - - - +// GPIO41 SDMMC1_CMD N - - - - 8cd1h - - - +// GPIO42 MMC1_RESET_B N - - - - 208d51h - - - + +// GPIO43 SDMMC2_CLK N - - - - 208d51h - - - +// GPIO44 SDMMC2_D0 N - - - - 8cd1h - - - +// GPIO45 SDMMC2_D1 N - - - - 8cd1h - - - +// GPIO46 SDMMC2_D2 N - - - - 8cd1h - - - +// GPIO47 SDMMC2_D3_CD_B N - - - - 8cd1h - - - +// GPIO48 SDMMC2_CMD N - - - - 8cd1h - - - + +// GPIO49 SDMMC3_CLK N - - - - 8d51h - - - +// GPIO50 SDMMC3_D0 N - - - - 8cd1h - - - +// GPIO51 SDMMC3_D1 N - - - - 8cd1h - - - +// GPIO52 SDMMC3_D2 N - - - - 8cd1h - - - +// GPIO53 SDMMC3_D3 N - - - - 8cd1h - - - +// GPIO54 SDMMC3_CD_B N - - - - cca9h - - - +// GPIO55 SDMMC3_CMD N - - - - 8cd1h - - - +// GPIO56 SDMMC3_1P8_EN N - - - - cd29h - - - + +// GPIO57 LPC_AD0 N - - - - - - - - +// GPIO58 LPC_AD1 N - - - - - - - - +// GPIO59 LPC_AD2 N - - - - - - - - +// GPIO60 LPC_AD3 N - - - - - - - - +// GPIO61 LPC_FRAMEB N O - - - - - - - +// GPIO62 LPC_CLKOUT0 N O - - - - - - - +// GPIO63 LPC_CLKOUT1 N O - - - - - - - +// GPIO64 LPC_CLKRUNB N - - - - - - - - + +// GPIO65 SMB_DATA N - - - - - - - - +// GPIO66 SMB_CLK N - - - - - - - - +// GPIO67 SMB_ALERTB N - - - - - - - - + +// GPIO68 ILB_SEIRQ N - - - - - - - - +// GPIO69 SPKR N O - - - - - - - + +//SUS WELL + +//GPIO_SUS0 BT_WAKEUP_VLV N O - - - CCA8h - - - +//GPIO_SUS1 BT_CLOCK_REQ N O - - - CCA8h - - - +//GPIO_SUS2 WIFI_PWR_EN N O - - - CCA8h - - - +//GPIO_SUS3 SD_CARD_PWR_EN N O - - - CD28h - - - +//GPIO_SUS4 GPIO_SUS4 N O - - - CD28h - - - +//GPIO_SUS5 GPIO_SUS5 N O - - - CD28h - - - +//GPIO_SUS6 SUSPWRDNACK N O - - - 8850h - - - +//GPIO_SUS7 PMU_SLP_DDRVTT_B N O - - - 8850h - - - +//GPIO_SUS8 PMU_WAKE_B N O - - - CCA8h - - - +//GPIO_SUS9 PMU_PWRBTN_B N O - - - CCA8h - - - +//GPIO_SUS10 PMU_WAKE_LAN_B N O - - - CCA8h - - - +//GPIO_SUS11 SUS_STAT_B N O - - - C828h - - - +//GPIO_SUS12 GPIO_SUS12 N O - - - C828h - - - +//GPIO_SUS13 USB_OC0_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS14 GPIO_SUS14 N O - - - CCA8h - - - +//GPIO_SUS15 SPI_CS1_B-20K,H N O - - - 8C80h - - - +//GPIO_SUS16 PMU_SUSCLK N O - - - C828h - - - +// + + +#define VF_TAB_GPIO_USE_SEL_VAL_0_31 0x00000000 +#define VF_TAB_GPIO_USE_SEL_VAL_32_63 0x00000000 +#define VF_TAB_GPIO_USE_SEL_VAL_64_70 0x00000000 +#define VF_TAB_GPIO_USE_SEL_VAL_SUS 0x00000000 + +// +//1010 --00 0100 01-- 0101 --0- 0001 1010 +// +#define VF_TAB_GPIO_IO_SEL_VAL_0_31 0x00000000 // BIT30 | BIT28 | BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0 +#define VF_TAB_GPIO_IO_SEL_VAL_32_63 0x00000000 +#define VF_TAB_GPIO_IO_SEL_VAL_64_70 0x00000000 +#define VF_TAB_GPIO_IO_SEL_VAL_SUS 0x00000000 + + +#define VF_TAB_GPIO_LVL_VAL_0_31 0x00000000 +#define VF_TAB_GPIO_LVL_VAL_32_63 0x00000000 +#define VF_TAB_GPIO_LVL_VAL_64_70 0x00000000 +#define VF_TAB_GPIO_LVL_VAL_SUS 0x00000000 + +#define VF_TAB_GPIO_TPE_VAL_0_31 0x00000000 +#define VF_TAB_GPIO_TPE_VAL_SUS 0x00000000 + +#define VF_TAB_GPIO_TNE_VAL_0_31 0x00000000 +#define VF_TAB_GPIO_TNE_VAL_SUS 0x00000000 + +#define VF_TAB_GPIO_TS_VAL_0_31 0x00000000 +#define VF_TAB_GPIO_TS_VAL_SUS 0x00000000 + + +// +// Memory space registers +// + +// +// CONF0 +// +#define VF_TAB_PAD_CONF0_GPIO0 0xcd29 +#define VF_TAB_PAD_CONF0_GPIO1 0xcd29 +#define VF_TAB_PAD_CONF0_GPIO2 0xcca9 +#define VF_TAB_PAD_CONF0_GPIO3 0xcca9 +#define VF_TAB_PAD_CONF0_GPIO4 0xcca9 +#define VF_TAB_PAD_CONF0_GPIO5 0xcca9 +#define VF_TAB_PAD_CONF0_GPIO6 0x8d51 +#define VF_TAB_PAD_CONF0_GPIO7 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO8 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO9 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO10 0x8d51 +#define VF_TAB_PAD_CONF0_GPIO11 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO12 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO13 0x8d51 +#define VF_TAB_PAD_CONF0_GPIO14 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO15 0xccaa +#define VF_TAB_PAD_CONF0_GPIO16 0xC828 +#define VF_TAB_PAD_CONF0_GPIO17 0xcd2a +#define VF_TAB_PAD_CONF0_GPIO18 0xccaa +#define VF_TAB_PAD_CONF0_GPIO19 0xccaa +#define VF_TAB_PAD_CONF0_GPIO20 0xccaa +#define VF_TAB_PAD_CONF0_GPIO21 0xCCA9 +#define VF_TAB_PAD_CONF0_GPIO22 0xccaa +#define VF_TAB_PAD_CONF0_GPIO23 0xCD2A +#define VF_TAB_PAD_CONF0_GPIO24 0x8d02 +#define VF_TAB_PAD_CONF0_GPIO25 0x8d02 +#define VF_TAB_PAD_CONF0_GPIO26 0x8d02 +#define VF_TAB_PAD_CONF0_GPIO27 0x8d02 +#define VF_TAB_PAD_CONF0_GPIO28 0x8D02 +#define VF_TAB_PAD_CONF0_GPIO29 0x8D02 +#define VF_TAB_PAD_CONF0_GPIO30 0x8D00 +#define VF_TAB_PAD_CONF0_GPIO31 0xCD2A +#define VF_TAB_PAD_CONF0_GPIO32 0x208d51 +#define VF_TAB_PAD_CONF0_GPIO33 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO34 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO35 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO36 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO37 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO38 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO39 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO40 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO41 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO42 0x208d51 +#define VF_TAB_PAD_CONF0_GPIO43 0x208d51 +#define VF_TAB_PAD_CONF0_GPIO44 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO45 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO46 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO47 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO48 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO49 0x8d51 +#define VF_TAB_PAD_CONF0_GPIO50 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO51 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO52 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO53 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO54 0xcca9 +#define VF_TAB_PAD_CONF0_GPIO55 0x8cd1 +#define VF_TAB_PAD_CONF0_GPIO56 0xcd29 +#define VF_TAB_PAD_CONF0_GPIO57 0x8C80 +#define VF_TAB_PAD_CONF0_GPIO58 0x8C80 +#define VF_TAB_PAD_CONF0_GPIO59 0x8C80 +#define VF_TAB_PAD_CONF0_GPIO60 0x8C80 +#define VF_TAB_PAD_CONF0_GPIO61 0x8800 +#define VF_TAB_PAD_CONF0_GPIO62 0x8D00 +#define VF_TAB_PAD_CONF0_GPIO63 0x8800 +#define VF_TAB_PAD_CONF0_GPIO64 0x8800 +#define VF_TAB_PAD_CONF0_GPIO65 0xC828 +#define VF_TAB_PAD_CONF0_GPIO66 0xC828 +#define VF_TAB_PAD_CONF0_GPIO67 0xC828 +#define VF_TAB_PAD_CONF0_GPIO68 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO69 0xC828 +#define VF_TAB_PAD_CONF0_GPIO70 0xCCA8 + + + +// +// PAD_CONF1 +// +#define VF_TAB_PAD_CONF1_GPIO0 0x20002 +#define VF_TAB_PAD_CONF1_GPIO1 0x20002 +#define VF_TAB_PAD_CONF1_GPIO2 0x20002 +#define VF_TAB_PAD_CONF1_GPIO3 0x20002 +#define VF_TAB_PAD_CONF1_GPIO4 0x20002 +#define VF_TAB_PAD_CONF1_GPIO5 0x20002 +#define VF_TAB_PAD_CONF1_GPIO6 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO7 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO8 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO9 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO10 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO11 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO12 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO13 0x1F000F +#define VF_TAB_PAD_CONF1_GPIO14 0x20002 +#define VF_TAB_PAD_CONF1_GPIO15 0x20002 +#define VF_TAB_PAD_CONF1_GPIO16 0x20002 +#define VF_TAB_PAD_CONF1_GPIO17 0x20002 +#define VF_TAB_PAD_CONF1_GPIO18 0x20002 +#define VF_TAB_PAD_CONF1_GPIO19 0x20002 +#define VF_TAB_PAD_CONF1_GPIO20 0x20002 +#define VF_TAB_PAD_CONF1_GPIO21 0x20002 +#define VF_TAB_PAD_CONF1_GPIO22 0x20002 +#define VF_TAB_PAD_CONF1_GPIO23 0x20002 +#define VF_TAB_PAD_CONF1_GPIO24 0x00000 +#define VF_TAB_PAD_CONF1_GPIO25 0x00000 +#define VF_TAB_PAD_CONF1_GPIO26 0x00000 +#define VF_TAB_PAD_CONF1_GPIO27 0x00000 +#define VF_TAB_PAD_CONF1_GPIO28 0x00000 +#define VF_TAB_PAD_CONF1_GPIO29 0x00000 +#define VF_TAB_PAD_CONF1_GPIO30 0x00000 +#define VF_TAB_PAD_CONF1_GPIO31 0x20002 +#define VF_TAB_PAD_CONF1_GPIO32 0x00000 +#define VF_TAB_PAD_CONF1_GPIO33 0x00000 +#define VF_TAB_PAD_CONF1_GPIO34 0x00000 +#define VF_TAB_PAD_CONF1_GPIO35 0x00000 +#define VF_TAB_PAD_CONF1_GPIO36 0x00000 +#define VF_TAB_PAD_CONF1_GPIO37 0x00000 +#define VF_TAB_PAD_CONF1_GPIO38 0x00000 +#define VF_TAB_PAD_CONF1_GPIO39 0x00000 +#define VF_TAB_PAD_CONF1_GPIO40 0x00000 +#define VF_TAB_PAD_CONF1_GPIO41 0x00000 +#define VF_TAB_PAD_CONF1_GPIO42 0x00000 +#define VF_TAB_PAD_CONF1_GPIO43 0x00000 +#define VF_TAB_PAD_CONF1_GPIO44 0x00000 +#define VF_TAB_PAD_CONF1_GPIO45 0x00000 +#define VF_TAB_PAD_CONF1_GPIO46 0x00000 +#define VF_TAB_PAD_CONF1_GPIO47 0x00000 +#define VF_TAB_PAD_CONF1_GPIO48 0x00000 +#define VF_TAB_PAD_CONF1_GPIO49 0x00000 +#define VF_TAB_PAD_CONF1_GPIO50 0x00000 +#define VF_TAB_PAD_CONF1_GPIO51 0x00000 +#define VF_TAB_PAD_CONF1_GPIO52 0x00000 +#define VF_TAB_PAD_CONF1_GPIO53 0x00000 +#define VF_TAB_PAD_CONF1_GPIO54 0x20002 +#define VF_TAB_PAD_CONF1_GPIO55 0x00000 +#define VF_TAB_PAD_CONF1_GPIO56 0x20002 +#define VF_TAB_PAD_CONF1_GPIO57 0x00000 +#define VF_TAB_PAD_CONF1_GPIO58 0x00000 +#define VF_TAB_PAD_CONF1_GPIO59 0x00000 +#define VF_TAB_PAD_CONF1_GPIO60 0x00000 +#define VF_TAB_PAD_CONF1_GPIO61 0x00000 +#define VF_TAB_PAD_CONF1_GPIO62 0x00000 +#define VF_TAB_PAD_CONF1_GPIO63 0x00000 +#define VF_TAB_PAD_CONF1_GPIO64 0x00000 +#define VF_TAB_PAD_CONF1_GPIO65 0x20002 +#define VF_TAB_PAD_CONF1_GPIO66 0x20002 +#define VF_TAB_PAD_CONF1_GPIO67 0x20002 +#define VF_TAB_PAD_CONF1_GPIO68 0x20002 +#define VF_TAB_PAD_CONF1_GPIO69 0x20002 +#define VF_TAB_PAD_CONF1_GPIO70 0x20002 + + +// +// PAD_VAL +// +#define VF_TAB_PAD_VAL_GPIO0 0x2 +#define VF_TAB_PAD_VAL_GPIO1 0x2 +#define VF_TAB_PAD_VAL_GPIO2 0x2 +#define VF_TAB_PAD_VAL_GPIO3 0x2 +#define VF_TAB_PAD_VAL_GPIO4 0x2 +#define VF_TAB_PAD_VAL_GPIO5 0x2 +#define VF_TAB_PAD_VAL_GPIO6 0x2 +#define VF_TAB_PAD_VAL_GPIO7 0x2 +#define VF_TAB_PAD_VAL_GPIO8 0x2 +#define VF_TAB_PAD_VAL_GPIO9 0x2 +#define VF_TAB_PAD_VAL_GPIO10 0x2 +#define VF_TAB_PAD_VAL_GPIO11 0x2 +#define VF_TAB_PAD_VAL_GPIO12 0x2 +#define VF_TAB_PAD_VAL_GPIO13 0x2 +#define VF_TAB_PAD_VAL_GPIO14 0x2 +#define VF_TAB_PAD_VAL_GPIO15 0x2 +#define VF_TAB_PAD_VAL_GPIO16 0x4 +#define VF_TAB_PAD_VAL_GPIO17 0x2 +#define VF_TAB_PAD_VAL_GPIO18 0x2 +#define VF_TAB_PAD_VAL_GPIO19 0x2 +#define VF_TAB_PAD_VAL_GPIO20 0x2 +#define VF_TAB_PAD_VAL_GPIO21 0x2 +#define VF_TAB_PAD_VAL_GPIO22 0x2 +#define VF_TAB_PAD_VAL_GPIO23 0x2 +#define VF_TAB_PAD_VAL_GPIO24 0x2 +#define VF_TAB_PAD_VAL_GPIO25 0x2 +#define VF_TAB_PAD_VAL_GPIO26 0x2 +#define VF_TAB_PAD_VAL_GPIO27 0x2 +#define VF_TAB_PAD_VAL_GPIO28 0x2 +#define VF_TAB_PAD_VAL_GPIO29 0x2 +#define VF_TAB_PAD_VAL_GPIO30 0x2 +#define VF_TAB_PAD_VAL_GPIO31 0x2 +#define VF_TAB_PAD_VAL_GPIO32 0x2 +#define VF_TAB_PAD_VAL_GPIO33 0x2 +#define VF_TAB_PAD_VAL_GPIO34 0x2 +#define VF_TAB_PAD_VAL_GPIO35 0x2 +#define VF_TAB_PAD_VAL_GPIO36 0x2 +#define VF_TAB_PAD_VAL_GPIO37 0x2 +#define VF_TAB_PAD_VAL_GPIO38 0x2 +#define VF_TAB_PAD_VAL_GPIO39 0x2 +#define VF_TAB_PAD_VAL_GPIO40 0x2 +#define VF_TAB_PAD_VAL_GPIO41 0x2 +#define VF_TAB_PAD_VAL_GPIO42 0x2 +#define VF_TAB_PAD_VAL_GPIO43 0x2 +#define VF_TAB_PAD_VAL_GPIO44 0x2 +#define VF_TAB_PAD_VAL_GPIO45 0x2 +#define VF_TAB_PAD_VAL_GPIO46 0x2 +#define VF_TAB_PAD_VAL_GPIO47 0x2 +#define VF_TAB_PAD_VAL_GPIO48 0x2 +#define VF_TAB_PAD_VAL_GPIO49 0x2 +#define VF_TAB_PAD_VAL_GPIO50 0x2 +#define VF_TAB_PAD_VAL_GPIO51 0x2 +#define VF_TAB_PAD_VAL_GPIO52 0x2 +#define VF_TAB_PAD_VAL_GPIO53 0x2 +#define VF_TAB_PAD_VAL_GPIO54 0x2 +#define VF_TAB_PAD_VAL_GPIO55 0x2 +#define VF_TAB_PAD_VAL_GPIO56 0x2 +#define VF_TAB_PAD_VAL_GPIO57 0x2 +#define VF_TAB_PAD_VAL_GPIO58 0x2 +#define VF_TAB_PAD_VAL_GPIO59 0x2 +#define VF_TAB_PAD_VAL_GPIO60 0x2 +#define VF_TAB_PAD_VAL_GPIO61 0x4 +#define VF_TAB_PAD_VAL_GPIO62 0x2 +#define VF_TAB_PAD_VAL_GPIO63 0x2 +#define VF_TAB_PAD_VAL_GPIO64 0x2 +#define VF_TAB_PAD_VAL_GPIO65 0x2 +#define VF_TAB_PAD_VAL_GPIO66 0x2 +#define VF_TAB_PAD_VAL_GPIO67 0x0 +#define VF_TAB_PAD_VAL_GPIO68 0x2 +#define VF_TAB_PAD_VAL_GPIO69 0x4 +#define VF_TAB_PAD_VAL_GPIO70 0x2 + + +// +// PAD_DFT +// +#define VF_TAB_PAD_DFT_GPIO0 0xC +#define VF_TAB_PAD_DFT_GPIO1 0xC +#define VF_TAB_PAD_DFT_GPIO2 0xC +#define VF_TAB_PAD_DFT_GPIO3 0xC +#define VF_TAB_PAD_DFT_GPIO4 0xC +#define VF_TAB_PAD_DFT_GPIO5 0xC +#define VF_TAB_PAD_DFT_GPIO6 0xC +#define VF_TAB_PAD_DFT_GPIO7 0xC +#define VF_TAB_PAD_DFT_GPIO8 0xC +#define VF_TAB_PAD_DFT_GPIO9 0xC +#define VF_TAB_PAD_DFT_GPIO10 0xC +#define VF_TAB_PAD_DFT_GPIO11 0xC +#define VF_TAB_PAD_DFT_GPIO12 0xC +#define VF_TAB_PAD_DFT_GPIO13 0xC +#define VF_TAB_PAD_DFT_GPIO14 0xC +#define VF_TAB_PAD_DFT_GPIO15 0xC +#define VF_TAB_PAD_DFT_GPIO16 0xC +#define VF_TAB_PAD_DFT_GPIO17 0xC +#define VF_TAB_PAD_DFT_GPIO18 0xC +#define VF_TAB_PAD_DFT_GPIO19 0xC +#define VF_TAB_PAD_DFT_GPIO20 0xC +#define VF_TAB_PAD_DFT_GPIO21 0xC +#define VF_TAB_PAD_DFT_GPIO22 0xC +#define VF_TAB_PAD_DFT_GPIO23 0xC +#define VF_TAB_PAD_DFT_GPIO24 0xC +#define VF_TAB_PAD_DFT_GPIO25 0xC +#define VF_TAB_PAD_DFT_GPIO26 0xC +#define VF_TAB_PAD_DFT_GPIO27 0xC +#define VF_TAB_PAD_DFT_GPIO28 0xC +#define VF_TAB_PAD_DFT_GPIO29 0xC +#define VF_TAB_PAD_DFT_GPIO30 0xC +#define VF_TAB_PAD_DFT_GPIO31 0xC +#define VF_TAB_PAD_DFT_GPIO32 0xC +#define VF_TAB_PAD_DFT_GPIO33 0xC +#define VF_TAB_PAD_DFT_GPIO34 0xC +#define VF_TAB_PAD_DFT_GPIO35 0xC +#define VF_TAB_PAD_DFT_GPIO36 0xC +#define VF_TAB_PAD_DFT_GPIO37 0xC +#define VF_TAB_PAD_DFT_GPIO38 0xC +#define VF_TAB_PAD_DFT_GPIO39 0xC +#define VF_TAB_PAD_DFT_GPIO40 0xC +#define VF_TAB_PAD_DFT_GPIO41 0xC +#define VF_TAB_PAD_DFT_GPIO42 0xC +#define VF_TAB_PAD_DFT_GPIO43 0xC +#define VF_TAB_PAD_DFT_GPIO44 0xC +#define VF_TAB_PAD_DFT_GPIO45 0xC +#define VF_TAB_PAD_DFT_GPIO46 0xC +#define VF_TAB_PAD_DFT_GPIO47 0xC +#define VF_TAB_PAD_DFT_GPIO48 0xC +#define VF_TAB_PAD_DFT_GPIO49 0xC +#define VF_TAB_PAD_DFT_GPIO50 0xC +#define VF_TAB_PAD_DFT_GPIO51 0xC +#define VF_TAB_PAD_DFT_GPIO52 0xC +#define VF_TAB_PAD_DFT_GPIO53 0xC +#define VF_TAB_PAD_DFT_GPIO54 0xC +#define VF_TAB_PAD_DFT_GPIO55 0xC +#define VF_TAB_PAD_DFT_GPIO56 0xC +#define VF_TAB_PAD_DFT_GPIO57 0xC +#define VF_TAB_PAD_DFT_GPIO58 0xC +#define VF_TAB_PAD_DFT_GPIO59 0xC +#define VF_TAB_PAD_DFT_GPIO60 0xC +#define VF_TAB_PAD_DFT_GPIO61 0xC +#define VF_TAB_PAD_DFT_GPIO62 0xC +#define VF_TAB_PAD_DFT_GPIO63 0xC +#define VF_TAB_PAD_DFT_GPIO64 0xC +#define VF_TAB_PAD_DFT_GPIO65 0xC +#define VF_TAB_PAD_DFT_GPIO66 0xC +#define VF_TAB_PAD_DFT_GPIO67 0xC +#define VF_TAB_PAD_DFT_GPIO68 0xC +#define VF_TAB_PAD_DFT_GPIO69 0xC +#define VF_TAB_PAD_DFT_GPIO70 0xC + + +// +//SUS WELL +// + +// +// CONF0 +// +#define VF_TAB_PAD_CONF0_GPIO_SUS0 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS1 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS2 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS3 0xCD28 +#define VF_TAB_PAD_CONF0_GPIO_SUS4 0xCD28 +#define VF_TAB_PAD_CONF0_GPIO_SUS5 0xCD28 +#define VF_TAB_PAD_CONF0_GPIO_SUS6 0x8850 +#define VF_TAB_PAD_CONF0_GPIO_SUS7 0x8850 +#define VF_TAB_PAD_CONF0_GPIO_SUS8 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS9 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS10 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS11 0xC828 +#define VF_TAB_PAD_CONF0_GPIO_SUS12 0xC828 +#define VF_TAB_PAD_CONF0_GPIO_SUS13 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS14 0xCCA8 +#define VF_TAB_PAD_CONF0_GPIO_SUS15 0x8C80 +#define VF_TAB_PAD_CONF0_GPIO_SUS16 0xC828 + +// +// CONF1 +// +#define VF_TAB_PAD_CONF1_GPIO_SUS0 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS1 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS2 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS3 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS4 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS5 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS6 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS7 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS8 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS9 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS10 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS11 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS12 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS13 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS14 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS15 0 +#define VF_TAB_PAD_CONF1_GPIO_SUS16 0 + +// +// PAD_VAL +// +#define VF_TAB_PAD_VAL_GPIO_SUS0 0 +#define VF_TAB_PAD_VAL_GPIO_SUS1 0 +#define VF_TAB_PAD_VAL_GPIO_SUS2 0 +#define VF_TAB_PAD_VAL_GPIO_SUS3 0 +#define VF_TAB_PAD_VAL_GPIO_SUS4 0 +#define VF_TAB_PAD_VAL_GPIO_SUS5 0 +#define VF_TAB_PAD_VAL_GPIO_SUS6 0 +#define VF_TAB_PAD_VAL_GPIO_SUS7 0 +#define VF_TAB_PAD_VAL_GPIO_SUS8 0 +#define VF_TAB_PAD_VAL_GPIO_SUS9 0 +#define VF_TAB_PAD_VAL_GPIO_SUS10 0 +#define VF_TAB_PAD_VAL_GPIO_SUS11 0 +#define VF_TAB_PAD_VAL_GPIO_SUS12 0 +#define VF_TAB_PAD_VAL_GPIO_SUS13 0 +#define VF_TAB_PAD_VAL_GPIO_SUS14 0 +#define VF_TAB_PAD_VAL_GPIO_SUS15 0 +#define VF_TAB_PAD_VAL_GPIO_SUS16 0 + +// +// PAD_DFT +// +#define VF_TAB_PAD_DFT_GPIO_SUS0 0 +#define VF_TAB_PAD_DFT_GPIO_SUS1 0 +#define VF_TAB_PAD_DFT_GPIO_SUS2 0 +#define VF_TAB_PAD_DFT_GPIO_SUS3 0 +#define VF_TAB_PAD_DFT_GPIO_SUS4 0 +#define VF_TAB_PAD_DFT_GPIO_SUS5 0 +#define VF_TAB_PAD_DFT_GPIO_SUS6 0 +#define VF_TAB_PAD_DFT_GPIO_SUS7 0 +#define VF_TAB_PAD_DFT_GPIO_SUS8 0 +#define VF_TAB_PAD_DFT_GPIO_SUS9 0 +#define VF_TAB_PAD_DFT_GPIO_SUS10 0 +#define VF_TAB_PAD_DFT_GPIO_SUS11 0 +#define VF_TAB_PAD_DFT_GPIO_SUS12 0 +#define VF_TAB_PAD_DFT_GPIO_SUS13 0 +#define VF_TAB_PAD_DFT_GPIO_SUS14 0 +#define VF_TAB_PAD_DFT_GPIO_SUS15 0 +#define VF_TAB_PAD_DFT_GPIO_SUS16 0 + + +// +// +// GPIO Register Settings for ValleyFalls (Netbook) +// +// +// IO Space configyuration registers +// Field Descriptions: +// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode. +// I/O: Defines whether GPIOs are inputs (I) or outputs (O). +// (Note: Only meaningful for pins used as GPIOs.) +// LVL: This field gives you the initial value for "output" GPIO's. +// (Note: The output level is dependent upon whether the pin is inverted.) +// TPE: Defines whether Trigger Positive Edge Enable. +// TNE: Defines whether Trigger Negative Edge Enable. +// WAKE_EN: only support in SUS community +// (Note: Only affects the level sent to the GPE logic and does not +// affect the level read through the GPIO registers.) +// +// +// Memory spcae configuration registers +// +// Field Descriptions: +// PAD releated: +// PAD_CONF0 +// PAD_CONF1 +// PAD_VAL +// PAD_DFT +// +// Notes: +// 1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE +// +// Signal UsedAs USE I/O LVL TPE TNE PCONF0 PCONF1 PVAL PDFT +// ------------------------------------------------------------------------------------------------------------------------- +// GPIO0 UART1_RXD-L N I - - - cd29h - - - +// GPIO1 UART1_TXD-0 N O - - - cd29h - - - +// *GPIO2 UART1_RTS_B-1 N I - - - cca9h - - - +// *GPIO3 UART1_CTS_B-H N O - - - cca9h - - - + +// GPIO4 NMI_B-H G - - - - cca9h - - - +// GPIO5 GPIO_D5 G - - - - cca9h - - - +// GPIO6 GPIO_D6 G O - - - 8d51h - - - +// GPIO7 GPIO_D7 G O - - - 8cd1h - - - +// GPIO8 GPIO_D8 G O - - - 8cd1h - - - +// GPIO9 GPIO_D9 G I - - - 8cd1h - - - + +// GPIO10 GPIO_D10 G O - - - 8d51h - - - +// GPIO11 GPIO_D11 G O - - - 8cd1h - - - +// GPIO12 GPIO_D12 G O - - - 8cd1h - - - +// GPIO13 GPIO_D13 G I - - - 8d51h - - - + +// GPIO14 SATA_GP0 N - - - - - - - - +// GPIO15 SATA_GP1-L N - - - - ccaah - - - + +// GPIO16 SATA_LEDN-OD-O N O - - - - - - - +// GPIO17 PCIE_CLKREQ0B-20K,H N I - - - cd2ah - - - +// GPIO18 PCIE_CLKREQ1B-20K,H N O - - - ccaah - - - +// GPIO19 PCIE_CLKREQ2B-20K,H N I - - - ccaah - - - +// GPIO20 PCIE_CLKREQ3B-20K,H N - - - - ccaah - - - +// GPIO21 PCIE_CLKREQ4B-20K,H N - - - - - - - - +// GPIO22 FLEX_CLK_SE0-20K,L N O - - - ccaah - - - +// GPIO23 FLEX_CLK_SE1-20K,L N - - - - - - - - + +// GPIO24 HDA_RSTB N O - - - 8d02h - - - +// GPIO25 HDA_SYNC N O - - - 8d02h - - - +// GPIO26 HDA_CLK N O - - - 8d02h - - - +// GPIO27 HDA_SDO N I - - - 8d02h - - - +// GPIO28 HDA_SDI0 N I - - - - - - - +// GPIO29 HDA_SDI1 N O - - - - - - - +// GPIO30 HDA_DOCKRSTB N I - - - - - - - +// GPIO31 HDA_DOCKENB N O - - - - - - - + +// GPIO32 SDMMC1_CLK N - - - - 208d51h - - - +// GPIO33 SDMMC1_D0 N - - - - 8cd1h - - - +// GPIO34 SDMMC1_D1 N - - - - 8cd1h - - - +// GPIO35 SDMMC1_D2 N - - - - 8cd1h - - - +// GPIO36 SDMMC1_D3_CD_B N - - - - 8cd1h - - - +// GPIO37 MMC1_D4_SD_WE N - - - - 8cd1h - - - +// GPIO38 MMC1_D5 N - - - - 8cd1h - - - +// GPIO39 MMC1_D6 N - - - - 8cd1h - - - +// GPIO40 MMC1_D7 N - - - - 8cd1h - - - +// GPIO41 SDMMC1_CMD N - - - - 8cd1h - - - +// GPIO42 MMC1_RESET_B N - - - - 208d51h - - - + +// GPIO43 SDMMC2_CLK N - - - - 208d51h - - - +// GPIO44 SDMMC2_D0 N - - - - 8cd1h - - - +// GPIO45 SDMMC2_D1 N - - - - 8cd1h - - - +// GPIO46 SDMMC2_D2 N - - - - 8cd1h - - - +// GPIO47 SDMMC2_D3_CD_B N - - - - 8cd1h - - - +// GPIO48 SDMMC2_CMD N - - - - 8cd1h - - - + +// GPIO49 SDMMC3_CLK N - - - - 8d51h - - - +// GPIO50 SDMMC3_D0 N - - - - 8cd1h - - - +// GPIO51 SDMMC3_D1 N - - - - 8cd1h - - - +// GPIO52 SDMMC3_D2 N - - - - 8cd1h - - - +// GPIO53 SDMMC3_D3 N - - - - 8cd1h - - - +// GPIO54 SDMMC3_CD_B N - - - - cca9h - - - +// GPIO55 SDMMC3_CMD N - - - - 8cd1h - - - +// GPIO56 SDMMC3_1P8_EN N - - - - cd29h - - - + +// GPIO57 LPC_AD0 N - - - - - - - - +// GPIO58 LPC_AD1 N - - - - - - - - +// GPIO59 LPC_AD2 N - - - - - - - - +// GPIO60 LPC_AD3 N - - - - - - - - +// GPIO61 LPC_FRAMEB N O - - - - - - - +// GPIO62 LPC_CLKOUT0 N O - - - - - - - +// GPIO63 LPC_CLKOUT1 N O - - - - - - - +// GPIO64 LPC_CLKRUNB N - - - - - - - - + +// GPIO65 SMB_DATA N - - - - - - - - +// GPIO66 SMB_CLK N - - - - - - - - +// GPIO67 SMB_ALERTB N - - - - - - - - + +// GPIO68 ILB_SEIRQ N - - - - - - - - +// GPIO69 SPKR N O - - - - - - - + +//SUS WELL + + +//GPIO_SUS0 GPIO_SUS0 N O - - - CCA8h - - - +//GPIO_SUS1 GPIO_SUS1 N O - - - CCA8h - - - +//GPIO_SUS2 GPIO_SUS2 N O - - - CCA8h - - - +//GPIO_SUS3 GPIO_SUS3 N O - - - CD28h - - - +//GPIO_SUS4 GPIO_SUS4 N O - - - CD28h - - - +//GPIO_SUS5 GPIO_SUS5 N O - - - CD28h - - - +//GPIO_SUS6 SUSPWRDNACK-0 N O - - - 8850h - - - +//GPIO_SUS7 PMU_SLP_DDRVTT_B-0 N O - - - 8850h - - - +//GPIO_SUS8 PMU_WAKE_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS9 PMU_PWRBTN_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS10 PMU_WAKE_LAN_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS11 SUS_STAT_B-1 N O - - - C828h - - - +//GPIO_SUS12 PMU_SUSCLK-0 N O - - - C828h - - - +//GPIO_SUS13 USB_OC0_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS14 USB_OC1_B-20K,H N O - - - CCA8h - - - +//GPIO_SUS15 SPI_CS1_B-20K,H N O - - - 8C80h - - - +//GPIO_SUS16 SPI_CS1_B-20K,H N O - - - C828h - - - +// + +#define VF_NET_GPIO_USE_SEL_VAL_0_31 0x00000000 +#define VF_NET_GPIO_USE_SEL_VAL_32_63 0x00000000 +#define VF_NET_GPIO_USE_SEL_VAL_64_70 0x00000000 +#define VF_NET_GPIO_USE_SEL_VAL_SUS 0x00000000 + +// +//1010 --00 0100 01-- 0101 --0- 0001 1010 +// +#define VF_NET_GPIO_IO_SEL_VAL_0_31 0x00000000 // BIT30 | BIT28 | BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0 +#define VF_NET_GPIO_IO_SEL_VAL_32_63 0x00000000 +#define VF_NET_GPIO_IO_SEL_VAL_64_70 0x00000000 +#define VF_NET_GPIO_IO_SEL_VAL_SUS 0x00000000 + + +#define VF_NET_GPIO_LVL_VAL_0_31 0x00000000 +#define VF_NET_GPIO_LVL_VAL_32_63 0x00000000 +#define VF_NET_GPIO_LVL_VAL_64_70 0x00000000 +#define VF_NET_GPIO_LVL_VAL_SUS 0x00000000 + +#define VF_NET_GPIO_TPE_VAL_0_31 0x00000000 +#define VF_NET_GPIO_TPE_VAL_SUS 0x00000000 + +#define VF_NET_GPIO_TNE_VAL_0_31 0x00000000 +#define VF_NET_GPIO_TNE_VAL_SUS 0x00000000 + +#define VF_NET_GPIO_TS_VAL_0_31 0x00000000 +#define VF_NET_GPIO_TS_VAL_SUS 0x00000000 + + +// +// Memory space registers +// + + +// +// CONF0 +// +#define VF_NET_PAD_CONF0_GPIO0 0xcd29 +#define VF_NET_PAD_CONF0_GPIO1 0xcd29 +#define VF_NET_PAD_CONF0_GPIO2 0xcca9 +#define VF_NET_PAD_CONF0_GPIO3 0xcca9 +#define VF_NET_PAD_CONF0_GPIO4 0xcca8 +#define VF_NET_PAD_CONF0_GPIO5 0xcca8 +#define VF_NET_PAD_CONF0_GPIO6 0x8d50 +#define VF_NET_PAD_CONF0_GPIO7 0x8cd0 +#define VF_NET_PAD_CONF0_GPIO8 0x8cd0 +#define VF_NET_PAD_CONF0_GPIO9 0x8cd0 +#define VF_NET_PAD_CONF0_GPIO10 0x8d50 +#define VF_NET_PAD_CONF0_GPIO11 0x8cd0 +#define VF_NET_PAD_CONF0_GPIO12 0x8cd0 +#define VF_NET_PAD_CONF0_GPIO13 0x8d50 +#define VF_NET_PAD_CONF0_GPIO14 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO15 0xccaa +#define VF_NET_PAD_CONF0_GPIO16 0xC828 +#define VF_NET_PAD_CONF0_GPIO17 0xcd2a +#define VF_NET_PAD_CONF0_GPIO18 0xccaa +#define VF_NET_PAD_CONF0_GPIO19 0xccaa +#define VF_NET_PAD_CONF0_GPIO20 0xccaa +#define VF_NET_PAD_CONF0_GPIO21 0xCCA9 +#define VF_NET_PAD_CONF0_GPIO22 0xccaa +#define VF_NET_PAD_CONF0_GPIO23 0xCD2A +#define VF_NET_PAD_CONF0_GPIO24 0x8d02 +#define VF_NET_PAD_CONF0_GPIO25 0x8d02 +#define VF_NET_PAD_CONF0_GPIO26 0x8d02 +#define VF_NET_PAD_CONF0_GPIO27 0x8d02 +#define VF_NET_PAD_CONF0_GPIO28 0x8D02 +#define VF_NET_PAD_CONF0_GPIO29 0x8D02 +#define VF_NET_PAD_CONF0_GPIO30 0x8D00 +#define VF_NET_PAD_CONF0_GPIO31 0xCD2A +#define VF_NET_PAD_CONF0_GPIO32 0x208d51 +#define VF_NET_PAD_CONF0_GPIO33 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO34 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO35 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO36 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO37 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO38 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO39 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO40 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO41 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO42 0x208d51 +#define VF_NET_PAD_CONF0_GPIO43 0x208d51 +#define VF_NET_PAD_CONF0_GPIO44 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO45 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO46 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO47 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO48 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO49 0x8d51 +#define VF_NET_PAD_CONF0_GPIO50 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO51 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO52 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO53 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO54 0xcca9 +#define VF_NET_PAD_CONF0_GPIO55 0x8cd1 +#define VF_NET_PAD_CONF0_GPIO56 0xcd29 +#define VF_NET_PAD_CONF0_GPIO57 0x8C80 +#define VF_NET_PAD_CONF0_GPIO58 0x8C80 +#define VF_NET_PAD_CONF0_GPIO59 0x8C80 +#define VF_NET_PAD_CONF0_GPIO60 0x8C80 +#define VF_NET_PAD_CONF0_GPIO61 0x8800 +#define VF_NET_PAD_CONF0_GPIO62 0x8D00 +#define VF_NET_PAD_CONF0_GPIO63 0x8800 +#define VF_NET_PAD_CONF0_GPIO64 0x8800 +#define VF_NET_PAD_CONF0_GPIO65 0xC828 +#define VF_NET_PAD_CONF0_GPIO66 0xC828 +#define VF_NET_PAD_CONF0_GPIO67 0xC828 +#define VF_NET_PAD_CONF0_GPIO68 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO69 0xC828 +#define VF_NET_PAD_CONF0_GPIO70 0xCCA8 + + + + +// +// PAD_CONF1 +// +#define VF_NET_PAD_CONF1_GPIO0 0x20002 +#define VF_NET_PAD_CONF1_GPIO1 0x20002 +#define VF_NET_PAD_CONF1_GPIO2 0x20002 +#define VF_NET_PAD_CONF1_GPIO3 0x20002 +#define VF_NET_PAD_CONF1_GPIO4 0x20002 +#define VF_NET_PAD_CONF1_GPIO5 0x20002 +#define VF_NET_PAD_CONF1_GPIO6 0x1F000F +#define VF_NET_PAD_CONF1_GPIO7 0x1F000F +#define VF_NET_PAD_CONF1_GPIO8 0x1F000F +#define VF_NET_PAD_CONF1_GPIO9 0x1F000F +#define VF_NET_PAD_CONF1_GPIO10 0x1F000F +#define VF_NET_PAD_CONF1_GPIO11 0x1F000F +#define VF_NET_PAD_CONF1_GPIO12 0x1F000F +#define VF_NET_PAD_CONF1_GPIO13 0x1F000F +#define VF_NET_PAD_CONF1_GPIO14 0x20002 +#define VF_NET_PAD_CONF1_GPIO15 0x20002 +#define VF_NET_PAD_CONF1_GPIO16 0x20002 +#define VF_NET_PAD_CONF1_GPIO17 0x20002 +#define VF_NET_PAD_CONF1_GPIO18 0x20002 +#define VF_NET_PAD_CONF1_GPIO19 0x20002 +#define VF_NET_PAD_CONF1_GPIO20 0x20002 +#define VF_NET_PAD_CONF1_GPIO21 0x20002 +#define VF_NET_PAD_CONF1_GPIO22 0x20002 +#define VF_NET_PAD_CONF1_GPIO23 0x20002 +#define VF_NET_PAD_CONF1_GPIO24 0x00000 +#define VF_NET_PAD_CONF1_GPIO25 0x00000 +#define VF_NET_PAD_CONF1_GPIO26 0x00000 +#define VF_NET_PAD_CONF1_GPIO27 0x00000 +#define VF_NET_PAD_CONF1_GPIO28 0x00000 +#define VF_NET_PAD_CONF1_GPIO29 0x00000 +#define VF_NET_PAD_CONF1_GPIO30 0x00000 +#define VF_NET_PAD_CONF1_GPIO31 0x20002 +#define VF_NET_PAD_CONF1_GPIO32 0x00000 +#define VF_NET_PAD_CONF1_GPIO33 0x00000 +#define VF_NET_PAD_CONF1_GPIO34 0x00000 +#define VF_NET_PAD_CONF1_GPIO35 0x00000 +#define VF_NET_PAD_CONF1_GPIO36 0x00000 +#define VF_NET_PAD_CONF1_GPIO37 0x00000 +#define VF_NET_PAD_CONF1_GPIO38 0x00000 +#define VF_NET_PAD_CONF1_GPIO39 0x00000 +#define VF_NET_PAD_CONF1_GPIO40 0x00000 +#define VF_NET_PAD_CONF1_GPIO41 0x00000 +#define VF_NET_PAD_CONF1_GPIO42 0x00000 +#define VF_NET_PAD_CONF1_GPIO43 0x00000 +#define VF_NET_PAD_CONF1_GPIO44 0x00000 +#define VF_NET_PAD_CONF1_GPIO45 0x00000 +#define VF_NET_PAD_CONF1_GPIO46 0x00000 +#define VF_NET_PAD_CONF1_GPIO47 0x00000 +#define VF_NET_PAD_CONF1_GPIO48 0x00000 +#define VF_NET_PAD_CONF1_GPIO49 0x00000 +#define VF_NET_PAD_CONF1_GPIO50 0x00000 +#define VF_NET_PAD_CONF1_GPIO51 0x00000 +#define VF_NET_PAD_CONF1_GPIO52 0x00000 +#define VF_NET_PAD_CONF1_GPIO53 0x00000 +#define VF_NET_PAD_CONF1_GPIO54 0x20002 +#define VF_NET_PAD_CONF1_GPIO55 0x00000 +#define VF_NET_PAD_CONF1_GPIO56 0x20002 +#define VF_NET_PAD_CONF1_GPIO57 0x00000 +#define VF_NET_PAD_CONF1_GPIO58 0x00000 +#define VF_NET_PAD_CONF1_GPIO59 0x00000 +#define VF_NET_PAD_CONF1_GPIO60 0x00000 +#define VF_NET_PAD_CONF1_GPIO61 0x00000 +#define VF_NET_PAD_CONF1_GPIO62 0x00000 +#define VF_NET_PAD_CONF1_GPIO63 0x00000 +#define VF_NET_PAD_CONF1_GPIO64 0x00000 +#define VF_NET_PAD_CONF1_GPIO65 0x20002 +#define VF_NET_PAD_CONF1_GPIO66 0x20002 +#define VF_NET_PAD_CONF1_GPIO67 0x20002 +#define VF_NET_PAD_CONF1_GPIO68 0x20002 +#define VF_NET_PAD_CONF1_GPIO69 0x20002 +#define VF_NET_PAD_CONF1_GPIO70 0x20002 + + + +// +// PAD_VAL +// +#define VF_NET_PAD_VAL_GPIO0 0x2 +#define VF_NET_PAD_VAL_GPIO1 0x2 +#define VF_NET_PAD_VAL_GPIO2 0x2 +#define VF_NET_PAD_VAL_GPIO3 0x2 +#define VF_NET_PAD_VAL_GPIO4 0x2 +#define VF_NET_PAD_VAL_GPIO5 0x2 +#define VF_NET_PAD_VAL_GPIO6 0x2 +#define VF_NET_PAD_VAL_GPIO7 0x2 +#define VF_NET_PAD_VAL_GPIO8 0x2 +#define VF_NET_PAD_VAL_GPIO9 0x2 +#define VF_NET_PAD_VAL_GPIO10 0x2 +#define VF_NET_PAD_VAL_GPIO11 0x2 +#define VF_NET_PAD_VAL_GPIO12 0x2 +#define VF_NET_PAD_VAL_GPIO13 0x2 +#define VF_NET_PAD_VAL_GPIO14 0x2 +#define VF_NET_PAD_VAL_GPIO15 0x2 +#define VF_NET_PAD_VAL_GPIO16 0x4 +#define VF_NET_PAD_VAL_GPIO17 0x2 +#define VF_NET_PAD_VAL_GPIO18 0x2 +#define VF_NET_PAD_VAL_GPIO19 0x2 +#define VF_NET_PAD_VAL_GPIO20 0x2 +#define VF_NET_PAD_VAL_GPIO21 0x2 +#define VF_NET_PAD_VAL_GPIO22 0x2 +#define VF_NET_PAD_VAL_GPIO23 0x2 +#define VF_NET_PAD_VAL_GPIO24 0x2 +#define VF_NET_PAD_VAL_GPIO25 0x2 +#define VF_NET_PAD_VAL_GPIO26 0x2 +#define VF_NET_PAD_VAL_GPIO27 0x2 +#define VF_NET_PAD_VAL_GPIO28 0x2 +#define VF_NET_PAD_VAL_GPIO29 0x2 +#define VF_NET_PAD_VAL_GPIO30 0x2 +#define VF_NET_PAD_VAL_GPIO31 0x2 +#define VF_NET_PAD_VAL_GPIO32 0x2 +#define VF_NET_PAD_VAL_GPIO33 0x2 +#define VF_NET_PAD_VAL_GPIO34 0x2 +#define VF_NET_PAD_VAL_GPIO35 0x2 +#define VF_NET_PAD_VAL_GPIO36 0x2 +#define VF_NET_PAD_VAL_GPIO37 0x2 +#define VF_NET_PAD_VAL_GPIO38 0x2 +#define VF_NET_PAD_VAL_GPIO39 0x2 +#define VF_NET_PAD_VAL_GPIO40 0x2 +#define VF_NET_PAD_VAL_GPIO41 0x2 +#define VF_NET_PAD_VAL_GPIO42 0x2 +#define VF_NET_PAD_VAL_GPIO43 0x2 +#define VF_NET_PAD_VAL_GPIO44 0x2 +#define VF_NET_PAD_VAL_GPIO45 0x2 +#define VF_NET_PAD_VAL_GPIO46 0x2 +#define VF_NET_PAD_VAL_GPIO47 0x2 +#define VF_NET_PAD_VAL_GPIO48 0x2 +#define VF_NET_PAD_VAL_GPIO49 0x2 +#define VF_NET_PAD_VAL_GPIO50 0x2 +#define VF_NET_PAD_VAL_GPIO51 0x2 +#define VF_NET_PAD_VAL_GPIO52 0x2 +#define VF_NET_PAD_VAL_GPIO53 0x2 +#define VF_NET_PAD_VAL_GPIO54 0x2 +#define VF_NET_PAD_VAL_GPIO55 0x2 +#define VF_NET_PAD_VAL_GPIO56 0x2 +#define VF_NET_PAD_VAL_GPIO57 0x2 +#define VF_NET_PAD_VAL_GPIO58 0x2 +#define VF_NET_PAD_VAL_GPIO59 0x2 +#define VF_NET_PAD_VAL_GPIO60 0x2 +#define VF_NET_PAD_VAL_GPIO61 0x4 +#define VF_NET_PAD_VAL_GPIO62 0x2 +#define VF_NET_PAD_VAL_GPIO63 0x2 +#define VF_NET_PAD_VAL_GPIO64 0x2 +#define VF_NET_PAD_VAL_GPIO65 0x2 +#define VF_NET_PAD_VAL_GPIO66 0x2 +#define VF_NET_PAD_VAL_GPIO67 0x0 +#define VF_NET_PAD_VAL_GPIO68 0x2 +#define VF_NET_PAD_VAL_GPIO69 0x4 +#define VF_NET_PAD_VAL_GPIO70 0x2 + + +// +// PAD_DFT +// +#define VF_NET_PAD_DFT_GPIO0 0xC +#define VF_NET_PAD_DFT_GPIO1 0xC +#define VF_NET_PAD_DFT_GPIO2 0xC +#define VF_NET_PAD_DFT_GPIO3 0xC +#define VF_NET_PAD_DFT_GPIO4 0xC +#define VF_NET_PAD_DFT_GPIO5 0xC +#define VF_NET_PAD_DFT_GPIO6 0xC +#define VF_NET_PAD_DFT_GPIO7 0xC +#define VF_NET_PAD_DFT_GPIO8 0xC +#define VF_NET_PAD_DFT_GPIO9 0xC +#define VF_NET_PAD_DFT_GPIO10 0xC +#define VF_NET_PAD_DFT_GPIO11 0xC +#define VF_NET_PAD_DFT_GPIO12 0xC +#define VF_NET_PAD_DFT_GPIO13 0xC +#define VF_NET_PAD_DFT_GPIO14 0xC +#define VF_NET_PAD_DFT_GPIO15 0xC +#define VF_NET_PAD_DFT_GPIO16 0xC +#define VF_NET_PAD_DFT_GPIO17 0xC +#define VF_NET_PAD_DFT_GPIO18 0xC +#define VF_NET_PAD_DFT_GPIO19 0xC +#define VF_NET_PAD_DFT_GPIO20 0xC +#define VF_NET_PAD_DFT_GPIO21 0xC +#define VF_NET_PAD_DFT_GPIO22 0xC +#define VF_NET_PAD_DFT_GPIO23 0xC +#define VF_NET_PAD_DFT_GPIO24 0xC +#define VF_NET_PAD_DFT_GPIO25 0xC +#define VF_NET_PAD_DFT_GPIO26 0xC +#define VF_NET_PAD_DFT_GPIO27 0xC +#define VF_NET_PAD_DFT_GPIO28 0xC +#define VF_NET_PAD_DFT_GPIO29 0xC +#define VF_NET_PAD_DFT_GPIO30 0xC +#define VF_NET_PAD_DFT_GPIO31 0xC +#define VF_NET_PAD_DFT_GPIO32 0xC +#define VF_NET_PAD_DFT_GPIO33 0xC +#define VF_NET_PAD_DFT_GPIO34 0xC +#define VF_NET_PAD_DFT_GPIO35 0xC +#define VF_NET_PAD_DFT_GPIO36 0xC +#define VF_NET_PAD_DFT_GPIO37 0xC +#define VF_NET_PAD_DFT_GPIO38 0xC +#define VF_NET_PAD_DFT_GPIO39 0xC +#define VF_NET_PAD_DFT_GPIO40 0xC +#define VF_NET_PAD_DFT_GPIO41 0xC +#define VF_NET_PAD_DFT_GPIO42 0xC +#define VF_NET_PAD_DFT_GPIO43 0xC +#define VF_NET_PAD_DFT_GPIO44 0xC +#define VF_NET_PAD_DFT_GPIO45 0xC +#define VF_NET_PAD_DFT_GPIO46 0xC +#define VF_NET_PAD_DFT_GPIO47 0xC +#define VF_NET_PAD_DFT_GPIO48 0xC +#define VF_NET_PAD_DFT_GPIO49 0xC +#define VF_NET_PAD_DFT_GPIO50 0xC +#define VF_NET_PAD_DFT_GPIO51 0xC +#define VF_NET_PAD_DFT_GPIO52 0xC +#define VF_NET_PAD_DFT_GPIO53 0xC +#define VF_NET_PAD_DFT_GPIO54 0xC +#define VF_NET_PAD_DFT_GPIO55 0xC +#define VF_NET_PAD_DFT_GPIO56 0xC +#define VF_NET_PAD_DFT_GPIO57 0xC +#define VF_NET_PAD_DFT_GPIO58 0xC +#define VF_NET_PAD_DFT_GPIO59 0xC +#define VF_NET_PAD_DFT_GPIO60 0xC +#define VF_NET_PAD_DFT_GPIO61 0xC +#define VF_NET_PAD_DFT_GPIO62 0xC +#define VF_NET_PAD_DFT_GPIO63 0xC +#define VF_NET_PAD_DFT_GPIO64 0xC +#define VF_NET_PAD_DFT_GPIO65 0xC +#define VF_NET_PAD_DFT_GPIO66 0xC +#define VF_NET_PAD_DFT_GPIO67 0xC +#define VF_NET_PAD_DFT_GPIO68 0xC +#define VF_NET_PAD_DFT_GPIO69 0xC +#define VF_NET_PAD_DFT_GPIO70 0xC + +// +// PCONF0 +// +#define VF_NET_PAD_CONF0_GPIO_SUS0 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS1 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS2 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS3 0xCD28 +#define VF_NET_PAD_CONF0_GPIO_SUS4 0xCD28 +#define VF_NET_PAD_CONF0_GPIO_SUS5 0xCD28 +#define VF_NET_PAD_CONF0_GPIO_SUS6 0x8850 +#define VF_NET_PAD_CONF0_GPIO_SUS7 0x8850 +#define VF_NET_PAD_CONF0_GPIO_SUS8 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS9 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS10 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS11 0xC828 +#define VF_NET_PAD_CONF0_GPIO_SUS12 0xC828 +#define VF_NET_PAD_CONF0_GPIO_SUS13 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS14 0xCCA8 +#define VF_NET_PAD_CONF0_GPIO_SUS15 0x8C80 +#define VF_NET_PAD_CONF0_GPIO_SUS16 0xC828 + +// +// PCONF1 +// +#define VF_NET_PAD_CONF1_GPIO_SUS0 0 +#define VF_NET_PAD_CONF1_GPIO_SUS1 0 +#define VF_NET_PAD_CONF1_GPIO_SUS2 0 +#define VF_NET_PAD_CONF1_GPIO_SUS3 0 +#define VF_NET_PAD_CONF1_GPIO_SUS4 0 +#define VF_NET_PAD_CONF1_GPIO_SUS5 0 +#define VF_NET_PAD_CONF1_GPIO_SUS6 0 +#define VF_NET_PAD_CONF1_GPIO_SUS7 0 +#define VF_NET_PAD_CONF1_GPIO_SUS8 0 +#define VF_NET_PAD_CONF1_GPIO_SUS9 0 +#define VF_NET_PAD_CONF1_GPIO_SUS10 0 +#define VF_NET_PAD_CONF1_GPIO_SUS11 0 +#define VF_NET_PAD_CONF1_GPIO_SUS12 0 +#define VF_NET_PAD_CONF1_GPIO_SUS13 0 +#define VF_NET_PAD_CONF1_GPIO_SUS14 0 +#define VF_NET_PAD_CONF1_GPIO_SUS15 0 +#define VF_NET_PAD_CONF1_GPIO_SUS16 0 + + +#define VF_NET_PAD_VAL_GPIO_SUS0 0 +#define VF_NET_PAD_VAL_GPIO_SUS1 0 +#define VF_NET_PAD_VAL_GPIO_SUS2 0 +#define VF_NET_PAD_VAL_GPIO_SUS3 0 +#define VF_NET_PAD_VAL_GPIO_SUS4 0 +#define VF_NET_PAD_VAL_GPIO_SUS5 0 +#define VF_NET_PAD_VAL_GPIO_SUS6 0 +#define VF_NET_PAD_VAL_GPIO_SUS7 0 +#define VF_NET_PAD_VAL_GPIO_SUS8 0 +#define VF_NET_PAD_VAL_GPIO_SUS9 0 +#define VF_NET_PAD_VAL_GPIO_SUS10 0 +#define VF_NET_PAD_VAL_GPIO_SUS11 0 +#define VF_NET_PAD_VAL_GPIO_SUS12 0 +#define VF_NET_PAD_VAL_GPIO_SUS13 0 +#define VF_NET_PAD_VAL_GPIO_SUS14 0 +#define VF_NET_PAD_VAL_GPIO_SUS15 0 +#define VF_NET_PAD_VAL_GPIO_SUS16 0 + + +#define VF_NET_PAD_DFT_GPIO_SUS0 0 +#define VF_NET_PAD_DFT_GPIO_SUS1 0 +#define VF_NET_PAD_DFT_GPIO_SUS2 0 +#define VF_NET_PAD_DFT_GPIO_SUS3 0 +#define VF_NET_PAD_DFT_GPIO_SUS4 0 +#define VF_NET_PAD_DFT_GPIO_SUS5 0 +#define VF_NET_PAD_DFT_GPIO_SUS6 0 +#define VF_NET_PAD_DFT_GPIO_SUS7 0 +#define VF_NET_PAD_DFT_GPIO_SUS8 0 +#define VF_NET_PAD_DFT_GPIO_SUS9 0 +#define VF_NET_PAD_DFT_GPIO_SUS10 0 +#define VF_NET_PAD_DFT_GPIO_SUS11 0 +#define VF_NET_PAD_DFT_GPIO_SUS12 0 +#define VF_NET_PAD_DFT_GPIO_SUS13 0 +#define VF_NET_PAD_DFT_GPIO_SUS14 0 +#define VF_NET_PAD_DFT_GPIO_SUS15 0 +#define VF_NET_PAD_DFT_GPIO_SUS16 0 + + +// +// Function Prototypes +// +EFI_STATUS +PlatformPchInit ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 PlatformType + ); + +EFI_STATUS +PlatformCpuInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN EFI_PLATFORM_CPU_INFO *PlatformCpuInfo + ); + +EFI_STATUS +PeimInitializeFlashMap ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +PeimInstallFlashMapPpi ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +EFIAPI +IchReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +; + +BOOLEAN +GetSleepTypeAfterWakeup ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT16 *SleepType + ); + +EFI_STATUS +EFIAPI +GetWakeupEventAndSaveToHob ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +; + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +; + +EFI_STATUS +EFIAPI +PeiGetVariable ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CHAR16 *VariableName, + IN EFI_GUID * VendorGuid, + OUT UINT32 *Attributes OPTIONAL, + IN OUT UINTN *DataSize, + OUT VOID *Data + ) +; + +EFI_STATUS +EFIAPI +PeiGetNextVariableName ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VendorGuid + ) +; + +EFI_STATUS +UpdateBootMode ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +EFI_STATUS +EFIAPI +EndOfPeiPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +PeimInitializeRecovery ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +; + +VOID +CheckPowerOffNow ( + VOID + ); + +VOID +IchGpioInit ( + IN UINT16 PlatformType, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ); + +EFI_STATUS +PcieSecondaryBusReset ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun + ); + +VOID +SetPlatformBootMode ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +BOOLEAN +CheckIfJumperSetForRecovery( + VOID + ); + +EFI_STATUS +EFIAPI +FindFv ( + IN EFI_PEI_FIND_FV_PPI *This, + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT8 *FvNumber, + OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress + ); + +BOOLEAN +IsA16Inverted ( + ); + +EFI_STATUS +EFIAPI +CpuOnlyReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +EFIAPI +InitLan ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *Buffer + ); + +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ); + +EFI_STATUS +MultiPlatformInfoInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +BOOLEAN +IsRecoveryJumper ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob +); + +EFI_STATUS +CheckOsSelection ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ); + +EFI_STATUS +PlatformInfoUpdate ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ); + +VOID +PlatformSsaInit ( +IN SYSTEM_CONFIGURATION *SystemConfiguration, +IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +InitializePlatform ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob, + IN SYSTEM_CONFIGURATION *SystemConfiguration +); + +VOID +MchInit ( +IN CONST EFI_PEI_SERVICES **PeiServices + ); + + +EFI_STATUS +EFIAPI +SetPeiCacheMode ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +EFIAPI +SetDxeCacheMode ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +GPIO_initialization ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *SmbusPpi + ); + + +BOOLEAN +IsRtcUipAlwaysSet ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + + + +EFI_STATUS +InitPchUsb ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +EFI_STATUS +EFIAPI +PublishMemoryTypeInfo ( + void + ); + + +#endif diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c new file mode 100644 index 0000000000..48d69a3a59 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c @@ -0,0 +1,186 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + PlatformInfoInit.c + +Abstract: + Platform Info Driver. + +--*/ + +#include "PlatformEarlyInit.h" + +#define LEN_64M 0x4000000 + +// +// Default PCI32 resource size +// +#define RES_MEM32_MIN_LEN 0x38000000 + +#define RES_IO_BASE 0x0D00 +#define RES_IO_LIMIT 0xFFFF + +#define MemoryCeilingVariable L"MemCeil." + +EFI_STATUS +CheckOsSelection ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN VariableSize; + EFI_OS_SELECTION_HOB *OsSelectionHob; + UINT8 OsSelection; + UINT8 *LpssDataHobPtr; + UINT8 *LpssDataVarPtr; + UINTN i; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + if (!EFI_ERROR(Status)) { + VariableSize = sizeof (OsSelection); + Status = Variable->GetVariable ( + Variable, + L"OsSelection", + &gOsSelectionVariableGuid, + NULL, + &VariableSize, + &OsSelection + ); + + if (!EFI_ERROR(Status) && (SystemConfiguration->ReservedO != OsSelection)) { + // + // Build HOB for OsSelection + // + OsSelectionHob = BuildGuidHob (&gOsSelectionVariableGuid, sizeof (EFI_OS_SELECTION_HOB)); + ASSERT (OsSelectionHob != NULL); + + OsSelectionHob->OsSelectionChanged = TRUE; + OsSelectionHob->OsSelection = OsSelection; + SystemConfiguration->ReservedO = OsSelectionHob->OsSelection; + + // + // Load LPSS and SCC defalut configurations + // + OsSelectionHob->LpssData.LpsseMMCEnabled = FALSE; + OsSelectionHob->LpssData.LpssSdioEnabled = TRUE; + OsSelectionHob->LpssData.LpssSdcardEnabled = TRUE; + OsSelectionHob->LpssData.LpssSdCardSDR25Enabled = FALSE; + OsSelectionHob->LpssData.LpssSdCardDDR50Enabled = TRUE; + OsSelectionHob->LpssData.LpssMipiHsi = FALSE; + OsSelectionHob->LpssData.LpsseMMC45Enabled = TRUE; + OsSelectionHob->LpssData.LpsseMMC45DDR50Enabled = TRUE; + OsSelectionHob->LpssData.LpsseMMC45HS200Enabled = FALSE; + OsSelectionHob->LpssData.LpsseMMC45RetuneTimerValue = 8; + OsSelectionHob->LpssData.eMMCBootMode = 1; // Auto Detect + + + SystemConfiguration->Lpe = OsSelectionHob->Lpe; + SystemConfiguration->PchAzalia = SystemConfiguration->PchAzalia; + LpssDataHobPtr = &OsSelectionHob->LpssData.LpssPciModeEnabled; + LpssDataVarPtr = &SystemConfiguration->LpssPciModeEnabled; + + for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) { + *LpssDataVarPtr = *LpssDataHobPtr; + LpssDataVarPtr++; + LpssDataHobPtr++; + } + } + } + + return EFI_SUCCESS; +} + + +EFI_STATUS +PlatformInfoUpdate ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob, + IN SYSTEM_CONFIGURATION *SystemConfiguration + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN VariableSize; + UINT32 MemoryCeiling; + + // + // Checking PCI32 resource from previous boot to determine the memory ceiling + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (void **)&Variable + ); + if (!EFI_ERROR(Status)) { + // + // Get the memory ceiling + // + VariableSize = sizeof(MemoryCeiling); + Status = Variable->GetVariable ( + Variable, + MemoryCeilingVariable, + &gEfiGlobalVariableGuid, + NULL, + &VariableSize, + &MemoryCeiling + ); + if(!EFI_ERROR(Status)) { + // + // Set the new PCI32 resource Base if the variable available + // + PlatformInfoHob->PciData.PciResourceMem32Base = MemoryCeiling; + PlatformInfoHob->MemData.MemMaxTolm = MemoryCeiling; + PlatformInfoHob->MemData.MemTolm = MemoryCeiling; + + // + // Platform PCI MMIO Size in unit of 1MB + // + PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20); + } + } + + return EFI_SUCCESS; +} + +/** + Initialize the platform related info hob according to the + pre-determine value or setup option + + @retval EFI_SUCCESS Memory initialization completed successfully. + @retval Others All other error conditions encountered result in an ASSERT. +**/ +EFI_STATUS +InitializePlatform ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob, + IN SYSTEM_CONFIGURATION *SystemConfiguration +) +{ +// +// -- cchew10 need to update here. +// + return EFI_SUCCESS; +} + diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf new file mode 100644 index 0000000000..fc517ef6f3 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf @@ -0,0 +1,122 @@ +# +# +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +# +# Module Name: +# +# PlatformEarlyInit.inf +# +# Abstract: +# +# Component description file for PlatformEarlyInit module +# +#--*/ + +[defines] +INF_VERSION = 0x00010005 +BASE_NAME = PlatformEarlyInit +FILE_GUID = 0A5EA2E1-BE0B-44a0-A775-F429C9A018A0 +MODULE_TYPE = PEIM +VERSION_STRING = 1.0 +PI_SPECIFICATION_VERSION = 0x0001000A +ENTRY_POINT = PlatformEarlyInitEntry + +[sources.common] + BootMode.c + CpuInitPeim.c + PchInitPeim.c + MchInit.c + MemoryCallback.c + MemoryPeim.c + PlatformEarlyInit.c + PlatformEarlyInit.h + PlatformInfoInit.c + LegacySpeaker.c + LegacySpeaker.h + Stall.c + PlatformSsaInitPeim.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + +[LibraryClasses] + PeimEntryPoint + DebugLib + HobLib + IoLib +# PeiKscLib + MultiPlatformLib + PcdLib + PchPlatformLib + MtrrLib + +[Ppis] + gEfiPeiStallPpiGuid + gPeiSpeakerInterfacePpiGuid + gEfiPeiMemoryDiscoveredPpiGuid + gVlvPolicyPpiGuid + gEfiPeiReadOnlyVariable2PpiGuid + gEfiPeiResetPpiGuid + gEfiEndOfPeiSignalPpiGuid + gPeiSmbusPolicyPpiGuid + gEfiFindFvPpiGuid + gPeiCapsulePpiGuid + gEfiPeiBootInRecoveryModePpiGuid + gEfiPeiRecoveryModulePpiGuid + gEfiPeiDeviceRecoveryModulePpiGuid + gPeiCachePpiGuid + gEfiPeiMasterBootModePpiGuid + gEfiPeiSmbusPpiGuid + gPchInitPpiGuid + gPchUsbPolicyPpiGuid + +[Guids] + gEfiSetupVariableGuid + gEfiPlatformInfoGuid + gEfiPlatformBootModeGuid + gEfiPlatformCpuInfoGuid + gEfiGlobalVariableGuid + gRecoveryOnFatFloppyDiskGuid + gRecoveryOnFatUsbDiskGuid + gRecoveryOnFatIdeDiskGuid + gRecoveryOnDataCdGuid + gMfgModeVariableGuid + gEfiNormalSetupGuid + gEfiMemoryTypeInformationGuid + gOsSelectionVariableGuid + +[Pcd.common] + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase + gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress + + gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base + gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size + +[Pcd] + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid AND gPeiCachePpiGuid diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c new file mode 100644 index 0000000000..c2cffb8be8 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + PlatformSsaInitPeim.c + +Abstract: + + +--*/ + +#include "PlatformEarlyInit.h" + +/** + Perform SSA related platform initialization. + +**/ +VOID +PlatformSsaInit ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Start\n")); + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - SystemConfiguration->ISPDevSel 0x%x\n",SystemConfiguration->ISPDevSel)); + if(SystemConfiguration->ISPDevSel == 0x02) + { + // + // Device 3 Interrupt Route + // + MmioWrite16 ( + (ILB_BASE_ADDRESS + R_PCH_ILB_D3IR), + V_PCH_ILB_DXXIR_IAR_PIRQH // For IUNIT + ); + MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR); // Read Posted Writes Register + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 3 Interrupt Route Done\n")); + } + + // + // Device 2 Interrupt Route + // + MmioWrite16 ( + (ILB_BASE_ADDRESS + R_PCH_ILB_D2IR), + V_PCH_ILB_DXXIR_IAR_PIRQA // For IGD + ); + MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D2IR); // Read Posted Writes Register + DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 2 Interrupt Route Done\n")); + + return; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c b/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c new file mode 100644 index 0000000000..a29d8c5481 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c @@ -0,0 +1,366 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + + Recovery.c + +Abstract: + + Tiano PEIM to provide the platform recovery functionality. + +--*/ + +#include "PlatformEarlyInit.h" + +#define PEI_FVMAIN_COMPACT_GUID \ + {0x4A538818, 0x5AE0, 0x4eb2, 0xB2, 0xEB, 0x48, 0x8b, 0x23, 0x65, 0x70, 0x22}; + +EFI_GUID FvMainCompactFileGuid = PEI_FVMAIN_COMPACT_GUID; + +// +// Required Service +// +EFI_STATUS +EFIAPI +PlatformRecoveryModule ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_MODULE_PPI *This + ); + +// +// Module globals +// + +typedef struct { + EFI_GUID CapsuleGuid; + UINT32 HeaderSize; + UINT32 Flags; + UINT32 CapsuleImageSize; + UINT32 SequenceNumber; + EFI_GUID InstanceId; + UINT32 OffsetToSplitInformation; + UINT32 OffsetToCapsuleBody; + UINT32 OffsetToOemDefinedHeader; + UINT32 OffsetToAuthorInformation; + UINT32 OffsetToRevisionInformation; + UINT32 OffsetToShortDescription; + UINT32 OffsetToLongDescription; + UINT32 OffsetToApplicableDevices; +} OLD_EFI_CAPSULE_HEADER; + + +static EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = { + PlatformRecoveryModule +}; + +static EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiRecoveryModulePpiGuid, + &mRecoveryPpi +}; + +/** + Provide the functionality of the Recovery Module. + + @param PeiServices General purpose services available to every PEIM. + + @retval Status EFI_SUCCESS if the interface could be successfully + installed + +**/ +EFI_STATUS +EFIAPI +PeimInitializeRecovery ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + Status = (*PeiServices)->InstallPpi ( + PeiServices, + &mRecoveryPpiList + ); + + return Status; +} + +/** + Provide the functionality of the Ea Recovery Module. + + @param PeiServices General purpose services available to every PEIM. + @param This Pointer to PEI_RECOVERY_MODULE_INTERFACE. + + @retval EFI_SUCCESS If the interface could be successfully + installed. + @retval EFI_UNSUPPORTED Not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformRecoveryModule ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_MODULE_PPI *This + ) +{ + EFI_STATUS Status; + EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule; + UINTN NumberOfImageProviders; + BOOLEAN ProviderAvailable; + UINTN NumberRecoveryCapsules; + UINTN RecoveryCapsuleSize; + EFI_GUID DeviceId; + BOOLEAN ImageFound; + EFI_PHYSICAL_ADDRESS Address; + VOID *Buffer; + OLD_EFI_CAPSULE_HEADER *CapsuleHeader; + EFI_PEI_HOB_POINTERS Hob; + EFI_PEI_HOB_POINTERS HobOld; + EFI_HOB_CAPSULE_VOLUME *CapsuleHob; + BOOLEAN HobUpdate; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + UINTN Index; + BOOLEAN FoundFvMain; + BOOLEAN FoundCapsule; + static EFI_GUID mEfiCapsuleHeaderGuid = EFI_CAPSULE_GUID; + EFI_PEI_STALL_PPI *StallPpi; + + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_PROGRESS_CODE, + EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN, + 0, + NULL, + NULL + ); + + Status = (**PeiServices).LocatePpi ( + PeiServices, + &gEfiPeiStallPpiGuid, + 0, + NULL, + &StallPpi + ); + ASSERT_EFI_ERROR (Status); + + StallPpi->Stall( + PeiServices, + StallPpi, + 5000000 + ); + + + Index = 0; + + Status = EFI_SUCCESS; + HobUpdate = FALSE; + + ProviderAvailable = TRUE; + ImageFound = FALSE; + NumberOfImageProviders = 0; + + DeviceRecoveryModule = NULL; + + FoundCapsule = FALSE; + FoundFvMain = FALSE; + + DEBUG ((EFI_D_ERROR | EFI_D_LOAD, "Recovery Entry\n")); + + // + // Search the platform for some recovery capsule if the DXE IPL + // discovered a recovery condition and has requested a load. + // + while (ProviderAvailable == TRUE) { + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiDeviceRecoveryModulePpiGuid, + Index, + NULL, + &DeviceRecoveryModule + ); + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n")); + NumberOfImageProviders++; + + Status = DeviceRecoveryModule->GetNumberRecoveryCapsules ( + (EFI_PEI_SERVICES**)PeiServices, + DeviceRecoveryModule, + &NumberRecoveryCapsules + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules)); + + if (NumberRecoveryCapsules == 0) { + Index++; + } else { + break; + } + } else { + ProviderAvailable = FALSE; + } + } + + // + // If there is an image provider, get the capsule ID + // + if (ProviderAvailable) { + RecoveryCapsuleSize = 0; + + Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo ( + (EFI_PEI_SERVICES**)PeiServices, + DeviceRecoveryModule, + 0, + &RecoveryCapsuleSize, + &DeviceId + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize)); + + // + // Only support the 2 capsule types known + // Future enhancement is to rank-order the selection + // + if ((!CompareGuid (&DeviceId, &gRecoveryOnFatIdeDiskGuid)) && + (!CompareGuid (&DeviceId, &gRecoveryOnFatFloppyDiskGuid)) && + (!CompareGuid (&DeviceId, &gRecoveryOnDataCdGuid)) && + (!CompareGuid (&DeviceId, &gRecoveryOnFatUsbDiskGuid)) + ) { + return EFI_UNSUPPORTED; + } + + Buffer = NULL; + Status = (*PeiServices)->AllocatePages ( + PeiServices, + EfiBootServicesCode, + (RecoveryCapsuleSize - 1) / 0x1000 + 1, + &Address + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Returns: %r\n", Status)); + + if (EFI_ERROR(Status)) { + return Status; + } + + Buffer = (UINT8 *) (UINTN) Address; + + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_PROGRESS_CODE, + EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD, + 0, + NULL, + NULL + ); + + Status = DeviceRecoveryModule->LoadRecoveryCapsule ( + (EFI_PEI_SERVICES**)PeiServices, + DeviceRecoveryModule, + 0, + Buffer + ); + + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status)); + + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Update FV Hob if found + // + Status = (*PeiServices)->GetHobList (PeiServices, &Hob.Raw); + HobOld.Raw = Hob.Raw; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_FV) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length)); + // + // BUGBUG Why is it a FV hob if it is greater than 0x50000? + // + if (Hob.FirmwareVolume->Length > 0x50000) { + HobUpdate = TRUE; + // + // This looks like the Hob we are interested in + // + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n")); + Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer; + Hob.FirmwareVolume->Length = RecoveryCapsuleSize; + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Buffer; + CapsuleHeader = (OLD_EFI_CAPSULE_HEADER *)Buffer; + + // + // Check if top of file is a capsule + // + if (CompareGuid ((EFI_GUID *)CapsuleHeader, &mEfiCapsuleHeaderGuid)) { + FoundCapsule = TRUE; + } else if (FvHeader->Signature == EFI_FVH_SIGNATURE) { + // + // Assume the Firmware volume is a "FVMAIN" image + // + FoundFvMain = TRUE; + } + + if (FoundFvMain) { + // + // build FV Hob if it is not built before + // + if (!HobUpdate) { + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n")); + + BuildFvHob ( + (UINTN)FvHeader, + FvHeader->FvLength + ); + } + } + + if (FoundCapsule) { + // + // Build capsule hob + // + Status = (*PeiServices)->CreateHob ( + PeiServices, + EFI_HOB_TYPE_CV, + sizeof (EFI_HOB_CAPSULE_VOLUME), + &CapsuleHob + ); + if (EFI_ERROR (Status)) { + return Status; + } + CapsuleHob->BaseAddress = (UINT64)((UINTN)CapsuleHeader + (UINTN)CapsuleHeader->OffsetToCapsuleBody); + CapsuleHob->Length = (UINT64)((UINTN)CapsuleHeader->CapsuleImageSize -(UINTN)CapsuleHeader->OffsetToCapsuleBody); + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_PROGRESS_CODE, + EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START, + 0, + NULL, + NULL + ); + } + } + DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status)); + return Status; +} diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c b/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c new file mode 100644 index 0000000000..46df63aed7 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c @@ -0,0 +1,96 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + Stall.c + +Abstract: + + Produce Stall Ppi. + +--*/ + + +#include "PlatformEarlyInit.h" + + +/** + + Waits for at least the given number of microseconds. + + @param PeiServices General purpose services available to every PEIM. + @param This PPI instance structure. + @param Microseconds Desired length of time to wait. + + @retval EFI_SUCCESS If the desired amount of time was passed. + +*/ +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ) +{ + UINTN Ticks; + UINTN Counts; + UINT32 CurrentTick; + UINT32 OriginalTick; + UINT32 RemainingTick; + + if (Microseconds == 0) { + return EFI_SUCCESS; + } + + OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR); + OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1); + CurrentTick = OriginalTick; + + // + // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks + // + Ticks = Microseconds * 358 / 100 + OriginalTick + 1; + + // + // The loops needed for timer overflow + // + Counts = (UINTN)RShiftU64((UINT64)Ticks, 24); + + // + // Remaining clocks within one loop + // + RemainingTick = Ticks & 0xFFFFFF; + + // + // Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra + // one I/O operation, and may generate SMI + // + while (Counts != 0) { + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL; + if (CurrentTick <= OriginalTick) { + Counts--; + } + OriginalTick = CurrentTick; + } + + while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) { + OriginalTick = CurrentTick; + CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL; + } + + return EFI_SUCCESS; +} -- cgit v1.2.3