### @file
#
# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License which accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
###

[Defines]
  DEC_SPECIFICATION              = 0x00010005
  PACKAGE_NAME                   = PurleyRcPkg
  PACKAGE_GUID                   = 7DE2B07E-0E4A-4eba-B7B6-CE1E8D2B8408
  PACKAGE_VERSION                = 0.1

[Includes]
  Include
  Include/Library
  Library/BaseMemoryCoreLib/Core
  Library/BaseMemoryCoreLib/Core/Include
  Library/BaseMemoryCoreLib/Platform/Purley/Include

  Library/BaseMemoryCoreLib/Chip/Skx
  Library/BaseMemoryCoreLib/Chip/Skx/Include
  Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio
  Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol
  Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup

[LibraryClasses]
  
  ##  @libraryclass  Provides services to get the silicon access library.
  SiliconAccessLib|Include/Library/UsraAccessApi.h

  ##  @libraryclass  Provides services to convert CSR to PCIE address library.
  CsrToPcieLib|PurleyRcPkg/Include/Library/CsrToPcieAddress.h
  
  ##  @libraryclass  Provides services to PCIE address library.
  PcieAddrLib|PurleyRcPkg/Include/Library/PcieAddress.h
  
  ##  @libraryclass  Provides services to get PCI Express Address Base library.
  MmPciLib|PurleyRcPkg/Include/Library/MmPciBaseLib.h
  
  ##  @libraryclass  Provides services to get the silicon access library.
  UsraLib|PurleyRcPkg/Include/Protocol/SiliconRegAccess.h

[Guids]

  ## Include/Guid/CpRcPkgTokenSpace.h
  gEfiCpRcPkgTokenSpaceGuid  = { 0xfcdd2efc, 0x6ca8, 0x4d0b, { 0x9d, 0x0, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
  
[Protocols]
  ## Include/Protocol/SiliconRegAccess.h
  gUsraProtocolGuid              = { 0xfd480a76, 0xb134, 0x4ef7, { 0xad, 0xfe, 0xb0, 0xe0, 0x54, 0x63, 0x98, 0x7 }}

[PPIs]
  ## Include/Protocol/SiliconRegAccess.h
  gUsraPpiGuid                   = { 0x90766a99, 0x9ca5, 0x44de, { 0x94, 0xda, 0xdc, 0xc1, 0xd2, 0xd6, 0xda, 0x1f }}

[PcdsFeatureFlag]
  ## Indicate whether USRA can support S3
  gEfiCpRcPkgTokenSpaceGuid.PcdUsraSupportS3|TRUE|BOOLEAN|0x00000012

  ## Use this feature PCD to support Single PCIe segment with static MMCFG Base
  gEfiCpRcPkgTokenSpaceGuid.PcdSingleSegFixMmcfg|FALSE|BOOLEAN|0x00000014

  ## enable/disable USRA trace.
  gEfiCpRcPkgTokenSpaceGuid.PcdUsraTraceEnable|FALSE|BOOLEAN|0x00000016

  ## enable/disable Quiesce feature.
  gEfiCpRcPkgTokenSpaceGuid.PcdQuiesceSupport|TRUE|BOOLEAN|0x00000017

[PcdsFixedAtBuild]
  ## Indicates the size of each PCIE segment
  gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize|0x10000000|UINT64|0x00000010
  gEfiCpRcPkgTokenSpaceGuid.PcdNumOfPcieSeg|0x00000008|UINT32|0x00000013
  ## Indicates the max nested level
  gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000008|UINT32|0x00000018
  ## Maximum number of sockets supported for this firmware build.
  # This PCD should be used sparingly.  Dynamic allocation of data and
  # dynamic control flows are preferred over using this PCD for static
  # data allocation and control.
  gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|0x04|UINT32|0x00000019

[PcdsDynamicEx]
  ##                                                 |                           MMCFG Table Header                                 |                               Segment 0                                        |                              Segment 1                                       |                               Segment 2                                        |                               Segment 3                                       |                               Segment 4                                        |                               Segment 5                                       |                               Segment 6                                       |                               Segment 7                                      |
  gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,  0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}|VOID*|0x00000011
  gEfiCpRcPkgTokenSpaceGuid.PcdRcRevision|0|UINT32|0x00000015

[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]