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*******************************************************************************/

#ifndef __RTCLIB_H__
#define __RTCLIB_H__

/* Armada 70x0 SoC registers */
#define RTC_STATUS_REG                          0x0
#define RTC_TIME_REG                            0xC
#define RTC_IRQ_2_CONFIG_REG                    0x8
#define RTC_IRQ_ALARM_EN                        0x1
#define RTC_ALARM_2_REG                         0x14
#define RTC_BRIDGE_TIMING_CTRL1_REG_OFFS        0x84
#define RTC_IRQ_STATUS_REG                      0x90
#define RTC_IRQ_ALARM_MASK                      0x1
#define RTC_READ_OUTPUT_DELAY_MASK              0xFFFF
#define RTC_READ_OUTPUT_DELAY_DEFAULT           0x1F

#endif /* __RTCLIB_H__ */