1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
|
/*++
Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PlatformIoLib.c
Abstract:
--*/
#include "Tiano.h"
#include "EfiRuntimeLib.h"
#include EFI_PROTOCOL_DEFINITION (CpuIo)
#define PCI_CONFIG_INDEX_PORT 0xcf8
#define PCI_CONFIG_DATA_PORT 0xcfc
#define REFRESH_CYCLE_TOGGLE_BIT 0x10
UINT32
GetPciAddress (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register
)
/*++
Routine Description:
Constructs PCI Address 32 bits
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Returns:
PciAddress to be written to Config Port
--*/
{
UINT32 Data;
Data = 0;
Data = (((UINT32) Segment) << 24);
Data |= (((UINT32) Bus) << 16);
Data |= (((UINT32) DevFunc) << 8);
Data |= (UINT32) Register;
return Data;
}
UINT8
PciRead8 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register
)
/*++
Routine Description:
Perform an one byte PCI config cycle read
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Returns:
Data read from PCI config space
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
UINT8 Data;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return 0;
}
EfiIoRead (EfiCpuIoWidthUint8, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
return Data;
}
UINT16
PciRead16 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register
)
/*++
Routine Description:
Perform an two byte PCI config cycle read
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Returns:
Data read from PCI config space
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
UINT16 Data;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return 0;
}
EfiIoRead (EfiCpuIoWidthUint16, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
return Data;
}
UINT32
PciRead32 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register
)
/*++
Routine Description:
Perform an four byte PCI config cycle read
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Returns:
Data read from PCI config space
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
UINT32 Data;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return 0;
}
EfiIoRead (EfiCpuIoWidthUint32, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
return Data;
}
VOID
PciWrite8 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register,
UINT8 Data
)
/*++
Routine Description:
Perform an one byte PCI config cycle write
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Data - Data to write
Returns:
NONE
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return ;
}
EfiIoWrite (EfiCpuIoWidthUint8, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
}
VOID
PciWrite16 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register,
UINT16 Data
)
/*++
Routine Description:
Perform an two byte PCI config cycle write
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Data - Data to write
Returns:
NONE
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return ;
}
EfiIoWrite (EfiCpuIoWidthUint16, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
}
VOID
PciWrite32 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register,
UINT32 Data
)
/*++
Routine Description:
Perform an four byte PCI config cycle write
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Data - Data to write
Returns:
NONE
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return ;
}
EfiIoWrite (EfiCpuIoWidthUint32, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
}
//
// Delay Primative
//
VOID
EfiStall (
IN UINTN Microseconds
)
/*++
Routine Description:
Delay for at least the request number of microseconds
Arguments:
Microseconds - Number of microseconds to delay.
Returns:
NONE
--*/
{
UINT8 Data;
UINT8 InitialState;
UINTN CycleIterations;
CycleIterations = 0;
Data = 0;
InitialState = 0;
if (EfiAtRuntime ()) {
//
// The time-source is 30 us granular, so calibrate the timing loop
// based on this baseline
// Error is possible 30us.
//
CycleIterations = (Microseconds - 1) / 30 + 1;
//
// Use the DMA Refresh timer in port 0x61. Cheap but effective.
// The only issue is that the granularity is 30us, and we want to
// guarantee "at least" one full transition to avoid races.
//
//
// _____________/----------\__________/--------
//
// |<--15us-->|<--15us-->|
//
// --------------------------------------------------> Time (us)
//
while (CycleIterations--) {
EfiIoRead (EfiCpuIoWidthUint8, 0x61, 1, &Data);
Data &= REFRESH_CYCLE_TOGGLE_BIT;
InitialState = Data;
//
// Capture first transition (strictly less than one period)
//
while (InitialState == Data) {
EfiIoRead (EfiCpuIoWidthUint8, 0x61, 1, &Data);
Data &= REFRESH_CYCLE_TOGGLE_BIT;
}
InitialState = Data;
//
// Capture next transition (guarantee at least one full pulse)
//
while (InitialState == Data) {
EfiIoRead (EfiCpuIoWidthUint8, 0x61, 1, &Data);
Data &= REFRESH_CYCLE_TOGGLE_BIT;
}
}
} else {
gBS->Stall (Microseconds);
}
}
|