1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
|
/** @file
Internal library declaration for PCI Bus module.
Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _EFI_PCI_LIB_H_
#define _EFI_PCI_LIB_H_
//
// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
//
#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01
#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02
#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04
#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08
#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a
typedef struct {
EFI_HANDLE Handle;
} EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;
typedef struct {
UINT32 Bar;
UINT16 DevicePathSize;
UINT16 ReqResSize;
UINT16 AllocResSize;
UINT8 *DevicePath;
UINT8 *ReqRes;
UINT8 *AllocRes;
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
/**
Retrieve the PCI Card device BAR information via PciIo interface.
@param PciIoDevice PCI Card device instance.
**/
VOID
GetBackPcCardBar (
IN PCI_IO_DEVICE *PciIoDevice
);
/**
Remove rejected pci device from specific root bridge
handle.
@param RootBridgeHandle Specific parent root bridge handle.
@param Bridge Bridge device instance.
**/
VOID
RemoveRejectedPciDevices (
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
);
/**
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
@param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
@retval EFI_SUCCESS Successfully finished resource allocation.
@retval EFI_NOT_FOUND Cannot get root bridge instance.
@retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.
@retval other Some error occurred when allocating resources for the PCI Host Bridge.
@note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
**/
EFI_STATUS
PciHostBridgeResourceAllocator (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
Scan pci bus and assign bus number to the given PCI bus system.
@param Bridge Bridge device instance.
@param StartBusNumber start point.
@param SubBusNumber Point to sub bus number.
@param PaddedBusRange Customized bus number.
@retval EFI_SUCCESS Successfully scanned and assigned bus number.
@retval other Some error occurred when scanning pci bus.
@note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
**/
EFI_STATUS
PciScanBus (
IN PCI_IO_DEVICE *Bridge,
IN UINT8 StartBusNumber,
OUT UINT8 *SubBusNumber,
OUT UINT8 *PaddedBusRange
);
/**
Process Option Rom on the specified root bridge.
@param Bridge Pci root bridge device instance.
@retval EFI_SUCCESS Success process.
@retval other Some error occurred when processing Option Rom on the root bridge.
**/
EFI_STATUS
PciRootBridgeP2CProcess (
IN PCI_IO_DEVICE *Bridge
);
/**
Process Option Rom on the specified host bridge.
@param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
@retval EFI_SUCCESS Success process.
@retval EFI_NOT_FOUND Can not find the root bridge instance.
@retval other Some error occurred when processing Option Rom on the host bridge.
**/
EFI_STATUS
PciHostBridgeP2CProcess (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
This function is used to enumerate the entire host bridge
in a given platform.
@param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.
@retval EFI_SUCCESS Successfully enumerated the host bridge.
@retval EFI_OUT_OF_RESOURCES No enough memory available.
@retval other Some error occurred when enumerating the host bridge.
**/
EFI_STATUS
PciHostBridgeEnumerator (
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
/**
Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The address within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoRead (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
If PCI incompatibility check is enabled, do incompatibility check.
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
@param Width Signifies the width of the memory operations.
@param Offset The offset within the PCI configuration space for the PCI controller.
@param Count The number of PCI configuration operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI controller.
@retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
valid for the PCI configuration header of the PCI controller.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
**/
EFI_STATUS
PciIoWrite (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Address The address within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
/**
Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Pci A pointer to PCI_TYPE00.
@param Width Signifies the width of the memory operations.
@param Address The address within the PCI configuration space for the PCI controller.
@param Count The number of unit to be read.
@param Buffer For read operations, the destination buffer to store the results. For
write operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
PciRootBridgeIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci, OPTIONAL
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
#endif
|