1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
|
/** @file
Header file for Setup Variable.
Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SETUP_VARIABLE_H
#define _SETUP_VARIABLE_H
#include <ScLimits.h>
//
// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
//
#define SYSTEM_CONFIGURATION_GUID { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }
#define ROOT_SECURITY_GUID { 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 }
//
// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
//
#define SYSTEM_ROOT_MAIN_GUID { 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 }
//
// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
//
#define ADDITIONAL_SYSTEM_INFO_GUID { 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c }
//
// {EC87D643-EBA4-4BB5-A1E5-3F3E36B20DA9}
//
#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
//
// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0}
//
#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead, 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }
#define PASSWORD_MAX_SIZE 20
#define MAX_CUSTOM_VID_TABLE_STATES 6
#define OVERCLOCK_SOURCE_BIOS 0
#define OVERCLOCK_SOURCE_OS 1
#define PCIE_MAX_ROOT_PORT 6
#define LPSS_I2C_DEVICE_NUM 8
#define LPSS_HSUART_DEVICE_NUM 4
#define LPSS_SPI_DEVICE_NUM 3
#define HDAUDIO_FEATURES 10
#define HDAUDIO_PP_MODULES 32
#define GUID_CHARS_NUMBER 37 // 36 GUID chars + null termination
#define TPM2_SUPPORTED_BANK_NULL 0
#define TPM2_SUPPORTED_BANK_SHA1 1
#define TPM2_SUPPORTED_BANK_SHA2 2
#define TPM2_SUPPORTED_BANK_BOTH 3
#define PS2_CONSOLE 0x00
#define RECONNECT_LAST_GOOD_INPUT_CONSOLE 0x01
#define WINDOWS_CONSOLE 0x02
//
// #defines for Drive Presence
//
#define EFI_HDD_PRESENT 0x01
#define EFI_HDD_NOT_PRESENT 0x00
#define EFI_CD_PRESENT 0x02
#define EFI_CD_NOT_PRESENT 0x00
#define EFI_HDD_WARNING_ON 0x01
#define EFI_CD_WARNING_ON 0x02
#define EFI_SMART_WARNING_ON 0x04
#define EFI_HDD_WARNING_OFF 0x00
#define EFI_CD_WARNING_OFF 0x00
#define EFI_SMART_WARNING_OFF 0x00
#define OFFSET_0 0x00
#ifndef VFRCOMPILE
extern EFI_GUID gEfiSetupVariableGuid;
#endif
#ifndef PLATFORM_SETUP_VARIABLE_NAME
#define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
#endif
#define SETUP_DATA SYSTEM_CONFIGURATION
#pragma pack(push,1)
typedef struct {
//
// Floppy
//
UINT8 Floppy;
UINT8 FloppyWriteProtect;
//
// System ports
//
UINT8 UsbLegacy;
//
// Keyboard
//
UINT8 Numlock;
//
// Power State
//
UINT8 PowerState;
UINT8 PciDelayOptimizationEcr;
//
// Wake on RTC variables
//
UINT8 WakeOnRtcS5;
UINT8 RTCWakeupDate;
UINT8 RTCWakeupTimeHour;
UINT8 RTCWakeupTimeMinute;
UINT8 RTCWakeupTimeSecond;
//
// Wake On Lan
//
UINT8 WakeOnLanS5;
//
// Boot Order
//
UINT8 BootOrder[8];
//
// Hard Drive Boot Order
//
UINT8 HardDriveBootOrder[8];
//
// CD Drive Boot Order
//
UINT8 CdDriveBootOrder[4];
//
// FDD Drive Boot Order
//
UINT8 FddDriveBootOrder[4];
//
// Drive Boot Order
//
UINT8 DriveBootOrder[16];
//
// Boot Menu Type
//
UINT8 BootMenuType;
//
// Boot from Network
//
UINT8 BootNetwork;
//
// Boot USB
//
UINT8 BootUsb;
//
// Dummy place holder to prevent VFR compiler problem.
//
UINT16 DummyDataForVfrBug; // Don't change or use.
//
// Fixed Disk Boot Sector (Fdbs)
//
UINT8 Fdbs;
//
// Event Logging
//
UINT8 EventLogging;
//
// Video Adaptor
//
UINT8 PrimaryVideoAdaptor;
//
// Hybrid Graphics
//
UINT8 HgCardSelect;
UINT16 DelayAfterPwrEn;
UINT16 DelayAfterHoldReset;
//
// Maximum FSB Automatic/Disable
//
UINT8 MaxFsb;
//
// Hard Disk Pre-delay
//
UINT8 HddPredelay;
//
// S.M.A.R.T. Mode
//
UINT8 SmartMode;
//
// ACPI Suspend State
//
UINT8 AcpiSuspendState;
//
// PCI Latency Timer
//
UINT8 PciLatency;
//
// Processor (CPU)
//
//
// EIST or GV3 setup option
//
UINT8 ProcessorEistEnable;
//
// C1E Enable
//
UINT8 ProcessorC1eEnable;
//
// Enabling CPU C-States of processor
//
UINT8 ProcessorCcxEnable;
//
// Package C-State Limit
//
UINT8 PackageCState;
//
// Enable/Disable NHM C3(ACPI C2) report to OS
//
UINT8 OSC2Report;
//
// Enable/Disable NHM C6(ACPI C3) report to OS
//
UINT8 C6Enable;
//
// Enable/Disable NHM C7(ACPI C3) report to OS
//
UINT8 C7Enable;
//
// EIST/PSD Function select option
//
UINT8 ProcessorEistPsdFunc;
//
// CPU Active Cores and SMT
//
UINT8 ActiveProcessorCores;
//
// Core0 is always Enable.
//
UINT8 Core0;
//
// Enable/Disable Individual core1
//
UINT8 Core1;
//
// Enable/Disable Individual core2
//
UINT8 Core2;
//
// Enable/Disable Individual core3
//
UINT8 Core3;
//
// Hyper Threading
//
UINT8 ProcessorHyperThreadingDisable;
//
// Enabling VMX
//
UINT8 ProcessorVmxEnable;
//
// Enabling VTD
//
UINT8 VTdEnable;
//
// Enabling BIST
//
UINT8 ProcessorBistEnable;
//
// Disabling XTPR
//
UINT8 ProcessorxTPRDisable;
//
// Enabling XE
//
UINT8 ProcessorXEEnable;
//
// Fast String
//
UINT8 FastStringEnable;
//
// Monitor/Mwait
//
UINT8 MonitorMwaitEnable;
//
// Machine Check
//
UINT8 MachineCheckEnable;
//
// Turbo mode
//
UINT8 TurboModeEnable;
//
// Enable Processor XAPIC
//
UINT8 ProcessorXapic;
//
// Select BSP
//
UINT8 BspSelection;
//
// Turbo-XE Mode Processor TDC Limit Override Enable
//
UINT8 ProcessorTDCLimitOverrideEnable;
//
// Turbo-XE Mode Processor TDC Limit
//
UINT16 ProcessorTDCLimit;
//
// Turbo-XE Mode Processor TDP Limit Override Enable
//
UINT8 ProcessorTDPLimitOverrideEnable;
//
// Turbo-XE Mode Processor TDP Limit
//
UINT16 ProcessorTDPLimit;
//
// Virtual wire A or B
//
UINT8 ProcessorVirtualWireMode;
//
// FSB Frequency Override in MHz
//
UINT16 FsbFrequency;
//
// Ecc 0/1 Disable/Enable if supported
//
UINT8 EccEnable;
//
// Memory
//
UINT16 ChannelHashMask;
UINT16 SliceHashMask;
UINT8 InterleavedMode;
UINT8 ChannelsSlicesEnabled;
UINT8 MinRefRate2xEnabled;
UINT8 DualRankSupportEnabled;
UINT8 DualRankSupportEnableLockHide;
//
// Port 80 decode 0/1 - PCI/LPC
//
UINT8 Port80Route;
//
// ECC Event Logging
//
UINT8 EccEventLogging;
//
// VT-d Option
//
UINT8 InterruptRemap;
UINT8 Isoc;
UINT8 ATS;
//
// IGD option
//
UINT8 GraphicsDriverMemorySize;
//
// IGD Aperture Size question
//
UINT8 IgdApertureSize;
//
// Boot Display Device
//
UINT8 BootDisplayDevice;
//
// Integrated Graphics Device
//
UINT8 Igd;
//
// Flash update sleep delay
//
UINT8 FlashSleepDelay;
//
// FSC system Variable
//
UINT8 IgdFlatPanel;
UINT8 EnableC10;
UINT8 FastBoot;
UINT8 EfiNetworkSupport;
UINT8 PxeRom;
UINT8 Knob001;
UINT8 EnableGv;
UINT8 EnableCx;
UINT8 EnableCxe;
UINT8 EnableTm;
UINT8 EnableProcHot;
UINT8 BootPState;
UINT8 FlexRatio;
UINT8 FlexVid;
UINT8 QuietBoot;
//
// Thermal Policy Values
//
UINT8 AutoThermalReporting;
UINT8 EnableDigitalThermalSensor;
UINT8 PassiveThermalTripPoint;
UINT8 PassiveTc1Value;
UINT8 PassiveTc2Value;
UINT8 PassiveTspValue;
UINT8 CriticalThermalTripPoint;
UINT8 ActiveTripPoint;
UINT8 DeepStandby;
UINT8 AlsEnable;
UINT8 IgdLcdIBia;
UINT8 LogBootTime;
//
// EM-1 related
//
UINT16 IaAppsRun;
UINT8 IaAppsCap;
UINT8 CapOrVoltFlag;
UINT8 BootOnInvalidBatt;
UINT8 ScramblerSupport;
UINT8 SecureBoot;
UINT8 SecureBootCustomMode;
UINT8 MaxPkgCState;
UINT8 PanelScaling;
UINT8 IgdLcdIGmchBlc;
UINT8 SecEnable;
UINT8 TPM;
UINT8 TPMSupportedBanks;
UINT8 TpmDetection;
UINT8 PttSuppressCommandSend; // For PTT Debug
UINT8 SecFlashUpdate;
UINT8 SecFirmwareUpdate;
//
//Image Processing Unit PCI Device Configuration
//
UINT8 IpuEn;
UINT8 IpuAcpiMode;
//
// Passwords
//
UINT8 Recovery;
UINT8 Suspend;
//
// South Cluster Area - START
//
//
// Security options
//
UINT8 ScBiosLock;
//
// Miscellaneous options
//
UINT8 Hpet;
UINT8 Cg8254;
UINT8 EnableClockSpreadSpec;
UINT8 StateAfterG3;
UINT8 UartInterface;
UINT8 Wol;
//
// SCC Configuration
//
UINT8 SccSdcardEnabled;
UINT8 ScceMMCEnabled;
UINT8 ScceMMCHostMaxSpeed;
UINT8 SccSdioEnabled;
UINT8 GPPLock;
UINT8 GppLockOptionHide;
//
// LPSS Configuration
//
UINT8 LpssI2C0Enabled;
UINT8 LpssI2C1Enabled;
UINT8 LpssI2C2Enabled;
UINT8 LpssI2C3Enabled;
UINT8 LpssI2C4Enabled;
UINT8 LpssI2C5Enabled;
UINT8 LpssI2C6Enabled;
UINT8 LpssI2C7Enabled;
UINT8 LpssHsuart0Enabled;
UINT8 LpssHsuart1Enabled;
UINT8 LpssHsuart2Enabled;
UINT8 LpssHsuart3Enabled;
UINT8 LpssSpi0Enabled;
UINT8 LpssSpi1Enabled;
UINT8 LpssSpi2Enabled;
UINT8 LpssNFCSelect;
UINT8 LpssI2cClkGateCfg[LPSS_I2C_DEVICE_NUM];
UINT8 LpssHsuartClkGateCfg[LPSS_HSUART_DEVICE_NUM];
UINT8 LpssSpiClkGateCfg[LPSS_SPI_DEVICE_NUM];
UINT8 S0ixEnable;
//
// Usb Config
//
UINT8 UsbXhciSupport;
UINT8 ScUsb30Mode;
UINT8 ScUsb30Streams;
UINT8 ScUsb20;
UINT8 ScUsbPortDisable;
UINT8 PortUsb20[SC_MAX_USB2_PORTS];
UINT8 ScUsbOtg;
UINT8 ScUsbVbusOn; //OTG VBUS control
UINT8 DisableComplianceMode;
UINT8 IddigComp;
//
//Hsic and SSic Config
//
UINT8 Hsic1Support;
UINT8 Ssic1Support;
UINT8 Ssic2Support;
UINT8 Ssic1Rate;
UINT8 Ssic2Rate;
UINT8 SsicDlanePg;
//
// Lan Config
//
UINT8 Lan;
UINT8 SlpLanLowDc;
//
// HD-Audio Config
//
UINT8 ScHdAudio;
UINT8 ScHdAudioDsp;
UINT8 ScHdAudioCtlPwrGate; // Deprecated option
UINT8 ScHdAudioDspPwrGate; // Deprecated option
UINT8 ScHdAudioMmt;
UINT8 ScHdAudioHmt;
UINT8 ScHdAudioIoBufferOwnership;
UINT8 ScHdAudioBiosCfgLockDown;
UINT8 ScHdAudioPwrGate;
UINT8 ScHdAudioClkGate;
UINT8 ScHdAudioPme;
UINT8 ScHdAudioFeature[HDAUDIO_FEATURES];
UINT8 ScHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
CHAR16 ScHdAudioPostProcessingModCustomGuid1[GUID_CHARS_NUMBER];
CHAR16 ScHdAudioPostProcessingModCustomGuid2[GUID_CHARS_NUMBER];
CHAR16 ScHdAudioPostProcessingModCustomGuid3[GUID_CHARS_NUMBER];
UINT8 ScHdAudioNhltEndpointDmic;
UINT8 ScHdAudioNhltEndpointBt;
UINT8 ScHdAudioNhltEndpointI2sSKP;
UINT8 ScHdAudioNhltEndpointI2sHP;
UINT8 ScHdAduioRsvd1;
UINT8 SvHdaVcType;
UINT8 HdAudioLinkFrequency;
UINT8 IDispLinkFrequency;
UINT8 IDispLinkTmode;
//
// GMM Config
//
UINT8 Gmm;
UINT8 GmmCgPGCBEnabled;
UINT8 GmmCgSBDEnabled;
UINT8 GmmCgSBTEnabled;
UINT8 GmmCgSBPEnabled;
UINT8 GmmCgCoreEnabled;
UINT8 GmmCgDmaEnabled;
UINT8 GmmCgRAEnabled;
UINT8 GmmCgHostEnabled;
UINT8 GmmCgPEnabled;
UINT8 GmmCgTEnabled;
UINT8 GmmPgHwAutoEnabled;
UINT8 GmmPgD3HotEnabled;
UINT8 GmmPgI3Enabled;
UINT8 GmmPgPMCREnabled;
//
// ISH Config
//
UINT8 ScIshEnabled;
UINT8 IshI2c0PullUp;
UINT8 IshI2c1PullUp;
//
// SATA_CONFIG
//
UINT8 Sata;
UINT8 SataTestMode;
UINT8 SataInterfaceMode;
UINT8 SataPort[SC_MAX_SATA_PORTS];
UINT8 SataHotPlug[SC_MAX_SATA_PORTS];
UINT8 SataMechanicalSw[SC_MAX_SATA_PORTS];
UINT8 SataSpinUp[SC_MAX_SATA_PORTS];
UINT8 SataExternal[SC_MAX_SATA_PORTS];
UINT8 SataType[SC_MAX_SATA_PORTS];
UINT8 SataSalp;
UINT8 PxDevSlp[SC_MAX_SATA_PORTS];
UINT8 EnableDitoConfig[SC_MAX_SATA_PORTS];
UINT16 DitoVal[SC_MAX_SATA_PORTS];
UINT8 DmVal[SC_MAX_SATA_PORTS];
//
// PCI_EXPRESS_CONFIG, 6 ROOT PORTS
//
UINT8 PcieClockGatingDisabled;
UINT8 PcieRootPort8xhDecode;
UINT8 Pcie8xhDecodePortIndex;
UINT8 PcieRootPortPeerMemoryWriteEnable;
UINT8 PcieComplianceMode;
UINT8 PcieRootPortEn[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortAspm[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortURE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortFEE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortNFE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortCEE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortCTD[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortPIE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSFE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSNE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSCE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortPMCE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortHPE[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSpeed[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortTHS[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortL1SubStates[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortACS[SC_MAX_PCIE_ROOT_PORTS];
//
// PCIe LTR Configuration
//
UINT8 PchPcieLtrEnable[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieLtrConfigLock[SC_MAX_PCIE_ROOT_PORTS];
UINT16 PcieLtrMaxSnoopLatency[SC_MAX_PCIE_ROOT_PORTS];
UINT16 PcieLtrMaxNoSnoopLatency[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieSnoopLatencyOverrideMode[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieSnoopLatencyOverrideMultiplier[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieNonSnoopLatencyOverrideMode[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[SC_MAX_PCIE_ROOT_PORTS];
UINT16 PchPcieSnoopLatencyOverrideValue[SC_MAX_PCIE_ROOT_PORTS];
UINT16 PchPcieNonSnoopLatencyOverrideValue[SC_MAX_PCIE_ROOT_PORTS];
//
// PCI Bridge Resources
//
UINT8 PcieExtraBusRsvd[SC_MAX_PCIE_ROOT_PORTS];
UINT16 PcieMemRsvd[SC_MAX_PCIE_ROOT_PORTS];
UINT8 PcieIoRsvd[SC_MAX_PCIE_ROOT_PORTS];
//
// South Cluster Area - END
//
UINT8 GTTSize;
UINT8 PeiGraphicsPeimInit;
//
// DVMT5.0 Graphic memory setting
//
UINT8 IgdDvmt50PreAlloc;
UINT8 IgdDvmt50TotalAlloc;
UINT8 GOPEnable;
UINT8 GOPBrightnessLevel; //Gop Brightness level
UINT8 VbtSelect;
//
// Gt Config
//
UINT8 PmSupport;
UINT8 EnableRenderStandby;
UINT8 PavpEnable;
UINT8 CdClock;
UINT8 SeCOpEnable;
UINT8 SeCModeEnable;
UINT8 SeCEOPEnable;
UINT8 SeCEOPDone;
UINT8 SeCLockDir;
//
// DPTF
//
UINT8 EnableDptf; // Option to enable/disable DPTF
UINT16 EnableDCFG; // Option to enable/disable DPTF Configuration
UINT8 DptfProcessor; // Enable processor participant
UINT16 DptfProcCriticalTemperature; // Processor critical temperature
UINT16 DptfProcPassiveTemperature; // Processor passive temperature
UINT16 DptfProcActiveTemperature; // Processor active temperature
UINT16 DptfProcCriticalTemperatureS3; // Processor warm temperature
UINT16 DptfProcHotThermalTripPoint; // Processor hot temperature
UINT16 GenericCriticalTemp0; // Critical temperature value for generic sensor0 participant
UINT16 GenericPassiveTemp0; // Passive temperature value for generic sensor0 participant
UINT16 GenericCriticalTemp1; // Critical temperature value for generic sensor1 participant
UINT16 GenericPassiveTemp1; // Passive temperature value for generic sensor1 participant
UINT16 GenericCriticalTemp2; // Critical temperature value for generic sensor2 participant
UINT16 GenericPassiveTemp2; // Passive temperature value for generic sensor2 participant
UINT16 GenericCriticalTemp3; // Critical temperature value for generic sensor3 participant
UINT16 GenericPassiveTemp3; // Passive temperature value for generic sensor3 participant
UINT16 GenericCriticalTemp4; // Critical temperature value for generic sensor3 participant
UINT16 GenericPassiveTemp4; // Passive temperature value for generic sensor3 participant
UINT8 ThermalSamplingPeriodTCPU; //
UINT8 Clpm; // Current low power mode
UINT32 LPOEnable; // DPTF: Instructs the policy to use Active Cores if they are available. If this option is set to 0, then policy does not use any active core controls ?even if they are available
UINT32 LPOStartPState; // DPTF: Instructs the policy when to initiate Active Core control if enabled. Returns P state index.
UINT32 LPOStepSize; // DPTF: Instructs the policy to take away logical processors in the specified percentage steps
UINT32 LPOPowerControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P0 or when power control is applied. 1 ?SMT Off lining 2- Core Off lining
UINT32 LPOPerformanceControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P1 or when performance control is applied.1 ?SMT Off lining 2- Core Off lining
UINT8 EnableDppm; // DPTF: Controls DPPM Policies (enabled/disabled)
UINT8 EnableSen0Participant;
UINT8 PassiveThermalTripPointSen0;
UINT8 CriticalThermalTripPointSen0;
UINT8 CriticalThermalTripPointSen0S3;
UINT8 HotThermalTripPointSen0;
UINT8 EnableSen3Participant;
UINT8 PassiveThermalTripPointSen3;
UINT8 CriticalThermalTripPointSen3;
UINT8 CriticalThermalTripPointSen3S3;
UINT8 HotThermalTripPointSen3;
UINT8 DptfChargerDevice;
UINT8 DptfDisplayDevice;
UINT8 DisplayHighLimit;
UINT8 DisplayLowLimit;
UINT8 EnablePowerParticipant;
UINT16 PowerParticipantPollingRate;
UINT8 DptfFanDevice;
UINT8 DptfWwanDevice;
UINT8 PassiveThermalTripPointWWAN;
UINT8 CriticalThermalTripPointWWANS3;
UINT8 HotThermalTripPointWWAN;
UINT8 CriticalThermalTripPointWWAN;
UINT8 HighPerfMode;
UINT8 PmicEnable;
UINT8 APEIBERT;
UINT8 ACPIMemDbg;
UINT8 BatteryChargingSolution; //0-non ULPMC 1-ULPMC
UINT8 EnableActivePolicy;
UINT8 EnablePassivePolicy;
UINT8 TrtRevision;
UINT8 EnableCriticalPolicy;
UINT8 EnableAPPolicy;
UINT8 EnablePowerBossPolicy;
UINT8 EnableVSPolicy;
UINT8 EnableMemoryDevice;
UINT8 ActiveThermalTripPointTMEM;
UINT8 PassiveThermalTripPointTMEM;
UINT8 CriticalThermalTripPointTMEM;
UINT8 ThermalSamplingPeriodTMEM;
UINT8 EnableSen1Participant;
UINT8 ActiveThermalTripPointSen1;
UINT8 PassiveThermalTripPointSen1;
UINT8 CriticalThermalTripPointSen1;
UINT8 CriticalThermalTripPointSen1S3;
UINT8 HotThermalTripPointSen1;
UINT8 SensorSamplingPeriodSen1;
UINT8 EnableGen1Participant;
UINT8 ActiveThermalTripPointGen1;
UINT8 PassiveThermalTripPointGen1;
UINT8 CriticalThermalTripPointGen1;
UINT8 CriticalThermalTripPointGen1S3;
UINT8 HotThermalTripPointGen1;
UINT8 ThermistorSamplingPeriodGen1;
UINT8 EnableGen2Participant;
UINT8 ActiveThermalTripPointGen2;
UINT8 PassiveThermalTripPointGen2;
UINT8 CriticalThermalTripPointGen2;
UINT8 CriticalThermalTripPointGen2S3;
UINT8 HotThermalTripPointGen2;
UINT8 ThermistorSamplingPeriodGen2;
UINT8 EnableGen3Participant;
UINT8 ActiveThermalTripPointGen3;
UINT8 PassiveThermalTripPointGen3;
UINT8 CriticalThermalTripPointGen3;
UINT8 CriticalThermalTripPointGen3S3;
UINT8 HotThermalTripPointGen3;
UINT8 ThermistorSamplingPeriodGen3;
UINT8 EnableGen4Participant;
UINT8 ActiveThermalTripPointGen4;
UINT8 PassiveThermalTripPointGen4;
UINT8 CriticalThermalTripPointGen4;
UINT8 CriticalThermalTripPointGen4S3;
UINT8 HotThermalTripPointGen4;
UINT8 ThermistorSamplingPeriodGen4;
UINT8 OemDesignVariable0;
UINT8 OemDesignVariable1;
UINT8 OemDesignVariable2;
UINT8 OemDesignVariable3;
UINT8 OemDesignVariable4;
UINT8 OemDesignVariable5;
UINT8 EnableVS1Participant;
UINT8 ActiveThermalTripPointVS1;
UINT8 PassiveThermalTripPointVS1;
UINT8 CriticalThermalTripPointVS1;
UINT8 CriticalThermalTripPointVS1S3;
UINT8 HotThermalTripPointVS1;
UINT8 EnableVS2Participant;
UINT8 ActiveThermalTripPointVS2;
UINT8 PassiveThermalTripPointVS2;
UINT8 CriticalThermalTripPointVS2;
UINT8 CriticalThermalTripPointVS2S3;
UINT8 HotThermalTripPointVS2;
UINT8 EnableVS3Participant;
UINT8 ActiveThermalTripPointVS3;
UINT8 PassiveThermalTripPointVS3;
UINT8 CriticalThermalTripPointVS3;
UINT8 CriticalThermalTripPointVS3S3;
UINT8 HotThermalTripPointVS3;
UINT8 PnpSettings;
UINT8 EhciDebug;
UINT8 IrmtConfiguration;
UINT8 CRIDSettings;
//
//Dnx/Fastboot enable for PO
//
UINT8 OSDnX;
#if _SVBIOS_
//
// SV-SSA
//
#if _SVSSABIOS_
UINT16 MemorySize;
#endif
//
// SV-MRC
//
#if _SVMRCBIOS_
UINT8 MrcDebugMsgLevel;
#endif
//
// For FW Debug Menu Options
//
#if _SVSECBIOS_
UINT8 EndOfPostEnabled;
UINT8 HeciCommunication;
UINT8 TdtAssertStolen;
#endif
#endif //end _SVBIOS_
//
//OEM1 table
//
UINT8 CStateAutoDemotion;
UINT8 CStateUnDemotion;
UINT8 PkgCStateDemotion;
UINT8 PkgCStateUnDemotion;
UINT8 ProcTraceMemSize;
UINT8 ProcTraceEnable;
UINT8 ProcTraceOutputScheme;
// TDO
UINT8 TDO;
//
// Kernel Debugger (WinDBG)
//
UINT8 OsDbgEnable;
#ifdef PRAM_SUPPORT
UINT8 Pram;
#endif
//
// GNSS/GPS mode selection
//
UINT8 GpsModeSel;
UINT8 PreOsSelection;
//
//Trunk clock enable
//
UINT8 TrunkClockEnable;
UINT8 MaxCoreCState;
//
//Multi-BOM
//
UINT8 BomSelection;
UINT8 PanelSel;
UINT8 WorldCameraSel;
UINT8 UserCameraSel;
UINT8 AudioSel;
UINT8 ModemSel; // Modem selection: 0: Disabled, 1: 7260; 2: 7360;
UINT8 TouchSel; // Touch selection: 0: Disabled, 1: Atmel mXT1066T2; 2: Atmel mXT1668T2
UINT8 WifiSel; // Wi-Fi Device Select 0: SDIO Lightning Peak 1: SDIO Broadcom 2. PCIe Lightning Peak
UINT8 FirmwareConfiguration;
//
// ACPI
//
UINT8 PciExpNative;
UINT8 NativeAspmEnable;
UINT8 LowPowerS0Idle;
UINT8 TenSecondPowerButtonEnable;
UINT8 EcLowPowerMode;
UINT8 CSNotifyEC;
UINT8 CSDebugLightEC;
//
// RTD3
//
UINT8 Rtd3Support;
UINT8 Rtd3P0dl;
UINT8 Rtd3P3dl;
UINT8 RTD3UsbPt1;
UINT8 RTD3UsbPt2;
UINT8 RTD3I2C0SensorHub;
UINT16 RTD3AudioDelay;
UINT16 RTD3TouchPadDelay;
UINT16 RTD3TouchPanelDelay;
UINT16 RTD3SensorHub;
UINT16 VRStaggeringDelay;
UINT16 VRRampUpDelay;
UINT8 PstateCapping;
UINT8 RTD3ZPODD;
UINT8 RTD3Camera;
UINT8 RTD3SataPort1;
UINT8 RTD3SataPort2;
UINT8 RTD3SataPort3;
UINT8 Rtd3WaGpio;
UINT16 RTD3I2C0ControllerPS0Delay;
UINT16 RTD3I2C1ControllerPS0Delay;
UINT8 ConsolidatedPR;
UINT8 DciEn;
UINT8 DciAutoDetect;
//
// Secure NFC
//
UINT8 NfcSelect;
UINT8 SelectBtDevice;
UINT8 ResetSelect;
UINT8 FprrEnable;
//
// WIGIG enable switch
//
UINT8 WiGigEnable;
UINT16 WiGigSPLCPwrLimit;
UINT32 WiGigSPLCTimeWindow;
UINT16 RfemSPLCPwrLimit;
UINT32 RfemSPLCTimeWindow;
//
//PSM
//
UINT8 PsmEnable;
UINT8 PsmSPLC0DomainType;
UINT16 PsmSPLC0PwrLimit;
UINT32 PsmSPLC0TimeWindow;
UINT8 PsmSPLC1DomainType;
UINT16 PsmSPLC1PwrLimit;
UINT32 PsmSPLC1TimeWindow;
UINT8 PsmDPLC0DomainType;
UINT8 PsmDPLC0DomainPerference;
UINT8 PsmDPLC0PowerLimitIndex;
UINT16 PsmDPLC0PwrLimit;
UINT32 PsmDPLC0TimeWindow;
UINT8 PsmDPLC1DomainType;
UINT8 PsmDPLC1DomainPerference;
UINT8 PsmDPLC1PowerLimitIndex;
UINT16 PsmDPLC1PwrLimit;
UINT32 PsmDPLC1TimeWindow;
UINT8 VirtualKbEnable;
UINT8 EPIEnable;
UINT8 TypeCEnable;
//
//DDR and High Speed Serial IO SSC
//
UINT8 DDRSSCEnable;
UINT8 DDRSSCSelection;
UINT8 DDRCLKBending;
UINT8 HSSIOSSCEnable;
UINT8 HSSIOSSCSelection;
//
// LPSS devices
//
UINT8 I2s343A;
UINT8 I2s34C1;
UINT8 I2cNfc;
UINT8 I2cPss;
UINT8 UartBt;
UINT8 UartGps;
UINT8 Spi1SensorDevice;
UINT32 Uart2KernelDebugBaseAddress;
//
// SMRR for SMM source level debug
//
UINT8 SMRREnable;
//
// Windows Offline Crash Dump
//
#ifdef CRASHDUMP_SUPPORT
UINT8 CrashDump;
#endif
//
// S3 Setupvairable
//
UINT64 AcpiVariableSetCompatibility;
UINT32 BootPerformanceTablePointer;
UINT32 S3PerformanceTablePointer;
UINT8 CseBootDevice; // 0 - eMMC, 1- UFS, 2 - SPI
//
// Platform Default
//
UINT8 BoardId;
UINT8 PlatformSettingEn;
UINT8 Max2G;
UINT8 PmicSetupDefault;
UINT8 RTEn; //Real Time
//
// CPU Power Limit
//
UINT8 PowerLimit1Enable;
UINT8 PowerLimit1Clamp;
UINT8 PowerLimit1Time;
UINT8 PowerLimit1;
//
// IPC1 (PMI) device
//
UINT8 RtcLock;
UINT8 UseProductKey;
UINT8 PowerButterDebounceMode;
UINT8 PcieRootPortSelectableDeemphasis[SC_MAX_PCIE_ROOT_PORTS];
UINT8 ConInBehavior;
//
// Number Of Processors
//
UINT8 NumOfProcessors;
UINT8 GpioLock;
UINT8 CameraRotationAngle;
UINT8 PortUsb30[SC_MAX_USB3_PORTS];
//
// Touch Panel and Pad setting
//
UINT8 I2cTouchPanel;
UINT8 I2cTouchPad;
//
//I2C Speed
//
UINT8 I2C0Speed;
UINT8 I2C1Speed;
UINT8 I2C2Speed;
UINT8 I2C3Speed;
UINT8 I2C4Speed;
UINT8 I2C5Speed;
UINT8 I2C6Speed;
UINT8 I2C7Speed;
UINT8 TcoLock;
UINT8 EnableSen2Participant;
UINT8 PassiveThermalTripPointSen2;
UINT8 CriticalThermalTripPointSen2;
UINT8 CriticalThermalTripPointSen2S3;
UINT8 HotThermalTripPointSen2;
} SYSTEM_CONFIGURATION;
#pragma pack(pop)
#endif // #ifndef _SETUP_VARIABLE
|
