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## @file
# Provides drivers and definitions to support fsp in EDKII bios.
#
# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = IntelFsp2WrapperPkg
PACKAGE_GUID = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0
PACKAGE_VERSION = 0.1
[Includes]
Include
[LibraryClasses]
## @libraryclass Provide FSP API related function.
FspWrapperApiLib|Include/Library/FspWrapperApiLib.h
FspWrapperApiTestLib|Include/Library/FspWrapperApiTestLib.h
## @libraryclass Provide FSP hob process related function.
FspHobProcessLib|Include/Library/FspHobProcessLib.h
## @libraryclass Provide FSP platform information related function.
FspPlatformInfoLib|Include/Library/FspPlatformInfoLib.h
## @libraryclass Provide FSP wrapper platform sec related function.
FspPlatformSecLib|Include/Library/FspPlatformSecLib.h
[Guids]
#
# GUID defined in package
#
gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }
gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }
[Ppis]
gFspSiliconInitDonePpiGuid = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }
gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }
[Protocols]
################################################################################
#
# PCD Declarations section - list of all PCDs Declared by this Package
# Only this package should be providing the
# declaration, other packages should not.
#
################################################################################
[PcdsFixedAtBuild, PcdsPatchableInModule]
## Provides the memory mapped base address of the BIOS CodeCache Flash Device.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001
## Provides the size of the BIOS Flash Device.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
## Indicates the base address of the factory FSP binary.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003
## Indicates the base address of the updatable FSP binary to support Dual FSP.
# There could be two FSP images at different locations in a flash -
# one factory version (default) and updatable version (updatable).
# TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.
# FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,
# FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,
# PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase
# is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means
# there is no updatable FSP.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008
## Provides the size of the factory FSP binary.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004
## Provides the size of the updatable FSP binary to support Dual FSP.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009
## Indicates the base address of the first Microcode Patch in the Microcode Region
gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006
## Indicates the offset of the Cpu Microcode.
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x90|UINT32|0x10000007
##
# Maximum number of Ppi is provided by SecCore.
##
gIntelFsp2WrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported|0x6|UINT32|0x20000001
## Stack size in the temporary RAM.
# 0 means half of TemporaryRamSize.
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x40000001
# This is temporary DRAM base and size for StackTop in FspInit
gIntelFsp2WrapperTokenSpaceGuid.PcdTemporaryRamBase|0x00080000|UINT32|0x40000002
gIntelFsp2WrapperTokenSpaceGuid.PcdTemporaryRamSize|0x00010000|UINT32|0x40000003
# This is stack base and size for FSP in MemoryInit
gIntelFsp2WrapperTokenSpaceGuid.PcdFspStackBase|0x00000000|UINT32|0x40000004
gIntelFsp2WrapperTokenSpaceGuid.PcdFspStackSize|0x00000000|UINT32|0x40000005
## Indicate the PEI memory size platform want to report
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000006
## Indicate the PEI memory size platform want to report
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000007
[PcdsDynamic,PcdsDynamicEx]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
|