blob: fd0b55333740635ceb19d987daffc5aba4d09a4b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
|
/** @file
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PCH_RC_CONFIG_DATA_H__
#define __PCH_RC_CONFIG_DATA_H__
#include <PchLimits.h>
#define HDAUDIO_FEATURES 3
#define HDAUDIO_PP_MODULES 2
/// sSATA max ports for Wellsburg
#define PCH_SSATA_MAX_PORTS 6
#pragma pack(1)
typedef struct {
UINT8 BiosGuard;
UINT8 Dwr_Enable;
UINT8 Dwr_Stall;
UINT8 Dwr_BmcRootPort;
UINT8 DwrEn_PMCGBL;
UINT8 DwrEn_CPUTHRM;
UINT8 DwrEn_PCHTHRM;
UINT8 DwrEn_PBO;
UINT8 DwrEn_MEPBO;
UINT8 DwrEn_MEWDT;
UINT8 DwrEn_MEGBL;
UINT8 DwrEn_CTWDT;
UINT8 DwrEn_PMCWDT;
UINT8 DwrEn_ME_UERR;
UINT8 DwrEn_SYSPWR;
UINT8 DwrEn_OCWDT;
UINT8 DwrEn_IEPBO;
UINT8 DwrEn_IEWDT;
UINT8 DwrEn_IEGBLN;
UINT8 DwrEn_IE_UERRN;
UINT8 DwrEn_ACRU_ERR_2H_EN;
UINT8 DwrPmcEn_HOST_RESET_TIMEOUT;
UINT8 DwrPmcEn_SX_ENTRY_TIMEOUT;
UINT8 DwrPmcEn_HOST_RST_PROM;
UINT8 DwrPmcEn_HSMB_MSG;
UINT8 DwrPmcEn_IE_MTP_TIMEOUT;
UINT8 DwrPmcEn_MTP_TIMEOUT;
UINT8 DwrPmcEn_ESPI_ERROR_DETECT;
UINT8 Dwr_MeResetPrepDone;
UINT8 Dwr_IeResetPrepDone;
//
// PCH_DEVICE_ENABLES
//
UINT8 BoardCapability;
UINT8 DeepSxMode;
UINT8 Gp27WakeFromDeepSx;
UINT8 GbeRegionInvalid;
UINT8 LomLanSupported;
UINT8 PchWakeOnLan;
UINT8 PchSlpLanLowDc;
UINT8 PchSmbus;
UINT8 PchPciClockRun;
UINT8 PchDisplay;
UINT8 PchCrid;
UINT8 PchRtcLock;
UINT8 PchBiosLock;
UINT8 PchAllUnLock;
UINT8 PchThermalUnlock;
UINT8 PchSerm;
UINT8 PchGbeFlashLockDown;
UINT8 PchSmmBwp;
UINT8 Hpet;
UINT8 PchPort80Route;
UINT8 EnableClockSpreadSpec;
UINT8 IchPort80Route;
UINT8 PchSirqMode;
//
// Usb Config
//
UINT8 PchUsbManualMode;
UINT8 PchGpioLockDown;
UINT8 RouteUsb2PinsToWhichHc;
UINT8 RouteUsb2Pin0;
UINT8 RouteUsb2Pin1;
UINT8 RouteUsb2Pin2;
UINT8 RouteUsb2Pin3;
UINT8 RouteUsb2Pin4;
UINT8 RouteUsb2Pin5;
UINT8 RouteUsb2Pin6;
UINT8 RouteUsb2Pin7;
UINT8 RouteUsb2Pin8;
UINT8 RouteUsb2Pin9;
UINT8 RouteUsb2Pin10;
UINT8 RouteUsb2Pin11;
UINT8 RouteUsb2Pin12;
UINT8 RouteUsb2Pin13;
UINT8 Usb3PinsTermination;
UINT8 EnableUsb3Pin[10];
UINT8 PchUsbHsPort[16];
UINT8 PchUsbSsPort[10];
UINT8 PchUsbPortDisable;
UINT8 UsbSensorHub;
UINT8 UsbSsicSupport[2];
UINT8 XhciDisMSICapability;
UINT8 PchUsbPerPortCtl;
UINT8 PchUsb30Port[6];
UINT8 UsbPrecondition;
UINT8 XhciIdleL1;
UINT8 Btcg;
UINT8 PchUsbDegradeBar;
//
// XHCI OC Map
//
UINT8 XhciOcMapEnabled;
//
// xDCI Config
//
UINT8 PchXdciSupport;
//
// Sata CONFIG
//
UINT8 PchSata;
//
// Sata Interface Mode
// 0 - IDE 1 - RAID 2 - AHCI
//
UINT8 SataInterfaceMode;
UINT8 SataPort[PCH_MAX_SATA_PORTS];
UINT8 SataHotPlug[PCH_MAX_SATA_PORTS];
UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS];
UINT8 SataSpinUp[PCH_MAX_SATA_PORTS];
UINT8 SataExternal[PCH_MAX_SATA_PORTS];
UINT8 SataType[PCH_MAX_SATA_PORTS];
UINT8 SataRaidR0;
UINT8 SataRaidR1;
UINT8 SataRaidR10;
UINT8 SataRaidR5;
UINT8 SataRaidIrrt;
UINT8 SataRaidOub;
UINT8 SataHddlk;
UINT8 SataLedl;
UINT8 SataRaidIooe;
UINT8 SataRaidSrt;
UINT8 SataRaidLoadEfiDriver;
UINT8 SataRaidOromDelay;
UINT8 SataAlternateId;
UINT8 SataSalp;
UINT8 SataTestMode;
UINT8 PxDevSlp[PCH_MAX_SATA_PORTS];
UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS];
UINT16 DitoVal[PCH_MAX_SATA_PORTS];
UINT8 DmVal[PCH_MAX_SATA_PORTS];
UINT8 SataTopology[PCH_MAX_SATA_PORTS];
//
// sSata CONFIG
//
UINT8 PchsSata;
//
// Sata Interface Mode
// 0 - IDE 1 - RAID 2 - AHCI
//
UINT8 sSataInterfaceMode;
UINT8 sSataPort[PCH_SSATA_MAX_PORTS];
UINT8 sSataHotPlug[PCH_SSATA_MAX_PORTS];
UINT8 sSataSpinUp[PCH_SSATA_MAX_PORTS];
UINT8 sSataExternal[PCH_SSATA_MAX_PORTS];
UINT8 sPxDevSlp[PCH_SSATA_MAX_PORTS];
UINT8 sSataType[PCH_SSATA_MAX_PORTS];
UINT8 sSataRaidR0;
UINT8 sSataRaidR1;
UINT8 sSataRaidR10;
UINT8 sSataRaidR5;
UINT8 sSataRaidIrrt;
UINT8 sSataRaidOub;
UINT8 sSataHddlk;
UINT8 sSataLedl;
UINT8 sSataRaidIooe;
UINT8 sSataRaidSrt;
UINT8 sSataRaidLoadEfiDriver;
UINT8 sSataRaidOromDelay;
UINT8 sSataAlternateId;
UINT8 sSataSalp;
UINT8 sSataTestMode;
UINT8 sEnableDitoConfig[PCH_SSATA_MAX_PORTS];
UINT8 sDmVal[PCH_SSATA_MAX_PORTS];
UINT8 sDitoVal[PCH_SSATA_MAX_PORTS];
UINT8 sSataTopology[PCH_SSATA_MAX_PORTS];
//PCH THERMAL SENSOR
UINT8 ThermalDeviceEnable;
UINT8 PchCrossThrottling;
UINT8 PchDmiExtSync;
UINT8 PcieDmiExtSync;
// AcpiDebug Setup Options
UINT8 PciDelayOptimizationEcr;
UINT8 PchPcieGlobalAspm;
UINT8 PcieDmiStopAndScreamEnable;
UINT8 DmiLinkDownHangBypass;
UINT8 XTpmLen;
UINT8 PcieRootPort8xhDecode;
UINT8 Pcie8xhDecodePortIndex;
UINT8 PcieRootPortPeerMemoryWriteEnable;
UINT8 PcieComplianceTestMode;
UINT8 PcieRootPortSBDE;
UINT8 PcieSBDEPort;
UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR];
UINT8 PcieRootPortFunctionSwapping;
UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortMSIE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieSwEqOverride;
UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX];
UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX];
UINT8 PchPcieUX8MaxPayloadSize;
UINT8 PchPcieUX16MaxPayloadSize;
UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieClockGatingDisabled;
UINT8 PcieUsbGlitchWa;
UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortMaxReadRequestSize;
UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];
//
// PCI Bridge Resources
//
UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 MemoryThermalManagement;
UINT8 ExttsViaTsOnBoard;
UINT8 ExttsViaTsOnDimm;
UINT8 FixupPlatformSpecificSoftstraps;
//
// SMBUS Configuration
//
UINT8 TestSmbusSpdWriteDisable;
//
// HD-Audio Configuration
//
UINT8 PchHdAudio;
UINT8 PchHdAudioDsp;
UINT8 PchHdAudioPme;
UINT8 PchHdAudioIoBufferOwnership;
UINT8 PchHdAudioIoBufferVoltage;
UINT8 PchHdAudioCodecSelect;
UINT8 PchHdAudioFeature[HDAUDIO_FEATURES];
UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
UINT8 RtoHdaVcType;
//
// DMI Configuration
//
UINT8 TestDmiAspmCtrl;
//
//
// PCIe LTR Configuration
//
UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS];
UINT8 PchSataLtrOverride;
UINT8 PchSataLtrEnable;
UINT16 PchSataSnoopLatencyOverrideValue;
UINT8 PchSataSnoopLatencyOverrideMultiplier;
UINT8 PchSataLtrConfigLock;
UINT8 PchSSataLtrOverride;
UINT16 PchSSataSnoopLatencyOverrideValue;
UINT8 PchSSataSnoopLatencyOverrideMultiplier;
UINT8 PchSSataLtrEnable;
UINT8 PchSSataLtrConfigLock;
UINT8 PchPcieUX16CompletionTimeout;
UINT8 PchPcieUX8CompletionTimeout;
//
// Interrupt Configuration
//
UINT8 PchIoApic24119Entries;
//
// DPTF SETUP items begin
//
UINT8 EnableDptf;
UINT8 EnablePchDevice;
//
// CPU
//
UINT8 DebugDciEnable;
UINT8 DebugInterfaceEnable;
//
// Miscellaneous options
//
UINT8 OsDebugPort;
UINT8 SlpLanLowDc;
UINT8 PchLanK1Off;
UINT8 PchWakeOnWlan;
UINT8 PchWakeOnWlanDeepSx;
UINT8 StateAfterG3;
UINT8 PciePllSsc;
UINT8 FirmwareConfiguration;
UINT8 PchDciEn;
UINT8 PchDciAutoDetect;
// Acpi.sd
UINT8 CSNotifyEC;
UINT8 EcLowPowerMode;
//
// TraceHub Setup Options
//
UINT8 TraceHubEnableMode;
UINT8 MemRegion0BufferSize;
UINT8 MemRegion1BufferSize;
//
// PCH P2SB hide and lock options
//
UINT8 PchP2sbDevReveal;
UINT8 PchP2sbUnlock;
//
// PCH SPI hide and lock options
//
UINT8 FlashLockDown;
//
// PCH PMC option
//
UINT8 PmcReadDisable;
//
// ADR Configuration
//
UINT8 PchAdrEn;
UINT8 AdrTimerEn;
UINT8 AdrTimerVal;
UINT8 AdrMultiplierVal;
UINT8 AdrGpioSel;
UINT8 AdrHostPartitionReset;
//
// Audio DSP Configuration
//
UINT8 PchAudioDsp;
UINT8 PchAudioDspD3PowerGating;
UINT8 PchAudioDspAcpiMode;
UINT8 PchAudioDspBluetooth;
UINT8 PchAudioDspAcpiInterruptMode;
//
// Miscellaneous options
//
UINT8 PchEvaMrom0HookEnable;
UINT8 PchEvaMrom1HookEnable;
UINT8 TestMctpBroadcastCycle;
UINT8 PchEvaLockDown;
UINT8 PchTraceHubHide;
} PCH_RC_CONFIGURATION;
#pragma pack()
#endif
|
