1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
|
/** @file
Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/ArmLib.h>
#include <Guid/ArmMpCoreInfo.h>
#include <Ppi/IscpPpi.h>
#include <Iscp.h>
/*----------------------------------------------------------------------------------------
* G L O B A L S
*----------------------------------------------------------------------------------------
*/
//
// CoreInfo table
//
STATIC ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
},
{
// Cluster 0, Core 1
0x0, 0x1,
},
{
// Cluster 1, Core 0
0x1, 0x0,
},
{
// Cluster 1, Core 1
0x1, 0x1,
},
{
// Cluster 2, Core 0
0x2, 0x0,
},
{
// Cluster 2, Core 1
0x2, 0x1,
},
{
// Cluster 3, Core 0
0x3, 0x0,
},
{
// Cluster 3, Core 1
0x3, 0x1,
}
};
//
// Core count
//
STATIC UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
/*----------------------------------------------------------------------------------------
* P P I L I S T
*----------------------------------------------------------------------------------------
*/
STATIC EFI_PEI_ISCP_PPI *PeiIscpPpi;
/*----------------------------------------------------------------------------------------
* P P I D E S C R I P T O R
*----------------------------------------------------------------------------------------
*/
STATIC EFI_PEI_PPI_DESCRIPTOR mPlatInitPpiDescriptor =
{
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gAmdStyxPlatInitPpiGuid,
NULL
};
/**
*---------------------------------------------------------------------------------------
* PlatInitPeiEntryPoint
*
* Description:
* Entry point of the PlatInit PEI module.
*
* Control flow:
* Query platform parameters via ISCP.
*
* Parameters:
* @param[in] FfsHeader EFI_PEI_FILE_HANDLE
* @param[in] **PeiServices Pointer to the PEI Services Table.
*
* @return EFI_STATUS
*
*---------------------------------------------------------------------------------------
*/
EFI_STATUS
EFIAPI
PlatInitPeiEntryPoint (
IN EFI_PEI_FILE_HANDLE FfsHeader,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status = EFI_SUCCESS;
AMD_MEMORY_RANGE_DESCRIPTOR IscpMemDescriptor = {0};
ISCP_FUSE_INFO IscpFuseInfo = {0};
ISCP_CPU_RESET_INFO CpuResetInfo = {0};
#if DO_XGBE == 1
ISCP_MAC_INFO MacAddrInfo = {0};
UINT64 MacAddr0, MacAddr1;
#endif
UINTN CpuCoreCount, CpuMap, CpuMapSize;
UINTN Index, CoreNum;
UINT32 *CpuIdReg = (UINT32 *)FixedPcdGet32 (PcdCpuIdRegister);
DEBUG ((EFI_D_ERROR, "PlatInit PEIM Loaded\n"));
// CPUID
PcdSet32 (PcdSocCpuId, *CpuIdReg);
DEBUG ((EFI_D_ERROR, "SocCpuId = 0x%X\n", PcdGet32 (PcdSocCpuId)));
// Update core count based on PCD option
if (mAmdCoreCount > PcdGet32 (PcdSocCoreCount)) {
mAmdCoreCount = PcdGet32 (PcdSocCoreCount);
}
if (FixedPcdGetBool (PcdIscpSupport)) {
Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi);
ASSERT_EFI_ERROR (Status);
// Get fuse information from ISCP
Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo);
ASSERT_EFI_ERROR (Status);
CpuMap = IscpFuseInfo.SocConfiguration.CpuMap;
CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount;
CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8;
ASSERT (CpuMap != 0);
ASSERT (CpuCoreCount != 0);
ASSERT (CpuCoreCount <= CpuMapSize);
// Update core count based on fusing
if (mAmdCoreCount > CpuCoreCount) {
mAmdCoreCount = CpuCoreCount;
}
}
//
// Update per-core information from ISCP
//
if (!FixedPcdGetBool (PcdIscpSupport)) {
DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n"));
} else {
//
// Walk CPU map to enumerate active cores
//
for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) {
if (CpuMap & 1) {
CpuResetInfo.CoreNum = CoreNum;
Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction (
PeiServices, &CpuResetInfo );
ASSERT_EFI_ERROR (Status);
ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED);
ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED);
mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n",
Index, mAmdMpCoreInfoTable[Index].ClusterId,
mAmdMpCoreInfoTable[Index].CoreId));
// Next core in Table
++Index;
}
// Next core in Map
CpuMap >>= 1;
}
// Update core count based on CPU map
if (mAmdCoreCount > Index) {
mAmdCoreCount = Index;
}
}
// Update SocCoreCount on Dynamic PCD
if (PcdGet32 (PcdSocCoreCount) != mAmdCoreCount) {
PcdSet32 (PcdSocCoreCount, mAmdCoreCount);
}
DEBUG ((EFI_D_ERROR, "SocCoreCount = %d\n", PcdGet32 (PcdSocCoreCount)));
// Build AmdMpCoreInfo HOB
BuildGuidDataHob (&gAmdStyxMpCoreInfoGuid, mAmdMpCoreInfoTable, sizeof (ARM_CORE_INFO) * mAmdCoreCount);
// Get SystemMemorySize from ISCP
IscpMemDescriptor.Size0 = 0;
if (FixedPcdGetBool (PcdIscpSupport)) {
Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor);
ASSERT_EFI_ERROR (Status);
// Update SystemMemorySize on Dynamic PCD
if (IscpMemDescriptor.Size0) {
PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0);
}
}
if (IscpMemDescriptor.Size0 == 0) {
DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n"));
}
DEBUG ((EFI_D_ERROR, "SystemMemorySize = %ld\n", PcdGet64 (PcdSystemMemorySize)));
#if DO_XGBE == 1
// Get MAC Address from ISCP
if (FixedPcdGetBool (PcdIscpSupport)) {
Status = PeiIscpPpi->ExecuteGetMacAddressTransaction (
PeiServices, &MacAddrInfo );
ASSERT_EFI_ERROR (Status);
MacAddr0 = MacAddr1 = 0;
for (Index = 0; Index < 6; ++Index) {
MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8);
MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8);
}
PcdSet64 (PcdEthMacA, MacAddr0);
PcdSet64 (PcdEthMacB, MacAddr1);
}
DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA)));
DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB)));
#endif
// Let other PEI modules know we're done!
Status = (*PeiServices)->InstallPpi (PeiServices, &mPlatInitPpiDescriptor);
ASSERT_EFI_ERROR (Status);
return Status;
}
|
