1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
/** @file
Intel Processor Power Management ACPI Code.
Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuPowerMgmt.h"
DefinitionBlock (
"CPU0CST.aml",
"SSDT",
2,
"PmRef",
"Cpu0Cst",
0x3001
)
{
External(\_PR.CPU0, DeviceObj)
External(PWRS)
External(\_PR.CFGD, IntObj)
External(PDC0)
External(FMBL)
External(FEMD)
External(PFLV)
External(C3MW) // Mwait Hint value for C3
External(C6MW) // Mwait Hint value for C6
External(C7MW) // Mwait Hint value for C7
External(CDMW) // Mwait Hint value for C8/C9/C10
External(C3LT) // Latency value for C3
External(C6LT) // Latency Value for C6
External(C7LT) // Latency Value for C7
External(CDLT) // Latency Value for C8/C9/C10
External(CDLV) // IO Level value for C8/C9/C10
External(CDPW) // Power value for C8/C9/C10
External(MWEN)
External(BDID)
External(BTDT)
External(BTMB)
Scope(\_PR.CPU0)
{
Method (_CST, 0)
{
If (LEqual(MWEN, 0)) {
Return( Package()
{
3,
Package()
{ // C1, LVT
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
1,
1,
1000
},
Package()
{
// C6L, LVT
ResourceTemplate(){Register(SystemIO, 8, 0, 0x415)},
2,
50,
10
},
Package()
{
// C10, LVT
ResourceTemplate(){Register(SystemIO, 8, 0, 0x419)},
3,
150, //Pre-silicon setting, 11 ms for worst-case exit latency
10
}
})
}
Return( Package()
{
3,
Package()
{ // C1, MWAIT
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x01, 1)},
1,
1,
1000
},
Package()
{
// C6L, MWAIT Extension
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x21, 1)},
2,
50,
10
},
Package()
{
// C10, MWAIT Extension
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x60, 1)},
3,
150, //Pre-silicon setting, 11 ms for worst-case exit latency
10
}
})
}
}
}
|
