blob: aa561e929ca357a743230607620f6de1dc751e90 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
|
/** @file
*
* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
* Copyright (c) 2015, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef _I2C_HW_H_
#define _I2C_HW_H_
#include <Uefi.h>
#include <Library/IoLib.h>
#define I2C_READ_TIMEOUT 500
#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
#define I2C_DRV_ONCE_READ_BYTES_NUM 8
#define I2C_READ_SIGNAL 0x0100
#define I2C_TXRX_THRESHOLD 0x7
#define I2C_SS_SCLHCNT 0x493
#define I2C_SS_SCLLCNT 0x4fe
#define I2C_CMD_STOP_BIT BIT9
#define I2C_REG_WRITE(reg,data) \
MmioWrite32 ((reg), (data))
#define I2C_REG_READ(reg,result) \
(result) = MmioRead32 ((reg))
#define I2C_CON_OFFSET 0x0
#define I2C_TAR_OFFSET 0x4
#define I2C_SAR_OFFSET 0x8
#define I2C_DATA_CMD_OFFSET 0x10
#define I2C_SS_SCL_HCNT_OFFSET 0x14
#define I2C_SS_SCL_LCNT_OFFSET 0x18
#define I2C_FS_SCL_HCNT_OFFSET 0x1c
#define I2C_FS_SCL_LCNT_OFFSET 0x20
#define I2C_INTR_STAT_OFFSET 0x2c
#define I2C_INTR_MASK_OFFSET 0x30
#define I2C_RAW_INTR_STAT_OFFSET 0x34
#define I2C_RX_TL_OFFSET 0x38
#define I2C_TX_TL_OFFSET 0x3c
#define I2C_CLR_INTR_OFFSET 0x40
#define I2C_CLR_RX_UNDER_OFFSET 0x44
#define I2C_CLR_RX_OVER_OFFSET 0x48
#define I2C_CLR_TX_OVER_OFFSET 0x4c
#define I2C_CLR_RD_REQ_OFFSET 0x50
#define I2C_CLR_TX_ABRT_OFFSET 0x54
#define I2C_CLR_RX_DONE_OFFSET 0x58
#define I2C_CLR_ACTIVITY_OFFSET 0x5c
#define I2C_CLR_STOP_DET_OFFSET 0x60
#define I2C_CLR_START_DET_OFFSET 0x64
#define I2C_CLR_GEN_CALL_OFFSET 0x68
#define I2C_ENABLE_OFFSET 0x6c
#define I2C_STATUS_OFFSET 0x70
#define I2C_TXFLR_OFFSET 0x74
#define I2C_RXFLR_OFFSET 0x78
#define I2C_SDA_HOLD 0x7c
#define I2C_TX_ABRT_SOURCE_OFFSET 0x80
#define I2C_SLV_DATA_ONLY_OFFSET 0x84
#define I2C_DMA_CR_OFFSET 0x88
#define I2C_DMA_TDLR_OFFSET 0x8c
#define I2C_DMA_RDLR_OFFSET 0x90
#define I2C_SDA_SETUP_OFFSET 0x94
#define I2C_ACK_GENERAL_CALL_OFFSET 0x98
#define I2C_ENABLE_STATUS_OFFSET 0x9c
typedef union tagI2c0Con
{
struct
{
UINT32 master : 1 ;
UINT32 spedd : 2 ;
UINT32 slave_10bit : 1 ;
UINT32 master_10bit : 1 ;
UINT32 restart_en : 1 ;
UINT32 slave_disable : 1 ;
UINT32 Reserved_0 : 25 ;
} bits;
UINT32 Val32;
} I2C0_CON_U;
typedef union tagI2c0Tar
{
struct
{
UINT32 ic_tar : 10 ;
UINT32 gc_or_start : 1 ;
UINT32 special : 1 ;
UINT32 ic_10bitaddr_master : 1 ;
UINT32 Reserved_1 : 19 ;
} bits;
UINT32 Val32;
} I2C0_TAR_U;
typedef union tagI2c0DataCmd
{
struct
{
UINT32 dat : 8 ;
UINT32 cmd : 1 ;
UINT32 Reserved_5 : 23 ;
} bits;
UINT32 Val32;
} I2C0_DATA_CMD_U;
typedef union tagI2c0SsSclHcnt
{
struct
{
UINT32 ic_ss_scl_hcnt : 16 ;
UINT32 Reserved_7 : 16 ;
} bits;
UINT32 Val32;
} I2C0_SS_SCL_HCNT_U;
typedef union tagI2c0SsSclLcnt
{
struct
{
UINT32 ic_ss_scl_lcnt : 16 ;
UINT32 Reserved_9 : 16 ;
} bits;
UINT32 Val32;
} I2C0_SS_SCL_LCNT_U;
typedef union tagI2c0FsSclHcnt
{
struct
{
UINT32 ic_fs_scl_hcnt : 16 ;
UINT32 Reserved_11 : 16 ;
} bits;
UINT32 Val32;
} I2C0_FS_SCL_HCNT_U;
typedef union tagI2c0FsSclLcnt
{
struct
{
UINT32 ic_fs_scl_lcnt : 16 ;
UINT32 Reserved_13 : 16 ;
} bits;
UINT32 Val32;
} I2C0_FS_SCL_LCNT_U;
typedef union tagI2c0IntrMask
{
struct
{
UINT32 m_rx_under : 1 ;
UINT32 m_rx_over : 1 ;
UINT32 m_rx_full : 1 ;
UINT32 m_tx_over : 1 ;
UINT32 m_tx_empty : 1 ;
UINT32 m_rd_req : 1 ;
UINT32 m_tx_abrt : 1 ;
UINT32 m_rx_done : 1 ;
UINT32 m_activity : 1 ;
UINT32 m_stop_det : 1 ;
UINT32 m_start_det : 1 ;
UINT32 m_gen_call : 1 ;
UINT32 Reserved_17 : 20 ;
} bits;
UINT32 Val32;
} I2C0_INTR_MASK_U;
typedef union tagI2c0RxTl
{
struct
{
UINT32 rx_tl : 8 ;
UINT32 Reserved_21 : 24 ;
} bits;
UINT32 Val32;
} I2C0_RX_TL_U;
typedef union tagI2c0TxTl
{
struct
{
UINT32 tx_tl : 8 ;
UINT32 Reserved_23 : 24 ;
} bits;
UINT32 Val32;
} I2C0_TX_TL_U;
typedef union tagI2c0Enable
{
struct
{
UINT32 enable : 1 ;
UINT32 Reserved_47 : 31 ;
} bits;
UINT32 Val32;
} I2C0_ENABLE_U;
typedef union tagI2c0Status
{
struct
{
UINT32 activity : 1 ;
UINT32 tfnf : 1 ;
UINT32 tfe : 1 ;
UINT32 rfne : 1 ;
UINT32 rff : 1 ;
UINT32 mst_activity : 1 ;
UINT32 slv_activity : 1 ;
UINT32 Reserved_49 : 25 ;
} bits;
UINT32 Val32;
} I2C0_STATUS_U;
typedef union tagI2c0Txflr
{
struct
{
UINT32 txflr : 4 ;
UINT32 Reserved_51 : 28 ;
} bits;
UINT32 Val32;
} I2C0_TXFLR_U;
typedef union tagI2c0Rxflr
{
struct
{
UINT32 rxflr : 4 ;
UINT32 Reserved_53 : 28 ;
} bits;
UINT32 Val32;
} I2C0_RXFLR_U;
typedef union tagI2c0EnableStatus
{
struct
{
UINT32 ic_en : 1 ;
UINT32 slv_disable_while_busy: 1 ;
UINT32 slv_rx_data_lost : 1 ;
UINT32 Reserved_69 : 29 ;
} bits;
UINT32 Val32;
} I2C0_ENABLE_STATUS_U;
#endif
|
