1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
|
/** @file
C based implemention of IA32 interrupt handling only
requiring a minimal assembly interrupt entry point.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "CpuDxe.h"
#include "CpuGdt.h"
//
// Global descriptor table (GDT) Template
//
STATIC GDT_ENTRIES GdtTemplate = {
//
// NULL_SEL
//
{
0x0, // limit 15:0
0x0, // base 15:0
0x0, // base 23:16
0x0, // type
0x0, // limit 19:16, flags
0x0, // base 31:24
},
//
// LINEAR_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_DATA_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x092, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// SYS_CODE_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09A, // present, ring 0, data, expand-up, writable
0x0CF, // page-granular, 32-bit
0x0,
},
//
// LINEAR_CODE64_SEL
//
{
0x0FFFF, // limit 0xFFFFF
0x0, // base 0
0x0,
0x09B, // present, ring 0, code, expand-up, writable
0x0AF, // LimitHigh (CS.L=1, CS.D=0)
0x0, // base (high)
},
//
// SPARE4_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
//
// SPARE5_SEL
//
{
0x0, // limit 0
0x0, // base 0
0x0,
0x0, // present, ring 0, data, expand-up, writable
0x0, // page-granular, 32-bit
0x0,
},
};
/**
Initialize Global Descriptor Table.
**/
VOID
InitGlobalDescriptorTable (
VOID
)
{
GDT_ENTRIES *gdt;
IA32_DESCRIPTOR gdtPtr;
//
// Allocate Runtime Data for the GDT
//
gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
ASSERT (gdt != NULL);
gdt = ALIGN_POINTER (gdt, 8);
//
// Initialize all GDT entries
//
CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
//
// Write GDT register
//
gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
AsmWriteGdtr (&gdtPtr);
//
// Update selector (segment) registers base on new GDT
//
SetCodeSelector ((UINT16)CPU_CODE_SEL);
SetDataSelectors ((UINT16)CPU_DATA_SEL);
}
|
