1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
|
TITLE Cpu.asm: Assembly code for the x64 resources
;
; This file contains an 'Intel Sample Driver' and is
; licensed for Intel CPUs and chipsets under the terms of your
; license agreement with Intel or your vendor. This file may
; be modified by the user, subject to additional terms of the
; license agreement
;
;
; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
;
; This program and the accompanying materials are licensed and made available under
; the terms and conditions of the BSD License that accompanies this distribution.
; The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;
;
;
;
;* Module Name:
;*
;* Cpu.asm
;*
;* Abstract:
;*
;------------------------------------------------------------------------------
text SEGMENT
;------------------------------------------------------------------------------
; VOID
; EfiHalt (
; VOID
; )
;------------------------------------------------------------------------------
EfiHalt PROC PUBLIC
hlt
ret
EfiHalt ENDP
;------------------------------------------------------------------------------
; VOID
; EfiWbinvd (
; VOID
; )
;------------------------------------------------------------------------------
EfiWbinvd PROC PUBLIC
wbinvd
ret
EfiWbinvd ENDP
;------------------------------------------------------------------------------
; VOID
; EfiInvd (
; VOID
; )
;------------------------------------------------------------------------------
EfiInvd PROC PUBLIC
invd
ret
EfiInvd ENDP
;------------------------------------------------------------------------------
; VOID
; EfiCpuid (
; IN UINT32 RegisterInEax, // rcx
; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
; )
;------------------------------------------------------------------------------
EfiCpuid PROC PUBLIC
push rbx
mov r8, rdx ; r8 = *Reg
mov rax, rcx ; RegisterInEax
cpuid
cmp r8, 0
je _Exit
mov [r8 + 0], eax ; Reg->RegEax
mov [r8 + 4], ebx ; Reg->RegEbx
mov [r8 + 8], ecx ; Reg->RegEcx
mov [r8 + 12], edx ; Reg->RegEdx
_Exit:
pop rbx
ret
EfiCpuid ENDP
;------------------------------------------------------------------------------
; UINT64
; EfiReadMsr (
; IN UINT32 Index, // rcx
; )
;------------------------------------------------------------------------------
EfiReadMsr PROC PUBLIC
rdmsr
sal rdx, 32 ; edx:eax -> rax
or rax, rdx ; rax = edx:eax
ret
EfiReadMsr ENDP
;------------------------------------------------------------------------------
; VOID
; EfiWriteMsr (
; IN UINT32 Index, // rcx
; IN UINT64 Value // rdx
; )
;------------------------------------------------------------------------------
EfiWriteMsr PROC PUBLIC
mov rax, rdx ; rdx = Value
sar rdx, 32 ; convert rdx to edx upper 32-bits
wrmsr ; wrmsr[ecx] result = edx:eax
ret
EfiWriteMsr ENDP
;------------------------------------------------------------------------------
; UINT64
; EfiReadTsc (
; VOID
; );
;------------------------------------------------------------------------------
EfiReadTsc PROC PUBLIC
rdtsc
shl rax, 32
shrd rax, rdx, 32
ret
EfiReadTsc ENDP
;------------------------------------------------------------------------------
; VOID
; EfiDisableCache (
; VOID
; );
;------------------------------------------------------------------------------
EfiDisableCache PROC PUBLIC
; added a check to see if cache is already disabled. If it is, then skip.
mov rax, cr0
and rax, 060000000h
cmp rax, 0
jne @f
mov rax, cr0
or rax, 060000000h
mov cr0, rax
wbinvd
@@:
ret
EfiDisableCache ENDP
;------------------------------------------------------------------------------
; VOID
; EfiEnableCache (
; VOID
; );
;------------------------------------------------------------------------------
EfiEnableCache PROC PUBLIC
wbinvd
mov rax, cr0
and rax, 09fffffffh
mov cr0, rax
ret
EfiEnableCache ENDP
;------------------------------------------------------------------------------
; UINTN
; EfiGetEflags (
; VOID
; );
;------------------------------------------------------------------------------
EfiGetEflags PROC PUBLIC
pushfq
pop rax
ret
EfiGetEflags ENDP
;------------------------------------------------------------------------------
; VOID
; EfiDisableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
EfiDisableInterrupts PROC PUBLIC
cli
ret
EfiDisableInterrupts ENDP
;------------------------------------------------------------------------------
; VOID
; EfiEnableInterrupts (
; VOID
; );
;------------------------------------------------------------------------------
EfiEnableInterrupts PROC PUBLIC
sti
ret
EfiEnableInterrupts ENDP
;------------------------------------------------------------------------------
; VOID
; EfiCpuidExt (
; IN UINT32 RegisterInEax,
; IN UINT32 CacheLevel,
; OUT EFI_CPUID_REGISTER *Regs
; )
;------------------------------------------------------------------------------
EfiCpuidExt PROC PUBLIC
push rbx
mov rax, rcx ; rax = RegisterInEax
mov rcx, rdx ; rcx = CacheLevel
cpuid
mov [r8 + 0 ], eax ; Reg->RegEax
mov [r8 + 4 ], ebx ; Reg->RegEbx
mov [r8 + 8 ], ecx ; Reg->RegEcx
mov [r8 + 12], edx ; Reg->RegEdx
pop rbx
ret
EfiCpuidExt ENDP
END
|
