diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-07-11 10:39:56 +0100 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-07-11 10:39:56 +0100 |
commit | f471cc22f0311fb12ae64236e56a6157ac40db06 (patch) | |
tree | cb155a9a0f96a230f54cb23c6e9155c8bb40eba4 | |
parent | 30cae3c21306b3942256e91a34525f9b83f99c3a (diff) | |
download | gem5-f471cc22f0311fb12ae64236e56a6157ac40db06.tar.xz |
arm: Don't consult the TLB test iface for functional translations
Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.
Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
-rw-r--r-- | src/arch/arm/isa.cc | 4 | ||||
-rw-r--r-- | src/arch/arm/tlb.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d3286a6b0..0b753087e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1520,7 +1520,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - Request req(0, val, 1, flags, Request::funcMasterId, + Request req(0, val, 0, flags, Request::funcMasterId, tc->pcState().pc(), tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); @@ -1765,7 +1765,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - req->setVirt(0, val, 1, flags, Request::funcMasterId, + req->setVirt(0, val, 0, flags, Request::funcMasterId, tc->pcState().pc()); req->setContext(tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f4d51546c..a499900e0 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1423,7 +1423,7 @@ TLB::setTestInterface(SimObject *_ti) Fault TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) { - if (!test) { + if (!test || !req->hasSize() || req->getSize() == 0) { return NoFault; } else { return test->translationCheck(req, isPriv, mode, domain); |