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authorGabe Black <gblack@eecs.umich.edu>2006-10-27 01:36:42 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-27 01:36:42 -0400
commit944bfde6b34a27f2438e38f7d870532ed6c0447a (patch)
tree7683a5edcdf350710c601ea441e37b678942e285
parent2cb190d1e3854f3d82b88ccd9b6b6365b87c331d (diff)
downloadgem5-944bfde6b34a27f2438e38f7d870532ed6c0447a.tar.xz
Clean up MiscRegFile
--HG-- extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
-rw-r--r--src/arch/sparc/miscregfile.cc65
-rw-r--r--src/arch/sparc/miscregfile.hh28
2 files changed, 11 insertions, 82 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index ada3c18e7..bf4572878 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -202,78 +202,27 @@ MiscReg MiscRegFile::readReg(int miscReg)
}
}
-MiscReg MiscRegFile::readRegWithEffect(int miscReg,
- Fault &fault, ThreadContext * tc)
+MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
{
- fault = NoFault;
switch (miscReg) {
- case MISCREG_Y:
- case MISCREG_CCR:
- case MISCREG_ASI:
- return readReg(miscReg);
-
case MISCREG_TICK:
case MISCREG_PRIVTICK:
- // Check for reading privilege
- if (tickFields.npt && !isNonPriv()) {
- fault = new PrivilegedAction;
- return 0;
- }
return tc->getCpuPtr()->curCycle() - tickFields.counter |
tickFields.npt << 63;
case MISCREG_FPRS:
- fault = new UnimpFault("FPU not implemented\n");
- return 0;
+ panic("FPU not implemented\n");
case MISCREG_PCR:
- fault = new UnimpFault("Performance Instrumentation not impl\n");
- return 0;
case MISCREG_PIC:
- fault = new UnimpFault("Performance Instrumentation not impl\n");
- return 0;
- case MISCREG_GSR:
- return readReg(miscReg);
-
- /** Privilged Registers */
- case MISCREG_TPC:
- case MISCREG_TNPC:
- case MISCREG_TSTATE:
- case MISCREG_TT:
- if (tl == 0) {
- fault = new IllegalInstruction;
- return 0;
- } // NOTE THE FALL THROUGH!
- case MISCREG_PSTATE:
- case MISCREG_TL:
- return readReg(miscReg);
-
- case MISCREG_TBA:
- return readReg(miscReg) & ULL(~0x7FFF);
-
- case MISCREG_PIL:
-
- case MISCREG_CWP:
- case MISCREG_CANSAVE:
- case MISCREG_CANRESTORE:
- case MISCREG_CLEANWIN:
- case MISCREG_OTHERWIN:
- case MISCREG_WSTATE:
- case MISCREG_GL:
- return readReg(miscReg);
+ panic("Performance Instrumentation not impl\n");
/** Floating Point Status Register */
case MISCREG_FSR:
panic("Floating Point not implemented\n");
- default:
-#if FULL_SYSTEM
- return readFSRegWithEffect(miscReg, fault, tc);
-#else
- fault = new IllegalInstruction;
- return 0;
-#endif
}
+ return readReg(miscReg);
}
-Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
+void MiscRegFile::setReg(int miscReg, const MiscReg &val)
{
switch (miscReg) {
case MISCREG_Y:
@@ -386,10 +335,9 @@ Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
default:
panic("Miscellaneous register %d not implemented\n", miscReg);
}
- return NoFault;
}
-Fault MiscRegFile::setRegWithEffect(int miscReg,
+void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
const uint64_t Bit64 = (1ULL << 63);
@@ -412,7 +360,6 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
break;
}
setReg(miscReg, val);
- return NoFault;
}
void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 0d81dae1e..771cb1ed6 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -365,31 +365,13 @@ namespace SparcISA
reset();
}
- /** read a value out of an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial. */
MiscReg readReg(int miscReg);
- /** Read a value from an IPR. Only the SE iprs are here and the rest
- * are are readFSRegWithEffect (which is called by readRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
-
- /** write a value into an either an SE or FS IPR. No checking is done
- * about SE vs. FS as this is mostly used to copy the regfile. Thus more
- * register are copied that are necessary for FS. However this prevents
- * a bunch of ifdefs and is rarely called so is not performance
- * criticial.*/
- Fault setReg(int miscReg, const MiscReg &val);
-
- /** Write a value into an IPR. Only the SE iprs are here and the rest
- * are are setFSRegWithEffect (which is called by setRegWithEffect()).
- * Checking is done for permission based on state bits in the miscreg
- * file. */
- Fault setRegWithEffect(int miscReg,
+ MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+
+ void setReg(int miscReg, const MiscReg &val);
+
+ void setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc);
void serialize(std::ostream & os);