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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit36eeee013339141994ef3091c4b3726d08395f04 (patch)
tree61fa325b9e9ff2b3275cb262b669d8450a9161b8
parent68f2908a70ae2582804fc9c6bb19d60e7d321324 (diff)
downloadgem5-36eeee013339141994ef3091c4b3726d08395f04.tar.xz
ARM: When changing the CPSR and branching, make sure the branch is second.
-rw-r--r--src/arch/arm/isa/operands.isa78
1 files changed, 39 insertions, 39 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f3534385..1a98a9087 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -88,72 +88,72 @@ let {{
def operands {{
#Abstracted integer reg operands
- 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
+ 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0,
+ 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
+ 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite),
- 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
+ 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeAIWPCWrite),
- 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
- 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
+ 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
+ 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
+ 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
- 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
+ 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
+ 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
+ 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
+ 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
+ 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7,
+ 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8,
+ 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
- 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9,
+ 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
maybePCRead, maybePCWrite),
#General Purpose Integer Reg Operands
- 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
+ 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
- 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
- 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
- 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
- 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
+ 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
+ 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
+ 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
+ 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
- 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
- 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
+ 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
+ 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
#Register fields for microops
- 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
- 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11,
+ 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
+ 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite),
- 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
- 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
+ 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
+ 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
#General Purpose Floating Point Reg Operands
- 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
- 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
- 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
+ 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
+ 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
+ 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
+ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
- 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
- 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
- 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
- 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
- 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
- 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
- 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
+ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
+ 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
+ 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
+ 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
+ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
+ 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeNPC),
- 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
+ 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, forceNPC),
- 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
+ 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeIWNPC),
}};