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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commit3a11412c995f462b9fc7eb7b688cb7d7e0011680 (patch)
treeded66c89f8515b41b7d83ec6de469b0a3e722d83
parentd5aee75efe68c37224eebb0c2f8e1c5fa3ba0d1e (diff)
downloadgem5-3a11412c995f462b9fc7eb7b688cb7d7e0011680.tar.xz
ARM: Add an fp version of one of the microop indexed registers.
-rw-r--r--src/arch/arm/isa/operands.isa1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index d80c0c712..84bd81ca0 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -114,6 +114,7 @@ def operands {{
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
+ 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
#General Purpose Floating Point Reg Operands