arm: Stop using the FloatReg and FloatRegBits types.

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

8 files changed, 62 insertions, 65 deletions

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 591f9fd79..eef2dfe27 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -563,8 +563,8 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst,
 
     unsigned eBytes = (1 << size);
     unsigned loadSize = eBytes * elems;
-    unsigned loadRegs M5_VAR_USED = (loadSize + sizeof(FloatRegBits) - 1) /
-                        sizeof(FloatRegBits);
+    unsigned loadRegs M5_VAR_USED =
+        (loadSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
 
     assert(loadRegs > 0 && loadRegs <= 4);
 
@@ -927,8 +927,8 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst,
 
     unsigned eBytes = (1 << size);
     unsigned storeSize = eBytes * elems;
-    unsigned storeRegs M5_VAR_USED = (storeSize + sizeof(FloatRegBits) - 1) /
-                         sizeof(FloatRegBits);
+    unsigned storeRegs M5_VAR_USED =
+        (storeSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
 
     assert(storeRegs > 0 && storeRegs <= 4);
 
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 6a33d1b9f..4bd3a2584 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -323,10 +323,10 @@ let {{
         microDeintNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
             const unsigned regs = 2 * dRegs;
-            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
-                                     sizeof(Element);
+            const unsigned perDReg =
+                (2 * sizeof(uint32_t)) / sizeof(Element);
             union convStruct {
-                FloatRegBits cRegs[regs];
+                uint32_t cRegs[regs];
                 Element elements[dRegs * perDReg];
             } conv1, conv2;
 
@@ -369,10 +369,10 @@ let {{
         microInterNeonCode = '''
             const unsigned dRegs = %(dRegs)d;
             const unsigned regs = 2 * dRegs;
-            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
-                                     sizeof(Element);
+            const unsigned perDReg =
+                (2 * sizeof(uint32_t)) / sizeof(Element);
             union convStruct {
-                FloatRegBits cRegs[regs];
+                uint32_t cRegs[regs];
                 Element elements[dRegs * perDReg];
             } conv1, conv2;
 
@@ -442,16 +442,15 @@ let {{
                     FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackNeonCode = '''
-            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
-                                     sizeof(Element);
+            const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
 
             union SourceRegs {
-                FloatRegBits fRegs[2 * %(sRegs)d];
+                uint32_t fRegs[2 * %(sRegs)d];
                 Element elements[%(sRegs)d * perDReg];
             } sourceRegs;
 
             union DestReg {
-                FloatRegBits fRegs[2];
+                uint32_t fRegs[2];
                 Element elements[perDReg];
             } destRegs[%(dRegs)d];
 
@@ -492,16 +491,15 @@ let {{
                     FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
                 ''' % { "reg" : reg }
             microUnpackAllNeonCode = '''
-            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
-                                     sizeof(Element);
+            const unsigned perDReg = (2 * sizeof(uint32_t)) / sizeof(Element);
 
             union SourceRegs {
-                FloatRegBits fRegs[2 * %(sRegs)d];
+                uint32_t fRegs[2 * %(sRegs)d];
                 Element elements[%(sRegs)d * perDReg];
             } sourceRegs;
 
             union DestReg {
-                FloatRegBits fRegs[2];
+                uint32_t fRegs[2];
                 Element elements[perDReg];
             } destRegs[%(dRegs)d];
 
@@ -543,16 +541,16 @@ let {{
                     sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw);
                 ''' % { "reg" : reg }
             microPackNeonCode = '''
-            const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
-                                     sizeof(Element);
+            const unsigned perDReg =
+                (2 * sizeof(uint32_t)) / sizeof(Element);
 
             union SourceReg {
-                FloatRegBits fRegs[2];
+                uint32_t fRegs[2];
                 Element elements[perDReg];
             } sourceRegs[%(sRegs)d];
 
             union DestRegs {
-                FloatRegBits fRegs[2 * %(dRegs)d];
+                uint32_t fRegs[2 * %(dRegs)d];
                 Element elements[%(dRegs)d * perDReg];
             } destRegs;
 
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 64419e46a..1e0c1164f 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1196,7 +1196,7 @@ let {{
                             readDest=False, pairwise=False, toInt=False):
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
-        typedef FloatReg FloatVect[rCount];
+        typedef float FloatVect[rCount];
         FloatVect srcRegs1, srcRegs2;
         '''
         if toInt:
@@ -1220,17 +1220,17 @@ let {{
         readDestCode = ''
         if readDest:
             readDestCode = 'destReg = destRegs[r];'
-        destType = 'FloatReg'
+        destType = 'float'
         writeDest = 'destRegs[r] = destReg;'
         if toInt:
-            destType = 'FloatRegBits'
+            destType = 'uint32_t'
             writeDest = 'destRegs.regs[r] = destReg;'
         if pairwise:
             eWalkCode += '''
             for (unsigned r = 0; r < rCount; r++) {
-                FloatReg srcReg1 = (2 * r < rCount) ?
+                float srcReg1 = (2 * r < rCount) ?
                     srcRegs1[2 * r] : srcRegs2[2 * r - rCount];
-                FloatReg srcReg2 = (2 * r < rCount) ?
+                float srcReg2 = (2 * r < rCount) ?
                     srcRegs1[2 * r + 1] : srcRegs2[2 * r + 1 - rCount];
                 %(destType)s destReg;
                 %(readDest)s
@@ -1244,8 +1244,8 @@ let {{
         else:
             eWalkCode += '''
             for (unsigned r = 0; r < rCount; r++) {
-                FloatReg srcReg1 = srcRegs1[r];
-                FloatReg srcReg2 = srcRegs2[r];
+                float srcReg1 = srcRegs1[r];
+                float srcReg2 = srcRegs2[r];
                 %(destType)s destReg;
                 %(readDest)s
                 %(op)s
@@ -1457,7 +1457,7 @@ let {{
     def twoEqualRegInstFp(name, Name, opClass, types, rCount, op, readDest=False):
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
-        typedef FloatReg FloatVect[rCount];
+        typedef float FloatVect[rCount];
         FloatVect srcRegs1, srcRegs2, destRegs;
         '''
         for reg in range(rCount):
@@ -1478,9 +1478,9 @@ let {{
                                                            mnemonic);
         } else {
             for (unsigned i = 0; i < rCount; i++) {
-                FloatReg srcReg1 = srcRegs1[i];
-                FloatReg srcReg2 = srcRegs2[imm];
-                FloatReg destReg;
+                float srcReg1 = srcRegs1[i];
+                float srcReg2 = srcRegs2[imm];
+                float destReg;
                 %(readDest)s
                 %(op)s
                 destRegs[i] = destReg;
@@ -1525,11 +1525,11 @@ let {{
                 readDestCode = 'destReg = gtoh(destRegs.regs[i]);'
         readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);'
         if fromInt:
-            readOpCode = 'FloatRegBits srcReg1 = gtoh(srcRegs1.regs[i]);'
+            readOpCode = 'uint32_t srcReg1 = gtoh(srcRegs1.regs[i]);'
         declDest = 'Element destElem;'
         writeDestCode = 'destRegs.elements[i] = htog(destElem);'
         if toInt:
-            declDest = 'FloatRegBits destReg;'
+            declDest = 'uint32_t destReg;'
             writeDestCode = 'destRegs.regs[i] = htog(destReg);'
         eWalkCode += '''
         for (unsigned i = 0; i < eCount; i++) {
@@ -1773,7 +1773,7 @@ let {{
             readDest=False, toInt=False):
         global header_output, exec_output
         eWalkCode = simdEnabledCheckCode + '''
-        typedef FloatReg FloatVect[rCount];
+        typedef float FloatVect[rCount];
         FloatVect srcRegs1;
         '''
         if toInt:
@@ -1796,14 +1796,14 @@ let {{
         readDestCode = ''
         if readDest:
             readDestCode = 'destReg = destRegs[i];'
-        destType = 'FloatReg'
+        destType = 'float'
         writeDest = 'destRegs[r] = destReg;'
         if toInt:
-            destType = 'FloatRegBits'
+            destType = 'uint32_t'
             writeDest = 'destRegs.regs[r] = destReg;'
         eWalkCode += '''
         for (unsigned r = 0; r < rCount; r++) {
-            FloatReg srcReg1 = srcRegs1[r];
+            float srcReg1 = srcRegs1[r];
             %(destType)s destReg;
             %(readDest)s
             %(op)s
@@ -3558,7 +3558,7 @@ let {{
     twoRegMiscInst("vcgt", "NVcgtQ", "SimdCmpOp", signedTypes, 4, vcgtCode)
     vcgtfpCode = '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgtFunc,
+        float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgtFunc,
                              true, true, VfpRoundNearest);
         destReg = (res == 0) ? -1 : 0;
         if (res == 2.0)
@@ -3575,7 +3575,7 @@ let {{
     twoRegMiscInst("vcge", "NVcgeQ", "SimdCmpOp", signedTypes, 4, vcgeCode)
     vcgefpCode = '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcgeFunc,
+        float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgeFunc,
                              true, true, VfpRoundNearest);
         destReg = (res == 0) ? -1 : 0;
         if (res == 2.0)
@@ -3592,7 +3592,7 @@ let {{
     twoRegMiscInst("vceq", "NVceqQ", "SimdCmpOp", signedTypes, 4, vceqCode)
     vceqfpCode = '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vceqFunc,
+        float res = binaryOp(fpscr, srcReg1, (float)0.0, vceqFunc,
                              true, true, VfpRoundNearest);
         destReg = (res == 0) ? -1 : 0;
         if (res == 2.0)
@@ -3609,7 +3609,7 @@ let {{
     twoRegMiscInst("vcle", "NVcleQ", "SimdCmpOp", signedTypes, 4, vcleCode)
     vclefpCode = '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcleFunc,
+        float res = binaryOp(fpscr, srcReg1, (float)0.0, vcleFunc,
                              true, true, VfpRoundNearest);
         destReg = (res == 0) ? -1 : 0;
         if (res == 2.0)
@@ -3626,7 +3626,7 @@ let {{
     twoRegMiscInst("vclt", "NVcltQ", "SimdCmpOp", signedTypes, 4, vcltCode)
     vcltfpCode = '''
         FPSCR fpscr = (FPSCR) FpscrExc;
-        float res = binaryOp(fpscr, srcReg1, (FloatReg)0.0, vcltFunc,
+        float res = binaryOp(fpscr, srcReg1, (float)0.0, vcltFunc,
                              true, true, VfpRoundNearest);
         destReg = (res == 0) ? -1 : 0;
         if (res == 2.0)
@@ -3639,7 +3639,7 @@ let {{
             4, vcltfpCode, toInt = True)
 
     vswpCode = '''
-        FloatRegBits mid;
+        uint32_t mid;
         for (unsigned r = 0; r < rCount; r++) {
             mid = srcReg1.regs[r];
             srcReg1.regs[r] = destReg.regs[r];
@@ -3836,13 +3836,13 @@ let {{
             union
             {
                 uint8_t bytes[32];
-                FloatRegBits regs[8];
+                uint32_t regs[8];
             } table;
 
             union
             {
                 uint8_t bytes[8];
-                FloatRegBits regs[2];
+                uint32_t regs[2];
             } destReg, srcReg2;
 
             const unsigned length = %(length)d;
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index eb130dbbd..855952d9e 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -828,13 +828,13 @@ let {{
         union
         {
             uint8_t bytes[64];
-            FloatRegBits regs[16];
+            uint32_t regs[16];
         } table;
 
         union
         {
             uint8_t bytes[%(rCount)d * 4];
-            FloatRegBits regs[%(rCount)d];
+            uint32_t regs[%(rCount)d];
         } destReg, srcReg2;
 
         const unsigned length = %(length)d;
diff --git a/src/arch/arm/isa/templates/crypto.isa b/src/arch/arm/isa/templates/crypto.isa
index 083ef1336..b432e9dfa 100644
--- a/src/arch/arm/isa/templates/crypto.isa
+++ b/src/arch/arm/isa/templates/crypto.isa
@@ -50,7 +50,7 @@ def template CryptoPredOpExecute {{
         const unsigned rCount = %(r_count)d;
 
         union RegVect {
-            FloatRegBits regs[rCount];
+            uint32_t regs[rCount];
         };
 
         if (%(predicate_test)s)
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 35bd3865e..a3a6c1a94 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -216,10 +216,10 @@ def template NeonEqualRegExecute {{
         %(op_rd)s;
 
         const unsigned rCount = %(r_count)d;
-        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
+        const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element);
 
         union RegVect {
-            FloatRegBits regs[rCount];
+            uint32_t regs[rCount];
             Element elements[eCount];
         };
 
@@ -262,16 +262,16 @@ def template NeonUnequalRegExecute {{
         %(op_rd)s;
 
         const unsigned rCount = %(r_count)d;
-        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
+        const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element);
 
         union RegVect {
-            FloatRegBits regs[rCount];
+            uint32_t regs[rCount];
             Element elements[eCount];
             BigElement bigElements[eCount / 2];
         };
 
         union BigRegVect {
-            FloatRegBits regs[2 * rCount];
+            uint32_t regs[2 * rCount];
             BigElement elements[eCount];
         };
 
diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa
index 26e6d98b5..3c36e6bae 100644
--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -180,16 +180,16 @@ def template NeonXEqualRegOpExecute {{
         %(op_rd)s;
 
         const unsigned rCount = %(r_count)d;
-        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
-        const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element);
+        const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element);
+        const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element);
 
         union RegVect {
-            FloatRegBits regs[rCount];
+            uint32_t regs[rCount];
             Element elements[eCount];
         };
 
         union FullRegVect {
-            FloatRegBits regs[4];
+            uint32_t regs[4];
             Element elements[eCountFull];
         };
 
@@ -214,22 +214,22 @@ def template NeonXUnequalRegOpExecute {{
         %(op_rd)s;
 
         const unsigned rCount = %(r_count)d;
-        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
-        const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element);
+        const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element);
+        const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element);
 
         union RegVect {
-            FloatRegBits regs[rCount];
+            uint32_t regs[rCount];
             Element elements[eCount];
             BigElement bigElements[eCount / 2];
         };
 
         union BigRegVect {
-            FloatRegBits regs[2 * rCount];
+            uint32_t regs[2 * rCount];
             BigElement elements[eCount];
         };
 
         union FullRegVect {
-            FloatRegBits regs[4];
+            uint32_t regs[4];
             Element elements[eCountFull];
         };
 
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 209f49efa..bfd447a19 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -96,7 +96,6 @@ union KvmFPReg {
 };
 
 #define FP_REGS_PER_VFP_REG 4
-static_assert(sizeof(FloatRegBits) == 4, "Unexpected float reg size");
 
 const std::vector<ArmV8KvmCPU::IntRegInfo> ArmV8KvmCPU::intRegMap = {
     { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },