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| author | Gabe Black <gabeblack@google.com> | 2018-10-12 23:33:34 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-16 20:25:42 +0000 |
| commit | f4d33283269aec8549027392516771bcc2850f88 (patch) | |
| tree | b502c8481e73053ce919335097b5f0dd2c4a37d7 | |
| parent | 60995026786d7e8000d379c0f47c7ee36b9c2444 (diff) | |
| download | gem5-f4d33283269aec8549027392516771bcc2850f88.tar.xz | |
arm: Make the fp register types 64 bits.
This matches the other ISAs.
Change-Id: I84de91efde2529f4aecc7b26b84266d97459738c
Reviewed-on: https://gem5-review.googlesource.com/c/13622
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
| -rw-r--r-- | src/arch/arm/registers.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index e7defd182..3c675cf77 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -62,8 +62,8 @@ using ArmISAInst::MaxMiscDestRegs; typedef uint64_t IntReg; // floating point register file entry type -typedef uint32_t FloatRegBits; -typedef float FloatReg; +typedef uint64_t FloatRegBits; +typedef double FloatReg; // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = 4; |