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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-27 04:56:10 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-27 04:56:10 -0400 |
| commit | aeffde5ed5007b5ebe330b03156e5cc58c5fe609 (patch) | |
| tree | 9012b0b5bbe3562cd0efff0f6055c3a25ebe847d /configs | |
| parent | cb8856f58059df962652243a9a9c7549571d79fa (diff) | |
| download | gem5-aeffde5ed5007b5ebe330b03156e5cc58c5fe609.tar.xz | |
arm, configs: Do not forward snoops from I cache
This fix simply tells the I cache to not forward snoops to the fetch
unit (since there is really no reason to do so).
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index ae4822a0c..b3607c518 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -150,7 +150,8 @@ class O3_ARM_v7a_ICache(BaseCache): tgts_per_mshr = 8 size = '32kB' assoc = 2 - is_top_level = 'true' + is_top_level = True + forward_snoops = False # Data Cache class O3_ARM_v7a_DCache(BaseCache): @@ -161,7 +162,7 @@ class O3_ARM_v7a_DCache(BaseCache): size = '32kB' assoc = 2 write_buffers = 16 - is_top_level = 'true' + is_top_level = True # TLB Cache # Use a cache as a L2 TLB @@ -173,7 +174,7 @@ class O3_ARM_v7aWalkCache(BaseCache): size = '1kB' assoc = 8 write_buffers = 16 - is_top_level = 'true' + is_top_level = True # L2 Cache @@ -185,7 +186,7 @@ class O3_ARM_v7aL2(BaseCache): size = '1MB' assoc = 16 write_buffers = 8 - prefetch_on_access = 'true' + prefetch_on_access = True # Simple stride prefetcher prefetcher = StridePrefetcher(degree=8, latency = 1) tags = RandomRepl() |