X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.

2 files changed, 16 insertions, 2 deletions

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 075f6d235..c4f91fd9e 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -43,8 +43,14 @@ def config_cache(options, system):
 
     for i in xrange(options.num_cpus):
         if options.caches:
-            system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                  L1Cache(size = '64kB'))
+            if buildEnv['TARGET_ISA'] == 'x86':
+                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                      L1Cache(size = '64kB'),
+                                                      PageTableWalkerCache(),
+                                                      PageTableWalkerCache())
+            else:
+                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                      L1Cache(size = '64kB'))
         if options.l2cache:
             system.cpu[i].connectMemPorts(system.tol2bus)
         else:
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 412cfd3b1..3adc7e5c9 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -42,6 +42,14 @@ class L2Cache(BaseCache):
     mshrs = 20
     tgts_per_mshr = 12
 
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64