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authorSteve Reinhardt <stever@eecs.umich.edu>2006-05-17 22:08:44 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-05-17 22:08:44 -0400
commit935ba67b4fbe595c0496e0230e39cd8ed87b7543 (patch)
tree7ca8a6e950915cb553ae8a57e47ec380bafe0dc5 /cpu
parent5da14ec60af9f6f9153963eef057257be9be8a62 (diff)
downloadgem5-935ba67b4fbe595c0496e0230e39cd8ed87b7543.tar.xz
Get basic full-system working with AtomicSimpleCPU.
SConscript: Comment out sinic for now... needs to be fixed to compile under newmem. configs/test/SysPaths.py: Fix paths. configs/test/fs.py: SimpleCPU -> AtomicSimpleCPU Fix vmlinux path cpu/simple/atomic.cc: Fix suspendContext() so quiesce works. Don't forget to checkForInterrupts(). cpu/simple/base.cc: Minor fix to interrupt check code. dev/ide_disk.hh: Don't declare regStats() in header since it's not in .cc file anymore (will need to add it back in when stats are added back). dev/io_device.cc: Set packet dest to Packet::Broadcast. dev/pciconfigall.cc: Set PCI config packet result to Success. python/m5/objects/Root.py: Add debug object to Root so things like break_cycles can be set from command line. --HG-- extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple/atomic.cc15
-rw-r--r--cpu/simple/base.cc3
2 files changed, 13 insertions, 5 deletions
diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc
index 8c38fe0d4..35a69cd4a 100644
--- a/cpu/simple/atomic.cc
+++ b/cpu/simple/atomic.cc
@@ -100,6 +100,9 @@ AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
void
AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
{
+ if (status == RangeChange)
+ return;
+
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
}
@@ -227,10 +230,13 @@ AtomicSimpleCPU::suspendContext(int thread_num)
assert(cpuXC);
assert(_status == Running);
- assert(tickEvent.scheduled());
+
+ // tick event may not be scheduled if this gets called from inside
+ // an instruction's execution, e.g. "quiesce"
+ if (tickEvent.scheduled())
+ tickEvent.deschedule();
notIdleFraction--;
- tickEvent.deschedule();
_status = Idle;
}
@@ -417,6 +423,8 @@ AtomicSimpleCPU::tick()
for (int i = 0; i < width; ++i) {
numCycles++;
+ checkForInterrupts();
+
ifetch_req->resetMin();
ifetch_pkt->reset();
Fault fault = setupFetchPacket(ifetch_pkt);
@@ -452,7 +460,8 @@ AtomicSimpleCPU::tick()
advancePC(fault);
}
- tickEvent.schedule(curTick + latency);
+ if (_status != Idle)
+ tickEvent.schedule(curTick + latency);
}
diff --git a/cpu/simple/base.cc b/cpu/simple/base.cc
index 40868e74d..30c002ed5 100644
--- a/cpu/simple/base.cc
+++ b/cpu/simple/base.cc
@@ -307,8 +307,7 @@ void
BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
- if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
- status() != IcacheAccessComplete) {
+ if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
int ipl = 0;
int summary = 0;
checkInterrupts = false;