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authorWendy Elsasser <wendy.elsasser@arm.com>2017-03-28 17:15:14 -0500
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-05-18 09:27:06 +0000
commitef96b32a28424e0d543198fee0964bb05c88704f (patch)
tree94b75a62b51e52385e60083f51c36e1ee8675e1a /include
parent76aebd9b607351e5601bf52c9ac42ede6496ee64 (diff)
downloadgem5-ef96b32a28424e0d543198fee0964bb05c88704f.tar.xz
mem: Add support for more flexible DRAM timing and topologies
This patch has 2 main aspects: 1) Add new parameter to adjust write-to-write delay 2) Enable support of more than 64 banks per controller Changes for new parameter: Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L. This parameter can be used to set a unique delay between writes and between reads. To incorporate this parameter in the controller, modified the DRAMCtrl class to have separate variables for read and write column delays. Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS as well as the new tCCD_L_WR parameter. Changes to support more than 64 banks: Modified the logic selecting the next command (reorderQueue and minBankPrep functions). Replaced the unint64_t variables with a vector of uint32_t elements. There is a uint32_t element defined per ranks to allow up to 32 banks per rank. This will automatically scale with ranks without issue. Change will allow analysis of memory sub-systems beyond the current landscape. Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10103 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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