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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:22 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:22 -0700 |
| commit | 3d39b6213265ceeb14b8089190e5a097f17fdc1b (patch) | |
| tree | 60094f669d10e2c3f52aff53789819145663b095 /src/arch/alpha/ev5.hh | |
| parent | b398b8ff1ba7e181e010afd6219074cf6f683820 (diff) | |
| download | gem5-3d39b6213265ceeb14b8089190e5a097f17fdc1b.tar.xz | |
Alpha: Pull the MiscRegFile fully into the ISA object.
Diffstat (limited to 'src/arch/alpha/ev5.hh')
| -rw-r--r-- | src/arch/alpha/ev5.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh index a135ac506..5abc7e57f 100644 --- a/src/arch/alpha/ev5.hh +++ b/src/arch/alpha/ev5.hh @@ -35,6 +35,8 @@ #include "arch/alpha/isa_traits.hh" +class ThreadContext; + namespace AlphaISA { const uint64_t AsnMask = ULL(0xff); @@ -106,6 +108,8 @@ inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } const Addr PalBase = 0x4000; const Addr PalMax = 0x10000; +void copyIprs(ThreadContext *src, ThreadContext *dest); + } // namespace AlphaISA #endif // __ARCH_ALPHA_EV5_HH__ |