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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-09 20:10:29 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:51:29 +0000 |
| commit | 47fd797f1ecd303da3263b180904a7a0b0e18581 (patch) | |
| tree | c1bdd2b5184ea89bb373922edbeb8e51602c4df0 /src/arch/arm/ArmISA.py | |
| parent | b045de7e6969d5a40d4a3f9b178844cc911ac4c2 (diff) | |
| download | gem5-47fd797f1ecd303da3263b180904a7a0b0e18581.tar.xz | |
arch-arm: Inital vector rename mode depending on A32/A64
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/ArmISA.py')
| -rw-r--r-- | src/arch/arm/ArmISA.py | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 52c42cb95..b4e8536a0 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -87,10 +87,6 @@ class ArmISA(SimObject): id_aa64afr1_el1 = Param.UInt64(0x0000000000000000, "AArch64 Auxiliary Feature Register 1") - # Initial vector register rename mode - vecRegRenameMode = Param.VecRegRenameMode('Full', - "Initial rename mode for vecregs") - # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006, "AArch64 Debug Feature Register 0") |