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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commitaa45fafb2e3667f907a2dcc491c57b9e83f8e940 (patch)
treebeefa346fd762e82f5b9c60f0da1ed554250a8b9 /src/arch/arm/isa/formats/branch.isa
parent2419903dc0c100b1eb3111a5e0fc9b186c79e6ed (diff)
downloadgem5-aa45fafb2e3667f907a2dcc491c57b9e83f8e940.tar.xz
ARM: Add support for "SUBS PC, LR and related instructions".
Diffstat (limited to 'src/arch/arm/isa/formats/branch.isa')
-rw-r--r--src/arch/arm/isa/formats/branch.isa7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index caf6f6227..45464018e 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -192,8 +192,11 @@ def format Thumb32BranchesAndMiscCtrl() {{
case 0x3c:
return new WarnUnimplemented("bxj", machInst);
case 0x3d:
- return new WarnUnimplemented("subs_pc_lr_and_rel_insts",
- machInst);
+ {
+ const uint32_t imm32 = bits(machInst, 7, 0);
+ return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
+ imm32, false);
+ }
case 0x3e:
case 0x3f:
return new WarnUnimplemented("mrs", machInst);