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| author | Matt Horsnell <matt.horsnell@arm.com> | 2018-05-09 12:40:24 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-09 09:12:28 +0000 |
| commit | b27545be48f7065aa6561e5d46e8316951f5eeee (patch) | |
| tree | 185a7657a136fa73dc51cb2dafc5366dd36d496b /src/arch/arm/isa/insts/crypto.isa | |
| parent | dd44f6bdff37fbd15a135da4d6a5b0fcf1ef2957 (diff) | |
| download | gem5-b27545be48f7065aa6561e5d46e8316951f5eeee.tar.xz | |
arch-arm: AArch32 Crypto AES
This patch implements the AArch32 AES instructions
from the Crypto extension.
Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matt Horsnell <matt.horsnell@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13248
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/crypto.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/crypto.isa | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa index cdc0293a4..20ba4c486 100644 --- a/src/arch/arm/isa/insts/crypto.isa +++ b/src/arch/arm/isa/insts/crypto.isa @@ -136,6 +136,11 @@ let {{ decoder_output += RegRegImmOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) + aeseCode = "crypto.aesEncrypt(output, input, input2);" + aesdCode = "crypto.aesDecrypt(output, input, input2);" + aesmcCode = "crypto.aesMixColumns(output, input);" + aesimcCode = "crypto.aesInvMixColumns(output, input);" + sha1_cCode = "crypto.sha1C(output, input, input2);" sha1_pCode = "crypto.sha1P(output, input, input2);" sha1_mCode = "crypto.sha1M(output, input, input2);" @@ -148,6 +153,16 @@ let {{ sha256_su0Code = "crypto.sha256Su0(output, input);" sha256_su1Code = "crypto.sha256Su1(output, input, input2);" + aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } + cryptoRegRegRegInst("aese", "AESE", "SimdAesOp", + aes_enabled, aeseCode) + cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp", + aes_enabled, aesdCode) + cryptoRegRegInst("aesmc", "AESMC", "SimdAesMixOp", + aes_enabled, aesmcCode) + cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp", + aes_enabled, aesimcCode) + sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp", sha1_enabled, sha1_cCode) |