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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
| commit | 68f2908a70ae2582804fc9c6bb19d60e7d321324 (patch) | |
| tree | f8cf3a6b935052723a8e35b0d8ea444c45b192a6 /src/arch/arm/isa/operands.isa | |
| parent | 741b24326040cfdd534d05ca46ba4c962bab18f1 (diff) | |
| download | gem5-68f2908a70ae2582804fc9c6bb19d60e7d321324.tar.xz | |
ARM: Ignore/warn when CSSELR or CCSIDR are accessed.
These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
0 files changed, 0 insertions, 0 deletions