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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:10 +0000 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
commit | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (patch) | |
tree | 9ea079dc4bc5b04cfc4b84a32c06225670be69dd /src/arch/arm/isa/templates/misc.isa | |
parent | b9edb351454c2601070fb9432f23fc3914eb33c1 (diff) | |
download | gem5-eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05.tar.xz |
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/isa/templates/misc.isa')
-rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 83 |
1 files changed, 82 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 0a23ba5d3..639ff3aca 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013 ARM Limited +// Copyright (c) 2010-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -614,3 +614,84 @@ def template RegImmRegShiftOpConstructor {{ } }}; +def template MiscRegRegImmMemOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + MiscRegIndex _dest, IntRegIndex _op1, + uint64_t _imm); + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + }; +}}; + +def template Mcr15Execute {{ + Fault %(class_name)s::execute(ExecContext *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (%(predicate_test)s) { + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + Addr size = 64; + EA &= ~(size - 1); + fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL); + } + } else { + xc->setPredicate(false); + } + + return fault; + } +}}; + +def template Mcr15InitiateAcc {{ + Fault %(class_name)s::initiateAcc(ExecContext *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (%(predicate_test)s) { + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + Addr size = 64; + EA &= ~(size - 1); + fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL); + } + } else { + xc->setPredicate(false); + } + + return fault; + } +}}; + +def template Mcr15CompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr pkt, + ExecContext *xc, + Trace::InstRecord *traceData) const + { + return NoFault; + } +}}; |