summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/templates/pred.isa
diff options
context:
space:
mode:
authorGene WU <gene.wu@arm.com>2010-08-25 19:10:42 -0500
committerGene WU <gene.wu@arm.com>2010-08-25 19:10:42 -0500
commit4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe (patch)
treedfc8029938e5580810c2a6b5cede6e72cf6f0524 /src/arch/arm/isa/templates/pred.isa
parentc2d5d2b53d1d3bfb83ce0cf0332f81c4ffea112f (diff)
downloadgem5-4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe.tar.xz
ARM: Use fewer micro-ops for register update loads if possible.
Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
-rw-r--r--src/arch/arm/isa/templates/pred.isa3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 1029cfaee..b5bdbc40e 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -146,7 +146,8 @@ def template PredOpExecute {{
xc->setPredicate(false);
}
- if (fault == NoFault && machInst.itstateMask != 0) {
+ if (fault == NoFault && machInst.itstateMask != 0&&
+ (!isMicroop() || isLastMicroop())) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
}