summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
commit556ea0ee571a20352856217427ec42e337ea4734 (patch)
tree18934f487efbf2872eb9da6d9da1cda1fef3eb8b /src/arch/arm/isa
parent5e6d28996ae80f2bd3afeadbb3454a9d1958e3a2 (diff)
downloadgem5-556ea0ee571a20352856217427ec42e337ea4734.tar.xz
ARM: Add some support for wfi/wfe/yield/etc
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa25
-rw-r--r--src/arch/arm/isa/includes.isa1
-rw-r--r--src/arch/arm/isa/operands.isa1
3 files changed, 23 insertions, 4 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 4c5d71ad9..f453d8299 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -86,10 +86,27 @@ format DataOp {
0x9: decode RN {
0: decode IMM {
0: PredImmOp::nop({{ ; }});
- 1: WarnUnimpl::yield();
- 2: WarnUnimpl::wfe();
- 3: WarnUnimpl::wfi();
- 4: WarnUnimpl::sev();
+#if FULL_SYSTEM
+ 1: PredImmOp::yield({{ ; }});
+ 2: PredImmOp::wfe({{
+ if (SevMailbox)
+ SevMailbox = 0;
+ else
+ PseudoInst::quiesce(xc->tcBase());
+ }}, IsNonSpeculative, IsQuiesce);
+ 3: PredImmOp::wfi({{
+ PseudoInst::quiesce(xc->tcBase());
+ }}, IsNonSpeculative, IsQuiesce);
+ 4: PredImmOp::sev({{
+ // Need a way for O3 to not scoreboard these
+ // accesses as pipeflushs
+ System *sys = xc->tcBase()->getSystemPtr();
+ for (int x = 0; x < sys->numContexts(); x++) {
+ ThreadContext *oc = sys->getThreadContext(x);
+ oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ }
+ }});
+#endif
}
default: PredImmOp::msr_i_cpsr({{
uint32_t newCpsr =
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 72c2e559a..c20b16724 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -76,6 +76,7 @@ output exec {{
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
#include "base/condcodes.hh"
+#include "sim/pseudo_inst.hh"
#include <cmath>
#if defined(linux)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 53a0e78f9..9f4a0ca2f 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -176,6 +176,7 @@ def operands {{
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
+ 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeNPC),
'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,