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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 14:24:06 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:29:25 +0000 |
| commit | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (patch) | |
| tree | 5e83244b5105e118d9634e88816b8e8531e4f739 /src/arch/riscv/isa | |
| parent | d72eafa64b4313f30f4c7a25000ff04f5cf30380 (diff) | |
| download | gem5-68b6f9c8a1819fdeee737cf369cc6a499b505a6c.tar.xz | |
riscv: Fix bugs with RISC-V decoder and detailed CPUs
This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa')
| -rw-r--r-- | src/arch/riscv/isa/decoder.isa | 10 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/fp.isa | 8 |
2 files changed, 12 insertions, 6 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 4f4ef7636..0e5567ac3 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -42,7 +42,8 @@ decode QUADRANT default Unknown::unknown() { CIMM8<7:6> << 4 | CIMM8<5:2> << 6; }}, {{ - assert(imm != 0); + if (machInst == 0) + fault = make_shared<IllegalInstFault>("zero instruction"); Rp2 = sp + imm; }}); format CompressedLoad { @@ -103,7 +104,12 @@ decode QUADRANT default Unknown::unknown() { if (CIMM1 > 0) imm |= ~((uint64_t)0x1F); }}, {{ - assert((RC1 == 0) == (imm == 0)); + if ((RC1 == 0) != (imm == 0)) { + if (RC1 == 0) { + fault = make_shared<IllegalInstFault>("source reg x0"); + } else // imm == 0 + fault = make_shared<IllegalInstFault>("immediate = 0"); + } Rc1_sd = Rc1_sd + imm; }}); 0x1: c_addiw({{ diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa index 1f60b9b70..3de0bb2ff 100644 --- a/src/arch/riscv/isa/formats/fp.isa +++ b/src/arch/riscv/isa/formats/fp.isa @@ -56,8 +56,8 @@ def template FloatExecute {{ std::fesetround(FE_UPWARD); break; case 0x4: - panic("Round to nearest, " - "ties to max magnitude not implemented."); + // Round to nearest, ties to max magnitude not implemented + fault = make_shared<IllegalFrmFault>(ROUND_MODE); break; case 0x7: { uint8_t frm = xc->readMiscReg(MISCREG_FRM); @@ -75,8 +75,8 @@ def template FloatExecute {{ std::fesetround(FE_UPWARD); break; case 0x4: - panic("Round to nearest," - " ties to max magnitude not implemented."); + // Round to nearest, ties to max magnitude not implemented + fault = make_shared<IllegalFrmFault>(ROUND_MODE); break; default: fault = std::make_shared<IllegalFrmFault>(frm); |